LowPower VLSI

Jan 7, 2010 Agrawal: Low Power CMOS Design 1

Vishwani D. AgrawalJames J. Danaher Professor

ECE Dept., Auburn University, Auburn, AL 36849www.eng.auburn.edu/~vagrawal

23rd International Conference on VLSI DesignEducation Forum, January 7, 2010

Bangalore, India

http://www.eng.auburn.edu/~vagrawal


F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid-State Circuits Conference Digest, vol. IV, February 1963, pp. 32-33.

No static leakage path exists for either 1 or 0 input.


VDD

Ground

CL

R

R

Dynamic Power= CLVDD

2/2 + Psc

Static power= VDD Ileakage

Vi

Vo

isc


Why is it a concern?


“Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now.

“Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .”

Patrick P. Gelsinger Senior Vice PresidentGeneral ManagerDigital Enterprise Group INTEL CORP.


400480088080

8085

8086

286 386486

Pentium®P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2 )

Hot Plate

NuclearReactor

RocketNozzle

Sun’sSurface

Source: Intel

Design practices that reduce power consumption by at least one order of magnitude; in practice 50% reduction is often acceptable.

Low-power design methods: Algorithms and architectures High-level and software techniques Gate and circuit-level methods Test power


Dynamic Power Signal transitions

Logic activity Glitches

Short-circuit Static Power

Leakage


Ptotal = Pdyn + Pstat

= Ptran + Psc + Pstat Then

= Ptran + Psc + Pstat Now

Each transition of a gate consumes CV 2/2. Methods of power saving:

Minimize load capacitances Transistor sizing

Reduce transitions Logic design Glitch reduction


Design a digital circuit for minimum transient energy consumption by eliminating hazards


Total transitions = 6Essential transitions = 2

Glitch transitions = 4


Delay D < DPD

A

BC

AB

C D D Hazard or glitch

DPD

DPD: Differential path delay

time


DelayD < DPD

A

BC

AB

C D No glitch

DPD

Delay buffer

time


Delay D > DPD

A

BC

AB

C

D > DPD

Filtered glitch

DPD

time

Maintain specified critical path delay. Glitch suppressed at all gates by

Path delay balancing Glitch filtering by increasing inertial delay of gates or by

inserting delay buffers when necessary. A linear program optimally combines all objectives.


DelayD

Path delay = d1

Path delay = d2

Minimum transient energy condition: |d1 – d2| < D

Variables: gate and buffer delays, arrival time variables.

Objective: minimize number of delay buffers. Subject to: overall circuit delay constraint for all

input-output paths. Subject to: minimum transient energy condition for

all multi-input gates. Reference:

T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” IEEE Trans. CAD, vol. 17, no. 10, pp. 1534-1545, Oct. 2009.



11

11

Critical path delay = 6

11

11

111111

11

11


Gate delay variables: d4 . . . d12 Buffer delay variables: d15 . . . d29 Arrival time variables (earliest): t4 . . . T29

(longest): T4 . . . . T29

For Gate 7:T7 ≥ T5 + d7 t7 ≤ t5 + d7 d7 > T7 - t7

T7 ≥ T6 + d7 t7 ≤ t6 + d7



T16 + d19 = T19

t16 + d19 = t19

Buffer 19:

T11 ≤ maxdelayT12 ≤ maxdelay

maxdelay is specified


Need to minimize the number of buffers. Because that leads to a nonlinear objective

function, we use an approximate criterion:minimize ∑ (all buffer delays)

i.e., minimize d15 + d16 + ∙ ∙ ∙ + d29

This gives near optimum results.



11

22


22

11

111111

22

11

22

11


11

11


33

22

111111

22

11

22


11

44


55

33

331111

22

11


Power Saving: Average 58%, Peak 68%


Dynamic Power Signal transitions

Logic activity Glitches

Short-circuit Static Power

Leakage



65nm CMOS technology:Low threshold transistors, gate delay 5ps, leakage current 10nA.High threshold transistors, gate delay 12ps, leakage 1nA.

Minimize leakage current without increasing critical path delay. What is the percentage reduction in leakage power?

What will be leakage power reduction if 30% critical path delay increase is allowed?


Reduction in leakage power = 1 – (4×1+7×10)/(11×10) = 32.73%Critical path delay = 25ps

5ps

5ps

5ps

5ps

5ps

5ps5ps

12ps

12ps

12ps

12ps


Several solutions are possible. Notice that any 3-gate path can have 2 high threshold gates. Four and five gate paths can have only one high threshold gate. One solution is shown in the figure below where six high threshold gates are shown with shading and the critical path is shown by a dashed red line arrow.

Reduction in leakage power = 1 – (6×1+5×10)/(11×10) = 49.09%Critical path delay = 29ps

12ps

12ps

12ps

12ps12ps

12ps5ps

5ps5ps

5ps

5ps

Assign every gate i an integer [0,1] variable Xi. Define ILP constraints for critical path delay. Define objective function to minimize total

leakage. Let ILP find values of Xi’s:

If Xi = 1, assign low threshold to gate i If Xi = 0, assign high threshold to gate i


1 1.1 1.2 1.3 1.4 1.5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalized Critical Path Delay

Nor

mal

ized

Lea

kage

Pow

er C432

C880

C1908


0100200300400500600700800900

Micr

owat

ts

Original circuit Optimizeddesign

Leakage powerDynamic powerTotal power


Leak

age

exce

eds

dyn

amic

power Y. Lu and V. D. Agrawal, “CMOS

Leakage and Glitch Minimization for Power-Performance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp. 378-387, December 2006.


M2

R4

A datapath

R1 R2

M1

R3


LFSR1 LFSR2

M1 M2

MISR1 MISR2

Test time

Test

pow

er

T1: test for M1

T2: test for M2


R1 LFSR2

M1 M2

MISR1 MISR2Test time

Test

pow

er

T1: test for M1T2: test for M2

Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR).

Test resources (R1, . . .) and tests (T1, . . .) are identified for the system to be tested.

Each test is characterized for test time, power dissipation and resources it requires.



T1 T2 T3 T4 T5 T6

R2R1 R3 R4 R5 R6 R7 R8 R9

Reference:R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI Systems Under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp. 175-185, June 1997.


T1(2, 100)

T2(1,10)

T3(1, 10)

T4(1, 5)

T5(2, 10)

T6(1, 100)

Tests that form a clique can be performed concurrently(test session)

Power Test time

Pmax = 4

CLIQUE NO. i TEST SESSION TEST LENGTH, Li POWER, Pi1 T1, T3, T5 100 52 T1, T3, T4 100 433 T1, T6T1, T6 100100 334 T1, T5 100 45 T1, T4 100 36 T1. T3 100 37 T2, T6 100 288 T2, T5T2, T5 1010 339 T3, T5 10 31010 T3, T4T3, T4 1010 2211 T1 100 212 T2 10 113 T3 10 114 T4 5 115 T5 10 216 T6 100 1


For each clique (test session) i, define: Integer variable, xi = 1, test session selected, or xi = 0,

test session not selected. Constants, Li = test length, Pi = power.

Constraints to cover all tests: T1 is covered if x1 + x2 + x3 + x4 + x5 + x6 + x11 ≥ 1 Similar constraint for each test, Tk

Constraints for power: Pi × xi ≤ Pmax


Objective function: Minimize Σ Li × xi

all cliques Solution:

x3 = x8 = x10 = 1, all other xi’s are 0 Test session 3 includes T1 and T6 Test session 8 includes T2 and T5 Test session 10 includes T3 and T4

Test length = L3 + L8 + L10 = 120 Peak power = max {P3, P8, P10} = 3 (Pmax = 4)


Underlying theme in our research – use of mathematical optimization methods for power reduction at gate level:

Dynamic power Leakage power Power minimization under process variation Test power

Other research Min-max power estimation Architecture level power management

Software, instruction set Multicore


T. Raja, MS 2002, PhD 2004 (NVIDIA) S. Uppalapati, MS 2004 (Intel) F. Hu, PhD 2006 (Intel) Y. Lu, PhD 2007 (Intel) J. D. Alexander, MS 2008 (Texas Instruments) K. Sheth, MS 2008 M. Allani, PhD J. Yao, PhD K. Kim, PhD M. Kulkarni, MS


Dissertations: http://www.eng.auburn.edu/~vagrawal/THESIS/thesis.html

Papers: http://www.eng.auburn.edu/~vagrawal/TALKS/talks.html


http://www.eng.auburn.edu/~vagrawal/THESIS/thesis.html

http://www.eng.auburn.edu/~vagrawal/TALKS/talks.html

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