Ver.8.1

NJM2573

- 1 -

LOW VOLTAGE 3ch VIDEO AMPLIFIER WITH LPF

GENERAL DESCRIPTION PACKAGE OUTLINE The NJM2573 is a Low Voltage 3ch Video Amplifier with LPF.

Internal 75Ω driver is easy to connect TV monitor directly. The NJM2573 corresponds to a clamp and bias inputs, and

selection of a clamp/ bias is possible for one circuit, and it corresponds to various video signals.

The NJM2573 features low power and small package, and is suitable for low power design on downsizing of DVC.

FEATURES Operating Voltage 2.8 to 5.5V Input type Vin1: CLAMP

Vin2: CLAMP/ BIAS Vin3: BIAS

Internal LPF Internal 6dB amplifier Internal 75Ω Driver Circuit (2-system drive) Internal Power Saving Circuit Bipolar Technology Package Outline PCSP16, SSOP14

Ω BLOCK DIAGRAM

NJM2573SE4 NJM2573V

LPF

6dB 75Ω driver

LPF

6dB

LPF

6dB

CLAMP

CLAMP BIAS

BIAS

CLAMP/BIASSW

Vin1

Vin2

Vin3

GND GNDPower Save

V+ V+

Vout1

Vsag1

Vout2

Vsag2

Vout3

75Ω driver

75Ω driver

NJM2573

- 2 -

PIN CONFIGURATION

1. Vin1 2. Power Save 3. Vin2 4. NC 5. GND1 6. Vin3 7. CLAMP/BIAS SW 8. Vout3 9. GND2

10. Vout2 11. Vsag2 12. V+2 13. Vout1 14. Vsag1 15. NC 16. V+1

1

2

3

4 11

12

13

14

5

6

7 8

9

10

1. Vsag1 2. V+1 3. Vin1 4. Power Save 5. Vin2 6. GND1 7. Vin3 8. CLAMP/BIAS SW 9. Vout3

10. GND2 11. Vout2 12. Vsag2 13. V+2 14. Vout1

PCSP16

SSOP14

1

2

3

4

5 6 7 8

9

10

11

12

13 14 15 16

NJM2573

- 3 -

ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATINGS UNIT

Supply Voltage V+ 7.0 V

Power Dissipation PD PCSP16 690 (Note) SSOP14 300 mW

Operating Temperature Range Topr -40 to +85 °C Storage Temperature Range Tstg -40 to +125 °C

(Note) At on a board of EIA/JEDEC specification. (76.2×114.3×1.6mm, 4 layers, FR-4)

ELECTRICAL CHARACTERISTICS (V+=3.0V,RL=150Ω,Ta=25°C)

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Operating Voltage Vopr 2.8 3.0 5.5 V

Operating Current ICC No Signal - 18.0 26.0 mA Operating Current

at Power Save Isave Power Save Mode - 60 90 µA

Vomv f=1kHz,THD=1%, CLAMP Input 2.2 2.4 - Maximum Output Voltage Swing Vom

RGB f=1kHz,THD=1%, BIAS Input 1.4 2.2 - Vp-p

Voltage Gain Gv Vin=100kHz, 1.0Vp-p,Sin Signal (CLAMP) Vin=100kHz 0.7Vp-p,Sin Signal (BIAS) 6.0 6.4 6.8 dB

Gfy4.5M Vin=4.5MHz/100kHz, 1.0Vp-p(CLAMP) Vin=4.5MHz/100kHz, 0.7Vp-p(BIAS) -0.5 0.0 +0.5

Gfy8M Vin=8MHz/100kHz, 1.0Vp-p(CLAMP) Vin=8MHz/100kHz, 0.7Vp-p(BIAS) - -2.0 - Low Pass Filter

Characteristic

Gfy16M Vin=16MHz/100kHz, 1.0Vp-p(CLAMP) Vin=16MHz/100kHz, 0.7Vp-p(BIAS) - -12 -

dB

Cross talk CT Vin=4.43MHz, 1.0Vp-p,Sin Signal (CLAMP) Vin=4.43MHz 0.7Vp-p,Sin Signal (BIAS) - -65 - dB

Differential Gain DG (CLAMP) Vin=1.0Vp-p Input 10step Video Signal - 0.2 - %

Differential Phase DP (CLAMP) Vin=1.0Vp-p Input 10step Video Signal - 0.2 - deg

S/N Ratio SNv (CLAMP) Vin=1.0Vp-p,100% White Video Signal(BIAS) Vin=0.7Vp-p,100% Red field Signal - +60 - dB

2nd. Distortion Hv

(CLAMP) Vin=1.0Vp-p, 3.58MHz, Sin Signal, RL=75Ω (BIAS) Vin=0.7Vp-p, 3.58MHz, Sin Signal, RL=75Ω

- -40 - dB

SW Change Voltage High Level VthPH 1.8 - V+

SW Change Voltage Low Level VthPL 0 - 0.3

V

CONTROL TERMINAL

PARAMETER STATUS NOTE

H Power Save: ON L Power Save: OFF Power Save

OPEN Power Save: OFF H BIAS L CLAMP CLAMP/BIAS SW

OPEN CLAMP

NJM2573

- 4 -

TEST CIRCUIT (SSOP14)

+

0.1µF

75Ω

IN2

IN1

1

IN3

+

+

75Ω 75Ω33µF

33µF

OUT1-1 OUT1-22

3

4

5

6

7

+

0.1µF

75Ω

+

0.1µF

75Ω

14

13

12

11

10

9

8

+

+

75Ω 75Ω33µF

33µF

OUT2-1 OUT2-2

+75Ω 75Ω10µF

OUT3-1 OUT3-2

10µF+0.1µFV+

Vsag1

V+1

Vin1

Power Save Vout2

Vsag2

V+2

Vout1

NJM2573V

Vin2

GND1

Vin3 C/B SW

Vout3

GND2

NJM2573

- 5 -

APPLICATION CIRCUIT (SSOP14, VIN2: CLAMP) (1) Standard circuit (2) SAG correction unused circuit (3) Two-line driving circuit (1) Standard circuit

The SAG correction reduces output coupling capacitor values. The capacitor of C1 (33µF) is recommended for the portable application. However, the 33µF capacitor may deteriorate SAG, and lose synchronization by luminance fluctuation. Adjust the C1 value, checking the waveform containing a lot of low frequency components like a bounce waveform (In case of worst condition). Change the capacitor of C1 into a large value to improve SAG.

(2) SAG correction unused circuit Cancel the SAG correction to improve lost synchronization. Connect the coupling capacitor after connecting the Vout pin and Vsag pin. The recommended value is 470µF or more.

(3) Two-line driving circuit The NJM2573 drives two-line load of 150Ω. The capacitance value of C1 should be 100µF or more, because SAG is deteriorated than a standard circuit.

0.1µF

75Ω

10µF+0.1µFV+

IN2

IN1

1

IN3

+

+

75Ω33µF

33µF

OUT1

2

3

4

5

6

7

0.1µF

75Ω

0.1µF

75Ω

14

13

12

11

10

9

8

+

+

75Ω33µF

33µF

+75Ω10µF

OUT2

OUT3

Vsag1

V+1

Vin1

Power Save Vout2

Vsag2

V+2

Vout1

NJM2573V

Vin2

GND1

Vin3 C/B SW

Vout3

GND2

C1

C1 (CLAMP)

0.1µF

75Ω

IN2

IN1

1

IN3

75ΩOUT1

2

3

4

5

6

7

0.1µF

75Ω

0.1µF

75Ω

14

13

12

11

10

9

8

+75Ω470µF

+75Ω10µF

OUT2

OUT3

Vsag1

V+1

Vin1

Power Save Vout2

Vsag2

V+2

Vout1

NJM2573V

Vin2

GND1

Vin3 C/B SW

Vout3

GND2

+470µF

10µF+0.1µFV+

(CLAMP)

0.1µF

75Ω

IN2

IN1

1

IN3

+

+

75Ω

100µF

33µF

OUT2

2

3

4

5

6

7

0.1µF

75Ω

0.1µF

75Ω

14

13

12

11

10

9

8

+

+

100µF

33µF

+10µF

75ΩOUT1

75ΩOUT2

75ΩOUT1

75ΩOUT2

75ΩOUT1

10µF+0.1µFV+

C1

C1

Vsag1

V+1

Vin1

Power Save Vout2

Vsag2

V+2

Vout1

NJM2573V

Vin2

GND1

Vin3 C/B SW

Vout3

GND2(CLAMP)

NJM2573

- 6 -

EQUIVALENT CIRCUIT PCSP16 PIN No.

SSOP14 PIN No. PIN NAME FUNCTION INSIDE EQUIVALENT CIRCUIT

1 3 VIN1 Clamp input

2 4 Power Save Power save

3 5 Vin2 Clamp/Bias input

4 - NC Non connection

5 6 GND1 GND

6 7 Vin3 Bias input

270

V+

GND

Vin1270

270

V+

GND

Vin2270

20k 270

V+

GND

Vin3

20k 270

32k

48k

GND

SW

V+

NJM2573

- 7 -

PCSP16 PIN No.

SSOP14 PIN No. PIN NAME FUNCTION INSIDE EQUIVALENT CIRCUIT

7 8 CLAMP/ BIAS SW Clamp/Bias switch

8 9 Vout3 Bias output

9 10 GND2 GND

10 11 Vout2 Clamp/Bias output

11 12 Vsag2 Sag compensation

12 13 V+2 Power Supply

32k

48k

GND

SW

V+

8.8k

GND

Vout3

V+

750

GND

Vout28.8k

V+

750

GND

Vsag2

8.8k

NJM2573

- 8 -

PCSP16 PIN No.

SSOP14 PIN No. PIN NAME FUNCTION INSIDE EQUIVALENT CIRCUIT

13 14 Vout1 Clamp output

14 1 Vsag1 Sag compensation

15 - NC Non connection

16 2 V+1 Power Supply

APPLICATION When the power supply voltage is not impressing, don’t impress voltage to the control terminal.

V+

750

GND

Vout18.8k

V+

750

GND

Vsag1

8.8k

NJM2573

- 9 -

APPLICATION ♦ SAG correction circuit

SAG correction circuit is a circuit to correct for low-frequency attenuation by high-pass filter consisting of the output coupling capacitance and load resistance. Low-frequency attenuation raises the sag in the vertical period of the video signal.

Capacitor for Vsag (Csag) is connected to the negative feedback of the amplifier. This Csag increase the low frequency gain to correct for the attenuation of low frequency gain.

Example SAG collection circuit

Example of not using sag compensation circuit

Waveform of Vout terminal and Vout1 terminal

using SAG correction circuit not using SAG correction circuit Waveform of Vout Waveform of Vout

Waveform of Vout1 Waveform of Vout1

1Vertical period

Vout

Vsag

CoutVout1

resistance:RL

Vout

Vsag

Cout

Csag

Vout1

resistance:RL

1Vertical period

NJM2573

- 10 -

SAG correction circuit generates a low frequency component signal amplified to Vout terminal. Changes of the luminance signal will be low-frequency components, if you want to output a large signal luminance changes. Therefore, generate correction signal of change of a luminance signal to Vout pin. At this time, signal is over the dynamic range of Vout pin. This may cause a lack of sync signal, and waveform distortion.

Please see diagram below (green waveform), if you want to output large changes of a signal luminance, such as 100% white video signal and black signal. Thus, output signal exceed dynamic range of Vout pin and may be the signal lack.

< Countermeasure for waveform distortion > 1. Please using small value the Sag compensation capacitor (VSAG).

It can ensure the dynamic range by using small value the capacitor (VSAG). It because of low-frequency variation of Vout pin is smaller. However, the output (VOUT) must be use large capacitor for this reason sag characteristics become exacerbated. 2. Please do not use the sag correction circuit.

Signal can output within dynamic range for reason it does not change the DC level of the output terminal. However, the output (VOUT) must be use large capacitor for this reason sag characteristics become

exacerbated.

Input signal

The sync signal is missing because exceed thedynamic range of Vout.

Waveform of Vout1

Waveform of Vout

Dynamic range of Vout

NJM2573

- 11 -

< Dual drive at using SAG correction circuit > Using sag correction circuit at dual drive circuit is below. Dual drives are less load resistance. Thus, the cut-off frequency of HPF that is composed of the output capacitor and load resistance will be small. Therefore, the sag characteristics deteriorate. Please size up to the output capacitor (Vout) for not to deteriorate the sag characteristics. < Dual drive at not using SAG correction circuit >

We recommended two-example dual drive circuit with not use sag correction circuit. Please change the configuration to be used according to the situation. Please configure to meet the following conditions. Then you can adjust the characteristics of each configuration.

21 CoutCoutCout += 21 CoutCout =

(A) In case of using one output capacitor

(B) In case of using two output capacitors

NJM2573

- 12 -

< Using SAG correction circuit > Input signal: bounce signal (IRE0%, IRE100%, 30Hz), resistance=150Ω Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal Csag=10uF Csag=22uF Csag=33uF

Cou

t=33

uF

Cou

t=47

uF

Cou

t=10

0uF

Cou

t=22

0uF

Cou

t=33

0uF

NJM2573

- 13 -

Input signal: bounce signal (IRE0%, IRE100%, 30Hz), resistance=75Ω Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal Csag=10uF Csag=22uF Csag=33uF

Cou

t=10

0uF

Cou

t=22

0uF

Cou

t=33

0uF

Cou

t=47

0uF

Cou

t=10

00uF

NJM2573

- 14 -

< Not using SAG correction circuit > Input signal: bounce signal (IRE0%, IRE100%, 30Hz), resistance=150Ω Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal

RL=75Ω RL=150Ω

Cou

t=10

0uF

Cou

t=22

0uF

Cou

t=33

0uF

Cou

t=47

0uF

Cou

t=10

00uF

NJM2573

- 15 -

< Using SAG correction circuit > Input signal: Black to White100%, resistance150Ω Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal Csag=10uF Csag=22uF Csag=33uF

Cou

t=33

uF

Cou

t=47

uF

Cou

t=10

0uF

Cou

t=22

0uF

Cou

t=33

0uF

NJM2573

- 16 -

Input signal: White100% to Black, resistance150Ω Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal Csag=10uF Csag=22uF Csag=33uF

Cou

t=33

uF

Cou

t=47

uF

Cou

t=10

0uF

Cou

t=22

0uF

Cou

t=33

0uF

NJM2573

- 17 -

< Using SAG correction circuit > Input signal: Black to White100%, resistance=75Ω Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal Csag=10uF Csag=22uF Csag=33uF

Cou

t=33

uF

Cou

t=47

uF

Cou

t=10

0uF

Cou

t=22

0uF

Cou

t=33

0uF

NJM2573

- 18 -

Input signal: White100% to Black, resistance=75Ω Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal Csag=10uF Csag=22uF Csag=33uF

Cou

t=33

uF

Cou

t=47

uF

Cou

t=10

0uF

Cou

t=22

0uF

Cou

t=33

0uF

NJM2573

- 19 -

♦Clamp circuit

1. Operation of Sync-tip-clamp Input circuit will be explained. Sync-tip clamp circuit (below the clamp circuit) operates to keep a sync tip of the

minimum potential of the video signal. Clamp circuit is a circuit of the capacitor charging and discharging of the external input Cin. It is charged to the capacitor to the external input Cin at sync tip of the video signal. Therefore, the potential of the sync tip is fixed.

And it is discharged charge by capacitor Cin at period other than the video signal sync tip. This is due to a small discharge current to the IC.

In this way, this clamp circuit is fixed sync tip of video signal to a constant potential from charging of Cin and discharging of Cin at every one horizontal period of the video signal.

The minute current be discharged an electrical charge from the input capacitor at the period other than the sync tip of video signals. Decrease of voltage on discharge is dependent on the size of the input capacitor Cin.

If you decrease the value of the input capacitor, will cause distortion, called the H sag. Therefore, the input capacitor recommend on more than 0.1uF.

< Clamp circuit >

A. Cin is large B. Cin is small (H sag experience)

< Waveform of input terminal >

2. Input impedance The input impedance of the clamp circuit is different at the capacitor discharge period and the charge period. The input impedance of the charging period is a few kΩ. On the other hand, the input impedance of the

discharge period is several MΩ. Because is a small discharge-current through to the IC. Thus the input impedance will vary depending on the operating state of the clamp circuit.

3. Impedance of signal source

Source impedance to the input terminal, please lower than 200Ω. A high source impedance, the signal may be distorted. If so, please to connect a buffer for impedance conversion.

Cin Vin

Clamp circuit

chargecurrent

dicchargecurrent

signal input

charge period discharge period

clamp potential

charge period

clamp potential

charge period discharge period charge period

Ver.8.1

NJM2573

- 20 -

TYPICAL CHARACTERISTICS

-40

-30

-20

-10

0.0

10

105 106 107 108

Voltage Gain vs. FrequencyVin=1.0Vpp

1ch2ch_clamp2ch_bias3ch

Gv[

dB]

Frequency[Hz]

0

50

100

150

200

250

300

V+ vs Isave

2 3 4 5 6 7 8

Isav

e[uA

]

V+[V]

16

18

20

22

24

26

28

30

32

V+ vs Icc

2 3 4 5 6 7 8

Icc[

mA

]V+[V]

0

1

2

3

4

5

6

7

8

V+ vs Vomc

Vom2BVom3

2 3 4 5 6 7 8

Vom

c[V

pp]

V+[V]

0

1

2

3

4

5

6

7

8

V+ vs Vomv

Vom1Vom2C

2 3 4 5 6 7 8

Vom

v[V

pp]

V+[V]

5

5.5

6

6.5

7

7.5

8

V+ vs Gv

Gv1Gv2CGv2BGv3

2 3 4 5 6 7 8

Gv[

dB]

V+[V]

NJM2573

- 21 -

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

V+ vs Gfy4.5M

Gf4.5_1Gf4.5_2CGf4.5_2BGf4.5_3

2 3 4 5 6 7 8

Gfy

4.5M

[dB]

V+[V]

-10

-8

-6

-4

-2

0

2

V+ vs Gfy8M

Gf8_1Gf8_2CGf8_2BGf8_3

2 3 4 5 6 7 8

Gfy

8M[d

B]

V+[V]

-30

-25

-20

-15

-10

-5

0

V+ vs Gfy16M

Gf16_1Gf16_2CGf16_2BGf16_3

2 3 4 5 6 7 8

Gfy

16M[d

B]

V+[V]

0

1

2

3

4

5

V+ vs DP

DP1DP2C

2 3 4 5 6 7 8

DP

[deg

]

V+[V]

0

1

2

3

4

5

V+ vs DG

DG1DG2C

2 3 4 5 6 7 8

DG

[%]

V+[V]

-100

-90

-80

-70

-60

-50

-40

V+ vs CTave

2 3 4 5 6 7 8

CTa

ve[d

B]

V+[V]

NJM2573

- 22 -

40

50

60

70

80

90

100

V+ vs SNv

SN1SN2CSN2BSN3

2 3 4 5 6 7 8

SN

v[dB

]

V+[V]

-100

-90

-80

-70

-60

-50

-40

-30

-20

V+ vs Hv

Hv1Hv2CHv2BHv3

2 3 4 5 6 7 8

Hv[

dB]

V+[V]

0

0.5

1

1.5

2

2.5

3

V+ vs VthHL

VthPSHVthPSLVthC/BHVthC/BL

2 3 4 5 6 7 8

VthH

L[V

]

V+[V]

16

18

20

22

24

26

28

30

32

T vs Icc

-60 -40 -20 0 20 40 60 80 100 120

Icc[

mA]

T [oC]

0

20

40

60

80

100

T vs Isave

-60 -40 -20 0 20 40 60 80 100 120

Isav

e[uA

]

T [oC]

0

1

2

3

4

5

6

7

8

T vs Vomc

Vom2BVom3

-60 -40 -20 0 20 40 60 80 100 120

Vom

c[V

pp]

T [oC]

NJM2573

- 23 -

0

1

2

3

4

5

6

7

8

T vs Vomv

Vom1Vom2C

-60 -40 -20 0 20 40 60 80 100 120

Vom

v[Vp

p]

T [oC]

5

5.5

6

6.5

7

7.5

8

T vs Gv

Gv1Gv2CGv2BGv3

-60 -40 -20 0 20 40 60 80 100 120

Gv[

dB]

T [oC]

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

T vs Gfy4.5M

Gf4.5_1Gf4.5_2CGf4.5_2BGf4.5_3

-60 -40 -20 0 20 40 60 80 100 120

Gfy

4.5M

[dB

]

T [oC]

-10

-8

-6

-4

-2

0

2

T vs Gfy8M

Gf8_1Gf8_2CGf8_2BGf8_3

-60 -40 -20 0 20 40 60 80 100 120

Gfy

8M[d

B]

T [oC]

-30

-25

-20

-15

-10

-5

0

T vs Gfy16M

Gf16_1Gf16_2CGf16_2BGf16_3

-60 -40 -20 0 20 40 60 80 100 120

Gfy

16M[d

B]

T [oC]

0

1

2

3

4

5

T vs DG

DG1DG2C

-60 -40 -20 0 20 40 60 80 100 120

DG

[%]

T [oC]

NJM2573

- 24 -

[CAUTION] The specifications on this databook are only

given for information , without any guarantee as regards either mistakes or omissions. Theapplication circuits in this databook are described only to show representative usagesof the product and not intended for the guarantee or permission of any right includingthe industrial rights.

0

1

2

3

4

5

T vs DP

DP1DP2C

-60 -40 -20 0 20 40 60 80 100 120

DP

[deg

]

T [oC]

40

50

60

70

80

90

100

T vs SNv

SN1SN2CSN2BSN3

-60 -40 -20 0 20 40 60 80 100 120

SN

v[dB

]

T [oC]

-100

-90

-80

-70

-60

-50

-40

-30

-20

T vs Hv

Hv1Hv2CHv2BHv3

-60 -40 -20 0 20 40 60 80 100 120

Hv[

dB]

T [oC]

-100

-90

-80

-70

-60

-50

-40

T vs CTave

-60 -40 -20 0 20 40 60 80 100 120

CTa

ve[d

B]

T [oC]

0

0.5

1

1.5

2

2.5

3

T vs VthHL

VthPSHVthPSLVthC/BHVthC/BL

-60 -40 -20 0 20 40 60 80 100 120

VthH

L[V]

T [oC]