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September 1999
This data sheet describes a mono-lithic integrated potentiostat for chemical and biochemical mea-surements. The potentiostat is invented for a two-chip microsystem.
The ASIC is fabricated in a 1.5 µm/5 V Low Power Silicon-Gate CMOS process. The circuit itself has a die size of 0.6 mm
2 (fig. 1).
Predominant component of the electrode control is a three-stage operational amplifier in low-power design. The analog output voltage is linear dependent on the working electrode current.
The polarization voltage can be applied in a wide range, in DC, AC or CV-mode. Due to the wide redox current input range a variety of electrode types are allowed to use.
Features
•••• Supports two- and three-electrode measurements
•••• Amperometric and voltammetric mode
•••• Amplification part in sc-technique
•••• Low power consumption
A low power single-chip CMOS potentiostat supporting both two- and three-electrode measurement techniques was developed at the IMS. This signal processing chip can be mounted either on the same substrate as the sensor electrodes or in a plug where it is shielded from the measurement environment. Due to the fabrica-tion of the potentiostat in a stan-dard CMOS process, both chip size and costs are kept to a minimum.
Fig. 1: Chip photomicrograph
Low Power
Single-Chip
CMOS Potentiostat
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme Finkenstraße 61 D - 47057 Duisburg Phone: +49 (0) 2 03 / 37 83-0 Fax: +49 (0) 2 03 / 37 83-266 Internet: http://www.ims.fhg.de Contact: Michael Bollerott Phone: +49 (0) 2 03 / 37 83-277 E-Mail: [email protected] FhG-IMS reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or other-wise under patents or other right. Application circuits shown, if any, are typical examples illustrating the opera-tion of the devices. FhG-IMS cannot assume responsibility for any problems rising out of the use of these circuits.
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potentio-e.doc
Electrical Performance
The control part of the circuit is realized by an analog controller (fig. 2). The counter electrode potential is adjusted in a way that the poten-tial difference between the refe-rence electrode and the working electrode is always close to the applied polarization voltage. Since the reference electrode impedance is very high (>10 GΩ), the inevitable potential drop is reduced to a minimum.
The block diagram of the CMOS Potentiostat is given in fig. 3.
The amplification part of the poten-tiostat has a time-continuous rail-to-rail voltage output. The circuit is realized in switched-capacitor technique. The amplification is scaled by the sampling period
Ts = 1 / (2 fc), where fc is the master clock frequency. The transfer function of the complete amplification part is thus inverse proportional to the master clock frequency, giving an easy way to adjust the potentiostat to the input current. In summary, the amplifier of the potentiostat converts the input current over a range of four decades from +/- 100 pA up to +/- 1500 nA into an output voltage with a maximum slope of approximitely 130 mV/nA.
W
R
C
Vpol
Vpol
Solution
Amplification Part
Fig. 2:
Range Zero Adj.
Inte-grator S/H
ElectrodeControl
ClockGeneration
CentralBias
W
RC
Vpol MClk CenBias
Vout
Fig. 3: Block diagram of the Potentiostat. W, R and C are the ports for the sensor electrodes.
Power Supply UB = U− ... U+: ±1.5 V ... ±2.5 V U− − 5 % ... U+ + 5 % Gain (Open-Loop): 85 dB Unity Gain Bandwidth: 500 kHz Output Voltage: U+−0.2V ... U− +0.2 V Load Driving Capability: RL = 1 kΩ, CL = 100 pF Output Ripples (peak-to-peak): max. 220 mV (UB = 5 V) Power Supply Rejection Ratio: 40 dB Power Consumption: 0.55 mW bei 5 V
external Master Clock Signal1: 2 kHz ... 20 kHz
Polarisation Voltage: -1.5 V ... +1.5 V Redox Current: ± 0.1 ... ± 1500 nA Impedance Reference Elektrode: > 10 GΩ Slew Rate: 0.2 V/µs Pinouts 14 Chiparea Prototype: 1.44 x 1.84 mm2
Fig. 4: Operating characteristics
