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“Low-Power, Real-Time Object-Recognition Processors for Mobile Vision Systems”,

IEEE Micro 2012.

Jinwook Oh ; Gyeonghoon Kim ; Injoon Hong ; Junyoung Park ; Seungjin Lee ; Joo-Young Kim ;

Jeong-Ho Woo ; Hoi-Jun Yoo

Presenter: Juseong Lee, 2013021037

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Outline• Introduction

• Background

• Main Idea

• Implementation

• Conclusion

• EvaluationObject Recognition by Juseong Lee

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Outline• Introduction

• Background

• Main Idea

• Implementation

• Conclusion

• EvaluationObject Recognition by Juseong Lee

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Introduction

Source by MBN News

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Introduction• Object recognition system

– Require real-time operation• High performance• Low power in mobile system

• How can implement?– Find suitable algorithm

• SIFT algorithm– Hardware optimization

• Algorithm optimization• Make exclusive processor

– Parallel computation• Multi-threading• NoC

SIFT - Scale Invariant Feature TransformNoC - Network on Chip

Source by VOLVO

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Outline• Introduction

• Background

• Main Idea

• Implementation

• Conclusion

• EvaluationObject Recognition by Juseong Lee

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Background Knowledge• What is SIFT algorithm?

– Scale Invariant Feature Transform– The most popular candidate

• For how to extract some interest points out of the object and describe them

– Robust against changes in translation, scaling, and rotation.

Image matching by SIFT

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Background Knowledge• What’s the problem in SIFT-based object recognition?

– Consumes a lot of power• Owing to the heavy computation required in descriptor Gen. and matching

– Today’s high-resolution image sensors & tight power budgets• Make real-time SIFT implementation in mobile device even harder

Scare resources problem

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Outline• Introduction

• Background

• Main Idea

• Implementation

• Conclusion

• EvaluationObject Recognition by Juseong Lee

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Main Idea• How can we solve the problem?

– Make an object-recognition processor• Using an attention-based recognition algorithm

– For energy efficiency• A heterogeneous multicore architecture

– For data and thread parallelism• Network-on-Chip(NoC) communication

– For high bandwidth

• The processor determines Regions of Interest(ROI) part of image– For minimizing unnecessary computations

• Heterogeneous multicore architecture– provides several types of parallelism– achieves high throughput– low power consumption

• High-bandwidth NoC plays a role as the communications backbone

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Why find ROI?• Image processing algorithm has no regard throughput

Image size

480 x 360

Objects have feature!172,800 computations!

Example) Edge detection

You can select part for reducing computation!

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Main Idea – BONE V

Using Conventional method

Using Main Idea

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Main Idea – Algorithm• Attention-based object recognition

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Main Idea – Architecture

Pixel level parallelVery long instruction word

3 stage task level pipeline1.5x↓ power consumption

5 stage fine-grained pipeline3.45x↑ pipeline throughput

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SMT-enabled heteroge-neous multicore processor

• Throughput-optimized SFEC– Find ROI tile for energy efficiency– Memory locality with high bandwidth utilization

• Latency-optimized FMP– ROI tile and NoC help latency

• Power-optimized MLE– Changes the core’s thread allocation – and operating voltage and frequency dynamically

BONE-V5:

SFEC: SMT-enabled Feature Extraction ClusterFMP: Feature Matching ProcessorMLE: Machine Learning Engine

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Outline• Introduction

• Background

• Main Idea

• Implementation

• Conclusion

• EvaluationObject Recognition by Juseong Lee

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Implementation

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Implementation - Comparing

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Implementation - Comparing

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Outline• Introduction

• Background

• Main Idea

• Implementation

• Conclusion

• EvaluationObject Recognition by Juseong Lee

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Conclusion• Energy efficient system is important to improve

performance

• Algorithm and architecture have to optimize at the same time

• BONE-V multicore processors can apply real-time object recognition system

• Future BONE-V processors will further lower the power consumption.

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Outline• Introduction

• Background

• Main Idea

• Implementation

• Conclusion

• EvaluationObject Recognition by Juseong Lee

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Evaluation• Table 3 has to contain the result that

comparing other recognition processor

• When hardware optimization, Not only overall algorithm but particular algorithm block optimization are needed– CORDIC based gradient and magnitude computation

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Thanks for Ur listening!

Thanks!Juseong_lee@korea.ac.kr