Low Power NTSC/PAL/SECAM Video Decoder with …read.pudn.com/downloads198/ebook/933744/TW9910A_SPEC.pdfTECHWELL, INC. 1 REV. A 04/19/2005 Techwell, Inc. TW9910 – Low Power NTSC/PAL/SECAM

TECHWELL, INC. 1 REV. A 04/19/2005

Techwell, Inc.

TW9910 – Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer

Preliminary Data Sheet

Techwell Confidential. Information may change without notice.

Disclaimer

This document provides technical information for the user. Techwell, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Techwell, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Techwell, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.

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TW9910


Techwell, Inc. ...............................................................................1 Disclaimer.................................................................................1

Features........................................................................................3 Functional Description...............................................................4

General description..................................................................4 General description..................................................................5 Analog Front-end .....................................................................5

Video Source Selection........................................................5 Clamping and Automatic Gain Control ................................6 Analog to Digital Converter ..................................................6

Sync Processing ......................................................................6 Horizontal sync processing ..................................................6 Vertical sync processing ......................................................6

Color Decoding ........................................................................7 Y/C separation......................................................................7 Color demodulation ..............................................................7 Automatic Chroma Gain Control..........................................8 Low Color Detection and Removal......................................8 Automatic standard detection ..............................................8 Video Format support...........................................................9

Component Processing ...........................................................9 Luminance Processing.........................................................9 Gamma.................................................................................9 Sharpness.............................................................................9 The Hue and Saturation.....................................................10 Color Transient Improvement ............................................10

Power Management ..............................................................10 Control Interface.....................................................................10 Output Interface .....................................................................11

ITU-R BT.656 .....................................................................11 ITU-R BT.656 SAV and EAV code sequence...................11

Down-scaling and Cropping ..................................................11 TW9910 Down-Scaling ......................................................11 TW9910 Cropping..............................................................12

VDELAY + VACTIVE < Total number of lines per field........13 VBI Data Processing..............................................................14

Raw VBI data output ..........................................................14 VBI Data Slicer ...................................................................14 Sliced VBI Data output format............................................15

Two Wire Serial Bus Interface...............................................21 Test Modes ............................................................................23 Filter Curves...........................................................................24

Decimation filter..................................................................24 Chroma Band Pass Filter Curves......................................24 Luma Notch Filter Curve for NTSC and PAL/SECAM......24 Luma Notch Filter Curve for NTSC and PAL/SECAM......25 Chrominance Low-Pass Filter Curve.................................25 Horizontal Scaler Pre- Filter curves ...................................25 Horizontal Scaler Pre- Filter curves ...................................26 Vertical Interpolation Filter curves......................................26 Peaking Filter Curves.........................................................27

Control Register ........................................................................28 TW9910 Register SUMMARY...........................................28 0x00 – Product ID Code Register (ID)..............................31 0x01 – Chip Status Register I (STATUS1)........................31 0x02 – Input Format (INFORM).........................................32 0x03 – Output Format Control Register (OPFORM) ........33 0x04 – GAMMA and HSYNC Delay Control.....................33 0x05 – Output Control I ......................................................34 0x06 – Analog Control Register (ACNTL) .........................35 0x07 – Cropping Register, High (CROP_HI) ....................35 0x08 – Vertical Delay Register, Low (VDELAY_LO) ........36 0x09 – Vertical Active Register, Low (VACTIVE_LO).......36 0x0A – Horizontal Delay Register, Low (HDELAY_LO) ...36 0x0B – Horizontal Active Register, Low (HACTIVE_LO)..36 0x0C – Control Register I (CNTRL1).................................37 0x0D – Vertical Scaling Register, Low (VSCALE_LO).....37 0x0E – Scaling Register, High (SCALE_HI)......................37

0x0F – Horizontal Scaling Register, Low (HSCALE_LO).38 0x10 – BRIGHTNESS Control Register (BRIGHT) ..........38 0x11 – CONTRAST Control Register (CONTRAST) .......38 0x12 – SHARPNESS Control Register I (SHARPNESS) 38 0x13 – Chroma (U) Gain Register (SAT_U) .....................39 0x14 – Chroma (V) Gain Register (SAT_V)......................39 0x15 – Hue Control Register (HUE)..................................39 0x16 – Sharpness Control II (SHARP2)............................39 0x17 – Vertical Sharpness (VSHARP)..............................40 0x18 – Coring Control Register (CORING).......................40 0x19 – VBI Control Register (VBICNTL)...........................41 0x1A – Analog Control II ....................................................42 0x1B – Output Control II ....................................................42 0x1C – Standard Selection (SDT).....................................43 0x1D – Standard Recognition (SDTR)..............................44 0x1E – Component Video Format (CVFMT) ....................44 0x1F – Test Control Register (TEST)................................44 0x20 – Clamping Gain (CLMPG) ......................................44 0x21 – Individual AGC Gain (IAGC)..................................44 0x22 – AGC Gain (AGCGAIN) ..........................................44 0x23 – White Peak Threshold (PEAKWT)........................44 0x24– Clamp level (CLMPL)..............................................44 0x25– Sync Amplitude (SYNCT).......................................44 0x26 – Sync Miss Count Register (MISSCNT).................44 0x27 – Clamp Position Register (PCLAMP) .....................44 0x28 – Vertical Control I (VCNTL1)...................................44 0x29 – Vertical Control II (VCNTL2)..................................44 0x2A – Color Killer Level Control (CKILL).........................44 0x2B – Comb Filter Control (COMB).................................44 0x2C – Luma Delay and H Filter Control (LDLY)..............44 0x2D – Miscellaneous Control I (MISC1)..........................44 0x2E – LOOP Control Register (LOOP) ...........................44 0x2F – Miscellaneous Control II (MISC2) .........................44 0x30 – Macrovision Detection (MVSN) .............................44 0x31 – Chip STATUS II (STATUS2) ................................44 0x32 – H monitor (HFREF)................................................44 0x33 – CLAMP MODE (CLMD) ........................................44 0x34 – ID Detection Control (IDCNTL)..............................44 0x35 – Clamp Control I (CLCNTL1) ..................................44 0x4F – WSS3.....................................................................44 0x50 – FILLDATA ..............................................................44 0x51 – SDID.......................................................................44 0x52 – DID..........................................................................44 0x53 – WSS1 .....................................................................44 0x54 – WSS2 .....................................................................44 0x55 – VVBI .......................................................................44 0x56~6A LCTL6~LCTL26 .................................................44 0x6B – HSGEGIN ..............................................................44 0x6C – HSEND..................................................................44 0x6D – OVSDLY................................................................44 0x6E – OVSEND................................................................44 0x6F – VBIDELAY .............................................................44

Pin Diagram ...............................................................................44 Pin Description.......................................................................44 Pin Description.......................................................................44

Power and Ground Pins.....................................................44 Parametric Information ............................................................44

AC/DC Electrical Parameters................................................44 Clock Timing Diagram........................................................44

Mechanical Data....................................................................44 Mechanical Data....................................................................44 Application Schematics ........................................................44

PCB Layout Considerations ..............................................44 Copyright Notice.......................................................................44 Disclaimer ..................................................................................44 Life Support Policy ...................................................................44

TW9910


TW9910 – Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer

Features

Video decoder

− NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N combination), PAL (60), SECAM support with automatic format detection

− Software selectable analog inputs allows any of the following combinations, e.g. 4 CVBS or ( 3 CVBS and 1 Y/C ).

− Two 9-bit ADCs and analog clamping circuit. − Fully programmable static gain or automatic gain control

for the Y channel − Programmable white peak control for the Y or CVBS

channel

− 4-H adaptive comb filter Y/C separation

− PAL delay line for color phase error correction

− Image enhancement with 2D peaking and CTI.

− Digital sub-carrier PLL for accurate color decoding

− Digital Horizontal PLL for synchronization processing and pixel sampling

− Advanced synchronization processing and sync detection for handling non-standard and weak signal

− Programmable hue, brightness, saturation, contrast, sharpness, Gamma control, and noise suppression

− Automatic color control and color killer

− Detection of level of copy protection according to Macrovision standard

− Programmable output cropping − ITU-R 601 or ITU-R 656 compatible YCbCr(4:2:2) output

format − VBI slicer supporting industrial standard data services

− VBI data pass through, raw ADC data for Intercast™ Video scaler

− High quality horizontal filtered scaling with arbitrary scale down ratio

− Phase accuracy better than 1/32 pixel

− Selectable anti-alias filter

− Vertical down scaling by line dropping

Miscellaneous

− Two wire MPU serial bus interface

− Power-down mode

− Typical power consumption <200mW

− Single 27MHz crystal for all standards

− Supports 24.54MHz and 29.5MHz crystal for high resolution square pixel format decoding

− 3V tolerant I/O

− 1.8V/3.3 V power supply

− 44-pin LQFP package

TW9910


Functional Description

Figure 1: TW9910 Block Diagram

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TW9910


General description

The TW9910 is a multi-standard video decoder and encoder chip that is designed for multimedia applications. It uses the mixed-signal 1.8V CMOS technology to provide a low-power integrated solution.

The video encoder is used to encoder digital YCbCr input into analog CVBS or S-video output. With five built-in DACs, it can simultaneously support analog YCbCr output in addition to S-video output for various applications. It can support both NTSC (60Hz) and PAL (50Hz) output. A stable crystal generated 27MHz clock is used for all necessary sub-carrier generation. It accepts ITU-R 656 compatible digital input externally.

The video decoder decodes the analog CVBS or S-video signals into digital YCbCr for output. It consists of analog front-end with input source selection, variable gain amplifier and analog-to-digital converters, Y/C separation circuit, multi-standard color decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC 4.43 and SECAM) and synchronization circuitry. The Y/C separation is done with highly adaptive 4H comb filter for reduced cross color and cross luminance. The advanced synchronization processing circuitry can produce stable pictures for non-standard signal as well as weak signal. A video scaler is provided to arbitrarily scale down the output video. The output of the decoder is formatted to the ITU-R 656 compatible output. It includes various control circuits like brightness, contrast, saturation, and dynamic aperture correction for best video quality.

A 2-wire serial MPU interface is used to simplify system integration. All the functions can be controlled through this interface.

Analog Front-end

The analog front-end converts analog video signals to the required digital format. There are two analog channels with clamping circuits and ADCs. The Y channel has 4-input multiplexer, and a variable gain amplifier for automatic gain control (AGC). Its four inputs are identified as MUX0, MUX1, MUX2, and MUX3. The C channel is internally clamped to the zero level of the bipolar input source when enabled.

Video Source Selection

All analog signals should be AC-coupled to these inputs.

The Y channel analog multiplexer selects one of the four inputs MUX[0-3]. MUX[0-3] can be connected to composite video inputs or the Y signal of an S-Video or component input. When decoding a S-Video input, the Y signal should connect to one of the MUX inputs and the C signal to Cin0.

Software selectable analog inputs allow several possible input combinations:

1. Up to four composite video inputs. 2. Three composites and one S-video input.

The input video signals in any certain channel maybe momentarily connected together through the equivalent of a 200 ohm resistor during multiplexer switching. Therefore, the multiplexer cannot be used for switching on a real-time pixel-by-pixel basis.

TW9910


Clamping and Automatic Gain Control

All two analog channels have built-in clamping circuit that restores the signal DC level. The Y channel restores the back porch of the digitized video to a level of 60 or a programmable level. The C channel restores the back porch of the digitized video to a level of 128. This operation is automatic through internal feedback loop.

The Automatic Gain Control (AGC) of the Y channel adjusts input gain so that the sync tip is at a desired level. A programmable white peak protection logic is included to prevent saturation in the case of abnormal proportion between sync and white peak level.

Analog to Digital Converter

TW9910 contains two 9-bit pipelined ADCs that consume less power than conventional flash ADC. The output of the Clamp and AGC connects to one ADC that digitizes the composite input or the Y signal of the S-Video input. The second ADC digitizes the C signal when decoding S-video signal.

Sync Processing

The sync processor of TW9910 detects horizontal synchronization and vertical synchronization signals in the composite video or in the Y signal of an S-video or component signal. The processor contains a digital phase-locked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from VCR fast forward or backward.

Horizontal sync processing

The horizontal synchronization processing contains a sync separator, a phase-locked-loop (PLL), and the related decision logic.

The horizontal sync detector detects the presence of a horizontal sync tip by examining low-pass filtered input samples whose level is lower than a threshold. After sufficient low levels are detected, a horizontal sync is recognized. Additional logic is also used to avoid false detection on glitches.

The horizontal PLL locks onto the extracted horizontal sync in all conditions to provide jitter free image output. From there, the PLL also provides orthogonal sampling raster for the down stream processor. The PLL has free running frequency that matches the standard raster frequency. It also has wide lock-in range for tracking any non-standard video signal.

In case the horizontal sync is missing, a “free-wheel” mechanism keeps generating horizontal sync signal until horizontal sync is detected again. This option can also be turned off for some applications that determine video loss by detecting the existence of horizontal sync.

Vertical sync processing

The vertical sync separator detects the vertical synchronization pattern in the input video signals. In addition, the actual sync determination is controlled by a detection window to provide more reliable synchronization. It achieves the functionality of a PLL without the complexity of a PLL. An option is available to provide faster responses for certain applications. The field status is determined at vertical synchronization time. When the location of the detected vertical sync is inline with a horizontal sync, it indicates a frame start or the odd field

TW9910


start. Otherwise, it indicates an even field. The field logic can also be controlled to toggle automatically while tracking the input.

Color Decoding

Y/C separation

The color-decoding block contains the luma/chroma separation for the composite video signal and multi-standard color demodulation. For NTSC and PAL standard signals, the luma/chroma separation can be done either by comb filter or notch/band-pass filter combination. For SECAM standard signals, only notch/band-pass filter is available. The default selection for NTSC/PAL is comb filter. The characteristics of the band-pass filter are shown in the filter curve section.

In the case of comb filter, the TW9910 separates luma (Y) and chroma © of a NTSC composite video signal using a proprietary 2H adaptive comb filter. The filter uses a two-line buffer. Adaptive logic combines the upper-comb and the lower-comb results based on the signal changes among the previous, current and next lines. This technique leads to good Y/C separation with small cross luma and cross color at both horizontal and vertical edges. Due to the 90-degree phase difference on adjacent lines of a PAL chroma signal, the 4H adaptive comb filter is used to give better performance.

Due to the line buffer used in the comb filter, there is always two lines processing delay in the output images no matter what standard or filter option is chosen.

If notch/band-pass filter is selected, the characteristics of the filters are shown in the filter curve section.

Color demodulation

The color demodulation for NTSC and PAL standard is done by first quadrature mixing the chroma signal to the base band. The mixing frequency is equal to the sub-carrier frequency for NTSC and PAL. After the mixing, a low-pass filter is used to remove carrier signal and yield chroma components. The low-pass filter characteristic can be selected for optimized transient color performance. For the PAL system, the PAL ID or the burst phase switching is identified to aid the PAL color demodulation.

For SECAM, the mixing frequency is 4.286Mhz. After the mixer and low-pass filter, it yields the FM modulated chroma. The SECAM demodulation process therefore consists of low-pass filter, FM demodulator and de-emphasis filter. The filter characteristics are shown in filter curve section. During the FM demodulation, the chroma carrier frequency is identified and used to control the SECAM color demodulation.

The sub-carrier signal for use in the color demodulator is generated by direct digital synthesis PLL that locks onto the input sub-carrier reference (color burst). This arrangement allows any sub-standard of NTSC and PAL to be demodulated easily with single crystal frequency.

During S-video operation, the Y signal bypasses the comb filter. The C signal connects directly to the color demodulator. During component input operation, all the chroma processing and color demodulator blocks are bypassed.

TW9910


Automatic Chroma Gain Control

The Automatic Chroma Gain Control (ACC) compensates for reduced amplitudes caused by high-frequency loss in video signal. In the NTSC/PAL standard, the color reference signal is the burst on the back porch. This color-burst amplitude is calculated and compared to standard amplitude. The chroma (Cx) signals are then increased or decreased in amplitude accordingly. The range of ACC control is –6db to +26db.

This function is always enabled to provide consistent image quality under different signal conditions.

Low Color Detection and Removal

For low color amplitude signals, black and white video, or very noisy signals, the color will be “killed”. The color killer uses the burst amplitude measurement to switch-off the color when the measured burst amplitude falls below a programmed threshold. The threshold has programmed hysteresis to prevent oscillation of the color killer function. The color killer function can be disabled by programming a low threshold value.

Automatic standard detection

The TW9910 has build-in automatic standard discrimination circuitry. The circuit uses burst-phase, burst-frequency and frame rate to identify NTSC, PAL or SECAM color signals. The standards that can be identified are NTSC (M), NTSC (4.43), PAL (B, D, G, H, I), PAL (M), PAL (N), PAL (60) and SECAM (M). Each standard can be included or excluded in the standard recognition process by software control. The identified standard is indicated by the Standard Selection (SDT) register. Automatic standard detection can be overridden by software controlled standard selection.

TW9910


Video Format support

TW9910 supports all common video formats as shown in Table 1. The video decoder needs to be programmed appropriately for each of the composite video input formats.

Table 1. Video Input Formats Supported by the TW9910 Format Lines Fields Fsc Country

NTSC-M 525 60 3.579545 MHz U.S., many others

NTSC-Japan (1) 525 60 3.579545 MHz Japan

PAL-B, G, N 625 50 4.433619 MHz Many

PAL-D 625 50 4.433619 MHz China

PAL-H 625 50 4.433619 MHz Belgium

PAL-I 625 50 4.433619 MHz Great Britain, others

PAL-M 525 60 3.575612 MHz Brazil

PAL-CN 625 50 3.582056 MHz Argentina

SECAM 625 50 4.406MHz 4.250MHz

France, Eastern Europe, Middle East, Russia

PAL-60 525 60 4.433619 MHz China

NTSC (4.43) 525 60 4.433619 MHz Transcoding

Notes: (1). NTSC-Japan has 0 IRE setup.

Component Processing

Luminance Processing

The TW9910 adjusts brightness by adding a programmable value (in register BRIGHTNESS) to the Y signal. It adjusts the picture contrast by changing the gain (in register CONTRAST) of the Y signal.

The TW9910 video decoder also performs a coring function. It can force all values below a certain level, programmed in the Coring Control Register, to zero. This is useful because human eyes are sensitive to variations in nearly black images. Changing levels near black to true black, can make the image appears clearer.

Gamma

Y Gamma function is provided to compensate for different display types. Four pre-programmed Gamma levels can be selected through registers.

Sharpness

The TW9910 also provides a sharpness control function through control registers. It provides the control in 16 steps up to +12db. The center frequency of the enhancement curve is around 3.5Mhz. It also provides a high frequency coring function to minimize the amplification of high frequency noise. The coring level is adjustable through the Coring Control register. The same

TW9910


function can also be used to soften the images. This can be used to provide noise reduction on noisy signal.

To further enhance the image, a programmable vertical peaking function is provided for up to +6db of enhancement. A programmable coring level can be adjusted to minimize the noise enhancement.

The Hue and Saturation

When decoding NTSC signals, TW9910 can adjust the hue of the chroma signal. The hue is defined as a phase shift of the subcarrier with respect to the burst. This phase shift can be programmed through a control register.

The color saturation can be adjusted by changing the gain of Cb and Cr signals for all NTSC, PAL and SECAM formats. The Cb and Cr gain can be adjusted independently for flexibility.

Color Transient Improvement

A programmable Color Transient Improvement circuit is provided to enhance the color bandwidth. Low level noise enhancement can be suppressed by a programmable coring logic. Overshoot and undershoot are also removed by special circuit to prevent false color generation at the color edge.

Power Management

The TW9910 can be put into power-down mode in which its clock is turned off for most of the circuits. The Y and C path can be separately powered down.

Control Interface

The TW9910 registers are accessed via 2-WIRE SERIAL MPU interface. It operates as a slave device. Serial clock and data lines, SCL and SDA, transfer data from the bus master at a rate of 400 Kbits/s. The TW9910 has one serial interface address select pins to program up to two unique serial addresses TW9910. This allows as many as two TW9910 to share the same serial bus. Reset signals are also available to reset the control registers to their default values.

TW9910


Output Interface

ITU-R BT.656

ITU-R BT.656 defines strict EAV/SAV Code, video data output timing, H blanking timing, and V Blanking timing. In this mode, VD[15:8] pins are only effective and CLKx2 pin should be used for data clock signal. EAV/SAV Code format is shown as follows. Bit 7 of forth byte in EAV/SAV code must be “1” in ITU-R BT.656 standard. For that reason, VIPCFG Register bit must be set to “1”.

ITU-R BT.656 SAV and EAV code sequence

VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 1st byte 1 1 1 1 1 1 1 1

2nd byte 0 0 0 0 0 0 0 0 3rd byte 0 0 0 0 0 0 0 0 4th byte *C F V H V XOR H F XOR H F XOR V F XOR V XOR H

*C is set by VIPCFG register bit.

For complete IRU-R BT.656 standard,following registers are required.

ITU-R BT.656 Register set up. Register 525 line system 625 line systemMODE 1 1 LEN 0 0

VDELAY 0x012 0x018 VACTIVE 0X0F4 0x120 HACTIVE 0x2D0 0x2D0 HA_EN 1 1 VIPCFG 1 1

NTSC656 1 0

ITU-R BT.656 for 525-line system has 244 video active lines in odd field and 243 vide active lines in even field. NTSC656 register bit controls this video active line length.

Down-scaling and Cropping

The TW9910 provides two methods to reduce the amount of output video pixel data, downscaling and cropping. The downscaling provides full video image at lower resolution. Cropping provides only a portion of the video image output. All these mechanisms can be controlled independently to yield maximum flexibility in the output stream.

TW9910 Down-Scaling

The TW9910 can independently reduce the output video image size in both horizontal and vertical directions using arbitrary scaling ratios up to 1/16 in each direction. The horizontal scaling employs a dynamic 6-tap 32-phase interpolation filter for luma and a 2-tap 8-phase interpolation filter for chroma because of the limited bandwidth of the chroma data. The vertical scaling uses the simple line dropping method. It is recommended to choose integer vertical scaling ratio for best result.

TW9910


Downscaling is achieved by programming the horizontal scaling ratio register (HSCALE) and vertical scaling ratio register (VSCALE). When outputting unscaled video, the TW9910 will output CCIR601 compatible 720 pixels per line or any number of pixels per line as specified by the HACTIVE register. The standard output for Square Pixel mode is 640 pixels for 60 Hz system and 768 pixels for 50 Hz systems. If the number of output pixels required is smaller than 720 in CCIR601 compatible mode or the number specified by the HACTIVE register. The 12-bit HSCALE register, which is the concatenation of two 8-bit registers SCALE_HI and HSCALE_LO, is used to reduce the output pixels to the desired number.

Following is an example using pixel ratio to determine the horizontal scaling ratio. These equations should be used to determine the scaling ratio to be written into the 12-bit HSCALE register assuming HACTIVE is programmed with 720 active pixels per line:

NTSC: HSCALE = [720/Npixel_desired] * 256

PAL: HSCALE = [(720/Npixel_desired)] * 256

Where: Npixel_desired is the nominal number of pixel per line.

For example, to output a CCIR601 compatible NTSC stream at SIF resolution, the HSCALE value can be found as:

HSCALE = [(720/320)] * 256 = 576 = 0x0240

However, to output a SQ compatible NTSC stream at SIF resolution, the HSCALE value should be found as:

HSCALE = [(640/320)] * 256 = 512 = 0x200

In this case, with total resolution of 768 per line, the HACTIVE should have a value of 640.

The vertical scaling determines the number of vertical lines output by the TW9910. The vertical scaling register (VSCALE) is a 12-bit register, which is the concatenation of a 4-bit register SCALE_HI and an 8-bit register VSCALE_LO. The maximum scaling ratio is 16:1. Following equations should be used to determine the scaling ratio to be written into the 12-bit VSCALE register assuming VACTIVE is programmed with 240 or 288 active lines per field.

60Hz system: VSCALE = [240/ Nline_desired] * 256

50Hz system: VSCALE = [288/ Nline_desired] * 256

Where: Nline_desired is the number of active lines output per field.

The scaling ratios for some popular formats are listed in Table 3.

TW9910 Cropping

Cropping allows only subsection of a video image to be output. The VACTIVE signal can be programmed to indicate the number of active lines to be displayed in a video field, and the HACTIVE signal can be programmed to indicate the number of active pixels to be displayed in a video line. The start of the field or frame in the vertical direction is indicated by the leading edge of VSYNC. The start of the line in the horizontal direction is indicated by the leading edge of the HSYNC. The start of the active lines from vertical sync edge is indicated by the VDELAY register. The start of the active pixels from the horizontal edge is indicated by the HDELAY register. The sizes and location of the active video are determined by HDELAY, HACTIVE, VDELAY, and VACTIVE registers. These registers are 8-bit wide, the lower 8-bits is,

TW9910


respectively, in HDELAY_LO, HACTIVE_LO, VDELAY_LO, and VACTIVE_LO. Their upper 2-bit shares the same register CROP_HI.

The Horizontal delay register (HDELAY) determines the number of pixels delay between the leading edge of HSYNC and the leading edge of the HACTIVE. Note that this value is referenced to the unscaled pixel number. The Horizontal active register (HACTIVE) determines the number of active pixels to be output or scaled after the delay from the sync edge is met. This value is also referenced to the unscaled pixel number. Therefore, if the scaling ratio is changed, the active video region used for scaling remain unchanged as set by the HACTIVE register, but the valid pixels output are equal or reduced due to down scaling. In order for the cropping to work properly, the following equation should be satisfied.

HDELAY + HACTIVE < Total number of pixels per line.

For NTSC output at 13.5 MHz pixel rate, the total number of pixels is 858. The HDELAY should be set to 106 and HACTIVE set to 720. For PAL output at 13.5 MHz rate, the total number of pixels is 864. The HDELAY should be set to 108 and HACTIVE set to 720.

The Vertical delay register (VDELAY) determines the number of lines delay between the leading edge of the VSYNC and the start of the active video lines. It indicates number of lines to skip at the start of a frame before asserting the VACTIVE signal. This value is referenced to the incoming scan lines before the vertical scaling. The number of scan lines is 525 for the 60Hz systems and 625 for the 50Hz systems. The Vertical active register (VACTIVE) determines the number of lines to be used in the vertical scaling. Therefore, the number of scan lines output is equal or less than the value set in this register depending on the vertical scaling ratio. In order for the vertical cropping to work properly, the following equation should be observed.

VDELAY + VACTIVE < Total number of lines per field

Table 2 shows some popular video formats and its recommended register settings. The CCIR601 format refers to the sampling rate of 13.5 MHz. The SQ format for 60 Hz system refers to the sampling rate of 12.27 MHz, and the SQ format for 50 Hz system refers to the use of sampling rate of 14.75 MHz.

Scaling Ratio Format Total Resolution

Output Resolution

HSCALE values

VSCALE (frame)

1:1 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601

780x525 858x525 944x625 864x625

640x480 720x480 768x576 720x576

0x0100 0x0100 0x0100 0x0100

0x0100 0x0100 0x0100 0x0100

2:1 (CIF) NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601

390x262 429x262 472x312 432x312

320x240 360x240 384x288 360x288

0x0200 0x0200 0x0200 0x0200

0x0200 0x0200 0x0200 0x0200

4:1 (QCIF) NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601

195x131 214x131 236x156 216x156

160x120 180x120 192x144 180x144

0x0400 0x0400 0x0400 0x0400

0x0400 0x0400 0x0400 0x0400

Table 2. HSCALE and VSCALE value for some popular video formats.

TW9910


VBI Data Processing

Raw VBI data output

TW9910 supports raw VBI data output. Raw VBI data output has the same vertical line delay timing as video output. Horizontal output timing is also programmable by VBIDELAY register. Raw VBI data is generated during HACTIVE active period (from SAV to EAV) as Video data output. Total pixel number of raw VBI data per line is twice as many as HACTIVE register value. If VBI EN register is set to “1”, all vertical blanking output while VACTIVE is inactive will be raw VBI data output. If VVBI registers are set to more than “1”, the VVBI number lines from top video active lines will also be raw VBI data output lines.

VBI Data Slicer

The following VBI standards are supported by VBI Data slicer. The VBI Data slicing is controlled by the registers LCTL6 to LCTL26. Registers LCTL6 to LCTL26 are controlling the slicing process itself. LCTL6 to LCTL26 defines the Data Type to be decoded. The Data Type can be specified on a line by line basis for line6 to line26 and for even and odd field depending on the detected TV system standard. The setting for LCTL26 is valid for the rest of the corresponding field. Normally no text data 0H (video data) should be selected to render the VBI Data slicer inactive during active video. LCTRL26 is useful for Full-Field Teletext mode in the case of NABTS.

NABTS is 525 Teletext-C. Japan’s MOJI is 525 Teletext-D. Didon Antiope is 625 Teletext-A. VBI Data slicer supports up to Physical layer, Link layer in ITU-R BT.653-2. Japan’s EIAJ CPR-1204 shown as 525 WSS has the same physical layer protocol as that of CGMS.

The sliced VBI data is embedded in the ITU-R BT.656 output stream, using the intervals between the End of Active Video (EAV) and the Start of Active Vide(SAV) codes of each line and formatted according to ITU-R BT.1364 Ancillary data packet Type 2.

Table 3. VBI Standard. STANDARD TYPE TV Systems

(lines/freq) Bit Rate (Mbits/s)

Modulation Data Type

625 Teletext-B 625/50 6.9375 NRZ 1H 525 Teletext-B 525/60 5.727272 NRZ 1H 625 Teletext-C 625/50 5.734375 NRZ 2H 525 Teletext-C 525/60 5.727272 NRZ 2H 625 Teletext-D 625/50 5.6427875 NRZ 3H 525 Teletext-D 525/60 5.727272 NRZ 3H 625 CC 625/50 0.500 NRZ 4H 525 CC 525/60 0.503 NRZ 4H 625 WSS 626/50 5 Bi-phase 5H 525 WSS(CGMS) 525/60 0.447443 NRZ 5H 625 VITC 625/50 1.8125 NRZ 6H 525 VITC 525/60 1.7898 NRZ 6H Gemstar 2x 525/60 1.007 NRZ 7H Gemstar 1x 525/60 0.503 NRZ 8H VPS 625/50 5 Bi-phase 9H 625 Teletext-A 625/50 6.203125 NRZ AH

TW9910


Sliced VBI Data output format

After 4 bytes of EAV code, sliced VBI ANC data packets are generated by following format. Byte1 to Byte4N+7 data stream is formatted according to ITU-R BT.1364 ANC data packet type2. BC data byte is optional and not included in ANC data packet type 2 BC data byte is inserted after ANC data packet type2.

Table 4. Sliced VBI ANC data packet BYTE No.

D7 MSB

D6 D5 D4 D3 D2 D1 D0 LSB

DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary data flag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 NEP EP DC5 DC4 DC3 DC2 DC1 DC0 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 DT3 DT2 DT1 DT0 IDI2. UDW 2 9 Sliced VBI Data byte 1 Sliced VBI Data No.1. UDW3 10 Sliced VBI Data byte 2 Sliced VBI Data No.2. UDW4 11 Sliced VBI Data byte 3 Sliced VBI Data No.3 UDW5 12 Sliced VBI Data byte 4 Sliced VBI Data No.4. UDW6 13 Sliced VBI Data byte 5 Sliced VBI Data No.5. UDW7 . . . .

4N+6 Sliced VBI Data byte last or FILLDATA Sliced VBI Data Last or FILLDATA. UDW 4N4N+7 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 4N+8 OP 0 BC5 BC4 BC3 BC2 BC1 BC0 BC

1. EP is Even Parity of bits 5 to 0 in same 1 byte. 2. NEP is inverted EP in same 1 byte. 3. {DID4,DID3,DID2,DID1,DID0} is DID register value. 4. {SDID5,SDID4,SDID3,SDID2,SDID1,SDID0} is SDID register value. 5. {DC5,DC4,DC3,DC2,DC1,DC0} is the number of DOWRD data length from UDW1 to UDW4N.On this table,

{DC5,DC4,DC3,DC2,DC1,DC0} is N(decimal). 6. OP is Odd Parity of bits 6 to 0 in same 1 byte. 7. FID=0: odd field ; FID=1: even field. 8. {LN8,LN7,LN6,LN5,LN4,LN3,LN2,LN1,LN0} is the line number of current sliced VBI data. 9. {DT3,DT2,DT1,DT0} is the Data Type shown on Table 10. NCS6 is inverted CS6. 11. {CS6,CS5,CS4,CS3,CS2,CS1,CS0} is the checksum value calculated from DID to UDW4N. 12. UDW1 to UDW4N are the User data words(UDW) shown on ITU-R BT.1364 ANC data packet type 2. 13. [BC5,BC4,BC3,BC2,BC1,BC0] is the number of valid bytes from UDW1 to UDW4N. 14. FILLDATA is FILLDATA register value. FILLDATA is inserted after last valid bytes to make 4N number byte stream sometimes.

TW9910


Following shows various type of ANC data packet to be output

Table 5. Closed Captioning ANC data packet BYTE No.

D7 MSB


DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary data flag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 0 1 0 0 0 0 0 1 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 0 1 0 0 IDI2. UDW 2 9 1st Character byte UDW3 10 2nd Character byte UDW4 11 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 12 0 0 0 0 0 1 0 0 BC

Table 6. CGMS ANC data packet BYTE No.

D7 MSB


DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary dataflag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 0 1 0 0 0 0 1 0 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 0 1 0 1 IDI2. UDW 2 9 WSS[7:0] UDW3 10 WSS[15:8] UDW4 11 {0H,WSS[19:16]} UDW5 12 CRCERRORCODE UDW6 13 FILLDATA UDW7 14 FILLDATA UDW8 15 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 16 1 0 0 0 0 1 1 0 BC

1.CRCERRORCODE is optional byte. 41H means “this wss data has CRC Error”. 80H means no CRC error.

Table 7. 625 line Wide Screen signaling ANC data packet BYTE No.

D7 MSB


DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary dataflag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 0 1 0 0 0 0 0 1 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 0 1 0 1 IDI2. UDW 2 9 WSS[7:0] UDW3 10 {00b,WSS[13:8] UDW4 12 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 13 0 0 0 0 0 1 0 0 BC

TW9910


Table 8. 625 Teletext-A ANC data packet BYTE No.

D7 MSB


DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary dataflag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 0 1 0 0 1 0 1 1 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 1 0 1 0 IDI2. UDW 2 9 FRAME CDDE UDW3 10 BYTE4 UDW4 11 BYTE5 UDW5 . . . .

46 BYTE40 UDW40 47 HAMM84ERROR UDW41 48 FILLDATA UDW42 49 FILLDATA UDW43 50 FILLDATA UDW44 51 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 52 0 0 1 0 1 0 0 1 BC

1. FRAME CODE is E7H if it’s received correctly. 2. HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.

Table 9. 625 Teletext-B ANC data packet BYTE No.

D7 MSB


DESCRIPTION


50 BYTE44 UDW44 51 BYTE45 UDW45 52 HAMM84ERROR UDW46 53 FILLDATA UDW47 54 FILLDATA UDW48 55 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 56 1 0 1 0 1 1 1 0 BC

1.FRAME CODE is 27H if it’s received correctly. 2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.

TW9910


Table 10. 525 Teletext-B ANC data packet BYTE No.

D7 MSB


DESCRIPTION


30 BYTE36 UDW36 31 BYTE37 UDW37 32 HAMM84ERROR UDW38 33 FILLDATA UDW39 34 FILLDATA UDW40 35 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 36 1 0 1 0 0 1 1 0 BC

1.FRAME CODE is 27H if it’s received correctly. 2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.

Table 11. 625 Teletext-C and 525 Teletext-C ANC data packet BYTE No.

D7 MSB


DESCRIPTION


42 BYTE36 UDW36 43 HAMM84ERROR UDW37 44 FILLDATA UDW38 45 FILLDATA UDW39 46 FILLDATA UDW40 47 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 48 0 0 1 0 0 1 0 1 BC

1.FRAME CODE is E7H if it’s received correctly. 2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.

TW9910


Table 12. 625 Teletext-D and 525 Teletext-D ANC data packet BYTE No.

D7 MSB


DESCRIPTION


42 BYTE36 UDW36 43 BYTE37 UDW37 44 FILLDATA UDW38 45 FILLDATA UDW39 46 FILLDATA UDW40 47 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 48 0 0 1 0 0 1 0 1 BC

1.FRAME CODE is A7H if it’s received correctly.

Table 13. Line16 VPS ANC data packet BYTE No.

D7 MSB


DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary dataflag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 1 0 0 0 0 1 0 1 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 1 0 0 1 IDI2. UDW 2 9 START CDDE1(51H) UDW3 10 START CODE2(99H) UDW4 11 BYTE3 UDW5 . . . .

22 BYTE14 UDW16 23 BYTE15 UDW17 24 BI-PHASEERROR UDW18 25 FILLDATA UDW19 26 FILLDATA UDW20 27 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 28 1 0 0 1 0 0 1 0 BC

1.START CODE1 is the first byte of Start Code by 5Mbps slicing. 2.START CODE2 is the second byte of Start Code by 5Mbps slicing. 3. BYTE3~BYTE15 are data bytes by 5/2 Mbps Bi-phase slicing. 4. BI-PHASEEROOR is Bi-phase coding error detection.80H means No error.41H means Bi-phase coding error is detected.

TW9910


Table 14. VITC ANC data packet BYTE No.

D7 MSB


DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary dataflag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 1 0 0 0 0 0 1 1 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 0 1 1 0 IDI2. UDW 2 9 Bit[9:2] UDW3 10 Bit[19:12] UDW4 11 Bit[29:22] UDW5 12 .Bit[39:32] UDW6 13 .Bit[49:42] UDW7 14 Bit[59:52] UDW8 15 Bit[69:62] UDW9 16 Bit[79:72] UDW10 17 Bit[89:82] UDW11 18 CRCERROR UDW12 19 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 20 1 0 0 0 1 1 0 0 BC

1.CRCERROR is CRC Error information.41H means CRC Error is deteced.80H means no CRC error.

Table 15. Gemstar 1X ANC data packet BYTE No.

D7 MSB


DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary dataflag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 0 1 0 0 0 0 0 1 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 1 0 0 0 IDI2. UDW 2 9 1st Character byte UDW3 10 2 nd Character byte UDW4 11 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 12 0 0 0 0 0 1 0 0 BC

Table 16. Gemstar 2X ANC data packet BYTE No.

D7 MSB


DESCRIPTION

1 0 0 0 0 0 0 0 0 Ancillary dataflag 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 NEP EP 0 DID4 DID3 DID2 DID1 DID0 DID 5 NEP EP SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 SDID 6 0 1 0 0 0 0 1 0 DC 7 OP FID LN8 LN7 LN6 LN5 LN4 LN3 IDI1. UDW1 8 OP LN2 LN1 LN0 0 1 1 1 IDI2. UDW 2 9 FRAMECODE1 UDW3 10 FRAMECODE2 UDW4 11 Data Byte 1 UDW5 12 Data Byte 2 UDW6 13 Data Byte 3 UDW7 14 Data Byte 4 UDW8 15 NCS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS 16 0 0 0 0 1 0 0 0 BC

1. FRAMCODE1 is B9H if Frame Code is correctly received. 2. FRAMCODE2 is 05H if Frame Code is correctly received.

TW9910


Two Wire Serial Bus Interface

Figure 2. Definition of the serial bus interface bus start and stop

Figure 3. One complete register read sequence via the serial bus interface

Figure 4. One complete register write sequence via the serial bus interface

The two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the TW9910 registers. SCLK is the serial

SDA

Start Condition Stop Condition

SCL

SCLK

Device ID (1-7) R/W Index (1-8) Data (1-8)

SDAT

Start Condition

Stop Condition

AckAck Ack

Re-start Condition

SCLK

Device ID (1-7) R/W Index (1-8)SDAT

Ack Ack

Data (1-8)

Stop Condition Nack

Start Condition

Device ID (1-7) R/W

Ack

TW9910


clock and SDAT is the data line. Both lines are pulled high by resistors connected to VDD. ICs communicate on the bus by pulling SCLK and SDAT low through open drain outputs. In normal operation the master generates all clock pulses, but control of the SDAT line alternates back and forth between the master and the slave. For both read and write, each byte is transferred MSB first, and the data bit is valid whenever SCLK is high.

The TW9910 is operated as a bus slave device. It can be programmed to respond to one of two 7-bit slave device addresses by tying the SIAD (Serial Interface ADdress) pin ether to VDD or VSS (See Table 17) through a pullup or pulldown resister. The SIAD pin is multi-purpose pin and must not tied to VDD or VSS directly. If the SIAD pin is tied to VDD, then the least significant bit of the 7-bit address is a “1”. If the SIAD pin is tied to VSS then the least significant bit of the 7-bit address is a “0”. The most significant 6-bits are fixed. The 7-bit address field is concatenated with the read/write control bit to form the first byte transferred during a new transfer. If the read/write control bit is high the next byte will be read from the slave device. If it is low the next byte will be a write to the slave. When a bus master (the host microprocessor) drives SDA from high to low, while SCL is high, this is defined to be a start condition (See Figure 2.). All slaves on the bus listen to determine when a start condition has been asserted.

After a start condition, all slave devices listen for the their device addresses. The host then sends a byte consisting of the 7-bit slave device ID and the R/W bit. This is shown in Figure 3. (For the TW9910, the next byte is normally the index to the TW9910 registers and is a write to the TW9910 therefore the first R/W bit is normally low.)

After transmitting the device address and the R/W bit, the master must release the SDAT line while holding SCLK low, and wait for an acknowledgement from the slave. If the address matches the device address of a slave, the slave will respond by driving the SDAT line low to acknowledge the condition. The master will then continue with the next 8-bit transfer. If no device on the bus responds, the master transmits a stop condition and ends the cycle. Notice that a successful transfer always includes nine clock pulses.

To write to the internal register of theTW9910, the master sends another 8-bits of data, the TW9910 loads this to the register pointed by the internal index register. The TW9910 will acknowledge the 8-bit data transfer and automatically increment the index in preparation for the next data. The master can do multiple writes to the TW9910 if they are in ascending sequential order. After each 8-bit transfer the TW9910 will acknowledge the receipt of the 8-bits with an acknowledge pulse. To end all transfers to the TW9910 the host will issue a stop condition.

Serial Bus Interface 7-bit Slave Address Read/Write bit

1 0 0 0 1 0 SIAD0 1=Read 0=Write

Table 17 TW9910 serial bus interface 7-bit slave address and read write bit

A TW9910 read cycle has two phases. The first phase is a write to the internal index register. The second phase is the read from the data register. (See figure 3). The host initiates the first phase by sending the start condition. It then sends the slave device ID together with a 0 in the R/W bit position. The index is then sent followed by either a stop condition or a second start condition. The second phase starts with the second start condition. The master then resends the same slave device ID with a 1 in the R/W bit position to indicate a read. The slave will transfer the contents of the desired register. The master remains in control of the clock. After transferring eight bits, the slave releases and the master takes control of the SDAT line and

TW9910


acknowledges the receipt of data to the slave. To terminate the last transfer the master will issue a negative acknowledge (SDAT is left high during a clock pulse) and issue a stop condition.

Test Modes

The input pin TMODE combining with RESET# provide different test modes selection. If this pin is low at the rising edge of the RESET# pin and remaining low afterwards, TW9910 is in the normal operating mode. Other test modes can be obtained as shown in Table 18.

Table 18. Test mode selection and description Test mode TMODE

before RESET#

rising edge

TMODE after

RESET# rising edge

Description

Normal 0 0 Normal operation mode.

Pin tri-state 0 1 In this mode, all pin output drivers are tri-stated. Pin leakage current parameters can be measured.

Outputs high 1 0 In this mode, all pin output drivers are forced to the high output state. Pin output high voltage, VOH and IOH, can be measured.

Outputs low 1 1 In this mode, all pin output drivers are forced to the low output state. Pin output low voltage, VOL and IOL, can be measured.

TW9910


Filter Curves

Decimation filter

Chroma Band Pass Filter Curves

0 2 4 6 8 10 12

x 106

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

Frequency (Hertz)

Mag

nitu

de R

espo

nse

(dB

)

0 1 2 3 4 5 6 7 8 9

x 106

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

Frequency (Hertz)

Mag

nitu

de R

espo

nse

(dB

)

NTSC

PAL/SECAM

TW9910


Luma Notch Filter Curve for NTSC and PAL/SECAM

Chrominance Low-Pass Filter Curve

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 106

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

Frequency (Hertz)

Mag

nitu

de R

espo

nse

(dB

)

NTSC

PAL/SECAM

Low

Med

High

0 1 2 3 4 5 6 7 8 9

x 106

-80

-70

-60

-50

-40

-30

-20

-10

0

Frequency (Hertz)

Mag

nitu

de R

espo

nse

(dB

)

TW9910


Horizontal Scaler Pre- Filter curves

Vertical Interpolation Filter curves

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-40

-35

-30

-25

-20

-15

-10

-5

0

Fsig/Fsample

Mag

nitu

de R

espo

nse

(dB

) HFLT[1:0]=1

HFLT[1:0]=2

HFLT[1:0]=3

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-30

-25

-20

-15

-10

-5

0

Fv / Line Rate

Mag

nitu

de R

espo

nse

(dB

)

TW9910


Peaking Filter Curves

NTSC

PAL

0 1 2 3 4 5 6 7

x 106

0

2

4

6

8

10

12

14

16

Frequency (Hertz)

Mag

nitu

de R

espo

nse

(dB

)

0 1 2 3 4 5 6 7 8 9

x 106

0

2

4

6

8

10

12

14

16

Frequency (Hertz)

Mag

nitu

de R

espo

nse

(dB

)

TW9910


Control Register

TW9910 Register SUMMARY

Index (HEX)

7 6 5 4 3 2 1 0 Reset (hex)

00 ID REV 50 01 VDLOSS HLOCK SLOCK FIELD VLOCK - MONO DET50 00 02 YSEL2 FC27 IFSEL YSEL CSEL SEL 40 03 MODE LEN LLCMODE AINC VSCTL OEN TRI_SEL 04 04 GMEN GAMMA HSDLY 00 05 VSP VSSL HSP HSSL 00 06 SRESET IREF VREF AGC_EN CLKPDN Y_PDN C_PDN - 00 07 VDELAY_HI VACTIVE_HI HDELAY_HI HACTIVE_HI 02 08 VDELAY_LO 12 09 VACTIVE_LO F0 0A HDELAY_LO 0F 0B HACTIVE_LO D0 0C PBW DEM PALSW SET7 COMB HCOMP YCOMB PDLY CD 0D VSCALE_LO 00 0E VSCALE_HI HSCALE_HI 11 0F HSCALE_LO 00 10 BRIGHTNESS 00 11 CONTRAST 5C 12 SCURVE VSF CTI SHARPNESS 51 13 SAT_U 80 14 SAT_V 80 15 HUE 00 16 - - 53 17 SHCOR - VSHP 80 18 CTCOR CCOR VCOR CIF 44 19 VBI_EN VBI_BYT VBI_FRAM HA_EN CTL656 RTSEL 58 1A LLCTEST PLL_PDN - - YFLEN YSV CFLEN CSV 00 1B CK2S CK1S - - 00 1C DTSTUS STDNOW ATREG STANDARD 07 1D START PAL60 PALCN PALM NTSC4 SECAM PALB NTSC 7F 1E - CVSTD CVFMT 08 1F TEST 00

TW9910


Index (HEX)

7 6 5 4 3 2 1 0 Reset (hex)

20 CLPEND CLPST 50 21 NMGAIN WPGAIN Agcgain8 22 22 AGCGAIN[7:0] F0 23 PEAKWT F8 24 CLMPLD CLMPL 3C 25 SYNCTD SYNCT 38 26 MISSCNT HSWIN 84 27 PCLAMP 28 28 VLCKI VLCKO VMODE DETV AFLD VINT 00 29 BSHT VSHT 00 2A CKILMAX CKILMIN 78 2B HTL VTL 44 2C CKLM YDLY EVCNT HFLT 30 2D - - PALC SDET TBC_EN BYPASS SYOUT HADV 14 2E HPM ACCT SPM CBW A5 2F NKILL PKILL SKILL CBAL FCS LCS CCS BST E0 30 sf pf ff kf CSBAD MCVSN CSTRIPE CTYPE 00 31 - WKAIR WKAIR1 VSTD NINTL WSSDET EDSDET CCDET 00 32 HFREF X 33 FRM YNR CLMD PSP 05 34 IDX NSEN / SSEN / PSEN / WKTH 1E 35 CTEST YCLEN CCLEN VCLEN GTEST VLPF CKLY CKLC 00 36 - 37 - 38 - 39 - 3A - 3B - 3C - 3D - 3E - 3F - 40 - 41 - 42 - - 43 - 44 - 45 - - 46 - - 47 - - 48 - - - - - - - 4E 4F WSS[19:14] X

TW9910


Index (HEX)

7 6 5 4 3 2 1 0 Reset (hex)

50 FILLDATA A0 51 NODAEN SYRM SDID 22 52 ANCEN TOUTHA VIPCFG DID 31 53 CRCERR WSSFLD WSS[13:8] X 54 WSS[7:0] X 55 HA656 EAVSWAP HAMM84 NTSC656 VVBI 00 56 LCTL6 00 57 LCTL7 00 58 LCTL8 00 59 LCTL9 00 5A LCTL10 00 5B LCTL11 00 5C LCTL12 00 5D LCTL13 00 5E LCTL14 00 5F LCTL15 00 60 LCTL16 00 61 LCTL17 00 62 LCTL18 00 63 LCTL19 00 64 LCTL20 00 65 LCTL21 00 66 LCTL22 00 67 LCTL23 00 68 LCTL24 00 69 LCTL25 00 6A LCTL26 00 6B HSBEGIN 2C 6C HSEND 60 6D OVSDLY 00 6E HSPIN OFDLY VSMODE OVSEND 20 6F PDNSVBI VBIDELAY 24

TW9910


0x00 – Product ID Code Register (ID)

Bit Function R/W Description Reset

7-3 ID R The TW9910 Product ID code is 01010 . A

2-0 Revision R The revision number. 0

0x01 – Chip Status Register I (STATUS1)


7 VDLOSS R 1 = Video not present. (sync is not detected in number of consecutive line periods specified by Misscnt register)

0 = Video detected.

0

6 HLOCK R 1 = Horizontal sync PLL is locked to the incoming video source.

0 = Horizontal sync PLL is not locked. 0

5 SLOCK R 1 = Sub-carrier PLL is locked to the incoming video source.

0 = Sub-carrier PLL is not locked. 0

4 FIELD R 0 = Odd field is being decoded.

1 = Even field is being decoded. 0

3 VLOCK R 1 = Vertical logic is locked to the incoming video source.

0 = Vertical logic is not locked. 0

2 Reserved 0

1 MONO R 1 = No color burst signal detected.

0 = Color burst signal detected. 0

0 DET50 R 0 = 60Hz source detected

1 = 50Hz source detected

The actual vertical scanning frequency depends on the current standard invoked.

0

TW9910


0x02 – Input Format (INFORM)


7 YSEL2 R/W See YSEL 0

6 FC27 R/W 1 = Input crystal clock frequency is 27MHz.

0 = Square pixel mode. Must use 24.54MHz for 60Hz field rate source or 29.5MHz for 50Hz field rate source.

1

5-4 IFSEL R/W 01 = S-video decoding

00 = Composite video decoding 0

3-2 YSEL R/W YSEL2 together with these two bits control the Y input video selection.

000 = Mux0 selected

001 = Mux1 selected

010 = Mux2 selected

011 = Mux3 selected

100-111 = Invalid

0

1 CSEL R/W Reserved 0

0 R/W Reserved 0

TW9910


0x03 – Output Format Control Register (OPFORM)


7 MODE R/W 0 = CCIR601 compatible YCrCb 4:2:2 format with separate syncs and flags.

1 = ITU-R-656 compatible data sequence format.

0

6 LEN R/W 0 = 8-bit YCrCb 4:2:2 output format.

1 = 16-bit YCrCb 4:2:2 output format. 0

5 LLCMODE R/W 1 = LLC output mode. 0 = free-run output mode 0

4 AINC R/W Serial interface indexing control

0 = auto-increment 1 = non-auto 0

3 VSCTL R/W 1 = Vertical scale-downed output controlled by DVALID only.

0 = Vertical scale-downed output controlled by both HACTIVE and DVALID.

0

2 OEN R/W 0 = Enable outputs.

1 = Tri-state outputs defined by Tri-state select bits of this register. 1

1-0 TRI_SEL R/W These bits select the outputs to be tri-stated when the OEN bit is asserted high. There are three major groups that can be independently tri-stated: timing group (HS, VS, DVALID, MPOUT, FLD), data group (VD[15:0]), and clock (CLKX2/CLKX1) according to following definition.

00 = Timing and data group only.

01 = Data group only.

10 = All three groups.

11 = Clock and data group only.

0

0x04 – GAMMA and HSYNC Delay Control


7 GMEN R/W Luminance Gamma. 1 = enable, 0 = disable. 0

6-5 GAMMA R/W These bits select the Luminance Gamma Curve. 0

4-0 HSDLY R/W Reserved for test. 0

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0x05 – Output Control I


7 VSP R/W 0 = VS pin output polarity is active high

1 = VS pin output polarity is active low. 0

6-4 VSSL R/W VS pin output control

0 = VSYNC

1 = VACT

2 = FIELD

3 = VVALID

4 - 7 = Reserved

0

3 HSP R/W 0 = HS pin output polarity is active high

1 = HS pin output polarity is active low. 0

2-0 HSSL R/W HS pin output control

0 = HACT

1 = HSYNC

2 = DVALID

3 = Hlock

4 = Asyncw

5 - 7 = Reserved

0

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0x06 – Analog Control Register (ACNTL)


7 SRESET W An 1 written to this bit resets the device to its default state but all register content remain unchanged. This bit is self-resetting.

0

6 IREF R/W 0 = Internal current reference 1.

1 = Internal current reference 2. 0

5 VREF R/W 1 = Internal voltage reference.

0 = external voltage reference using VCOM, VREFP and VREFN. 0

4 AGC_EN R/W 0 = AGC loop function enabled.

1 = AGC loop function disabled. Gain is set to by AGCGAIN. 0

3 CLK_PDN R/W 0 = Normal clock operation.

1 = System clock in power down mode, but the MPU INTERFACE module and output clocks (CLKX1 and CLKX2) are still active.

0

2 Y_PDN R/W 0 = Luma ADC in normal operation.

1 = Luma ADC in power down mode. 0

1 C_PDN R/W 0 = Chroma ADC in normal operation.

1 = Chroma ADC in power down mode. 0

0 R/W Reserved for future use 0

0x07 – Cropping Register, High (CROP_HI)


7-6 VDELAY_HI

R/W These bits are bit 9 to 8 of the 10-bit Vertical Delay register. 0

5-4 VACTIVE_HI

R/W These bits are bit 9 to 8 of the 10-bit VACTIVE register. Refer to description on Reg09 for its shadow register.

0

3-2 HDELAY_HI

R/W These bits are bit 9 to 8 of the 10-bit Horizontal Delay register. 0

1-0 HACTIVE_HI

R/W These bits are bit 9 to 8 of the 10-bit HACTIVE register. 2

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0x08 – Vertical Delay Register, Low (VDELAY_LO)


7-0 VDELAY_LO

R/W These bits are bit 7 to 0 of the 10-bit Vertical Delay register. The two MSBs are in the CROP_HI register. It defines the number of lines between the leading edge of VSYNC and the start of the active video.

12

0x09 – Vertical Active Register, Low (VACTIVE_LO)


7-0 VACTIVE_LO

R/W These bits are bit 7 to 0 of the 10-bit Vertical Active register. The two MSBs are in the CROP_HI register. It defines the number of active video lines per frame output.

The VACTIVE register has a shadow register for use with 50Hz source when Atreg of Reg0x1C is not set. This register can be accessed through the same index address by first changing the format standard to any 50Hz standard.

F0

0x0A – Horizontal Delay Register, Low (HDELAY_LO)


7-0 HDELAY_LO

R/W These bits are bit 7 to 0 of the 10-bit Horizontal Delay register. The two MSBs are in the CROP_HI register. It defines the number of pixels between the leading edge of the HSYNC and the start of the image cropping for active video.

The HDELAY_LO register has two shadow registers for use with PAL and SECAM sources respectively. These register can be accessed using the same index address by first changing the decoding format to the corresponding standard.

0F

0x0B – Horizontal Active Register, Low (HACTIVE_LO)


7-0 HACTIVE_LO

R/W These bits are bit 7 to 0 of the 10-bit Horizontal Active register. The two MSBs are in the CROP_HI register. It defines the number of active pixels per line output.

D0

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0x0C – Control Register I (CNTRL1)


7 PBW R/W 1 = Wide Chroma BPF BW

0 = Normal Chroma BPF BW 1

6 DEM R/W Secam control

1 = reduction 0 = normal 1

5 PALSW R/W 1 = PAL switch sensitivity low.

0 = PAL switch sensitivity normal. 0

4 SET7 R/W 1 = The black level is 7.5 IRE above the blank level.

0 = The black level is the same as the blank level. 0

3 COMB R/W 1 = Adaptive comb filter on for NTSC

0 = Notch filter 1

2 HCOMP R/W 1 = operation mode 1. (recommended)

0 = mode 0. 1

1 YCOMB R/W This bit controls the Y comb.

1 = Y output is the averaging of two adjacent lines.

0 = No comb.

0

0 PDLY R/W PAL delay line.

1 = enabled. 0 = disabled. 1

0x0D – Vertical Scaling Register, Low (VSCALE_LO)


7-0 VSCALE_LO

R/W These bits are bit 7 to 0 of the 12-bit vertical scaling ratio register 00h

0x0E – Scaling Register, High (SCALE_HI)


7-4 VSCALE_HI

R/W These bits are bit 11 to 8 of the 12-bit vertical scaling ratio register. 1

3-0 HSCALE_HI

R/W These bits are bit 11 to 8 of the 12-bit horizontal scaling ratio register.

1

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0x0F – Horizontal Scaling Register, Low (HSCALE_LO)


7-0 HSCALE_LO

R/W These bits are bit 7 to 0 of the 12-bit horizontal scaling ratio register.

00

0x10 – BRIGHTNESS Control Register (BRIGHT)


7-0 BRIGHT R/W These bits control the brightness. They have value of –128 to 127 in 2’s complement form. Positive value increases brightness. A value 0 has no effect on the data.

00

0x11 – CONTRAST Control Register (CONTRAST)


7-0 CNTRST R/W These bits control the contrast. They have value of 0 to 3.98 (FFh). A value of 1 (‘100_0000‘) has no effect on the video data.

5C

0x12 – SHARPNESS Control Register I (SHARPNESS)


7 SCURVE R/W This bit controls the sharpness filter center frequency.

0 = Normal 1 = High 0

6 VSF R/W This bit is for internal used. 1

5-4 CTI R/W CTI level selection. 0 = lowest. 3 = hightest. 1

3-0 SHARP R/W These bits control the amount of sharpness enhancement on the luminance signals. There are 16 levels of control with ‘0’ having no effect on the output image. 1 through 7 provides sharpness enhancement with ‘7’ being the strongest. Value 8 through 15 are provided for noise reduction purpose.

1

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0x13 – Chroma (U) Gain Register (SAT_U)


7-0 SAT_U R/W These bits control the digital gain adjustment to the U (or Cb) component of the digital video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is 0 to 200%.

80

0x14 – Chroma (V) Gain Register (SAT_V)


7-0 SAT_V R/W These bits control the digital gain adjustment to the V (or Cr) component of the digital video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is 0 to 200%.

80

0x15 – Hue Control Register (HUE)


7-0 HUE R/W These bits control the color hue as 2’s complement number. They have value from +36o (7Fh) to -36o (80h) with an increment of 0.28o. The positive value gives greenish tone and negative value gives purplish tone. The default value is 0o (00h). This is effective only on NTSC system.

00

0x16 – Sharpness Control II (SHARP2)


7-4 R/W Reserved for future use. 5

3-0 R/W Reserved for future use. 3

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0x17 – Vertical Sharpness (VSHARP)


7-4 SHCOR R/W These bits provide coring function for the sharpness control. 8

3 Reserved 0

2-0 VSHP R/W Vertical peaking level. 0 = none. 7 = highest. 0

0x18 – Coring Control Register (CORING)


7-6 CTCOR R/W These bits control the coring for CTI. 1

5-4 CCOR R/W These bits control the low level coring function for the Cb/Cr output. 0

3-2 VCOR R/W These bits control the coring function of vertical peaking. 1

1-0 CIF R/W These bits control the IF compensation level.

0 = None 1 = 1.5dB 2 = 3dB 3 = 6dB 0

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0x19 – VBI Control Register (VBICNTL)


7 VBI_EN R/W 0 = VBI capture disabled.

1 = VBI capture enabled. 0

6 VBI Byte Order

R/W If LEN(Reg0x03[6]) is “1”

0 = Pixel 1, 3, 5 … on the VD[15:8] data bus, and pixel 2, 4, 6, … on the VD[7:0] data bus.

1 = Pixel 1, 3, 5, … on the VD[7:0] data bus, and pixel 2, 4, 6, … on the VD[15:8] data bus.

If LEN is “0”

0 = Pixel 2,1,4,3,6,5,…. on the VD[15:8] data bus.

1 = Pixel 1,2,3,4,5,6,…. on the VD[15:8] data bus.

1

5 VBI_ FRAM

R/W 0 = Normal mode

1 = ADC output mode

VD[15:8] is Y-ADC data,VD[7:0] pin is C-YADC data

0

4 HA_EN R/W 0 = HACTIVE output is disabled during vertical blanking period.

1 = HACTIVE output is enabled during vertical blanking period. 1

3 CNTL656 R/W 0 = 0x80 and 0x10 code will be output as invalid data during active video line.

1 = 0x00 code will be output as invalid data during active video line.

1

2-0 RTSEL R/W These bits control the real time signal output from the MPOUT pin.

000 = Video loss

001 = H-lock

010 = S-lock

011 = V-lock

100 = MONO

101 = Det50

110 = FIELD

111 = RTCO

0

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0x1A – Analog Control II


7 LLCTEST R/W LLC test mode 0

6 PLL_PDN R/W 0 = LLC PLL in normal operation.

1 = PLL in power down mode. 0

5-4 Reserved 0

3 YFLEN R/W Y-Ch anti-alias filter control

1 = enable 0 = disable 0

2 YSV R/W Y-Ch power saving mode


1 CFLEN R/W C-Ch anti-alias filter control


0 CSV R/W C-Ch power saving mode


0x1B – Output Control II


7-6 CK2S R/W CLKX2 pin output control. CK1S[0] together with these two bits (CK1S[0], CK2S) control CLKX2 pin output selection.

000 = VCLK

001 = CLKX1

010 = CLKX2

011 = LLCK

100 = LLCK2

101 = LLCK4

0

5-4 CK1S R/W See CK2S 0

3 R/W Reserved 0

2-0 R/W Reserved 0

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0x1C – Standard Selection (SDT)


7 DETSTUS R 0 = Idle 1 = detection in progress 0

6-4 STDNOW R Current standard invoked

0 = NTSC(M)

1 = PAL (B,D,G,H,I)

2 = SECAM

3 = NTSC4.43

4 = PAL (M)

5 = PAL (CN)

6 = PAL 60

7 = Not valid

0

3 ATREG R/W 1 = Disable the shadow registers.

0 = Enable VACTIVE and HDELAY shadow registers value depending on standard

0

2-0 STD R/W Standard selection

0 = NTSC(M)

1 = PAL (B,D,G,H,I)

2 = SECAM

3 = NTSC4.43

4 = PAL (M)

5 = PAL (CN)

6 = PAL 60

7 = Auto detection

7

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0x1D – Standard Recognition (SDTR)


7 ATSTART R/W Writing 1 to this bit will manually initiate the auto format detection process. This bit is a self-resetting bit.

0

6 PAL6_EN R/W 1 = enable recognition of PAL60.

0 = disable recognition. 1

5 PALN_EN R/W 1 = enable recognition of PAL (CN).


4 PALM_EN R/W 1 = enable recognition of PAL (M).


3 NT44_EN R/W 1 = enable recognition of NTSC 4.43.


2 SEC_EN R/W 1 = enable recognition of SECAM.


1 PALB_EN R/W 1 = enable recognition of PAL (B,D,G,H,I).


0 NTSC_EN R/W 1 = enable recognition of NTSC (M).


0x1E – Component Video Format (CVFMT)


7 R Reserved 0

6-4 CVSTD R Component video input format detection.

0 = 480i,

1 = 576i,

2 = 480p,

3 = 576p

0

3-0 CVFMT R/W Component video format selection.

0 = 480i,

1 = 576i,

2 = 480p,

3 = 576p,

8 = Auto

8

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0x1F – Test Control Register (TEST)


7-0 TEST R/W This register is reserved for testing purpose. In normal operation, only 0 should be written into this register.

1 = Analog test mode. Y and C channel portion of the device can be tested in this mode. The Y channel ADC output can be obtained from VD[15-8]. The C channel ADC output can be obtained from VD[7-0].

2 = Clamp test mode. Clamp control YU, YUX, YD, YDX, CU, CUX, CD, and CDX are mapped to VD[3-0].

3 = Reserved

4 = Digital test mode1. This is the CVBS test mode. The 8-bit input corresponds to VD[7-0] in the order of bit 7 to 0.

5 = Digital test mode 2. This is the Y/C test mode. Y input is defined by test mode 1. The C channel data is inputted from VD[7-0]. In this mode, only 8/10-bit output format is allowed.

6 = Reserved

7 = Reserved

8 = Reserved

9 = Sync output mode. The 6-bit Sync output corresponds to VD[5-0] in the order of bit 5 to 0. Y and Cb/Cr outputs correspond to VD[15-8] in 422 format

0

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0x20 – Clamping Gain (CLMPG)


7-4 CLPEND R/W These 4 bits set the end time of the clamping pulse in the increment of 8 system clocks. The clamping time is determined by this together with CLPST.

5

3-0 CLPST R/W These 4 bits set the start time of the clamping pulse in the increment of 8 system clocks. It is referenced to PCLAMP position.

0

0x21 – Individual AGC Gain (IAGC)


7-4 NMGAIN R/W These bits control the normal AGC loop maximum correction value.

2

3-1 WPGAIN R/W Peak AGC loop gain control. 1

0 AGCGAIN8

R/W This bit is the MSB of the 9-bit register that controls the AGC gain when AGC loop is disabled.

0

0x22 – AGC Gain (AGCGAIN)


7-0 AGCGAIN R/W These bits are the lower 8 bits of the 9-bit register that controls the AGC gain when AGC loop is disabled.

F0

0x23 – White Peak Threshold (PEAKWT)


7-0 PEAKWT R/W These bits control the white peak detection threshold. This function can be disabled by setting ‘FF’.

F8

0x24– Clamp level (CLMPL)


7 CLMPLD R/W 0 = Clamping level is set by CLMPL.

1 = Clamping level preset at 60d. 0

6-0 CLMPL R/W These bits determine the clamping level of the Y channel. 3C

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0x25– Sync Amplitude (SYNCT)


7 SYNCTD R/W 0 = Reference sync amplitude is set by SYNCT.

1 = Reference sync amplitude is preset to 38h. 0

6-0 SYNCT R/W These bits determine the standard sync pulse amplitude for AGC reference.

38

0x26 – Sync Miss Count Register (MISSCNT)


7-4 MISSCNT R/W These bits set the threshold for horizontal sync miss count threshold.

8

3-0 HSWIN R/W These bits determine the Hsync detection window. 4

0x27 – Clamp Position Register (PCLAMP)


7-0 PCLAMP R/W These bits set the clamping position from the PLL sync edge 28

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0x28 – Vertical Control I (VCNTL1)


7-6 VLCKI R/W Vertical lock in time.

0 = fastest 3 = slowest. 0

5-4 VLCKO R/W Vertical lock out time.

0 = fastest 3 = slowest. 0

3 VMODE R/W This bit controls the vertical detection window.

1 = search mode.

0 = vertical count down mode.

0

2 DETV R/W 1 = recommended for special application only.

0 = Normal Vsync logic 0

1 AFLD R/W Auto field generation control

0 = Off 1 = On 0

0 VINT R/W Vertical integration time control.

1 = long 0 = normal 0

0x29 – Vertical Control II (VCNTL2)


7-5 BSHT R/W Burst PLL center frequency control. 0

5-0 VSHT R/W Vsync output delay control in the increment of half line length. 00

0x2A – Color Killer Level Control (CKILL)


7-6 CKILMAX R/W These bits control the amount of color killer hysteresis. The hysteresis amount is proportional to the value.

1

5-0 CKILMIN R/W These bits control the color killer threshold. Larger value gives lower killer level.

28

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0x2B – Comb Filter Control (COMB)


7-4 HTL R/W Adaptive Comb filter control. 4

3-0 VTL R/W Adaptive Comb filter combing strength control. Higher value provides stronger comb filtering.

4

0x2C – Luma Delay and H Filter Control (LDLY)


7 CKLM R/W Color Killer mode.

0 = normal 1 = fast ( for special application) 0

6-4 YDLY R/W Luma delay fine adjustment. This 2’s complement number provide –4 to +3 unit delay control.

3

3 EVCNT R/W 1 = Even field counter in special mode.

0 = Normal operation 0

2-0 HFLT R/W Pre-filter selection for horizontal scaler

1** = Bypass

000 = Auto selection based on Horizontal scaling ratio.

001 = Recommended for CIF size image

010 = Recommended for QCIF size image

011 = Recommended for ICON size image

0

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0x2D – Miscellaneous Control I (MISC1)


6 R/W Reserved for future use. 0

5 PALC R/W Reserved for future use. 0

4 SDET R/W ID detection sensitivity. A ‘1’ is recommended. 1

3 TBC_EN R/W 1:TBC enable in freerun clock mode0:Disable 0

2 BYPASS R/W 1

1 SYOUT R/W 1 = Hsync output is disabled when video loss is detected

0 = Hsync output is always enabled 0

0 HADV R/W This bit advances the HACTIVE and DVALID pin output by one data clock when set.

0

0x2E – LOOP Control Register (LOOP)


7-6 HPM R/W Horizontal PLL acquisition time.

3 = Fast 2 = Auto 1 1 = Auto2 0 = Slow 2

5-4 ACCT R/W ACC time constant

0 = No ACC 1 = slow 2 = medium 3 = fast 2

3-2 SPM R/W Burst PLL control.

0 = Slowest 1 = Slow 2 = Fast 3 = Fastest 1

1-0 CBW R/W Chroma low pass filter bandwidth control.

Refer to filter curves. 1

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0x2F – Miscellaneous Control II (MISC2)


7 NKILL R/W 1 = Enable noisy signal color killer function in NTSC mode.

0 = Disabled. 1

6 PKILL R/W 1 = Enable automatic noisy color killer function in PAL mode.

0 = Disabled. 1

5 SKILL R/W 1 = Enable automatic noisy color killer function in SECAM mode.

0 = Disabled. 1

4 CBAL R/W 0 = Normal output

1 = special output mode. 0

3 FCS R/W 1 = Force decoder output value determined by CCS.

0 = Disabled. 0

2 LCS R/W 1 = Enable pre-determined output value indicated by CCS when video loss is detected.

0 = Disabled.

0

1 CCS R/W When FCS is set high or video loss condition is detected when LCS is set high, one of two colors display can be selected.

1 = Blue color.

0 = Black.

0

0 BST R/W 1 = Enable blue stretch.

0 = Disabled. 0

TW9910


0x30 – Macrovision Detection (MVSN)


7 SF R 0

6 PF R 0

5 FF R 0

4 KF R 0

3 CSBAD R 1 = Macrovision color stripe detection may be un-reliable 0

2 MCVSN R 1 = Macrovision AGC pulse detected.

0 = Not detected. 0

1 CSTRIPE R 1 = Macrovision color stripe protection burst detected.

0 = Not detected. 0

0 CTYPE R This bit is valid only when color stripe protection is detected, i.e. Cstripe=1.

1 = Type 2 color stripe protection

0 = Type 3 color stripe protection

0

0x31 – Chip STATUS II (STATUS2)


6 WKAIR R 1 = Weak signal 0 = Nomal 0

5 WKAIR1 R weak signal indicator 0

4 VSTD R 1 = Standard signal 0 = Non-standard signal 0

3 NINTL R 1 = Non-interlaced signal 0 = interlaced signal 0

2 WSSDET R 1 = WSS data detected. 0 = Not detected. 0

1 EDSDET R 1 = EDS data detected. 0 = Not detected. 0

0 CCDET R 1 = CC data detected. 0 = Not detected. 0

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0x32 – H monitor (HFREF)


7-0 HFREF R Horizontal line frequency indicator X

0x33 – CLAMP MODE (CLMD)


7-6 FRM R/W Free run mode control

0 = Auto 2 = default to 60Hz 3 = default to 50Hz 0

5-4 YNR R/W Y HF noise reduction

0 = None 1 = smallest 2 = small 3 = medium 0

3-2 CLMD R/W Clamping mode control.

0 = Sync top 1 = Auto 2 = Pedestal 3 = N/A 1

1-0 PSP R/W Slice level control

0 = low 1 = medium 2 = high 1

0x34 – ID Detection Control (IDCNTL)


7-6 IDX R/W These two bits indicates which of the four lower 6-bit registers is currently be controlled. The write sequence is a two steps process unless the same register is written. A write of {ID,000000} selects one of the four registers to be written. A subsequent write will actually write into the register.

0

5-0 NSEN / SSEN / PSEN / WKTH

R/W IDX = 0 controls the NTSC ID detection sensitivity (NSEN).

IDX = 1 controls the SECAM ID detection sensitivity (SSEN).

IDX = 2 controls the PAL ID detection sensitivity (PSEN).

IDX = 3 controls the weak signal detection sensitivity (WKTH).

1E / 18 / 1C / 21

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0x35 – Clamp Control I (CLCNTL1)


7 CTEST R/W Clamping control for debugging use. 0

6 YCLEN R/W 1 = Y channel clamp disabled

0 = Enabled. 0

5 CCLEN R/W 1 = C channel clamp disabled

0 = Enabled. 0

4 VCLEN R/W Reserved 0

3 GTEST R/W 1 = Test.

0 = Normal operation. 0

2 VLPF R/W Clamping filter control. 0

1 CKLY R/W Clamping current control 1. 0

0 CKLC R/W Clamping current control 2. 0

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0x4F – WSS3


7-0 WSS[19:14]

R CGMS(WSS525) Bit19-14 in 525 line video system.These bits show CRC 6bits in CGMS(WSS525). These bits are only valid in 525 line video system.

X

0x50 – FILLDATA


7-0 FILLDATA R/W Filled data as dummy data in ANC Dword data packet. A0

0x51 – SDID


7 NODAEN R/W 1:Bit7 in 4th byte of EAV/SAV code will be 0 when sync lost(No Video input.)

0: Bit7 in 4th byte of EAV/SAV is always VIPCFG register bit.

0

6 SYRM R/W 1: Minimum value in raw VBI will be 0x10 for Sync Level remove.

0:none. 0

5-0 SDID R/W Secondary data ID in ANC data packet type 2 22

0x52 – DID


7 ANCEN R/W 1:ANC data packet output enable. 0:disable. 0

6 TOUTHA R/W 1: reserved

0:should be “0” in normal mode. 0

5 VIPCFG R/W Set up Bit7 in 4th byte of EAV/SAV code. 1

4-0 DID R/W Data ID in ANC data packet type 2. 11

TW9910


0x53 – WSS1


7 CRCERR R This bit is only valid in 525 line video system.

1:CGMS(WSS525) CRC error detected in current field.

0:No CRC error

X

6 WSSFLD R 0:current WSS data is received in Oddfield.

1: current WSS data is received in Even field. X

5-0 WSS[13:8] R CGMS(WSS525) Bit13-8 in 525 line video system.

Wide Screen Signaling Bit13-8 in 625 line video system. X

0x54 – WSS2


7-0 WSS[7:8] R CGMS(WSS525) Bit7-0 in 525 line video system.

Wide Screen Signaling Bit7-0 in 625 line video system. X

0x55 – VVBI


7 HA656 R/W 1:HACTIVE signal is same as DVALID signal in H Down scaled video output.

0:HACTIVE signal is always HACTIVE register’s length.

0

6 EAVSWAP

R/W 1:EAV-SAV code is swapped.

0:EAV-SAV code is not swapped(standard 656 output mode) 0

5 HAMM84 R/W 1:enable 84 Hamming Code checking BI Slicer.0: disable. 0

4 NTSC656 R/W 1:Number of Even Field Video output line is (the number of Odd field Video output line – 1). This bit is required for ITU-R BT.656 output for 525 line system standard.

0: Number of Even Field Video output line is same as the number of Odd field Video output line.

0

3-0 VVBI R/W The number of raw VBI data output line counted from top video active line signal timing.

0

TW9910


0x56~6A LCTL6~LCTL26


7-4 R/W Set up VBI Data Slicer Decoding mode on Line-n.

Value is set up by upper bit7-4 meaning for Line-n in odd field. 0

3-0

LCTLn

R/W Value is set up by below bit3-0 meaning for Line-n in even field.

0h:disable decoding.

1h:Teletext-B

2h:Teletext-C

3h:Teletext-D

4h:Closed Captioning and Extended Data service. (EIA-608 type).

5h:CGMS (WSS525) in 525 line system or WSS625 in 625 line

system.

6h:VITC

7h:Gemstar 1x

8h:Gemstar 2x

9h:VPS (Line16 VPS type)

Ah: Teletext-A

Bh~Fh: reserved

0

0x6B – HSGEGIN


7-0 HSBEGIN R/W HSYNC Start position. 2C

0x6C – HSEND


7-0 HSEND R/W HSYNC End position. 60

0x6D – OVSDLY


7-0 OVSDLY R/W VSYNC Start position. 00

TW9910


0x6E – OVSEND


7 HSPIN R/W 1:HSYNC output is HACTIVE.

0:HSYNC output is HSYNC. 0

6-4 OFDLY R/W FIELD output delay.

0h:0H line delay FIELD output. (601 mode only)

1h-6h: 1H-6H line delay FIELD output.

7h:FIELD output is synchronized to the leading edge of VACTIVE.

2

3 VSMODE R/W 1:VSYNC output is HACTIVE-VSYNC mode.

0:VSYNC output is HSYNC-VSYNC mode. 0

2-0 OVSEND R/W Line delay for VSYNC end position. 0

0x6F – VBIDELAY


7 PDNSVBI R/W 1:VBI data slicer enable

0: VBI data slicer is in reset and power-down mode 0

6 Reserved R/W 0

5-0 VBIDELAY

R/W Raw VBI output delay 24

TW9910


Pin Diagram

VD[7] VD[8] VD[9] VD[10] VDD VD[11] VD[12] VD[13] VD[14] VD[15] VDDE

XTO

XT

I VS

SE

VD[0

]/SIA

D0

VD[1

] VS

S VD

[2]

VD[3

] VD

[4]

VD[5

] VD

[6]

TW9910

3332313029282726252423

1 2 3 4 5 6 7 8 9 10 11

12

13

14

15

16

17

18

19

20

21

22

44 43 42 41 40 39 38 37 36 35 34

VDDESCLKSDATPDN

RSTBTMODE

AVDYMUX3YMUX2YGND

YMUX1

YMU

X0AV

SC

IN0

AVD

AVS

VSS VS HS

MPO

UT

CLK

X2VS

SE

TW9910


Pin Description

Pin# I/O Pin Name Description

Analog video signals

12 I MUX0 Analog CVBS or Y input. Connect used input to AGND through 0.1uF capacitor.




10 YGND Analog Differential input for Y-ADC.

14 I CIN0 Analog chroma input. Connect unused input to AGND through 0.1uF capacitor.

Clock Signals

43 I XTI External clock input

44 O XTO External clock output

Host Interface

2 I SCLK The MPU Serial interface Clock Line.

3 I/O SDAT The MPU Serial interface Data Line.

General signals

5 I RSTB Reset input. Low active.

4 I PDN Power down control pin. It is high active.

6 I TMODE Test pin. It should be low for normal operation.

Video output Signals

19 O HS Horizontal sync and multi-purpose output pin. See register for control information.

18 O VS Vertical Sync and multi-purpose output. See register for control information.

21 O CLK2 Data Clock output. See register for control information.

24,25,26,27,28,30,

31,32

O VD[15:8] Digitized Video Data Outputs of Y/YCbCr. VD[8] is the LSB and VD[15] is the MSB.

33,34,35,36,37,38,

40

I/O VD[7:1] Digitized video data output of CbCr. VD[7] is the MSB.

41 I/O VD[0]/SIAD0

LSB of digitized video data output of CbCr.

SIAD0 : The MPU interface address select pin 0. A pullup or pulldown resister is needed for select one of the two addresses that chip will respond.

Power and Ground Pins


29 I VDD 1.8V digital core power.

17,39 I VSS 1.8V digital core return

1,23 I VDDE 3.3V digital I/O power.

22,42 I VSSE 3.3V digital I/O return

TW9910



7,15 I AVD 1.8V analog ADC supply

13,17 I AVS 1.8V analog ADC return

TW9910


Parametric Information

AC/DC Electrical Parameters

Table 19. Absolute Maximum Ratings Parameter Symbol Min Typ Max Units AVDD (measured to AVSS) VDDAM - - 2.7 V V DD (measured to DVSS) VDDM - 2.7 V Voltage on any signal pin (See the note below) - DVSS –

0.5 - VDDAM +

0.5 V

Analog Input Voltage - AVSS – 0.5

- VDDM + 0.5

V

Storage Temperature T S –65 - +150 °C Junction Temperature T J - - +125 °C Vapor Phase Soldering(15 Seconds) T VSOL - - +220 °C

NOTE: Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional operation at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device employs high-impedance CMOS devices on all signal pins. It must be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V or drops below ground by more than 0.5 V can induce destructive latchup.

Table 20. characteristics Parameter Symbol Min Typ Max Units

Supply

Power Supply — IO VDDE 3.15 3.3 3.6 V Power Supply — Analog VDDA V Power Supply — Digital VDD V Maximum |V DD – AVDD| - - 0.3 V MUX0, MUX1 , MUX2 and MUX3 Input Range (AC coupling required)

0.5 1.00 2.00 V

CIN0 Amplitude Range (AC coupling required) 0.5 1.00 2.00 V Ambient Operating Temperature T A 0 +70 °C Analog Supply current Iaa - TBD - mA Digital Supply current Idd - TBD - mA Digital Core Supply Current - TBD - mA

Digital Inputs

Input High Voltage (TTL) V IH 2.0 - V DDM + 0.5

V

Input Low Voltage (TTL) V IL - - 0.8 V Input High Voltage (XTI) V IH 2.0 - V DDM +

0.5 V

Input Low Voltage (XTI) V IL VSS -0.5 - 1.0 V Input High Current (V IN =V DD ) I IH - - 10 µA

TW9910


Input Low Current (V IN =VSS) I IL - - –10 µA Input Capacitance (f=1 MHz, V IN =2.4 V) C IN - 5 - pF

Parameter Symbol Min Typ Max Units Digital Outputs

Output High Voltage (I OH = –4 mA) V OH 2.4 - V DD V

Output Low Voltage (I OL = 4 mA) V OL - 0.2 0.4 V

3-State Current I OZ - - 10 µA

Output Capacitance C O - 5 - pF

Analog Input

Analog Pin Input voltage Vi - 1 - Vpp Analog Pin Input Capacitance C A - 7 - pF

ADCs

ADC resolution ADCR - 10 - bits ADC integral Non-linearity AINL - ±1 - LSB ADC differential non-linearity ADNL - ±1 - LSB ADC clock rate fADC 24 27 30 MHz Video bandwidth (-3db) BW - 10 - MHz

Horizontal PLL

Line frequency (50Hz) fLN - 15.625 - KHz Line frequency (60Hz) fLN - 15.734 - KHz static deviation ∆fH - - 6.2 %

Subcarrier PLL

subcarrier frequency (NTSC-M) fSC - 3579545 - Hz subcarrier frequency (PAL-BDGHI) fSC - 4433619 - Hz subcarrier frequency (PAL-M) fSC - 3575612 - Hz subcarrier frequency (PAL-N) fSC - 3582056 - Hz lock in range ∆fH ±450 - - Hz

Crystal spec

nominal frequency (fundamental) - 27 - MHz deviation - - ±50 ppm Temperature range Ta 0 - 70 oC load capacitance CL - 20 - pF series resistor RS - 80 - Ohm

Oscillator Input

nominal frequency - 27 - MHz deviation - - ±25 ppm duty cycle - - 55 %

TW9910


Parameter Symbol Min Typ Max Units Output CLK

CLKX1 12 13.5 15 MHz CLKX2 24 27 30 MHz CLKX1 Duty Cycle - - 55 % CLKX2 Duty Cycle - - 55 % CLKX2 to CLKX1 Delay 4 - - 2 ns CLKX1 to Data Delay 5 - 5 - ns CLKX2 to Data Delay 6 - 5 - ns CLKX1 (Falling Edge) to VCLK (Rising Edge) 41 - 0 - ns CLKX2 (Falling Edge) to VCLK (Rising Edge) 42 - 0 - ns

Output Video Data 8-bit Mode (1)

Data to VCLK (Rising Edge) Delay 7b - 18 - ns VCLK (Rising Edge) to Data Delay 8b - 18 - ns

16-bit Mode (1) Data to VCLK (Rising Edge) Delay 7a - 37 - ns VCLK (Rising Edge) to Data Delay 8a - 37 - ns

Clock Timing Diagram

XT

CLKX2

CLKX1

VCLK

Data

1 2

7b 8b6

4

7a 8a

5

41

42

3

VCLK

Data

(8-bit output mode)

(16-bit output mode)

TW9910


Mechanical Data

A1

A

A2

L1

c

E

E1E2

be

TW9910

Top View

D D1 D2

R2

R1

S L θ3

θ2

Gage Plane 0.25mm

θ

θ1

TW9910


NOTES:

1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.

2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and a adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.

MILLIMETER INCH SYMBOL MIN NOM MAX MIN NOM MAX

A --- --- 1.60 --- --- 0.063A1 0.05 --- 0.15 0.002 --- 0.006A2 1.35 1.40 1.45 0.053 0.055 0.057D 9.00 BSC. 0.354 BSC. D1 7.00 BSC. 0.276 BSC. E 9.00 BSC. 0.354 BSC. E1 7.00 BSC. 0.276 BSC. R2 0.08 --- 0.20 0.003 --- 0.008R1 0.08 --- --- 0.003 --- ---

θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° --- --- 0° --- ---

θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.09 --- 0.20 0.004 --- 0.008L 0.45 0.60 0.75 0.018 0.024 0.030L1 1.00 REF 0.039 REF S 0.20 --- --- 0.008 --- --- b 0.17 0.20 0.27 0.007 0.008 0.011e 0.50 BSC. 0.020 BSC.

D2 5.00 0.197 E2 5.00 0.197

TW9910


Application Schematics

MUX0

MUX1

CIN0

22pf27M1Mohm

22pf

L1, 3.3uHC1, 220pf

XTI

XTO

RST#

VD1-15

VideoTiming

SCL

SDA

TMODEPDN

AGND

DGND

0.1uF

AVDD

AGND

0.1uF

DVDD

DGNDGND

1.8V3.3V

Filtered 1.8V

Typical TW9910 External Circuitry

4.7k

4.7k

3.3/5V

TW9910

CVBS1

S-Video

Note: All unused digital input pins should be tied to DGND.

*

* For 3rd overtone crystal

0.1uF75 ohm

0.1uF75 ohm

0.1uF75 ohm

VD0 / SIAD0

3.3V

** option10k

TW9910


PCB Layout Considerations

The PCB layout should be done to minimize the power and ground noise on the TW9910. This is done by good power de-coupling with minimum lead length on the de-coupling capacitors; well-filtered and regulated analog power input shielding and ground plane isolation.

The ground plane should cover most of the PCB area with separated digital and analog ground planes surrounding the chip. These two planes should be at the same electrical potential and connected together under TW9910. The following figure shows a ground plane layout example.

AGND

DGND

TW9910

To minimize crosstalk, the digital signals of TW9910 should be separated from the analog circuitry. Moreover, the digital signals should not cross over the analog power and ground plane. Parallel running of digital lines for long distance should also be avoided.

Copyright Notice

This manual is copyrighted by Techwell, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of Techwell, Inc.

Disclaimer

This document provides technical information for the user. Techwell, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Techwell, Inc. holds no responsibility for any errors that

TW9910


may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Techwell, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.

Life Support Policy

Techwell, Inc. products are not authorized for use as critical components in life support devices or systems.

Documents

Low Power NTSC/PAL/SECAM Video Decoder with …read.pudn.com/downloads198/ebook/933744/TW9910A_SPEC.pdfTECHWELL, INC. 1 REV. A 04/19/2005 Techwell, Inc. TW9910 – Low Power NTSC/PAL/SECAM