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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2865254, IEEETransactions on Circuits and Systems II: Express Briefs

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS 1

Low-Power Fast-Transient Capacitor-less LDORegulator with High Slew-Rate Class-AB Amplifier

Jun Tang, Jaeseong Lee, and Jeongjin Roh, Senior Member, IEEE

Abstract—This brief presents a low-power fast-transientcapacitor-less low-dropout regulator (CL-LDO) for system-on-a-chip applications. A low-quiescent-current class-AB amplifierwith embedded slew-rate enhancement (SRE) circuit is proposedto improve both current efficiency and load transient perfor-mance. As the SRE circuit is directly controlled by the amplifier,only a minimum hardware overhead is required. The proposedCL-LDO is fabricated in a 0.18-µm standard CMOS process. Itoccupies an active area of 0.031mm2 and consumes a quiescentcurrent of 10.2µA. It is capable of delivering a maximum loadcurrent of 100mA at 1.0-V output from a 1.2-V power supply.The measured results show that a settling time of 0.22µs isachieved for load steps from 1mA to 100mA (and vice versa)with an edge time of 0.1µs.

Index Terms—high slew-rate (SR), capacitor-less low-dropoutregulator (CL-LDO), low-power, fast-transient.

I. INTRODUCTION

THE low-dropout regulator is widely used to provide cleanand ripple-free power supplies in battery-powered and

portable applications. To enable fully integrated for system-on-a-chip, CL-LDOs have been widely researched [1]. Theloop stability and load transient performance of CL-LDOs areregarded as the two most important design criteria due to thelack of a bulky output capacitor. To prolong the battery life,high power efficiency is required, which is indicated by a lowquiescent current (IQ) and low dropout voltage (VDO). Themain obstacle to load transient performance is the limited gate-voltage slew-rate (SR) of the pass transistor (MPT ). The SRis limited by the large gate capacitance of the MPT and thesmall slewing current (ISR) due to the low IQ. Therefore, alow-power error amplifier (EA) with high-SR is desirable forthe CL-LDO design.

In previous works, various strategies have been proposedfor improving the current efficiency and load transient perfor-mance of CL-LDOs. The main approaches include designinglow-power EAs with adaptive biasing techniques [3]-[6] and/ordynamic-operating SRE circuits [2]-[6], [8] to relieve thegate-voltage SR limitation. The adaptive biasing techniquesincrease IQ according to the load current (Iload), whichimproves the loop gain and unity-gain bandwidth (UGB) at

This research was supported by the MSIT (Ministry of Science andICT), Korea, under the ITRC (Information Technology Research Center)support program (IITP-2018–0-01421) supervised by the IITP (Institute forInformation & communications Technology Promotion). This research wassupported by the MOTIE (Ministry of Trade, Industry & Energy) (projectnumber 10080488) and KSRC (Korea Semiconductor Research Consortium)support program for the development of the future semiconductor device.

The authors are affiliated with the Department of Electronics andCommunications Engineering, Hanyang University, Korea (e-mail:[email protected]).

Vgate

VOUT

CL RL

VREFLS

Level-Shifter

Gmp

Gmn Cc

Error Amplifier VDD

VSS

VOUT

Ich

Idch

IloadISR

CurrentBooster

Drive Stage withEmbedded SRE Circuit

Ip

In

MPT

MSLTp

MSLTn

MDCTp

MDCTn

Fig. 1. Conceptual scheme of the proposed CL-LDO.

heavy load conditions. Thus, better load (line) regulation andtransient performances can be expected at the cost of higherpower consumption. The SRE circuit is a vital part of CL-LDOs with a low IQ for load transient improvement, and itusually consists of sensing and driving circuits. The sensingcircuit detects the load transient and generates control signalsfor the driving circuit, while the driving circuit is controlledto generate large extra currents only during transient response.Several techniques have been proposed to implement thesensing circuit, such as voltage-spike detector [2], [3], [6],capacitive coupling [4], current comparators [5], and high-passfilter [8]. However, the sensing circuit contributes to circuitcomplexity and requires extra area or current, which can beeliminated if the EA directly controls the driving circuit.

In this brief, a low-power CL-LDO with a high-SR class-AB amplifier is presented for improving both current efficiencyand load transient performance. The conceptual scheme of theproposed CL-LDO is shown in Fig.1. The SRE circuit consistsof two driving circuits, one is embedded into the main linearregulation loop, and the other forms fast nonlinear feedbackloops only for large transient steps. Hence, a dynamicallyboosted ISR is achieved with a minimum hardware overhead.

II. DESIGN OF THE PROPOSED CL-LDOA. Circuit Design and Implementation

As shown in Fig.1, CL stands for the parasitic capacitance ofthe load circuit. Cc is a choosable capacitor for extending themaximum CL if necessary. RL represents the load circuit. TheEA is a class-AB amplifier with complementary input pairs,a current-booster drive stage, and an embedded SRE circuit.Based on the compact two-stage cascode amplifier architecturein [10], the complementary input pairs are designed to obtain



2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS

Vgate

VOUT

CL RL

a b

c d

c d

a b

VBP

VBN

VDD

VSS

VOUTVREF

M1 M2

M3 M4

M5 M6

M7 M8

M9 M10

M11 M12

M13 M14

M15

M16

M17

M18

ISS

ISSIB2 IB2

IB

IB

VBN

VBP

MSLTp

MSLTn

d

b

Drive Stage with Embedded SRE Circuit

1 : 2

1 : 2

Iop

Ion

Ia Ib

Ic Id

Vp_mir

Vn_mir

Vop

Von

VBPVBN

Biasing Circuits

Ibias0.1μA

0.1μA 0.1μA 0.1μA 0.1μA 0.1μA 1.6μA 0.1μA 0.8μA

0.8μA0.1μA1.6μA0.1μA0.1μA0.1μA

0.5mA ~ 100mA

Ms0Ms1 Ms2 Ms3

Ms5Ms4Ms6 Ms7 Ms8

Mb0

Mb1

Mb2

Mb3

Mt0

Mt1

1.2V

1.0V

0.8μA

0.8μA

1 : 1

1 : 1

1.0V

20/0.18 m=400

2/0.18 m=4

1/0.18 m=4

0 ~ 100pF1.6μA 1.6μA

1.6μA 1.6μA 3.1μA

3.1μA

Iload

0.1μA

In

Ip

ISR

Ich

Idch

MDCTp

MDCTn

MPT

Fig. 2. Full schematic of the proposed CL-LDO.

class-AB operation for the drive stage instead of a floatingclass-AB control, and a current-mirror-based drive stage isapplied after the summing circuit, as shown in Fig.2. In orderto bias the two complementary input pairs that both work in thesaturation region at low voltage supplies, nMOS level shiftersare used for the pMOS input pair. The constant bias current IBis used to define the quiescent current of the summing circuitand drive stage for a constant total IQ. Active IB , such ascurrent recycling [11], or adaptive IB can also be applied toenhance the performance but with tradeoffs among the powerconsumption, stability, and circuit complexity.

The SRE circuit is based on dynamic techniques and isimplemented by using the source linear transistor (SLT) andthe dynamic charging transistor (DCT). The SLT consists ofMSLTp and MSLTn, which are embedded into the main linearregulation loop by adding them to the current mirrors in thedrive stage. The DCT consists of MDCTp and MDCTn, whichform fast nonlinear feedback loops to generate large extracharge (discharge) current Ich (Idch) only in large transientsteps when the DCT is turned on.

The size of MPT is 8, 000µm/0.18µm for a maximumIload of 100mA, as presented in Fig.2. For size reduction,the MPT is designed to operate in the triode region onceIload ≥ 80mA with a 1.2-V power supply since a nearly rail-to-rail gate-voltage swing is obtained. The other transistorsare implemented as unit transistors in parallel for betterdevice matching, except for the SLT and DCT. The designconsiderations of the SLT and DCT will be discussed later.

B. Stability Analysis

The small-signal modeling of the proposed CL-LDO isgiven in Fig.3, since the nonlinear feedback loop is onlyactivated in large transient steps. Cgdp consists of Cc and thegate-drain capacitor (Cgd) of MPT . Cgsp consists of the gate-source capacitor (Cgs) of MPT and the parasitic capacitorof EA. As current mirrors are used for the summing circuitand the drive stage, the poles inside of the EA are at highfrequencies. Therefore, it is modeled as a one-pole systemwith transconductance Gm and output impedance Rgate. The

Gm -gmptVin(s)

<feedbacknode>

Vout(s)

Cgsp CLRoutRgate

Cgdp

Error Amplifier Stage Pass Transistor Stage

VgatePole 1 Pole 2

≈ Cgs

Fig. 3. Small-signal modeling of the proposed CL-LDO.

frequency response of the proposed CL-LDO is given inEquation (1), which is similar to the conventional one.

Av(s) =Vout(s)

Vin(s)=−Adc(1− sCgdp/gmpt)(1 + s/p1)(1 + s/p2)

(1)

where the DC loop gain Adc = GmRgate · gmptRout, andRgate ≈ rds,M17 ‖ rds,M18, Rout ≈ rds,MPT

‖ RL.

p1 ≈1

[(1 + gmptRout)Cgdp + Cgsp]Rgate

p2 ≈(1 + gmptRout)Cgdp + Cgsp

(CLCgdp + CLCgsp + CgdpCgsp)Rout

UGB ≈ Adc · p1 ≈ Gm/[Cgdp + Cgsp/(gmptRout)]

(2)

The dominant pole p1 is located at the gate of MPT ,and the non-dominant pole p2 is at the output node. Sincegmpt ∝

√Iload and Rout ∝ 1/Iload, the UGB ∝ 1/

√Iload

and the p1, p2 ∝√Iload. The CL-LDO might be unstable at

certain small Iload values. To keep a phase margin (PM) above60◦, the p2 ≥ 2UGB should be ensured under all conditions.Therefore, the maximum CL and minimum gmpt can be foundas shown in Equation (3) by assuming gmptRout � 1.

CL ≤ (

gmpt

2GmCgdp − Cgsp

Cgdp + Cgsp)Cgdp

gmpt ≥ (CL + CgspCgdp

+CLCgsp(Cgdp)2

) · 2Gm(3)

A larger maximum CL can be obtained by a larger Cgdp, asmaller Gm, or a larger gmpt. Whereas a larger gmpt requires



J. TANG et al.: LOW-POWER FAST-TRANSIENT CL-LDO REGULATOR WITH HIGH-SR CLASS-AB AMPLIFIER 3

Vgate

M15

M16

M17

M18

1 : β

1 : β

Iop

Ion

Vop

Von

VDD

VSS

M15

M16

M17

M18

VBN

VBP d

b

with Embedded SRE Circuit

1 : β

1 : β

Iop

Ion

Vop

VonISR

Ich

Idch

Vgate

VDD

VSS

Basic Drive Stage

In

Ip

In

IpISR0 ISRs

MSLTp

MSLTn

MDCTp

MDCTn

Fig. 4. Error amplifier drive stage with embedded SRE circuit.

a larger Iload, a smaller Gm implies a smaller ISR, and alarger Cgdp can be obtained by a larger Cc at the penaltyof UGB reduction. The worst case of loop stability happensat the minimum Iload with the maximum CL. A wide UGBis desirable for a fast response time; hence, Cc should beminimized while keeping the linear regulation loop stable evenat the worst case. In this work, the maximum CL of 100 pFis obtained at a minimum Iload = 0.5mA, Cc = 0 pF , anda constant IQ of about 10µA. Since a small IQ limits thetransient performance, an embedded SRE circuit is developedto improve the transient performance while maintaining theconstant low IQ.

C. Design of the Embedded SRE Circuit

The basic drive stage is made up of current mirrors withratio β, as shown on the left side of Fig.4. The gate current is

ISR0 = Iop − Ion = β(Ip − In)

= β(gmp + gmn) ·∆Vin(4)

where gmp(gmn) is the transconductance of the input pairM1,2 (M3,4). ∆Vin is defined as (VOUT − VREF ). The gainsof the level shifters are neglected for simplicity. As shown inFig.2, the Ip and In are given as follows:

Ip = IB + Ia − Ib = IB + gmp ·∆VinIn = IB + Ic − Id = IB − gmn ·∆Vin

(5)

From Equation (4), the ISR0 is limited by the β, gmp, andgmn, namely by the small IQ. Thus, a dynamic SRE circuit isdesirable to improve the ISR for fast settling while maintainingthe small IQ for high current efficiency and loop stability. Thevoltage-spike detector in [2]-[3], the APPOS in [5], or thevoltage damper in [8], can be added to the current mirrors inthe drive stage or placed in parallel with the drive stage here.However, these SRE circuits require extra active area for thehigh-pass filter and/or extra current for the additional controlcircuits. As shown on the right side of Fig.4, the SRE circuitis developed and embedded into the EA in this work.

The SLT MSLTp (MSLTn) is biased into the deep triode re-gion for a small steady-state drain-source voltage VDS,MSLTp

(VDS,MSLTn), by sharing the bias voltage VBP (VBN ). The

gate-source voltage VGS,M17 (VGS,M18) is the sum of theVGS,M15 (VGS,M16) and the VDS,MSLTp

(VDS,MSLTn). At the

falling edge of Iload, any overshoot of VOUT will make Ipincrease from steady state. As a result, the VDS,MSLTp

willincrease dramatically because of triode operation; hence, theVGS,M17 will increase dramatically, as will the Iop. At therising edge of Iload, any undershoot of VOUT will make Ipdecrease from steady state. The extent of decrease in theVDS,MSLTp

is not significant due to the already small value atsteady state; therefore, the Iop will decrease mainly accordingto the β. A similar but contrary operation is found for theMSLTn, In, and Ion. Therefore, with properly designed SLT,the active value of Iop (Ion) can be significantly increased.The gate current becomes

ISRS≈ gm17 ·

1 + gm15rspgm15

Ip − gm18 ·1 + gm16rsn

gm16In

≈ β(1 +As)(gmp + gmn) ·∆Vin(6)

where gm17 ≈ βgm15, gm18 ≈ βgm16, and As = gm15rsp =gm16rsn are assumed. rsp (rsn) is the linear resistance ofMSLTp (MSLTn).

The ISRSis enhanced by the gain As, which implies the

enhanced Gm, Adc, and UGB. However, a larger Gm requiresa larger minimum Iload for stability. The size of SLT shouldbe designed well for an optimal As. In this work, As ≈ 2 isapplied. With β = 2, the quiescent value of Iop (Ion) suffersfrom 1.5-µA increment. The same IQ = 10.2µA is used fora fair comparison; hence, β = 4 without SLT, as shown inFig.5. With SLT, the settling time and undershoot are reducedby about 40%, from 0.49µs/683mV to 0.30µs/380mV . Theresponse time is also improved because of the enhanced UGBand ISRS

with SLT.For further improvement, the DCT MDCTp (MDCTn) is

added to form the nonlinear feedback loop when large transientstep happens. At such moment, large Ich (Idch) is generatedto quickly charge/discharge the gate capacitor of MPT . TheMDCTp (MDCTn) is directly controlled by the voltage Vd(Vb) at node d (b) of the folded cascode summing circuit. Noadditional sensing circuit is required, as the Vd (Vb) is naturallysensitive to the transient response. The MDCTp (MDCTn) isin the cutoff region at steady state, and it will be turned on(off) automatically when ∆VOUT > Vtrig (∆VOUT < Vtrig).The Vtrig is the trigger voltage of DCT, defined as the inputvariance that can turn on the DCT through the nonlinearfeedback loop, as given in Equation (7).

Vtrig,P ≈ (|Vth,MDCTp| − Vov,M8)/(gmnRd)

Vtrig,N ≈ (Vth,MDCTn− Vov,M14)/(gmpRb)

(7)

where Rb (Rd) is the equivalent resistance of node b (d).Although Vtrig is controlled by the threshold voltage (Vth)

of DCT, it is restrained by the gain of the nonlinear feedbackloop. With properly designed VBP (VBN ) and transistors’ size,the Vth variation has little effect on Vtrig. A smaller Vtrigimplies a smaller ∆VOUT . However, the Vtrig should be setproperly to ensure the DCT is cutoff at steady state, evenwith some offsets at the input pairs. In this work, the Vtrigis set to around 100mV , which is one-tenth of VOUT . The



4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS

VO

UT

(V)

Iop (A

)Io

n (A

)V

a, V

b (V

)V

c, V

d (V

)Il

oad (m

A) 100mA

1mA 1mA

3.2uA

10uA

16.6uA

3.2uA0uA

3.2uA

-3.2uA

-8.0uA

-3.2uA-3.2uA

0uA

Ich

, Idc

h (A

) 124uA

-86uA

380mV

Va

Vb

Vc

Vd

Idch

Ich

200mV0.49us

0.33us0.49us

(lin)

(lin)

(lin)

(lin)

(lin)

(lin)

(lin)

VO

UT

(V)

(lin)

post-layout simulation

210mV

0.21us145mV

0.21us

10080

6040

1020

VO

UT

(V)

1.11.0

0.6

0.8

0.4

1.101.05

0.85

1.000.950.90

12u

16u

8u

4u2u

-1u

-3u

-7u

-5u

-8u100u

50u

0

-50u

0.30.40.50.60.7

0.2

1.0

0.80.70.6

0.9

edge time = 0.1us

0.30us

with β=2 and SLTwith β=4

683mV

0.80

1.101.05

0.85

1.000.950.90 with β=2 and SLT & DCT

175mV

0.22us135mV

0.21us

75mV

(lin)

with β=2 and SLT & DCT

1.0u 1.4u 1.8u 2.4uTIME(sec)(lin)1.2u 2.2u2.0u

with β=2 and SLT & DCT

Fig. 5. Simulated load transient of the CL-LDO with SLT & DCT.

minimum length is used for the MDCTp (MDCTn) to obtainsmall parasitic capacitances for a fast response time of thenonlinear feedback loop.

As shown in Fig.5, since the fast nonlinear feedback loop isformed when the DCT is turned on, the ∆VOUT is significantlyreduced to about 175mV , as is the response time. As can beobserved from the Ich (Idch) waveform, the MDCTp (MDCTn)is fully turned off before VOUT entirely recovers. Therefore,the nonlinear feedback loops do not disturb the stability ofthe CL-LDO. However, the hysteresis effect can affect theDCT to avoid the ringing behavior at the rising edge of Iloadand the overshoot-undershoot behavior at the falling edge. Thehysteresis effect can be formed by either a hysteresis circuit,such as the current comparator in [5], or a short time delaythat can be obtained by the inherent parasitic RC componentsof the layout process. In this work, the hysteresis effect isimplemented via a parasitic RC delay to avoid the additionalcosts of using a hysteresis circuit. Once ∆VOUT < Vtrig,VOUT recovers with ISRS

that is proportional to ∆VOUT .Since the DCT is turned off while Iload is still rising, theremight be a plateau period for VOUT when the settling ofVOUT from the main linear regulation loop balances the loadvariation response of VOUT . The finite bandwidth of the mainlinear regulation loop also limits the transient response.

The AC simulation results of the proposed CL-LDO areshown in Fig.6. With an estimated CL of 20 pF when fully

@Iload=100mA

67°

2.2M

81°

3.2M

59.8dB

46.5dB 59.8dB

@ TTT, 27°C, CL=20pF@ SSS, -25°C, CL=20pF@ FFF, 100°C, CL=20pF@ TTT, 27°C, CL=100pF

50

-150

100

0

-50

-100

1 10 100 1k 10k 100k 1M 10MFrequency (Hz) (log)

81.1dB

63.5dB

42°

@Iload=0.5mA

4.6M

61°

7.5M77.2dB

Gai

n (d

B)

Pha

se (

deg.

)

@Iload=20mA

57°

4.2M

73°

6.9M

76.8dB

62.2dB74.9dB

Gai

n (d

B)

Pha

se (

deg.

)

50

-150

100

0

-50

-100



50

-150

100

0

-50

-100@ TTT, 27°C, CL=20pF@ SSS, -25°C, CL=20pF@ FFF, 100°C, CL=20pF@ TTT, 27°C, CL=100pF

@ TTT, 27°C, CL=20pF@ SSS, -25°C, CL=20pF@ FFF, 100°C, CL=20pF@ TTT, 27°C, CL=100pF

50

-150

100

0

-50

-100

worst-case @Iload=0.5 mA @CL=100 pF


81.1dB

77.2dB63.5dB/62.4dB 6.3M

48°

4.2M

22° @ FFF, 100°C@ FFF, 80°C@ SSS, -25°C@ TTT, 27°C

14°

Fig. 6. AC simulation results of the proposed CL-LDO.

160 um

Err_AmpMPT

105 um

105 um

75 um

145

um

160 um

Err_AmpMPT

105 um

105 um

75 um

145

um

Fig. 7. Chip micrograph and layout view of the proposed CL-LDO.

integrated, a PM > 60◦ is achieved for an Iload range from0.5mA to 100mA, over process corners and temperatures.It is stable even at worst case (Iload = 0.5mA and CL =100 pF ), though a small PM occurs at FFF corners withhigh temperature. At heavy load conditions, when the MPT

enters into the triode region and Rout reduces dramatically, thegain of the power stage gmptRout is reduced, as is the Adcand UGB. The minimum Adc of 59.8 dB with a minimumUGB of 2.2MHz is found at Iload = 100mA.

III. EXPERIMENTAL RESULTS

The proposed CL-LDO is fabricated using a 0.18-µmstandard CMOS process. The chip micrograph with a shieldinglayer is presented in Fig.7, which shows an active areaoccupation of 0.031mm2. The input supply VDD is 1.2Vto 1.8V , and VOUT is 0.8V to 1.6V with a minimumVDO of 200mV . The measured line transient response isshown in Fig.8 with VOUT = 1.0V , Iload = 1mA andCL = 100 pF . As VDD changes from 1.2V to 1.8V (and viceversa) within 5µs, the VOUT suffers from a 6mV variation.The measured load transient response is shown in Fig.9, wherean off-chip load switch is used to generate the load steps.For the Iload steps from 1mA to 100mA (and vice versa)within 0.1µs, the settling time is 0.22µs with an undershootless than 200mV . Due to the effects of the load switchand the effects of the parasitic components of the traces inmeasurement, the response time is a little longer than that in



J. TANG et al.: LOW-POWER FAST-TRANSIENT CL-LDO REGULATOR WITH HIGH-SR CLASS-AB AMPLIFIER 5

0.6 V

△V = 6 mV

5 us

10 us500 mV

=1.0V

DC Coupling

AC Coupling

VDD

VOUT

1.8 V

1.2 V

5 us

1.0 V

10 us500 mVDC

10 us10 mVAC

fT = 20 kHz

Fig. 8. Measured line transient response of the proposed CL-LDO with anedge time of 5µs, VOUT = 1.0V , Iload = 1mA, CL = 100 pF .

190mV

△V = 8mV0.22us

0.17us

Iload 1mA

100mA

1mA

200mV

0.1us50mA0.1us 0.07us

0.1us200mV

=1.0VDC Coupling

AC Coupling

VOUT

VOUT

Fig. 9. Measured load transient response of the proposed CL-LDO with anedge time of 0.1µs, VDD = 1.2V , VOUT = 1.0V .

simulation results. The measured load regulation is calculatedas 8mV/(100− 1)mA, which is about 0.081mV/mA.

The performance comparison with previously reported CL-LDOs is summarized in Table I. The figure-of-merit (FOM)in [2], FOM1, and in [3], FOM2, are adopted to evaluate thedifferent current efficient CL-LDOs. The smaller FOM1 andFOM2 indicate the better performance in terms of the currentefficiency and load transient response. Although the LDO in[6] achieves the best FOM1 as a larger CL is applied, thiswork achieves a FOM1 of 0.0206V . Except for [3], whichapplies a longer edge time, this work achieves the smallestFOM2 of 0.0224ns. When considering the effects of theminimum length (L) of transistors in different technologies,the FOM3 in [7] is adopted. This work achieves the smallestFOM3, which, together with FOM2 and FOM1, confirmsthe better performance regarding the current efficiency andload transient response.

IV. CONCLUSION

A low-power fast-transient CL-LDO employing a high-SR class-AB error amplifier is presented in this brief. TheSRE circuit (SLT & DCT) is embedded into the amplifierwith a minimum hardware overhead. The proposed CL-LDOis stable at a load current range from 0.5mA to 100mAwith a maximum allowable CL of 100 pF and without anycompensation. It occupies an active area of 0.031mm2 andconsumes a quiescent current of 10.2µA. A settling timeof about 0.22µs is measured when the load current stepsfrom 1mA to 100mA (and vice versa) within 0.1µs, andthe undershoot is less than 200mV .

TABLE ICOMPARISON WITH PREVIOUSLY REPORTED CL-LDOS.

Parameters [3] [5] [6] [7] [8] This Work

Year 2012 2013 2014 2016 2017 2018Tech. [µm] 0.35 0.35 0.065 0.18∗ 0.18 0.18Area [mm2] 0.064 0.04 0.0133 0.279 0.033 0.031VIN [V ] 2.5-4.0 1.2-1.5 0.75-1.2 2.3-5.5 1.8-2.2 1.2-1.8VOUT [V ] 2.35 1.0-1.3 0.55 1.2-5.4 1.6 0.8-1.6IQ [µA] 7.0∼ 1.2-14 15.9-487 40 71-101 10.2Iload max [mA] 100 100 50 150 100 100Iload min [mA]? 0.05 0.1 1 0 0.2 1Con chip [pF ] 7.5 0 4.1 29 12.7 0CL [F ] 0-100p 0-100p 470p-10n 0-470p 100p 0-100pTsettle [µs] ∼0.15 2.7 0.25 N/A 0.2 0.22∆Iload [mA]? 99.95 99.9 49 150 99.8 99∆VOUT [mV ] 243 270 24 420 110 200Tedge [µs] 0.5 N/A 0.1 0.15 0.1 0.1Edge Time Ratio K 5,000 - 1,000 1,500 1,000 1,000FOM1 [V ]♣ 0.0850 - 0.0079 0.1680 0.0783 0.0206FOM2 [ns]♣ 0.0105 0.0324 0.0795 - 0.1420 0.0224FOM3 [V/µm2]♣ 0.6939 - 1.8698 0.6720 2.4167 0.6358

? Iload min and ∆Iload are the values used in load transient measurement.∗ 0.18µm I/O CMOS process with a minimum length of 0.5µm for pMOS.♣ FOM1 = K(∆VOUT · IQ)/∆Iload, FOM2 = Tsettle · IQ/Iload max,

and FOM3 = FOM1/L2; the smaller FOM1,2,3, the better performance.

REFERENCES

[1] J. Torres, M. EI-Nozahi, A. Amer, S. Gopalraju, R. Abdullah, K. Entesari,and E. Snchez-Sinencio, “Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison”, IEEE Circuits and Systems Magazine,Second Quarter, 2014.

[2] J. Guo and K. N. Leung, “A 6-µW Chip-Area-Efficient Output-Capacitor-less LDO in 90-nm CMOS Technology”, IEEE J. Solid-State Circuits,vol. 45, no. 9, pp. 1896-1905, Sep. 2010.

[3] X. Ming, Q. Li, Z. K. Zhou, and B. Zhang, “An Ultrafast AdaptivelyBiased Capacitorless LDO with Dynamic Charging Control”, IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 59, no. 1, pp. 40-44, Jan. 2012.

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[5] X. Qu, Z. K. Zhou, B. Zhang, and Z. J. Li, “An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push-Pull Output Stage”, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60,no. 2, pp. 96-100, Feb. 2013.

[6] X. L. Tan, S. S. Chong, P. K. Chan, and U. Dasgupta, “A LDO RegulatorWith Weighted Current Feedback Technique for 0.47nF − 10nFCapacitive Load”, IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2658-2672, Nov. 2014.

[7] S. W. Hong and G. H. Cho, “High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator (LDO) for Mobile Applications UtilizingFrequency Response of Multiple Feedback Loops”, IEEE Trans. CircuitsSyst. I, Reg. Papers, vol. 63, no. 1, pp. 46-57, Jan. 2016.

[8] S. J. Yun, J. S. Kim, and Y. S. Kim, “Capless LDO Regulator Achieving-76 dB PSR and 96.3 fs FOM”, IEEE Trans. Circuits Syst. II, Exp. Briefs,vol. 64, no. 10, pp. 1147-1151, Oct. 2017.

[9] Y. Lim, J. Lee, Y. Lee, S. S. Song, H. T. Kim, O. Lee, and J. Choi, “AnExternal Capacitor-Less Ultralow-Dropout Regulator Using a Loop-GainStabilizing Technique for High Power-Supply Rejection Over a WideRange of Load Current”, IEEE Trans. Very Large Scale Integr. (VLSI)Syst., vol. 25, no. 11, pp. 3006-3018, Nov. 2017.

[10] R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, “ACompact Power-Efficient 3-V CMOS Rail-to-Rail Input/Output Opera-tional Amplifier for VLSI Cell Libraries”, IEEE J. Solid-State Circuits,vol. 29, no. 12, pp. 1505-1513, Dec. 1994.

[11] R. S. Assaad and J. Silva-Martinez, “The Recycling Folded Cascode: AGeneral Enhancement of the Folded Cascode Amplifier”, IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, Sep. 2009.

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