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Dynamic and Static Power in CMOS
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Low-Power Design and Test
Dynamic and Static Power in CMOS
Hyderabad, July 30-31, 2007
http://www.eng.auburn.edu/~vagrawal/hyd.html
Vishwani D. AgrawalAuburn University, [email protected] Srivaths RaviTexas Instruments [email protected]Low-Power Design and Test, Lecture 2
Components of Power
DynamicSignal transitionsLogic activityGlitchesShort-circuitStaticLeakagePtotal =Pdyn + Pstat
Ptran + Psc + Pstat
Low-Power Design and Test, Lecture 2
Power of a Transition: Ptran
VDD
Ground
CL
Ron
R = large
vi (t)
vo(t)
ic(t)
Low-Power Design and Test, Lecture 2
2
Charging of a Capacitor
V
C
R
i(t)
v(t)
Charge on capacitor, q(t)=C v(t)
Current, i(t)=dq(t)/dt=C dv(t)/dt
t = 0
Low-Power Design and Test, Lecture 2
i(t)=C dv(t)/dt=[V v(t)] /R
dv(t)V v(t)
=
dt RC
dv(t) dt
=
V v(t) RC
-t
ln [V v(t)]=+ A
RC
Initial condition, t = 0, v(t) = 0 A = ln V
-t
v(t)=V [1 exp()]
RC
Low-Power Design and Test, Lecture 2
-t
v(t)=V [1 exp( )]
RC
dv(t) V -t
i(t)=C = exp( )
dt R RC
Low-Power Design and Test, Lecture 2
Total Energy Per Charging Transition from Power Supply
V2 -t
Etrans= V i(t) dt= exp( ) dt
00 R RC
=CV2
Low-Power Design and Test, Lecture 2
Energy Dissipated per Transition in Resistance
V2 -2t
R i2(t) dt=R exp( ) dt
0 R2 0 RC
1
= CV2
2
Low-Power Design and Test, Lecture 2
Energy Stored in Charged Capacitor
-t V -t
v(t) i(t) dt = V [1-exp( )] exp( ) dt
0 0 RC R RC
1
= CV2
2
Low-Power Design and Test, Lecture 2
Transition Power
Gate output rising transitionEnergy dissipated in pMOS transistor = CV 2/2Energy stored in capacitor = CV 2/2Gate output falling transitionEnergy dissipated in nMOS transistor = CV 2/2Energy dissipated per transition = CV 2/2Power dissipation:Ptrans=Etrans fck= fck CV2/2
=activity factor
Low-Power Design and Test, Lecture 2
Components of Power
DynamicSignal transitionsLogic activityGlitchesShort-circuitStaticLeakagePtotal =Pdyn + Pstat
Ptran + Psc + Pstat
Low-Power Design and Test, Lecture 2
Short Circuit Power of a Transition: Psc
VDD
Ground
CL
vi (t)
vo(t)
isc(t)
Low-Power Design and Test, Lecture 2
2
Short Circuit Current, isc(t)
Time (ns)
0
1
Isc
Volt
VDD
isc(t)
0
Vi (t)
Vo(t)
VDD - VTp
VTn
tB
tE
Iscmaxf
p-transistor
starts
conducting
n-transistor
cuts-off
Low-Power Design and Test, Lecture 2
Peak Short Circuit Current
Increases with the size (or gain, ) of transistorsDecreases with load capacitance, CLLargest when CL = 0Reference: M. A. Ortega and J. Figueras, Short Circuit Power Modeling in Submicron CMOS, PATMOS 96, Aug. 1996, pp. 147-166.Low-Power Design and Test, Lecture 2
Short-Circuit Energy per Transition
Escf =tBtE VDD isc(t)dt= (tE tB) Iscmaxf VDD / 2
Escf = tf (VDD - |VTp| - VTn) Iscmaxf / 2Escr = tr (VDD - |VTp| - VTn) Iscmaxr / 2Escf = Escr = 0, when VDD = |VTp| + VTnLow-Power Design and Test, Lecture 2
Short-Circuit Energy
Increases with rise and fall times of inputDecreases for larger output load capacitanceDecreases and eventually becomes zero when VDD is scaled down but the threshold voltages are not scaled downLow-Power Design and Test, Lecture 2
Short-Circuit Power Calculation
Assume equal rise and fall timesModel input-output capacitive coupling (Miller capacitance)Use a spice model for transistorsT. Sakurai and A. Newton, Alpha-power Law MOSFET model and Its Application to a CMOS Inverter, IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594.Low-Power Design and Test, Lecture 2
Short Circuit Power
Psc= fckEsc
Low-Power Design and Test, Lecture 2
Psc, Rise Time and Capacitance
VDD
Ground
CL
Ron
R = large
vi (t)
vo(t)
ic(t)+isc(t)
tf
tr
vo(t)
R
vo(t)
VDD
Low-Power Design and Test, Lecture 2
isc, Rise Time and Capacitance
-t
VDD[1- exp()]
vo(t) R(t) C
Isc(t) = =
R(t) R(t)
Low-Power Design and Test, Lecture 2
iscmax, Rise Time and Capacitance
Small C
Large C
tf
1
R(t)
iscmax
vo(t)
vo(t)
i
t
Low-Power Design and Test, Lecture 2
Psc, Rise Times, Capacitance
For given input rise and fall times short circuit power decreases as output capacitance increases.Short circuit power increases with increase of input rise and fall times.Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times.Low-Power Design and Test, Lecture 2
Summary: Short-Circuit Power
Short-circuit power is consumed by each transition (increases with input transition time).Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power).Increasing the output load capacitance reduces short-circuit power.Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when VDD |Vtp|+Vtn .Low-Power Design and Test, Lecture 2
Components of Power
DynamicSignal transitionsLogic activityGlitchesShort-circuitStaticLeakageLow-Power Design and Test, Lecture 2
Leakage Power
IG
ID
Isub
IPT
IGIDL
n+
n+
Ground
VDD
R
Drain
Source
Gate
Bulk Si (p)
nMOS Transistor
Low-Power Design and Test, Lecture 2
Leakage Current Components
Subthreshold conduction, IsubReverse bias pn junction conduction, IDGate induced drain leakage, IGIDL due to tunneling at the gate-drain overlapDrain source punchthrough, IPT due to short channel and high drain-source voltageGate tunneling, IG through thin oxide; may become significant with scalingLow-Power Design and Test, Lecture 2
Subthreshold Current
Isub = 0 Cox (W/L) Vt2 exp{(VGS VTH ) / nVt }
0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
Low-Power Design and Test, Lecture 2
IDS for Short Channel Device
Isub= 0 Cox(W/L)Vt2 exp{(VGS VTH + VDS)/nVt}
VDS = drain to source voltage
: a proportionality factor
W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron
Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104
Low-Power Design and Test, Lecture 2
Increased Subthreshold Leakage
0
VTH
VTH
Log (Drain current)
Gate voltage
Scaled device
Ic
Isub
Low-Power Design and Test, Lecture 2
Summary: Leakage Power
Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power.For a gate it is a small fraction of the total power; it can be significant for very large circuits.Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking.Multiple-threshold devices are used to reduce leakage power.Low-Power Design and Test, Lecture 2
Technology Scaling
Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologiesConstant electric field assumedLow-Power Design and Test, Lecture 2
Constant Electric Field Scaling
B. Davari, R. H. Dennard and G. G. Shahidi, CMOS Scaling for High Performance and Low PowerThe Next Ten Years, Proc. IEEE, April 1995, pp. 595-606.Other forms of scaling are referred to as constant-voltage and quasi-constant-voltage.Low-Power Design and Test, Lecture 2
Bulk nMOSFET
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
Source
Drain
Polysilicon
Low-Power Design and Test, Lecture 2
Technology Scaling
A scaling factor (S ) reduces device dimensions as 1/S.Successive generations of technology have used a scaling S = 2, doubling the number of transistors per unit area. This produced 0.25, 0.18, 0.13, 90nm and 65nm technologies, continuing on to 45nm and 30nm.A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures.N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston:
Pearson Addison-Wesley, 2005, Section 4.9.1.
Low-Power Design and Test, Lecture 2
Constant Electric Field Scaling
Device ParameterScalingLength, L1/SWidth, W1/SGate oxide thickness, tox1/SSupply voltage, VDD1/SThreshold voltages, Vtn, Vtp1/SSubstrate doping, NASLow-Power Design and Test, Lecture 2
Constant Electric Field Scaling (Cont.)
Device CharacteristicScalingW / (L tox)SCurrent, Ids (VDD Vt ) 21/SResistance, RVDD / Ids1Gate capacitance, CW L / tox1/SGate delay, RC1/SClock frequency, f1/ SDynamic power per gate, PCV 2 f1/S 2Chip area, A1/S 2Power densityP/A1Current densityIds /ASLow-Power Design and Test, Lecture 2
Problem: A Design Example
A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power while the short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT. Compare two power reduction strategies for extending the battery life:Clock frequency is reduced to half, keeping all other parameters constant.
Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the design of transistors.
Low-Power Design and Test, Lecture 2
Solution: Part A. Clock Frequency Reduction
Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task. Energy consumption for the task will be,Energy = (P / 2 + P ) 2T = 3PT
which is greater than the original 2PT.
Low-Power Design and Test, Lecture 2
Solution: Part B. Supply Voltage Reduction
When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 2. The time of task is doubled and the total energy consumption is,Energy = (P / 8 + P / 2) 2T = 5PT / 4 =1.25PT
The voltage reduction strategy reduces energy consumption while a simple frequency reduction consumes more energy.Low-Power Design and Test, Lecture 2