Low-Power CMOS Design - 國立臺灣大學access.ee.ntu.edu.tw/course/advanced_VLSI_91/course... · Low Power Design – An Emerging Discipline Historical figure of merit for VLSI

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Low-Power CMOS Design

For Advanced VLSI Design and VLSI Signal Processing Courses

12-04-2002台大電機系吳安宇教授

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 2台灣大學吳安宇教授

Data SourceData Source“Low-power Circuit Design Basics,” by Prof. Jan M. Rabaey, UC Berkerly, in tutorial of ISCAS, London, 1994.“Can we simultaneously achieve High Speed and Low Power in IC Design?” by Prof. Wentai Liu in 7th

VLSI/CAD Symposium, 1996.Chapter 17 of Textbook.



Low Power Design Low Power Design ––An Emerging DisciplineAn Emerging Discipline

Historical figure of merit for VLSI design –performance (circuit speed) and chip area (circuit density/cost). ButPower dissipation is now an important metric in VLSI design.

No single major source for power savings across all design levels – Required a new way of THINKING!!!Companies lack the basic power-conscious culture and designers need to be educated in this respect.

Overall Goal – To reduce power dissipations but maintaining adequate throughput rate.



Motivation Motivation -- MicroprocessorMicroprocessor



Motivation Motivation -- MicroprocessorMicroprocessor



Competitive Reasons Competitive Reasons –– Low PowerLow PowerBattery Powered Systems – Extended Battery Life and reduce weight and size.High-Performance Systems

CostPackage (chip carrier, heat sink, card slots, plenum, …)Power Systems (supplies, distribution, regulators, …)Fans (noise, power, reliability, area, …)Operating cost to customer – Energy Star issue.

ReliabilityFailure rate increase by 4X for Tj @ 110C vs 70CMission critical operation at 100C

Size and Weight – Product footprint (office and deskspace)



The Power Crisis : PortabilityThe Power Crisis : Portability

Expected Battery Lifetime increaseOver next 5 years: 30-40%

PDA, Cellular Phone,Notebook Computer,etc.



A Multimedia Terminal A Multimedia Terminal –– The The InfopadInfopad

Present day battery technology (year 1990) – 20 lbs for 10hrs



IC Design SpaceIC Design Space



Low Power DesignLow Power DesignSource of power disspation

P = Pswitching + Pshort-circuit + Pleakage + Pstatic

Definitions:Switching power P = CV2fαShort circuit power P = IscVLeakage power P = IleakageVStatic power P = IstaticVα : switching activity factor

Low power design would look at the trade-offs of the above issues



Dynamic Power ConsumptionDynamic Power Consumption

Energy/transition = CL * Vdd2Power = Energy/transition * f = CL * Vdd

2 * f

Not a function of transistor sizes!Need to reduce CL, Vdd, and f ti reduce powerReduce the probability, P0 -> 1



Dynamic Power Consumption Dynamic Power Consumption --ExtendedExtended

Power = Energy/transition * transition rate= CL * Vdd

2 * f0->1= CL * Vdd

2 * P0->1 * f= CEFF * Vdd

2 * f

Power Dissipation is Data Dependent Function of Switching Activity

CEFF = Effective Capacitance = CL * P0->1



Ultra Low Power System DesignUltra Low Power System DesignPower minimization approaches:

Run at minimum allowable voltageMinimize effective switching capacitance



ProcessProcessProgress in SOI and bulk silicon

(a) 0.5V operation of ICs using SOI technology(b) 0.9V operation of bulk silicon memory, logic, and processors

Increasing densities and clock frequencies have pushed the power up even with reduce power supply



Choice of Logic StyleChoice of Logic Style



Choice of Logic StyleChoice of Logic Style

Power-delay product improves as voltage decreasesThe “best” logic style minimizes power-delay for a given delay constraint



Power Consumption is Data Power Consumption is Data DependentDependent

Example : Static 2 Input NOR Gate

Assume :P(A=1) = ½P(B=1) = ½

Then :P(Out=1) = ¼P(0→1)

= P(Out=0).P(Out=1)=3/4 * 1/4 = 3/16

CEFF = 3/16 * CL



Transition Probability of 2Transition Probability of 2--input NOR input NOR GateGate

as a function of input probabilities



Switching Activity (Switching Activity (αα) : Example) : Example



GlitchingGlitching in Static CMOSin Static CMOS



At the Datapath LevelAt the Datapath Level……ReusableIrregular



Balancing OperationsBalancing Operations



Carry RippleCarry Ripple



Data RepresentationData Representation



Low Power Design Consideration (contLow Power Design Consideration (cont’’))

(Binary v.s. Gray Encoding)



Resource Sharing Can Increase Resource Sharing Can Increase ActivityActivity

(Separate Bus Structure)



Resource Sharing Can Increase Resource Sharing Can Increase Activity (contActivity (cont’’d)d)



Operating at the Lowest Possible Operating at the Lowest Possible VoltageVoltage

Desire to operate at lowest possible speeds (using low supply voltages)Use Architecture optimization to compensate for slower operation

Approach : Trade-off AREA for lower POWER



Reducing VReducing Vdddd



Lowering VLowering Vdd dd Increases DelayIncreases Delay

• Concept of Dynamic Voltage Scaling (DVS)



Architecture TradeArchitecture Trade--offs : Reference offs : Reference Data PathData Path



Parallel Data PathParallel Data Path



Pipelined Data PathPipelined Data Path



A Simple Data Path : SummaryA Simple Data Path : Summary



Computational Complexity of DCT Computational Complexity of DCT AlgorithmsAlgorithms



Power Down TechniquesPower Down Techniques• Concept of Dynamic

Frequency Scaling (DFS)



EnergyEnergy--efficient Software Codingefficient Software CodingPotential for power reduction via software modification is relatively unexploited.Code size and algorithmic efficiency can significantly affect energy dissipationPipelining at software level- VLIW coding styleExamples -



Power Hunger Power Hunger –– Clock Network Clock Network (Always Ticking)(Always Ticking)

H-Tree – design deficiencies based on Elmore delay modelPLL – every designer (digital or analog) should have the knowledge of PLL

Multiple frequencies in chips/systems – by PLLLow main frequency, ButJitter and Noise, Gain and Bandwidth, Pull-in and Lock Time, Stability …

Local time zoneSelf-TimedAsynchronous => Use Gated Clocks, Sleep Mode



Power Analysis in the Design FlowPower Analysis in the Design Flow



Human Wearable Computing Human Wearable Computing -- PowerPowerWearable computing – embedding computer into clothing or creating a form that can be used like clothingCurrent computing is limited by battery capacity, output current, and electrical outlet for recharging



ConclusionsConclusionsHigh-speed design is a requirement for many applications

Low-power design is also a requirement for IC designers.

A new way of THINKING to simultaneously achieve both!!!

Low power impacts in the cost, size, weight, performance, and reliability.

Variable Vdd and Vt is a trend

CAD tools high level power estimation and management

Don’t just work on VLSI, pay attention to MEMS – lot of problems and potential is great.



ApplicationsApplicationsPortable Multimedia TerminalWireless C&CSystem on Chip (From Dr. Yang of Windbond)



Applications IApplications IWireless Computing/CommunicationWireless Computing/Communication



Applications IIApplications IIA Portable Multimedia TerminalA Portable Multimedia Terminal



Applications IIIApplications IIISystem Value of IC ProductSystem Value of IC Product

Concept of lays



Applications IVApplications IVSystem on ChipSystem on Chip

Entire system functionLogic + MemoryMore than two types of devices

Allow more freedom in architectureConst/Performance trade-off



Applications VApplications VNew Opportunity for Taiwan IC IndustryNew Opportunity for Taiwan IC Industry

PASTDigital ICµPIBM Compatible + MD-DOS

FUTURESystem On Chip

Reduce head-on competition on standard productsTechnology will be availableManufacturing Service availableSame starting point as other countriesCan have more R/D focus

Documents

Low-Power CMOS Design - 國立臺灣大學access.ee.ntu.edu.tw/course/advanced_VLSI_91/course... · Low Power Design – An Emerging Discipline Historical figure of merit for VLSI