Low power chips: A fabless ASIC perspective

Open-Silicon Confidential

Low power chips:A fabless ASIC perspective

Shashank Bhonge and Vamsi Boppana

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2Open-Silicon Confidential

Agenda

► The fabless ASIC model► Power problem and solutions scope► Low power solutions

― Low power system architecture― Low power solutions in the ASIC ecosystem (foundry, IP, pkg)― Low power design implementation― The power of transistors in ASIC

► Combating power variability► Test and power► Representative low power chips► Discussion





What we do

Product Concept

Product Definition

Design Engineering

LogisticsTest Engineering

Wafer Fabrication

Package and Assembly

Custom ASIC





The Open ASIC model

ARM1176

ARM1176Encryption

Engine(~300K g)

OtherFunctionblocks

(~2M g)

2MBSRAM

36KBNVRAM

4MBeDRAM

Serdes controller (~600K g)

16MB

Gb

Ethe

r MAC

DD

R2

10/1

00 E

ther

MAC

USB

2

HD

MI1

.3

PCI2

e ge

n-2

64b AHB

64b AXI

16

16 6G S

erde

s6G

Ser

des ASIC CustomerASIC Customer

Test 1 Test 2 Test 3 Test 4

IP 5 IP 6 IP 7 IP 8IP 4IP 3IP 2IP 1

Fab/Process 1

Fab/Process 2

Fab/Process 3

Fab/Process 4

Package 1 Package 2 Package 3 Other Other





The Open ASIC model

ARM1176

ARM1176Encryption

Engine(~300K g)

OtherFunctionblocks

(~2M g)

2MBSRAM

36KBNVRAM

4MBeDRAM


16MB

Gb

Ethe

r MAC

DD

R2

10/1

00 E

ther

MAC

USB

2

HD

MI1

.3

PCI2

e ge

n-2

64b AHB

64b AXI

16

16 6G S

erde

s6G

Ser




Fab/Process 1

Fab/Process 2

Fab/Process 3

Fab/Process 4


36KBNVRAM





The Open ASIC model

ARM1176

ARM1176Encryption

Engine(~300K g)

OtherFunctionblocks

(~2M g)

2MBSRAM

4MBeDRAM


16MB

Gb

Ethe

r MAC

DD

R2

10/1

00 E

ther

MAC

USB

2

HD

MI1

.3

PCI2

e ge

n-2

64b AHB

64b AXI

16

16 6G S

erde

s6G

Ser


Test 1 Test 2

IP 2IP 1

Fab/Process 1

Package 1 Package 2 Other36KB

NVRAM

Test 1

Test 2

IP 2

IP 1

Fab/Process 1

Package 1

Package 2

Other

OpenModel





Technology trends and challenges





Moore’s law

Intel, Horowitz IEDM 05





Moore’s original issues► Design cost► Power dissipation► What to do with all the functionality possible

ftp://download.intel.com/research/silicon/moorespaper.pdf

Horowitz IEDM 05


ftp://download.intel.com/research/silicon/moorespaper.pdf




Leakage, variability problems today250250

200200

150150

100100

5050

00Unc

onst

rain

ed p

ower

Unc

onst

rain

ed p

ower

TechnologyTechnology0.250.25µµ 0.180.18µµ 0.130.13µµ 0.100.10µµ 0.070.07µµ

Dynamic powerDynamic powerLeakage powerLeakage power

•• Leakage is a growing componentLeakage is a growing component

•• Leakage is extremely sensitive to variationsLeakage is extremely sensitive to variations

•• Leakage is extremely sensitive to temperatureLeakage is extremely sensitive to temperature

Source: Intel, DACSource: Intel, DAC





ASIC power spectrum





ASICs and power efficiency

Energy efficiency (OPS/W)

Flex

ibili

tyGeneral purpose processor

Application specific processor

ASIC





What do we mean by low power

1W-8W

20W-40+W

8W-20W

PowerPower

100mW-1W

>80W! Markets

10uW-100uW

Majority of applications

Large enterprise

Enterprise

ApplicationApplication

Mobile, cellular

Supercomputer

Sensor

A VERY WIDE RANGE OF POWER REQUIREMENTS





Key considerations

1W-8W

20W-40+W

8W-20W

PowerPower

100mW-1W

>80W! Markets

10uW-100uW

Majority of applications

Large enterprise

Enterprise

ApplicationApplication

Mobile, cellular

Supercomputer

Sensor

Perf, pkg

Feasibility, pkg, delivery

Pkg, perf, delivery

Key considerations Key considerations (cost, form factor critical for all)(cost, form factor critical for all)

Battery, perf, pkg

Feasibility of all aspects

Battery, replacement cost





What are the key power contributors?





Key power contributors

• 90G networking ASIC

• Total power: ~25W @ ML• ML: FF, VDD+10%, 125C

• TL: TT, VDD, 125C

• ML/TL Total Power: 1.6x

• ML/TL Leakage Power = 8x!

Power Distribution TL Corner

IO Power

Interface IP Power

Clock Tree power

Logic power

Memory Power

Leakage Power

Power Distribution ML Corner

IO Power

Interface IP Power

Clock Tree power

Logic power

Memory Power

Leakage Power





Low power solutions for fabless ASICs





Why do custom LSIs need lower power than ASICs?► Automated designs are higher power than custom because of …

ASIC design quality► Factor typ xlnt― Microarchitecture (pipelining, parall, bus, mem) ×2.6 ×1.3― Voltage scaling, multi-Vth, multi-Vdd ×4.0 ×1.0― Clock gating and power gating ×1.6 ×1.0― Logic design ×1.2 ×1.0― Logic styles (PTL, domino, …) ×1.3 ×1.3― Technology mapping ×1.4 ×1.0― Cell sizing and wire sizing ×1.6 ×1.1― Floorplanning and placement ×1.5 ×1.1― Process variation and process technology ×2.6 ×1.2

Chinnery et al DAC 05





Getting the lowest power ASIC

Low po

wer

ecos

ystem

soln

(proc

ess,

IP, pkg

)

Low po

wer

desig

n impl.

Transistor-level

techniques!

Low power

system arch

Lowest power ASIC






Low power

ecosy

stem so

ln

(proce

ss, IP

, pkg

)

Low po

wer

desig

n impl.

Transistor-level

techniques!

Low power

system arch

Lowest power ASIC





Choice of foundry, IP, package

► Process Technologies― 0.18u, 0.13u (G, LV, LVOD), 90nm (G, GT, LV),

65nm (G, LP), 45nm (G, LP), …― What is the right node? What is the right flavor?

► Packages― Wafer level CSP, QFP, QFN, QFP, BGA, HSBGA,

CSBGA, Flip-Chip, …― What is the right package for the environment and

power dissipation requirements?― Innovative packages allow significant power tradeoffs





Example Process, IP solutions

Example 65nm data, ARM libs, DesignCon 07

65 GP Process 65 LP Process

StdVt HighVt LowVt StdVt HighVt LowVtDelay [ps]NAND2, with 2x typical load

26.2 34.3 21.0 40.2 56.3 32.6

Dynamic Power [pW/MHz at SS] 1,180 1,180 1,350 1,690 1,690 1,744

Leakage Power [pW @ typ] 16,908 7,560 43,817 458 43 3,673

• Good dynamic power• Leakage very high

• Dynamic power high• Leakage very low

8-track 10-track 12-track

Delay [ps]NAND2, with 2x typical load 28.6 23.6 19.5

Dynamic Power [pW/MHz @ SS] 1,040 1,300 1,450

Leakage Power [pW @ typ] 15,500 20,290 29,500





► Enterprise and Digital Office― CPF SF Advantage-HS 12-track― TSMC 65G Advantage-HS 12-track

► Mobile Applications― CPF LP Metro 8-track with PMK― TSMC 65LP Metro 8-track with PMK― Advantage 10-track or Advantage-HS 12-track with PMK

► High Speed Consumer― CPF SF Advantage 9-track― TSMC 65G Advantage 9-track― UMC L65SP Advantage 9-track

► High Density Consumer― CPF LP Metro 8-track with PMK― TSMC 65G or LP Metro 8-track with PMK

ARM, Chipestimate, DesignCon 07

Example Process, IP solutions





Power tradeoffs: ARM11 example

100

200

300

400

500

600

700

800

900

50 100 150 200 250Dynamic Power (mW)

MH

z

TSMC 65G+

TSMC 65LP

Advantage-HS™ (Speed Opt)Advantage (Speed Opt)

Metro™ (Area Opt)Advantage (Area Opt)

ARM1176JZF-S™

ARM, TI, Open-Silicon, VLSI 08





Low power Analog IP

► Select the lowest power analog IP option― Look for low power architectures

― Analog processing at lower voltages― Driver architectures― Sleep or standby modes for power reduction

― Many times, there is simply not a choice

► Look for Silicon correlation― Analog power is NOT as well modeled/characterized

► Look for adaptive PVT compensation switches





Example low power IP: Std cell PMK

► Normal library + PMK library► Tapless standard cells with separate tap cell► Multi-Vt Library: LVT, RVT, HVT► Supported low power specific cells

― Power gating cells― Header and footer

― Isolation cells― AND-type and latch-type isolation cells

― Always-alive buffers/inverters― Retention F/Fs






Low po

wer

ecos

ystem

soln

(proc

ess,

IP, pkg

)

Low po

wer

desig

n impl.

Transistor-level

techniques!

Low power

system arch

Lowest power ASIC





Low power architecture choices

► Mainly implemented by our customers― Algorithms― Hardware / Software co-partitioning― System-level partitioning

― Analog, digital, DSP, …― Pipelining― Bus architecture― Memory organization

► Jointly implemented by customers and us― Memory organization― Voltage Islands― DVFS― Power gating, Architectural Clock Gating





Memory tradeoffs example

ARM1176

ARM1176Encryption

Engine(~300K g)

OtherFunctionblocks

(~2M g)

2MBSRAM

36KBNVRAM

4MBeDRAM


16MB

Gb

Ethe

r MAC

DD

R2

10/1

00 E

ther

MAC

USB

2

HD

MI1

.3

PCI2

e ge

n-2

64b AHB

64b AXI

16

16 6G S

erde

s6G

Ser




Fab/Process 1

Fab/Process 2

Fab/Process 3

Fab/Process 4


36KBNVRAM





DVFS example: ARM IEM► Batteries have finite amounts of energy stored in them► Running fast and then idling wastes energy

Time

Voltage Reduce VoltageReduce Voltage

ReduceVoltageReduceVoltage

Reduce VoltageReduce Voltage

Task 1 Task 2 Task 3Idle

Only need to run just fast enough to meet the application deadlinesOnly need to run just fast enough to meet the application deadlines

Energy

EnergySaved

Energy

Run Task Slow as Possible

Run Task Slow as Possible

Run Task in Available TimeRun Task in

Available Time






Multi-Voltage Flows

► Multi-VDD Designs― Dynamic power is saved ― Dynamic power is saved, but leakage

power is still dissipated

► Power Gated Designs― Insert high-resistance NMOS cell in

the leakage path― Reduce leakage power by as much

as 20X for ~10% area overhead






Low po

wer

ecos

ystem

soln

(proc

ess,

IP, pkg

)

Low power

design im

pl.Transistor-level

techniques!

Low power

system arch

Lowest power ASIC





It all begins with a

solid methodology foundation





Fixed design methodology

Die Size Estimation

Architectural Exploration

IP SelectionBehavioral

AnalysisPower

AnalysisPackage

Design Options

Analyze Explore Implement Converge Tape-Out

RTL Analysis Partitioning Constraints and Budgets

Initial Synthesis and STADFT Insertion and SimsSynthesis for TimingSTA and Power EstimationInitial floor Plan Power Grid

I/O and Block PlacementPhysical SynthesisClock Tree SynthesisBlock and Top RoutingRC-ExtractionSTA and Noise AnalysisRoute Optimization

(Timing and Noise)Verification (STA, Noise,

FV, PDV)

Finalize Constraints and BudgetFinalize Floor-Plan (Finalize Floor-Plan

(Optimize Block Pin Locs)

Optimized Physical SynthesisSTA (Setup and Hold)Optimize Clock Tree SynthesisSTA (Setup and Hold)Optimize Design for Timing ViolationsBlock and Top Routing Buffer InsertionSTA, Noise, Antenna, IR, Em AnalysisRoute Optimization (Timing, Noise,

Antenna)Verification (STA, Noise,

FV, PDV)

Incremental Floor-Plan Optimization

Incremental Physical SynthesisIncremental Clock Tree

RefinementSTA (Setup and Hold)Incremental Route Optimization

(Timing, Noise, Antenna)RC-ExtractionVerification (STA, Noise,

FV, PDV)

Formal VerificationPhysical Verification (LVS, DRC)Reliability Verification (IR, EM,

ESD)Noise Verification (Function and

Glitch)STA (Setup, Hold, Noise Delay

Push-Out)RC-ExtractionSign-Off Physical and Timing

VerificationStream-Out

One Comprehensive FlowMultiple Checklists

Dedicated Methodology TeamRigorous Revision Control

RTLHandoff

SignoffCheck List

SignoffCheck List

SignoffCheck List

SignoffCheck List

Optional





130nm Design Flow





PDV OK?

Changes @ 65nm

Physical Design VerificationDFM Rule ChecksDRM Repair AnalysisCritical Area Analysis

SimulationSimulation PDV OK?

Signal EM Repair File

Physical Design VerificationDFM Rule ChecksDRM Repair AnalysisCritical Area Analysis

Static timing analysisMulti-CornerMulti-SPEF

Signal EM Repair File

Static timing analysisMulti-CornerMulti-SPEF

Place and RouteMulti-Vt-OptimizationDFM Aware Routing

65nm Standard Design Flow





65nm low power flow

NO MAJOR ADDITIONAL FLOW REQUIRED





65nm multi-voltage flows





Low Power : Synthesis, PD► Clock Gating

► Low power Transformations

► Clock gate cloning





Low Power: Multi-Vt, Multi-VDD

► Sophisticated multi-Vt soln― Proprietary tools

► Isolation Logic Insertion― Power-gated Designs

► Level Shifter Insertion― Multi-VDD Designs

Timing Critical Path

High-Vth CellLow-Vth Cell





Low power signoff► Will you tape-out a chip with 10ps timing violation ? ► Will you tape-out a chip 10 mW higher power ?

► At design start do you know timing target within 5% ?► At design start do you know power target within 20% ?

► How much effort is spent in estimating timing ?► How much effort is spent in estimating power ?

► How much time do you spend in timing closure ?► How much time do you spend in power closure ?





Low power signoff► What corner do you signoff for power?

► Dependence on application, customer methodologies►Example: How do you signoff for DVFS?

► How critical is power signoff?► Temperature Inversion interaction

► Timing analysis at additional corner (slow @ low-temperature) at DSM

► Has more impact forHVT and RVT cells





Signoff level power optimization

► Reduces power on a sign-off ready net list► Implemented as a tool in signoff environment,

accounts for― Electrical design rules― Multiple corners and modes― SI effects

► Last mile optimization





Recent signoff optimization results

6612.87474.820065LP420K10G BLK2

6.146.3378.29 *51890G150KMIPS

65LP

65G

Tech node

3.147.8519557599KMULTI CORE

17.7424.35272201155K10G BLK1

Run time (hrs)

#instDesign Leakage improv(%)

Leakage (mW)

Freq (MHz)

* Data from Zen char






Low po

wer

ecos

ystem

soln

(proc

ess,

IP, pkg

)

Low po

wer

desig

n impl.

Transistor-level

techniques!

Low power

system arch

Lowest power ASIC





Transistor-level work can help bridge the gap► Automated designs are higher power than custom because of …

ASIC design quality► Factor typ xlnt― Microarchitecture (pipelining, parall, bus, mem) ×2.6 ×1.3― Voltage scaling, multi-Vth, multi-Vdd ×4.0 ×1.0― Clock gating and power gating ×1.6 ×1.0― Logic styles (PTL, domino, …) ×1.3 ×1.3― Logic design ×1.2 ×1.0― Technology mapping ×1.4 ×1.0― Cell sizing and wire sizing ×1.6 ×1.1― Floorplanning and placement ×1.5 ×1.1― Process variation and process technology ×2.6 ×1.2

Chinnery et al DAC 05





Leakage mitigation techniques

Non minimum size gate lengths

A Z

VDDB

VSSB

Substrate biasing

A Z

Stack Effect

Power Gating Dual Vt Cell sizing

3x

1x

Lower Operating Voltage

VDD

VSSnSLEEP

Virtual VDD

Virtual VSS

SLEEP

VDD

ABC

Y

Critical Path

ABC

Y

Low VtHigh Vt






ZenCore optimization solutions

ZenTime GT, PTfreq, leakage

ZITO Timing closureZILO Leakage opt

ZLIB

-GT

freq

uenc

y, le

akag

e, c

losu

re

ZITO Timing closure

ZenCore optimization solutions

Can create new cells

Does not createnew cells

Synthesis, physical synthesis

Extraction & sign-off

Design GDSII

Library ConstraintsDesign

Detailed route

State-of-the-art design flow





Critical Paths

ZenCell replacing gate level cluster

abd

ac b a

dc

a

d

y

4 Cells22 Transistors

8 Wires

acd

b

aGate-level view

y

► Critical Logic Analysis► Critical Logic Analysis► Gate Buffering and Sizing► Gate Buffering and Sizing► Gate Clustering► Gate Clustering► TX Mapping and ZenCell Insertion► TX Mapping and ZenCell Insertion

ZenTime optimization





Custom cells: Gain vs. effort

Increasing benefits

Lower effort, gain

Higher effort, gain

Incr

easin

g ce

ll cr

eatio

n ef

fort

GT:COMB. Macro cells

Re-use library layout

Drive strengths

Beta ratios

New functionsNew topologies

LIB ARCH. EXPLORE

Sequential

NON-STATIC CMOS





Custom cells offer power tradeoffs

Generate finer grain drive strengths

Better power vs delay tradeoffs





Combating power variability






► Fundamentally two solution approaches― Design with additional margin― Design with post Silicon tunable structures

► Additional margins getting huge at DSM― 65nm power variation between corners is 20x

► Post Silicon tunable structures offer some attractive alternatives

► Next generation ASICs will need a combination of both






► Post-Silicon tunable structures― Monitors on chip for PVT― Feedback to control circuit behavior based on

feedback form monitors― Two approaches for incorporating feedback

– One time programmable solutions (example: fuse-based) based on Silicon behavior

– On-the-fly tuning based on constant monitoring― Examples

― Adaptive body bias, post silicon tunable buffers, …― Open IP just starting to become available for these

solutions― Example: Analog IP for determining optimal voltage that can

meet a replica critical path speed





Body biasing

► Post-silicon solution to tackle variabilityand high leakage

► Fixed or adaptive biasing― Fixed: A single reverse body bias is applied, and

does not change with time― Adaptive: Body bias changes with time, based on

operating conditions, environment.― Slow down fast, leaky parts so that they leak much

less― Increase % of parts with acceptable speed and low

leakage― Parts at the ML corner will leak less― Controls impact of variability

A Z

VDDB

VSSB





Delay vs. leakage

Leakage vs frequency

0

0.2

0.4

0.6

0.8

1

1.2

0.8 0.85 0.9 0.95 1 1.05

Frequency (normalized)

Leak

age

(nor

mal

ized

)

Typical 65nm gate, fast process, 1.1v, 125C

Bias = 0.0V

0.25V

0.50V0.75V

1.0V

* Does not include next stage gate lkg





Body Bias: Technology considerations► Design impact

― Optimal bias voltage― Multi-Vt impact― Beta ratio impact

► Bias generation circuitry― Max bias current requirements― Generation circuitry

► Physical design― Tapcell design― Bias network design― DCAP impact― ESD impact

► Reliability► Signoff methodology

― OCV impact― Noise impact― Corners― Temp and voltage variation impact

A Z

VDDB

VSSB





Technology node vs. optimal bias

* Does not include next stage gate lkg





Interaction between power and test





Test and power► Test power is often higher than functional power

― Particularly true for low power designs― Clock gates might be ON― All domains might be powered ON― At-speed vectors― Test vectors are typically of much higher activity

► ATPG pattern counts increase at UDSM nodes





Dynamic Shift Frequency Scaling► Exploit the variance in power dissipation!

― Increase shift frequency of patterns with low power dissipation

Original Patterns Scaled PatternsShift Frequency Patterns Shift Frequency Patterns28MHZ 701 28MHZ 11

37MHZ 5452MHZ 47763MHZ 159

Test Time and Cost is reduced by ~45%





Low-power case studies





The next generation low power ASIC!► Will continue to have widely

varying requirements► Power is not a secondary

consideration!► Within the ASIC model, look at

― all levels of abstraction ― all components of eco system

► On-chip structures key to future― Power mgmt, variability

► More transistor work in ASIC than we imagine!

► ASICs continue to deliver substantial power benefits vs. general purpose hardware

Low po

wer

ecos

ystem

soln

(proc

ess,

IP, pkg

)

Low po

wer

desig

n impl.

Transistor -level

techniques!

Low power

system arch

Lowest power ASIC




Documents

Low power chips: A fabless ASIC perspective