Low power ASIC design CSEM/CERN workshop 23 rd May 2013

Low power ASIC designCSEM/CERN workshop23rd May 2013

Copyright 2013 CSEM | Title | Author | Page 2

Agenda

• Microelectronics @ CSEM

• Analogue ASIC design

• Sensor interfaces

• CMOS optical sensors

• Digital design and System-On-Chip

• System-on-chip ASIC design

• Ultra low power embedded processor cores


Low power microelectronics at CSEM

• 30 years history of low power IC design; roots in Swiss watch industry

• Leading edge low-power and low-voltage Analog/Digital IC experience

• Design of complex analog/digital ASICs and System-on-Chip (SoC)

• Team of 65 including 60 experienced designers

• Global ASIC service :

• Design

• Industrialization

• Management of the Production and Test

• Fabless One-Stop ASIC Shop

ULP Microelectronics


Extending battery life


Portable medical

Medical implants

Home automation

AMR

GPS

Consumer

Industrial control


Broad customer baseCSEM introduction

http://www.oclaro.com/index.php

http://www.google.ch/url?sa=i&rct=j&q=&esrc=s&frm=1&source=images&cd=&cad=rja&docid=YkRA44cVeaXdFM&tbnid=KjSQAp-KCDcsiM:&ved=0CAUQjRw&url=http://www.hearflorida.com/hearing-aid-products/phonak-hearing-aids&ei=J4KAUd6kBceskgXpioHACg&bvm=bv.45921128,d.dGI&psig=AFQjCNENhKCtbR3u02vRlLxucMLKqSbUow&ust=1367462818024562

http://www.google.ch/url?sa=i&rct=j&q=&esrc=s&frm=1&source=images&cd=&cad=rja&docid=gm3WrjcR1Vm3iM&tbnid=8bH0P2b-HRB_YM:&ved=0CAUQjRw&url=http://forums.logitech.com/t5/Design-Controllers-and/R400-or-R800-with-Mac-OS-10-5-amp-10-6/td-p/601092&ei=RYSAUYiPMon0lAWz3YGQCg&bvm=bv.45921128,d.dGI&psig=AFQjCNHF5nyAozVSBbsvGsoiiEZHE_3Lrw&ust=1367463340525054


Agenda









MUX

ADCLP

LP

LP

diff

diff

diff

ch. 1

ch. 2

ch. 3

1 2

3

4

Ro

ADC

ADC

2.5MΩ

2.5MΩ

2.5MΩ

16 bits

ch. gnd G(Active ground)

(Lead-off detection)

ch. 123

ADCcomaux

(0.35V)

Vref-cap (0.7V)

VDD-high (~3V)

VDD-low (~1V)

VSS (ground)

(Voltage reference & supply PADs)

(Interface to Icyflex)

1uF

100nF

(150nF)

(150nF)

(150nF)

IcyHeart, ECG Sensor Interface

• Three ECG channels

• Low-noise amplification

• Noise <1uVrms

• BW ~500Hz

• Sigma-Delta ADC

• 12-16 bits

• Lead-off detection

• Active-ground


ECG front-end specifications

Parameter Comments Min Typ Max Unit Supply voltage Analogue low voltage supply

Digital low voltage supply Analogue high voltage supply

0.9 0.9 2.4

1.0 1.0 3.0

1.8 1.8 3.6

V V V

Consumption 3 channels + aux. ADC engaged 1 ADC 1 programmable gain amplifier Active gnd, bandgap buf., biasing

580 830 140 65 75

1’200 uA uA uA uA

Input refereed noise Integrated from 0.67Hz to 500Hz at input of amplification chain at input of ADC

1.2 14

uVrms uVrms

Linearity THD Ampli. G=38dB, input=4mV ADC, input=300mV 200Hz

54 53

dB dB

Input clock from 48MHz quartz, divided by 3 12 MHz Temperature Operating temperature -25 +25 +75 °C Area Estimation 250x4000 um2 1.0 mm2


IcyHeart SoC

• SoC for ECG signal acquisition, processing and RF transmission

• Standard 0.18 μm technology

• Flexible supply voltage 1-1.8 V or 2-3.6 V

• Low power & low noise sensor interface

• Icyflex1 processor

• 868/915 MHz radio

• Low power mode: 1 uA with 32 KHz RTC

• Power management blocks: Vreg, 3xVmult, /2 Vdiv

• Digital peripherals


Capacitive sensor interface

• Sensor interface for MEMS accelerometer

• Makes use of a MEMs designed and fabricated at CSEM

• Closed-loop charge balancing approach

• Bandwidth: 2.5 kHz

• Current consumption: 800 µA

• Acceleration range: +/- 5 g

• Sensitivity: 400 mV/g


Low noise PGA

• Low noise PGA for resistive sensors

• Instrumentation amplifier architecture for high input impedance

• Use of chopper modulation to reduce flicker noise and offset

• Programmable gain: 0.5 to 256

• Programmable offset: 0 to 1 V

• Input range: 1.6 V

• Bandwidth: 25 KHz to 100 KHz

• Input referred noise: 10 µV

• Non linearity: 0.1 %

• Supply voltage: 3.3 V

• Consumption: 500 μA


Front-end for biosensor

• Noise cancelling chopper stabilization front-end for low noise performance

• Input referred noise: 1.8 pA/Hz1/2

• THD improved by 10 dB

• Asynchronous A/D converter for low power consumption

• Activity based operation

• No quantization noise

• Supply voltage: 1.8 V

• Consumption: < 50 µA


Low Power Sensor Interface for PoC Biosensing

• Biomedical sensor interface for DNA biosensing.

• Target application: Point-of-Care personalized patient treatment.

• Features of CMOS sensor interface include:

• Canceling and Chopper Stabilization based front-end amplifier for low power and low noise (1/f reduction).

• Asynchronous A/D Converter for reduced power dissipation and improved SNR.

CMOS Sensing



• 55 µA current consumption from 1.8 V Vdd.

• pA input referred noise current density thanks to canceling and chopping.

• Wide DR front-end (88 dB @ .2 % THD).

• Activity based sampling rate/power consumption thanks to asynchronous ADC operation.

• Increased ADC SNR (17 dB increase over nyquist case) by digital filtering.

AS-ADC

FE

Filter

I2C

Technology 0.18µ CMOS, 1.8V Vdd

Current Consumption 55 µA (FE – 50 µA, A/D – 4 µA) Input Noise 1.7 pA/rt(Hz) PSDDR 88 dB @ THD = .2%BW .3 Hz – 104 HzGain 300 kΩ – 4.28 MΩADC Res., SNDR 8 bit , 67 dB @ FS



67 dB

Measured Input Referred Noise PSD

Digitized ADC output spectrum showing the increase in SNR over nyquist case


Implantable artificial retina

• Battery-less micropower ASIC

• Customer: Nano-Retina


Ultra High Speed RGBW Line SensorHigh-performance image sensors

• Optical 4-line sensor acquiring up to4x 200’000 lines per second (lps)

• Several unique feature

• 4(++) white, red, green blue lines320columns, 24um2 5T pixels

• exposure time per line

• very short shutter time possible(0.5us to 13ms, in 0.2us steps)

• on-chip column parallel CDS and10-bit ADCs (1.2us readout)

• UMC 0.18um CIS with PPD

• 161-pin custom CuLGA

High-speed sensor

High-speed camera prototype

Measured performance small FW large FWconversion gain [e-/DN] 60 400SNR [dB] 46 54DR [dB] 60DSNU1288 <1%PRNU1288 <3%Lag no lag

Custom 161pin CLGA

Moving QR-code acquired @ 200’000lps


High Speed Imaging: Area array Sensors

• Image sensors with a few 1’000 frames/s @ megapixel resolution

• Test sensor with 256x256 pixels and 8’000 fps

• Scalable to 1.3Mpixels, @ 2’000 fps

• Potential applications: Imaging of fast processes in aerodynamics, crash test, ballistics, detection of defects…

High-performance image sensors


Low-Light / High-Dynamic Imager

• 0.18mm CIS technology with buried PD

• 11um2 5T pixel with a spill-over path via Log transistor

• Classical analog-only low-noise on-chip readoutwith external 16bit ADC

• Conv. Factor readout noise overall noisegain = 1 42uV/e- 3.4e- 3.5e-gain = 4 162uV/e- 1.3e- 1.6e-

• Dynamic range > 120dB

• Low power core< 10mW @ 1.8V


Low-light 12mLux scene (16ms texp):(left) Nikon D200 (right) CSEM imager

HDR >120dB scene:CSEM imager


In-pixel amplifying prototype imager

• 0.18mm CIS technology with buried PD

• 11um2 4T pixel with closed-loop resetand open-loop common-source amplifier

• Classical analog-only low-noise on-chip readoutwith external 16bit ADC

• Conv. Factor readout noise overall noisegain = 1 300uV/e- 0.9e- 1.5e-

• Dynamic range73dB linear90dB compressed


(left): low-light image with 6mean / 24max e-

irradiation and column FPN + row

temporal noise correction

(right): raw image with good lighting


Monolithically Integrated, NIR Sensors

• Motivation

• Enhanced NIR sensitivity up to 1600 nm

• Approach

• Ge photodiodes, directly grown on a CMOS chip

• Potential applications: surveillance, 3D imaging with active NIR illumination (OCT/TOF), …

NIR & X-ray imagers


Germanium based monolithic detectors

• Monolithic integration of Ge photodetectors on CMOS demonstrated for NIR application (3 µm layer thickness)

• 64 x 64 pixel NIR image sensor demonstrated with 100 mm X 100 mm pixels

NIR & X-ray imagers


Quantum Efficiency of NIR Image Sensor

Large area test diodes

NIR & X-ray imagers


GeonSi Sensor #10 @ 1300nm, integration time=2.5s, dark image subtracted.

10 20 30 40 50 60

10

20

30

40

50

601300 nm illumination

Sample-Image of NIR Image Sensor

• Illumination with LED at 1300 nm(bandwidth 1250 – 1350 nm)

• No cooling

• Process still under development

NIR & X-ray imagers


CSEM approach to X-ray Detectors

Direct detection with photon counting

combined with

Integrated thick layer of Germanium

good absorption for X-rays (>> Si) higher spatial resolution than CsI no expensive bumping technology monolithic integration for smart sensors

Higher resolutionLower doseSmarter sensorsLower costs

NIR & X-ray imagers


Comparison to Other X-ray Detector MaterialsNIR & X-ray imagers


Germanium based X-ray monolithic detectors

Thick Ge layer epitaxially grown on backside of CMOS wafer

Þ Monolithically integrated direct detector

Þ Challenges: Compatible CMOS process / growth of thick hetero-layers

n- Si

1 Pixel

n+p+

- HV

depletedarea

electricfieldlines

CMOS circuit

X-ray

p- Ge

e hNexray RTD 2009

NIR & X-ray imagers


INNOVATION: Self-aligned epitaxial Ge crystals

Micromachined Si pillars Epitaxial Ge pillars on Si

GeSi

5 mm

Ge

~30 mm No limitation for layer thickness!

NIR & X-ray imagers


Agenda









System on Chip (SOC)

• Beyond state-of-the-art SoC’s…

• …co-integrating a number of innovative digital & analog & RF blocks

Rx/

Tx

AN

A &

P

OW

DSP & DIGITAL& SRAM

Risc DSP, SRAMDMA, IRQ, Timers, RTC

2 x I2C, 2 x I2S, 2 x SPI 2 x UART32 x GPIO4 x PWM, etc

16 MHz RC osc48 MHz Xtal osc32 kiHz Xtal osc

2x step-up conv 1x step-down conv4x Lin Reg 10bit SAADC4 x LED drivers

1V 868/915 MHzRF transceiver



Digital: Ultra low-power processors at CSEM

• Powerful new processors with ultra low power consumption

• icyflex1

• 32-bit dual-MAC RISC processor for DSP and control tasks

• Implemented in several SoCs

• e.g. complete SoC with 150 nA consumption in sleep mode with RTC active

• icyflex2

• Ultra-low power 32-bit RISC processor for control tasks

• e.g. used in a networking device for consumer applications

• icyflex4

• Powerful 32-bit RISC processor for DSP applications

• e.g. for hearing aids and video decoding


icyflex family of processors

• Ultra low power consumption: customizable in VHDL, configurable at run-time

• Full Software Development Kit and Hardware Development Kit

• icyflex1: a flexible processor for DSP/control applications• DSP architecture: 2 MAC

• High parallelism (ex: 2.6k cycles for a 256 FFT)

• 120 µW/MHz at 1.0 V in 180 nm

• icyflex2: a smaller processor for control applications• 32-bit hardware multiplier

• 6 µW/MHz at 1.0 V in 65 nm

• icyflex4: a scalable processor for DSP/control applications• Scalar and Vector processing units. SIMD and MIMD.

• DSP architecture: from 4 to 36 MAC in parallel

• Very high parallelism (ex: 874 cycles for a 256 FFT radix 4, VPS=2)

• As low as 10 µW/MHz at 1.0 V in 65 nm (VPS=2)


icycom SoC – RF & DSP chip

Copyright 2012 | Overview of sector 161 "RF & Analog IC" activities | V. Peiris |

Slide 33

868-915 MHz RF + DSP SoCIcyflex 32bit DSP1V..3.3V3.5mA in Rx, 400kb/sTSMC 0.18um

NDA customer

Snapshots of CSEM RF ICs

Platform for EU projects


• Optical front-end of 320 x 240 pixels (QVGA)

• High Dynamic Range 130 dB (23 bits)

• Digital Log representation of the luminance, contrast and orientations

• 50 MHz 32 bit icyflex uC/DSP

• Programmable with gnu C

A complete low power Vision System on 43 mm2 (~20’000’000 transistors)

Combination of a Digital log pixel array and a 50 MHz DSP system

CSEM Vision SoC: IcyCAM

Digital HDR log pixel array

50 MHz DSP system

Memory

CSEM Centre Suisse d´Electronique et de Microtechnique

Thank you for your attention!

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Low power ASIC design CSEM/CERN workshop 23 rd May 2013