JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.1, FEBRUARY, 2019 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2019.19.1.109 ISSN(Online) 2233-4866

Manuscript received Jan. 10, 2019; accepted Jan. 31, 2019 Electrical Engineering, KAIST, Dae-jeon, Korea E-mail : jaeeun.jang@kaist.ac.kr

Low Power and Accurate Current Driver IC for Electrical Impedance Tomography Applications

Jaeeun Jang and Hoi-Jun Yoo

Abstract—In this paper, a current driver targeting for Electrical Impedance Tomography is proposed. The proposed IC is designed based on active electrode configuration. First, high output impedance current driver is implemented with phase compensation scheme through a delay-locked loop (DLL) to significantly alleviate a phase shift and a required power consumption in the driver. Second, low-power pseudo-sine wave generator is used not only for a low-harmonic distortion but also for a flexible injection frequency utilization. Third, the calibration unit is proposed to compensate injection-current amplitude variations among active electrodes. As a results, the proposed current driver IC guarantees more than 1 MΩ output impedance over a wide range of injection current up to 400 μA and operating frequency from 1 kHz to 5 MHz, only consuming 2.79 mW. Index Terms—Transmitter, digital, differential, termi-nation, inverter-based, low voltage

I. INTRODUCTION

Electrical Impedance Tomography (EIT) has been actively studied for many years as an alternative medical imaging solution. The most attractive point of EIT is that it can provide long-term and continuous patient monitoring based on electrical tissue properties, resulting in harmless measurement process without any ionizing

radiation and high intensity electromagnetic field [1]. Moreover, it can be implemented with small form-factor devices, such as smart belt, so that spatial constraints are dramatically reduced. The conventional EIT [2] system was limited in the bedside monitoring application, but nowadays, portable EIT application is getting more attention for real-time imaging system via its compactness [3].

In the portable EIT system, both low-power consumption and accurate measurement are key requirements since portable EIT system is powered by battery sources, low-power impedance measurement is of significant importance for a longer battery lifetime [4]. Moreover, accurate electrical impedance measurements and well-matched current injections are essential because EIT imaging is based on an inverse problem-solving algorithm which is vulnerable to electrode to electrode variations. Especially, the accurate measurements are hampered by a large number of electrodes unavoidably accompanying long cable length and stray capacitance issue [5]. Therefore, the active electrode configurations directly integrating current driver IC on the electrode are widely applied to mitigate the accuracy issues [6]. In such a configuration, each electrode injects electrical current through its own current driver. Since the accuracy of EIT imaging is directly affected by quality of injection current, high-accuracy and well-matched current driver becomes key-building block.

Consequently, the current driver in the active electrode configuration should satisfy following requirements. First, it has to provide accurate current amplitude under the variation of load impedance. The load impedance varies from hundreds Ω to tens of kΩ with respect to the injection frequency [7]. As shown in Fig. 1, the output

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impedance of current driver should be high enough for accurate current injection. Second, low-harmonic and reconfigurable sinusoidal signal generator that supports wide range of injection frequency (a few kHz to few MHz) needs to be integrated for the simultaneous current injection among various electrodes [8]. Last, the current driver-to-driver mismatch should be minimized for the high image quality.

To tackle the high output impedance issue, the previous work [9] proposed output impedance boosting technique. However, it consumes large power in order to achieve high gain-bandwidth performance under large parasitic capacitances, reducing output phase shift problem [10] at the high frequency signal. In addition, the sinusoidal generator is not integrated with current driver, which leads to its limited usage for EIT application. For a sinusoidal current driver, the previous work in [3] adopts differential sinusoidal current stimulator based on Wien-bridge oscillator, but it cannot cover wide range of frequencies because of its limited tuning scheme. Above all, these previous works have not considered current driver-to-driver matching issues in the active electrode configuration, so that they are not able to correspond to unpredictable current mismatch.

In this paper, we propose a low-power and accurate current driver IC for portable EIT system to fulfill three requirements with following key features. First, phase compensated high output impedance current driver is proposed for both low-power and accurate measurement. Second, low-harmonic pseudo-sine wave generator is integrated for low-power and flexible frequency generation. Third, the calibration unit is proposed for well-matched injection current between active electrodes.

The rest of this paper is organized as follows: In Section II, the basic principle and architecture of propose IC will be introduced. Section III shows detail circuit implementation and Section IV shows the measurement results. Finally, the conclusion will be made in Section V.

II. CURRENT DRIVER ARCHITECTURE

Fig. 2 shows basic principle of current driver. It consists of current sensing voltage feedback topology. Due to its feedback configuration, output impedance Rout is given by

(1 )out o m o sR r G r R= + +

where Gm is transconductance, ro is small signal output impedance, Rs is feedback current sensing resistor, and Rload is load resistance. According to the results, large Gm and ro increase output impedance of current driver.

Fig. 3. shows overall architecture of current driver IC. It consists of current driver, pseudo-sine wave generator, calibration and communication unit, controller, and receiver analog front-end block. Since each electrode

Fig. 1. Receiver front-end block diagram.

Fig. 2. Basic principle of high output impedance current driver.

Fig. 3. Overall Architecture of IC.

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should support both current injection and voltage sensing, the building blocks are connected to switch network. The signal paths are managed by the configuration of switching network. Each IC shares the same global clock received from Hub-SoC. From the global clock, pseudo-sine generator makes differential sinusoidal voltage used as input signals of current driver. From the input sinusoidal wave, the current driver generates sinusoidal injection current. The DLL based phase compensator senses input and output signals of current driver and generates the phase-synchronized I/Q clocks with respect to injection current. These clocks are forwarded to the switch network, and used in the demodulator of receiver analog front-end. Before impedance measurement, injection current from each electrode is equalized through the calibration unit. During the calibration, current paths to electrodes are turned off, and each node sequentially drive current to the reference resistor in calibration unit. The received peak amplitudes of currents are processed through the Hub-SoC and Hub-SoC delivers control code to each pseudo-sine wave generator.

III. CIRCUIT DESCRIPTION

1. Phase Compensated Current Driver Fig. 4 shows proposed current driver architecture [11].

It consists of gain stage with gain A, transconductance stage Gm, differential difference amplifier (DDA), on-chip current sensing resistor Rs with fully differential

configuration and DLL based phase compensator. The gain stage provides enhanced transconductance and loop gain to increase the total output impedance of the current driver. The output current is sensed by Rs and fed back to the gain stage through the DDA. Since common mode voltages in both sides of resistor are not equal, the voltage buffer using DDA maintains output voltage level to VCM. The DDA circuit is shown in Fig. 5, and VCM is set to common mode voltage in the outputs of pseudo-sine wave generators.

With proposed design, a gain-bandwidth requirement remains as a bottleneck for the low-power design. Due to its feedback topology, large bandwidth and phase margin consideration are required for high frequency injection. Moreover, the parasitic capacitance of output nodes contributes to increase input-to-output phase shift in current driver. Since it varies according to real measurement environment, it is hard to estimate parasitic capacitance accurately. As shown in the Fig. 6, to avoid phase shift in higher frequency, overall power consumption of building blocks should be increased.

Fig. 4. Proposed current driver architecture.

Fig. 5. Overall Architecture of IC.

Fig. 6. Overall Architecture of IC.

Hum

an B

ody

Current Driver

ICLKQCLK

PDVctrl

CP

LFVOUTPVOUTN

I

Q

VSIN

Fig. 7. Overall Architecture of IC.

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Fig. 7 shows proposed phase compensator circuit. It has two input signal path. VOUTP, VOUTN are output voltages of current driver and VSINP, VSINN are output voltage of pseudo-sine wave generator. Each input signal is amplified through the identical limiter block. With delay stage, delayed VSINP,N phase information is compared to VOUTP,N phase information in phase detector (PD), and its difference converted to vctrl through the charge pump (CP) and loop filter (LF). After phase locking, accurate in-phase (ICLK) and quadrature-phase (QCLK) are obtained. These clock signals are forwarded to the receiver demodulator. As a result, phase delay of injection current and demodulator is reduced to less than 1 degree in operating frequency range. The additional power consumption of phase compensator is only 120 μW and phase delay from two limiter circuits is negligible.

2. Low-harmonic Pseudo-sinewave Generator

Fig. 8(a) shows pseudo-sine generator with adaptive

quantization scheme [12]. By utilizing adaptive quantization scheme, dominant harmonic components are surpressed at a high frequency, improving power-linearity efficiency. However, because the previous implementation quantizes signal level using only two way, its THD performance is limited. Furthermore, its output impedance is not enough for EIT measurement as sinusoidal current is directly injected through cascoded current driver.

As shown in Fig. 8(b), the improved low-harmonic quantization scheme is proposed. The basic idea is that more LSBs (Least significant bits) are assigned in the peak region of sinewave. For the current amplitude higher than half of the peak current, quantization is fine such that its level is rounded off to the nearest unit current level. For the current amplitude less than half, each of quantization levels are rounded off to the nearest multiple of two or three of the unit current cell. With this configuration, more unit LSBs can be allocated to the peak region. According to simulation results, THD is reduced by 35%, from 0.736% to 0.48%.

Fig. 9 shows circuit implementation. Each unit LSB consists of a current source and NMOS switch pair. To resolve glitches, a latch is inserted before NMOS switches. According to code controller, each current source is turned on and off sequentially. The output currents are converted into voltage through 20kΩ on-chip resistors and forwarded to mixer to generate fully differential pseudo-sine wave. The layouts of resistors and current sources are carefully placed with common centroid configuration

3. Current Mismatch Calibration Unit

In Fig. 10, mismatch calibration scheme is shown.

Since each node consists of active electrode configuration, injection current scale should be matched identically. Before the measurement begins, calibration unit sequentially generates test current and each test current is measured through reference resistor. The measured current amplitude are processed in the Hub-SoC, and calibration codes are fed back to each active electrode IC, so each of injection current scale can be equalized.

The measured performance is summarized in Table 1.

(a) (b)

Fig. 8. Comparison between previous (a) and proposed, (b) low-harmonic quantization scheme.

Fig. 9. Pseudo-sine generator circuit implementation.

Fig. 10. Mismatch compensation scheme.

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IV. MEASUREMENT RESULTS

Fig. 11 shows chip photograph and performance summary table. The proposed current driver IC is implemented in 65 nm CMOS process and occupies 0.99 mm2. It uses 1.2 V supply voltage. The current driver supports current up to 400 μA and its power consumption is 2.42 mW. The measured output impedance is beyond 1 MΩ over wide frequency up to 1 MHz. The current driver maintains phase error less than 1 degree in operating frequency range from 10 kHz

to 5 MHz and pseudo-sine wave generator requires 0.37 mW at maximum frequency.

Fig. 12. shows measured output current peak-to-peak amplitude with different load impedance at 500 kHz. The injected current amplitudes are tested from 24 μA to 400 μA and the measured variation of current is less than 1%. The frequency spectrum of pseudo-sine wave generator is shown in Fig. 13. Thanks to adaptive quantization, low frequency harmonics are effectively reduced and measured THD distortion is less than 0.5% at maximum current injection.

Fig. 14 shows the EIT image results with calibration unit. With off-chip receiver, the proposed current driver

Fig. 11. Chip photo and performance summary.

Fig. 12. Output current amplitude for different load impedance.

Fig. 13. Output spectrum of pseudo-sine wave generator.

Fig. 14. Output spectrum of pseudo-sine wave generator.

Table 1. Comparison Table

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is used for measurement. With calibration unit, clean image is obtained, but with current mismatch, distorted image is obtained.

Table 1 shows the comparison table with previous current driver for EIT application. The proposed IC is the first work that fully integrates sine-wave generator in active electrode configuration.

V. CONCLUSIONS

In this paper, a current driver IC for portable EIT system with low-power and high accuracy is proposed. For the high output impedance current driver, DLL based phase compensator is proposed. It releases phase shift issue significantly with low-power consumption. For the low-harmonic and flexible injection frequency, pseudo-sine wave generator is adopted. Also, the calibration unit is proposed to compensate current variations among active electrodes. As a result, the proposed IC satisfying more than 1 MΩ output impedance in wide frequency range of injection current while consuming 2.79 mW only.

ACKNOWLEDGMENTS

This work was supported by Institute for Information and Communications Technology Promotion (IITP) grant funded by the Korea Government (MSIT) (R7117-16-0169)

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Jaeeun Jang received B.S. and M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2014 and 2016, where he is currently working toward the Ph.D. degree. He has worked on

developing a low-power wireless transceiver and low-power sensor front-end. His current research interest includes low-power transceiver design for body-area -networks and low-power biomedical SoC design.

Hoi-Jun Yoo received the bachelor’s degree from the Electronic Department, Seoul National University, Seoul, South Korea, in 1983 and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science

and Technology (KAIST), Daejeon, South Korea, in 1985 and 1988, respectively. Since 1998, he has been the Faculty Member with the Department of Electrical Engineering, KAIST, where he is currently a Full Professor. From 2001 to 2005, he was the Director of the Korean System Integration and IP Authoring Research Center, Seoul. In 2007, he founded the System Design Innovation and Application Research Center at KAIST. Since 2010, he has been serving as the General Chair for the Korean Institute of Next Generation Computing, Seoul. He has authored and co-authored DRAM Design (South Korea: Hongrung, 1996), High-Performance DRAM (South Korea:Sigma, 1999), Future Memory: FRAM (South Korea: Sigma, 2000), Networks On Chips (Morgan Kaufmann, 2006), Low-Power NoC for High-Performance SoC Design (CRC Press, 2008), Circuits at the Nanoscale (CRC Press, 2009), Embedded Memories for Nano-Scale VLSIs (Springer, 2009), Mobile 3-D Graphics SoC From Algorithm to Chip (Wiley, 2010), Biomedical CMOS ICs (Springer, 2011), Embedded

Systems (Wiley, 2012), and Ultra-Low-Power Short-Range Radios (Springer, 2015). He has published more than 400 papers and his current research interests include artificial intelligence, computer vision system-on-chip (SoC), body area networks, and biomedical devices and circuits. Dr. Yoo was a recipient of the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, the Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, the Best Research of KAIST Award in 2007, the Scientist/Engineer of this month Award from the Ministry of Education, Science and Technology of Korea in 2010, the Best Scholarship Awards of KAIST in 2011, and a co-recipient of the ASP-DAC Design Award 2001, the Outstanding Design Awards of 2005, 2006, 2007, 2010, 2011, and 2014 A-SSCC, and the Student Design Contest Award of 2007, 2008, 2010, and 2011 DAC/ISSCC. He received the Order of Service Merit from the Ministry of Public Administration and Security of Korea in 2011. He has served as a member for the Executive Committee of ISSCC, the Symposium on VLSI, and A-SSCC, and the TPC Chair of the A-SSCC 2008 and ISWC 2010, the IEEE Distinguished Lecturer from 2010 to 2011, the Far East Chair for the ISSCC from 2011 to 2012, the Technology Direction Sub-Committee Chair for the ISSCC in 2013, the TPC Vice Chair for the ISSCC in 2014, and the TPC Chair for the ISSCC in 2015. From 2003 to 2005, he was the full-time Advisor to the Minister of Korea, Ministry of Information and Communication, and National Project Manager of SoC and Computer.