Arasan Confidential 6/27/2012

Low Latency Interconnect

(LLI)

Jun 20, 2012

Authored by Ajay Jain (Arasan)

Presented by Wolfox Yang (Avant Tech)

Arasan Confidential

Arasan’s MIPI Compliant IP Portfolio

Antenna

Digital

Baseband

Processor

Co-processor

Applications

Processor

SPMI LLI

CSI-2

CSI-3

DSI

DSI-2

HSI

LLI

DigRF3G

DigRFv4

SLIMbus

Camera

Display

Flash

Memory

Available Future

RFIC

Digital Back End

Analog Front End

RFFE

Requires D-PHY Requires M-PHY

Audio Codec

Arasan Confidential

Application SW

Operating System

Ara

sa

n

SW

IP

Software Stack

RFFE HSI SLIMbus UniPro

Ara

sa

n

Ho

st

IP CSI-2

Controller DSI

Controller

RF

FE

C

on

trolle

r

HS

I C

on

trolle

r

SL

IMbu

s

Con

trolle

r UniPro Controller

D-PHY

Standard Interfaces

Ara

san

D

evic

e I

P A

ras

an

Veri

ficati

on

IP

Ara

san

Hard

ware

Valid

ati

on

Pla

tfo

rm

Delivered as a Total IP Solution

D-PHY M-PHY

LLI Controller

M-PHY

CSI-2 Controller

D-PHY

DSI Controller

D-PHY

RF

FE

C

on

trolle

r

HS

I C

on

trolle

r

SL

IMb

us

Co

ntr

olle

r UniPro

Controller

M-PHY

LLI Controller

M-PHY

Arasan Confidential

Baseband/AP Interconnects of Today

6/27/2012

Baseband

Processor

Applications

Processor HSI

• 200 Mbps in each direction

• Digital PHY, with 2 serial data lines, 1 clock, and 6 control signals

• Up to 8 virtual channels in each direction

• High priority traffic (like voice call) prioritized on dedicated virtual channel

DRAM DRAM

HS

I C

ontr

olle

r H

SI C

ontro

ller

Control

Data

Clock System Master System Slave

Arasan Confidential

Baseband/AP Interconnects of Tomorrow

6/27/2012

DRAM

.

.

. LLI

Lane 0

Up to Lane 5

• DRAM resources shared between two chips

• Up to 6 data lanes transferring data at up to 2.9Gbps each in either direction

• Analog PHY’s (MIPI M-PHY Type 1) with 100 – 400 mV differential signaling

• Bandwidth is great, but what about low latency needs for cache refills …

• While we think about it, how will voice calls be given priority …

Baseband

Processor

Applications

Processor M

-PH

Y

M-P

HY

M-P

HY

M

-PH

Y

.

.

.

.

.

.

LLI

Contr

olle

r LLI C

ontro

ller

Arasan Confidential

Low Latency Behind the Scenes

6/27/2012

• LLI Controller considered a device resident on the interconnect

• One chip, typically Apps Processor, is designated System Master • Manages overall system memory map

• Each device on the interconnect of one chip mapped to memory address space of other chip

• Inter-chip traffic classes defined to enable software programmable prioritization

• Low Latency Traffic Class applies to • Cache updates for Baseband

• Transfers of audio/video data for voice and video calls

• Best Effort Traffic Class applies to everything else

• Intra-chip prioritization handled by your existing local interconnect infrastructure

DRAM

.

.

.

LLI

Lane 0

Up to Lane 5

Baseband

Processor Applications

Processor

M-P

HY

M

-PH

Y

M-P

HY

M

-PH

Y

.

.

.

.

.

.

LL

I C

on

tro

ller

LL

I Co

ntro

ller

Interconnect

CPU + Cache

IP’s (Devices)

Interconnect CPU +

Cache

IP’s (Devices)

Memory Controller

System Master System Slave

Arasan Confidential

Controlling the LLI Infrastructure

6/27/2012

• LLI standard provides for Service Transactions for

• Local and remote LLI device configuration and status reporting

• Power Management

• Sideband Signaling

• All this performed under software control executing in System Master’s CPU

DRAM

.

.

.

LLI

Lane 0

Up to Lane 5

Baseband

Processor Applications

Processor

M-P

HY

M

-PH

Y

M-P

HY

M

-PH

Y

.

.

.

.

.

.

LL

I C

on

tro

ller L

LI C

on

trolle

r

Interconnect CPU +

Cache

IP’s (Devices)

Interconnect CPU +

Cache

IP’s (Devices)

Memory Controller

Service

Service

System Master System Slave

Arasan Confidential

Inside the LLI Controller

6/27/2012

• Each LLI Controller is an OSI-conformant layered protocol model

• As transmitter

• Frames transactions received from interconnect

• Distributes byte or symbol streams to M-PHY’s

• M-PHY’s serialize symbols and transmit as differential signal pair

• Reverse function as receiver; error handling managed between LLI Controllers

DRAM

.

.

.

LLI

Lane 0

Up to

Lane 5

Baseband

Processor Applications

Processor

Interconnect CPU +

Cache

IP’s (Devices)

Interconnect CPU +

Cache

IP’s (Devices)

Memory Controller

Service

Service

.

.

.

M-P

HY

_0

M-P

HY

_5

LLI Slave Controller

Inte

rconnect

Adapta

tio

n L

ayer

Tra

nsactio

n L

ayer

Data

Lin

k L

ayer

PH

Y A

dapte

r Layer

Sideband/ Power Mgmt

.

.

.

M-P

HY

_0

M-P

HY

_5

LLI Master Controller

Inte

rconnect A

dapta

tion L

ayer

Tra

nsactio

n L

ayer

Data

Lin

k L

ayer

PH

Y A

dapte

r Layer

Sideband/ Power Mgmt

System Slave System Master

Arasan Confidential

Architectural Tradeoffs

6/27/2012

DRAM

.

.

. LLI

Lane 0

Up to

Lane 5

Baseband

Processor Applications

Processor

Inte

rconnect

IP’s

(D

evic

es)

Inte

rconnect

IP’s

(Devices)

Memory Controller

.

.

.

M-PHY_0

M-PHY_5

D

F

E

A

F

E

LLI Slave Controller

D

F

E

A

F

E Inte

rconnect

Adapta

tio

n L

ayer

Tra

nsactio

n L

ayer

Data

Lin

k L

ayer

PH

Y A

dapte

r Layer

.

.

.

M-PHY_0

M-PHY_5

D

F

E

A

F

E

LLI Master Controller

D

F

E

A

F

E

Inte

rconnect A

dapta

tion L

ayer

Tra

nsactio

n L

ayer

Data

Lin

k L

ayer

PH

Y A

dapte

r Layer

System Slave System Master

Bu

s M

aste

r

or

Sla

ve o

r

Bo

th f

or

LL

Tra

ffic

Cla

ss

Bu

s M

aste

r

or

Sla

ve o

r

Bo

th f

or

BE

Tra

ffic

Cla

ss

Bu

s M

aste

r

or S

lave o

r

Bo

th fo

r LL

Tra

ffic C

lass

Bu

s M

aste

r

or S

lave o

r

Bo

th fo

r BE

Tra

ffic C

lass

• Configurable Interconnect Adaptation Layer can behave as either Bus Master or Slave for both Low Latency or Best

Effort traffic classes on either chip

• Bus type, data width, and bandwidth requirements configurable to match interconnect requirements

• Configurable memory map of devices on System Master and Slave

• By default only one clock domain crossing

• Latency/bandwidth/area/power tradeoffs

• Configurable number of bytes or symbols transferred across PHY interface

• Number of PHY lanes configurable

• Most LLI implementations expected to run with M-PHY Gear 2 (2.5 – 2.9 Gbps)

Arasan Confidential

M-PHY / LLI Interdependence

6/27/2012

• M-PHY is different from traditional SERDES; optimized for mobile applications

• Switchable between various speeds and power modes depending on

• Bandwidth requirements

• Application

• Presence of traffic

• LLI controller needs to be M-PHY compatible and vice versa

• M-PHY managed by upper protocols layers of LLI under software control

• LLI controller needs to be able to control multiple lanes of M-PHY

• LLI spec requires test mode features in PHY Adapter Layer to

• Execute Tx and Rx conformance tests with the M-PHY(s)

• Arasan went the extra step to architect LLI controller and M-PHY in configurable

fashion to meet different customer needs

• Digital portion configurable to match LLI controller

• Analog portion optimized for minimum area and power

Arasan Confidential

Customer Enablement

6/27/2012

• Consider LLI as a bridge between interconnect infrastructure of two chips • Allows transaction exchanges with minimal software intervention

• Planning and measurement of architectural tradeoffs • Area, power, throughput, latency

• Rapid configuration of IP’s to integrate into your design

• Verification environment with configurable, reusable verification components

• Hardware validation platforms to emulate “other chip” for • Validation

• Interoperability testing

• Software development

• Documentation for LLI Controller and M-PHY • MIPI Alliance membership to get standards specification

• Datasheets from www.arasan.com

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