Low-cost and high-quality method of outline font transformation

Electronics and Communications in Japan, Part 2, Vol. 79, No. 8, 1996 Translated from Denshi loho Tsushin Gakkai Ronbunshi, Vol. 78-C-11, No. 10, October 1995, pp. 506-512

Low-Cost and High-Quality Method of Outline Font Transformation

Hiroshi Wada

Information Systems R & D Division, Hitachi, Ltd., Yokohama, Japan 244

Shinji Wakisaka, Hiroko Sato, and Shigeo Hayashi

Semiconductor & Integrated Circuit Division, Hitachi, Ltd., Kodaira, Japan 187

Norio Kiriyama

Information & Image Systems Division, Hitachi, Ltd., Hitachi, Japan 316

SUMMARY

The outline font is used widely in operational amplifier (OA) equipment since the expansion and modi- fication of a character can be realized with a high quality. The authors developed a system which realizes LSI with a low cost that can expand the outline font with a high quality, aiming at the installation on a lowcost note-type word processor. The proposed system executes the character correction, the affrne transformation, the third-order Bezier curve interpolation, the outline generation, the painting, and the memory clear processings which are needed in the outline font expansion.

The processings are divided into two blocks from the viewpoint of the processing time, and the blocks are processed by a pipeline. The vertical/h:wizontal scaling of the character is indispensable as a function of the word processor. The vertical5orizontal operation is included in the operation matrix of the affine transformation, which helps to suppress the increase of the processing time.

To cope with the fluctuation of the line width due to the operation error, a powerful character correction function is installed in order to improve the quality. By those considerations of the architecture, all outline font expansion processings are installed on the single-chip MI, which is realized on 8.5 mm X 8.5 mm, by CMOS 1.0-pm process. The expansion speed of 860 character& (64 X 64 dot) is realized.

Key words: Outline font; LSI; affme transformation; character correction.

1 . Introduction

In recent years, the desktop publishing (DTP) is used widely in operational amplifier (OA) equipment, which is an electronic editing system including characters and figures. A rapid improvement in the resolution is observed in the output devices such as printer.

84 lSSN8756-663X/96/0008-0084 @ 1996 Scripta Technica, Inc.

Accompanying this trend, a more sophisticated graphical user interface (GUI) is required. Instead of the conventional dot font, where the image quality is deteriorated with a ug-zag contour when the character is ex- panded or contracted, the outline font, which c a ~ ~ generate characters with various sizes and modifications wieh a high quality, is now installed as the standard function in the expensive printer, such as the laser printer [l]. This trend gradually is prevailing in the printer of the

Painting

memory Affine Trans.: Affine Transformation Char Comct.: Character Correction Mem Clr: Memory Clear

low-cost word processor. At present, the outline font is installed as a standard function in most models.

In order to generate. the bitmap for printing from the outline font, several transformations as follows must be applied. There must be the affine transformation to execute the expansion and contraction, as well as to generate italics. The character correction is to adjust the line width in detail. The third-order Bezier curve interpolation gives a smoothness to the character [2]. The line generation function is to generate the outline to define the contour of the character. The painting is the processing to paint inside the contour. Finally, the memory clear function is to clear the used memory. Thus, a large amount of processing is required in the expansion of the outline font and speed improvements for those processings are required.

Another aspect is that the cost is reduced rapidly in recent OA equipment, and this is an important requirement in the design. In addition, the quality of the character is important in making the design significant on the market. At the present stage, the performance requirement for the outline font expansion in the highest-speed printer of the word processor (three-line parallel printing) i:; around 600 charactersls. It is required to produce the compact outline font expansion LSI that satisfies this performance requirement and has a small chip size.

Up to present, Kawada et al. developed the outline font expansion LSI with built-in RISC-type CPU and realized the performance of 500 characteds [4]. A problem is that the chip size is large, being 9.47 X 9.24 mm (0.8-pm CMOS), which is not sufficient to contrib- ute to the cost reduction of the OA equipment. Kai et al. implemented only a part of the outline font expansion processings (third-order Bezier curve interpolation, outline generation, and painting) on LSI and realized the expansion performance of approximately 4OOO characters/s [5, 61. The processing which is not included in LSI must be handled by CPU. Because of this situation, the system performance is deteriorated to 100 charactersh, which cannot satisfy the requirement for the performance as the word processor. From such a viewpoint, in this

Fig. 1. Architecture for fastest processing.

study it is intended first to develop the outline font expansion LSI, which is compact and satisfies the requirement for the performance and the character quality.

To reduce the chip size, the operational unit (arith- metic logical unit, ALU, register and shifter) as well as first-inlfirst-out (FIFO) memory are shared as much as possible in order to reduce the number of stages in the parallel processing (pipeline). To cope with the performance deterioration due to the reduction of the pipeline stages, a high-speed algorithm is devised. In addition, the character quality is improved by devising the character correction algorithm. This paper describes the reduction of the chip size, the improvement of speed, and the improvement of the character quality, which are considered in order to achieve the above requirement.

2. Consideration of Architecture Design

When the chip size is reduced by reducing the number of stages in the pipeline, the performance is deteriorated since the number of parallel processings is reduced. To suppress the performance deterioration within the specified range and to reduce the chip size, there must be an investigation of the size reduction and the speed improvement aiming at the realization of the required performance in the design for the architecture. The results of those investigations are described in the following.

2.1. Reduction of chip size

As already discussed in the previous section, a series of expansion processings, from the affine transformation to the memory clear, is required in order to expand the outline font. Those processings are indepen- dent. Consequently, the method generally known to

85

Control Unit I

Fig. 2. Internal archltecture of each block. .

Anme Tr

Char Cor

Bezier Curve

Line 4800 Painting

Memory Clear

Fig. 3. Steps of each function.

Table 1. Area percentage of each unit

improve the speed is to handle those processings as blocks and to form a pipeline by placing FIFO between the processings. In addition, the memory for the character pattern generation is included. When the configuration such as in Fig. 1 is employed, however, the chip size is expected to be enlarged. According to an estima- tion of the chip size by the design tool, the size well exceeds 10 mm X 10 mm. In order to realize the Affine Trans. block in Fig. 1 by a circuit, there must be the operation unit (execution unit, EU, such as ALU, multi- plier, register, and shifter) and the control unit to control those.

The Char. Correct and other blocks are of essen- tially the same configuration as in Fig. 2, except for some structure of the details. The area of each unit on the chip is calculated, and the effective method of relative area reduction is investigated. It is seen from the result of relative area calculation shown in Table 1 that FIFO + EU (execution unit) occupies more than 50 percent of the whole area. Consequently, it is expected to be important in reducing the size of the chip to reduce FIFO and share EU by more than one block. When an EU is shared by two blocks, for example, a size reduction of more than 25 percent can be expected. Which EU should be shared effectively among the four blocks shown in Fig. 1 is examined from the viewpoint of the overall performance.

Affine Trans. Char Correct. Painting Bezier Curve Memory Clear

FIFO

AEne Trans.: AtTw Transformation -1 Char Correct.: Character Correction

Fig. 4. Optimized architecture.

When more than one block is operated asynchron- ously through FIFO, the overall performance is determined by the performance of the slowest block. Con- sequently, it is most effective to design so that all blocks have nearly the same performance. The processing flow is constructed for each expansion processing. The algorithm is analyzed in detail and the required number of steps is estimated. Figure 3 shows the result of calculation.

There are 6900 steps in total for the affine transformation, the character correction and the third-order Bezier curve interpolation. The total number of steps for the outline generation, the painting, and the memory clear is 7200. Thus, as is seen, the two are almost equal. Consequently, it is intended to construct the blocks of the proposed LSI BS in Fig. 4. In other words, the architecture is composed of two blocks plus the memory for the character pattern generation. The former block is to execute the affine transformation, the character correction, and the curve interpolation; and the latter block 1s

to execute the outline generation, the painting, and the memory clear.

The printing performance is estimated roughly for this configuration. The result is 430 characterds (64 x 64 dot), which does not meet the requirement for the

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Laser Printer t Display Word Processor

Fig. 5 . Format of bitmap data.

performance of the word processor, i.e., 600 charac- tcrs/s. In the case of this LSI, however, it is anticipated that the performance deterioration due to the reduction of the pipeline stages can be compensated by the speed improvement discussed later. Consequently, the architecture of Fig. 4 is employed.

2.2. Improvement of speed

To improve the expansion performance, B series of processings in the word processor, from the outline font expansion to the printing, are examined anew and the neck that deteriorates the throughput most is pointed out. As is shown in Fig. 5 , the format for the bitmap data for printing is different in the laser printeddisplay and the word processor. In other words, the increment direction of the memory address is horizontal in the former and vertical in the latter.

The outline font is applied starting from the field of the laser printer. Consequently, the standard is the format for the laser printer. In the case of the word processor, the bitmap data for the laser printer is once generated and then is converted into the bitmap data for the word processor. This conversion forms the neck for the throughput.

From such a viewpoint, the series of outline font expansion processings from the affine transformation to the painting are examined and a method is devised that can directly generate the bitmap data for the word processor printer. The details of the method are shown in the following. Comparing the formats of the bitmap data shown in Fig. 5 , it is seen that the shape of the character is entirely the same, The only difference is the increment direction of the memory address. Then, it is intended to execute the process by utilizing the transformations main- taining the character shape, such as the rotation and the reversal of X or Y axis, using the affine transformation

Rot. : Rotation Y.A.R : Y Axis Reversal

Fig. 6. How to make bitmap data directly for word processor.

function installed on the proposed LSI. Figure 6 shows the details of the investigation of this point.

Figure 6(a) shows the outline font data for the laser printer. The font data usually are prepared for the laser printer. By applying the rotation of 90 deg to the font data of Fig. 6(a), Fig. 6(b) is obtained. By inverting Fig. 6(b) in regard to Y axis, Fig. 6(c) is obtained. Figure 6(d) shows the data for the word processor. By comparing the addresses 1, 2, 3, ... in Figs. 6(c) and (d), it is seen that they are completely the same. The affine trans-

formation usually is executed by a matrix (: :) I71.

If the 9Odeg rotation and the inversion in regard to Y axis are executed at the same time, the printing data for the word processor printer are obtained. The matrices can be integrated; and, by integrating the matrices for the inversion in regard to Y axis, the 90-deg rotation and the

ordinary affine transformation as

(: i) = (z i), the data for the word processor

printer can directly be generated.

The above reasoning can be summarized as follows:

d X (::) = (: )( I.) ... affine transformation for

word processor

In other words, no complex procedure is needed. Only by a and c, as well as b and d, in the affine transformation, the matrices are exchanged. Then, the printing data

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Table 2. Direction table

pN- 1 P" pN+ 1

Fig. 7. Concept of correction method.

for the word processor can be generated very simply and with a high speed. By this method, the processing time for a character can be reduced from 2.33 ms to 1.16 ms.

It may be possible to exchange X' and Y' after the transformation, but the above method is employed con- sidering the future extension. The reason is as follows. The technique is expected to be applied not only to printing but also to the screen display in the future. Then, it is required that the same LSI should be used to generate alternately the bitmap data for printing and for display. If the method is fixed to the method that exchanges X' and Y', it will become difficult to generate the bitmap data for display. By contrast, the proposed LSI can easily generate the bitmap data for the two formats simply by replacing the matrix according to the format to be generated. In other words, the proposed method is more versa- tile than the method that exchanges X' and Y'.

3. Improvement of Character Quality

The outline font has a problem in that the character may be smashed or the line width may become varied due to the operation error when small characters are generated. In order to cope with such phenomena, there must be the processing to thin the line to prevent the smashing and the processing to adjust the line width. Those processings are important in guaranteeing the character quality. In the following, the two character correction algorithms included in the proposed LSI are outlined .

3.1. Line thinning algorithm

In order to prevent the smashing of the character, the linewidth must be reduced in general. In the proposed LSI, a method is employed where the point pair pN(xN, y N ) for the correction as well as the relative location o f the coordinate data p N - l ( x N - 1, y N - 1) and p N +

l ( x N + I , yN + I) around pN points are used to calculate the pointpN' ( x N ' , yN') after the correction as shown in

: pN

Fig. 8. Movement method in each line type.

Fig. 7. The relative location between p N and pN - 1, p N + 1 is determined whether pN is an increase or decrease from pN - 1 in X and Y directions as well as its relation to p N + 1. As is shown in Table 2, 4-bit register for X P , X M , YP, and YM4 is prepared; 1 is set in X P if there is an increase in X direction, and 1 is set in XM if there is a decrease. A similar processing is applied to Y direction. In order to decide whether there is an increase or decrease, it suffices to execute the subtraction of coordinates (xN - xN - 1); X P - YM for pN - 1 as well as XP- YM for p N + 1, i s . , 8 bits in total, are used to

determine the relative location.

Based on the relative location, the kind of the line is determined. The point to make the correction is shifted by the necessary distance along the necessary direction, as is shown in Fig. 8. In Fig. 8, the horizontal line ( I ) and the vertical line (11) are shifted to the inner direction by n along the X or Y direction. In the case of the slant line (Ill), however, the point must be shifted both in the X and Y directions. If the shift distance is set as N both for the X and Y directions, the actual distance of shift is

88

Table 3. Sample of correction table

0 1 0 1 t h - h t h -0

0 -- n

I / I 0 t /I t (1

0 0 t / I h

/ I (1

I decimal 1 move register integer A -

Before Correction After Correction

Fig. 9. Sample of bad correction.

, ~ Z ( I , which makes the line too thin. Consequently, the distance of the shift is set separately for the horizontal/ vertical lines and for the slant line. The shift distance registers for the horimntal/vertical lines and the slant line inside of the LSI are provided, where the necessary values are set.

In this LSI, the point to be corrected is shifted according to the rules shown in Table 3. The kind of the line is decided based on 8-bit XP- M. Then, the point is shifted by the specified amount. The line indicated by the arrow in Table 3, for example, corresponds to (111) of Fig. 8. In this case, the point is shifted by +b along the X direction and by -b along the Y direction. Only a part of the table is shown in Table 3, but the table actual- ly is composed of 8 x 8 = 64 shifting rules.

The calculation for the values to be set in the shift distance registers for a and b is described using Fig. 9. The outline font data usually are composed as a large size (such as 256 x 256 dot). Consider the situation

I Y Coordinate value

Fig. 10. Sample of coordinate data.

where a character of 53 x 53 dot size is to be generated from this font data. When the point to be corrected is to be shifted by a dot in 53 x 53 dot character, the number of dots is calculated by the ratio to the 256 x 256 dot pattern (a x 256/53) and the result is set in the shft distance register in the figure. The reason for calculating the number of dots by the ratio to the size before the reduction is as follows.

When the size is reduced, i t may happen that origi- nally separated segments stack due to the calculation error in the affine transformation. When the point is shifted by each dot after the reduction, it may happen, as in the example shown in Fig. 9, that the vertical order is reversed. In order to prevent such a situation, the amount of shift distances is set and the points are shifted before the reduction, so that the vertical or horizontal orders are not reversed. Then the case of order reversal can completely be eliminated, even though there may remain a case where the segments stack after reduction.

3.2. Line width correction algorithm

In order to represent the kanji which has a large number of horizontal and vertical lines, the widths of those lines should be adjusted. In this LSI, the correction information is attached to every coordinate and the line width is adjusted based on the attached information.

As is shown in Fig. 10, the correction information is attached beforehand, preceding the coordinate data. The correction number (X, Y Correction No.) is stored as the correction information. In the X and Y correction numbers, the desirable widths of the horizontal and vertical lines in 53 x 53 dot size are stored. Five line width registers (LWRl -5) are provided in each LSI, as shown in Fig. 11, which set the required line width before generating the characters. It is set, for example, that LWR = 1, LWR2 = 2, and -LWR5 = 5. LSI aligns the line width to the value in LWR corresponding to the correction number. When the correction number is 3, for example, the line width is aligned to the value set in LWR3.

89

LWRB LWR4 LWR5

Fig. 11. Line width register.

Fig. 12. Sample of line-width correction.

The situation is described for the case shown in Fig. 12, where the widths of the horizontal and the vertical lines are to be corrected to 2 and 3 dots, respectively; P 1P2, P 2 P 3 , P 3 P 4 , and P 4 P 1 are segments to be used as the reference. Consequently, none of the points P 1, P2, P3, and P 4 is corrected; 0 is stored as the correction number for the coordinate which is not corrected. By contrast, P 5 P 6 must be corrected to 2 dot in regard to P 1P2, and P 8 P 5 must be corrected to 3 dot in regard to P 4 P 1. For this purpose, 2 and 3 are already stored as X and Y correction numbers for P 5 , respectively. Then, the coordinate of P5 is forced to be modified as P5' (P1X + LWR3, Ply + LWR2) = (P1X + 3 , P 1 Y + 2), where P 1X and P 1 Y are X and Y coordinates of P I , respectively. Similarly, P 6 , P 7 , and P 8 are modified as P6'(P2X - LWR3, P2Y + LWR2), P7'(P3X - LWR3, P3Y - LWR2), and P8'(P4X + LWR3, P 4 Y - LWR2), respectively. Then, the line widths of all horizontal and vertical lines are adjusted to 2 and 3 dot, respectively. Whether the value of LWR is added or subtracted is determined based on the magnitude relation between the coordinate before correction and the coordinate of the reference line.

Thus, using the correction numbers and the line- width registers, the widths of the horizontal and the

1

Correction NO Correction

Fig. 13. Print sample.

Fig. 14. Layout of outline font transformation LSI.

vertical lines can be adjusted to arbitrary values. When the correction is to be applied to the size other than 53 x 53 dot (such as 64 X 64), the line width can be corrected according to the output size, by adjusting the value of the line-width register according to the size ratio.

Figure 13 shows the samples of printed characters for the case where the line thinning is applied and not applied. As is seen from the figure, the line width is better adjusted and a thin and fine character is obtained by applying the line width correction, compared to the case without the correction.

4. Performance and Scale of Proposed LSI

By optimizing the archittxture described up to this stage, a series of outline font expansion processings is contained in a single-chip LSI with a very compact size of 8.5 x 8.5 mm using l.O-pm CMOS process. The s i x is estimated as 10 x 10 mm or more before the architecture is optimized. In other words, the s i x is reduced by approximately 30 percent. The speed is improved by improving the affine transformation algorithm, and the performance of 860 characterds or above is realized by 12.5-MHz operation. In addition, the quality for the

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Table 4. Specification of outline font transformation LSI

small-sized character is improved by devising the character correction method. Table 4 shows the specifications of the proposed LSI, and Fig. 14 shows its layout.

5. Conclusions

A special-purpose LSI was developed which con- tains a series of outline font expansion processings in a single chip. In the design of the architecture, the number of processing steps in each expansion processing, as well as the required system performance, are considered to amve at the optimal block configuration and to realize a compact structure. As to the character quality, a method is devised where the character is thinned as a whole and the horizontal/vertical line widths are adjusted, which helps to improve the quality of the character.

In this development, the special-purpose LSI is aimed at the downsizing of the OA equipment and improvement of the character quality. The realization of

small chip size is achieved by the architecture optimiza- tion and a highquality character correction method is devised. As a future study, the improvement of the graphical interface should be considered.

Acknowledgment. The authors appreciate the suggestions by Ms. K. Hasegawa, Mr. T. Kihara, Direc- tor of Hitachi Semiconductor Division, Mr. J. Enomoto, Hitachi Video Inf. Med. Div., and Mr. K. Haruna, President of Hitachi System Development Laboratories.

REFERENCES

1 . N. Murayama. Present status and trends in DTP. Jour. Inf. Proc. Soc., 31, No. 1 1 , pp. 1483-1494

2. F. Yoshimoto and K. Ichida. Spline Function and Its Applications, pp. 136-142. Kyoiku Publ. Co. (1979).

3. F. Yamaguchi. Figure Processing Engineering, pp. 54-56. Nikkan Kogyo Press (1981).

4. T. Kawada. Development of outline font transformation LSI with built-in RISC-type GPU. Aut. Conv. I.E.I.C.E., Japan, Div. 5, No. C-451, p. 131 [no date given]. N. Kai et al. A High-speed Outline Font Rasteriz- ing LSI. Proceedings of the IEEE Custom Integrat- ed Circuits Conference, 1989 (May 1989).

6. I. Nagashima et al. Design of an Outline Font Rasterizing LSI. 1989 Symposium on VLSI Cir- cuit. Digest of Technical Papers, pp. 117-118 (May 1989).

7. F. Yamaguchi. Figure Processing Engineering, pp. 68-82. Nikkan Kogyo Press (1981).

(1990).

5.

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AUTHORS (from left to right)

Hiroshi Wada graduated in 1988 from the Department of Mathematical Science, Keio University, and affiliated with Hitachi, Ltd. He is engaged in the development of display LSI in OA equipment and small-siwd client personal computer. At present, Planner Engineer, Inf. Systems R & D Division.

Shinji Wakizaka completed graduate program (Mechanical Engineering), Aoyama Gakuin University, and affiliated with Hitachi, Ltd. At present, he is a Researcher, Semiconductor and IC Division, Semiconductor Development Center. He is engaged in research and development of system LSI.

Hiroko &to graduated in 1991 from tbe Department of Mathematics, Ibaraki University, and affiliated with Hitachi, Ltd. At present, she is a Planner Engineer, Semiconductor and IC Division, Semiconductor Development Center. She is engaged in research and development of system LSI.

Norio Kiriyama graduated in 1984 from the Department of Electronic Engineering, Iwate University, and affiliated with Hitachi, Ltd. At present, he is with the Information and Image Systems Division, engaged in the design of Japanese word processor hardware.

Shigeo Hayashi graduated in 1971 from the Department of Electrical Engineering, Toyama Technical College, and affiliated with Hitachi, Ltd. At present, he is with the Semiconductor and IC Division of the Microcomputer ASIC Center and is engaged in the design and development of microcomputer LSI.

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Low-cost and high-quality method of outline font transformation