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Los tOHMales CalI e ntes. Lauren Cash, Chuhong Duan Rebecca Reed, Andrew Tyler. ECE 4332: Intro to VLSI. Introduction. ECE 4332: Intro to VLSI. Project: Design a high-speed 64KB SRAM cache Make optimizations that influence p ower c onsumption, area and total delay Metric: - PowerPoint PPT Presentation
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Los tOHMales CalIentesLauren Cash, Chuhong DuanRebecca Reed, Andrew Tyler
ECE 4332: Intro to VLSI
Introduction
ECE 4332: Intro to VLSI
Project:• Design a high-speed 64KB SRAM cache• Make optimizations that influence power
consumption, area and total delay• Metric: Delay^2*access-energy*idle-power*area
ECE 4332: Intro to VLSI
Overview
ECE 4332: Intro to VLSI
ECE 4332: Intro to VLSI
Figure : Simple SRAM 6T Bit Cell (U.Va ECE wiki)
Components
ECE 4332: Intro to VLSI
• Sized standard 6T Bit Cell• Row decoder: predecode stage (4-16)• Column deMUX: precode stage (3-8, 2-4)• PreCharge/BL/BLB• High Speed Sense Amp• Column MUX for output data
Figure : Hierarchical decoders
The Simulations
ECE 4332: Intro to VLSI
ECE 4332: Intro to VLSI
Simulations
ECE 4332: Intro to VLSI
Process Corners - FF
ECE 4332: Intro to VLSI
Process Corners - FS
ECE 4332: Intro to VLSI
Process Corners - SF
ECE 4332: Intro to VLSI
Process Corners - SS
Layout
ECE 4332: Intro to VLSI
Single Bit cell
Figure : Los tOHMales Calientes, Bit Cell LayoutECE 4332: Intro to VLSI
High Speed Sense Amp
Figure : Los tOHMales Calientes, Bit Cell LayoutECE 4332: Intro to VLSI
Figure : Los tOHMales Calientes, Pre-charge Layout
Pre-charge Layout
ECE 4332: Intro to VLSI
Figure : Los tOHMales Calientes, 32x1 Mux
32x1 Mux
ECE 4332: Intro to VLSI
Figure : Los tOHMales Calientes, Pre-Decoder Layout
Pre-Decoder
ECE 4332: Intro to VLSI
Figure : Los tOHMales Calientes, Row Decoder
Row Decoder
ECE 4332: Intro to VLSI
Figure : Los tOHMales Calientes, Full Layout
Full Layout
ECE 4332: Intro to VLSI
Optimizations
ECE 4332: Intro to VLSI
• High speed Sense Amp architecture• BL/BLB/PRECH Logic• Pre-decoder logic• Decoder location• Square cache architecture• Write drive size
ECE 4332: Intro to VLSI
High Speed Sense Amp
• Speeded up ~50%
Figure. High Speed Sense Amp for Cache Application (Hsu, Ho, (2004))
ECE 4332: Intro to VLSI
ECE 4332: Intro to VLSI
Write Driver Size
Figure. Write delay vs. BL driver size
Metrics
ECE 4332: Intro to VLSI
Power Breakdown Value
Bitline charger write power 58.34 μW
Column decoder write power 1.705 μW
Row decoder writer power 41.28 μW
Sense amp write power 78.45 μW
Bit cell write power: 20.03 μW
Bitline charger read power 16.96 μW
Cloumn decoder read power 1.05 μW
Row decoder read power 40.01 μWSense amp read power 137.4 μW
Bit cell read power 29.89 μW
Total write power 121.7 μW
Total read power 237.2 μW
ECE 4332: Intro to VLSI
Measurement Value
Metric 7.34x10-35 J·s2·mm2·W
Single Bitcell Area 1.1 μm2
Total Area 0.1148 mm2
Read Energy 0.3558 pJ
Write Energy 0.18255 pJ
Total Energy 0.326925 pJ
Read Delay .450 ns
Write Delay .397 nsTotal Delay .770 ns
(slower due to recharge)Idle Power 3.3 mW
ECE 4332: Intro to VLSI
References
ECE 4332: Intro to VLSI
Hsu, C.-L., & Ho, M.-H. (2004). High-speed sense amplifier for SRAM applications. The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings (Vol. 1, pp. 577 – 580 vol.1). Presented at the The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. doi:10.1109/APCCAS.2004.1412828
