L/O/G/O The Instruction Set Chapter 9 CS.216 Computer Architecture and Organization

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The Instruction Set

Chapter 9Chapter 9

CS.216 Computer Architecture and OrganizationCS.216 Computer Architecture and Organization

Overview• Much of the computer’s architecture / organization is

hidden from a HLL programmer– In the abstract sense, the programmer should not care what

the underlying architecture really is

• The instruction set is the boundary where the computer designer and the computer programmer can view the same machine

• Thus, an examination of the instruction set goes a long way to explaining the computer’s CPU itself

• This section investigates the design of the instruction set and the impact of the set on the design of the overall computer system

• Readings: Chapters 10 and 11

Instruction content (1/2)

• Each instruction must contain 4 basic pieces of information– Operation code: specifies the operation to be perfor

med, expressed as a binary code– Source operand references: operands required for th

e instruction are specified– Result reference: where should the result of the ope

ration be placed?

– Next instruction reference: how / where is the next instruction to be found

• In most cases, this is not explicitly stated in the instruction

• Next instruction is the one that logically follows the current one in the program (sequential / linear progression through the program)

Instruction content (2/2)

Instruction types (1/2)• An instruction set should be functionally complete

– Permit the user to formulate any high-level data processing task

• Five categories of instructions– Arithmetic operations– Logic operations– Data movement (internal to the system)– I/O (data movements between the computer and e

xternal devices)– Control operations

• Instruction sets have been designed with– Small numbers of instructions (1)– Hundreds of instructions– Trend today is to use “enough” to get the job done

well (more on this in the RISC/CISC discussions to come)

• Until the 1980s, the trend was to construct more and more complex instruction sets containing hundreds of instructions and variations

Instruction types (2/2)

Addresses in an Instruction (1/8)

• In a typical arithmetic or logical instruction, 3 addresses are required -- 2 operands and a result

• These addresses can be explicitly given or implied by the instruction

• 3 address instructions– Both operands and the destination for the result a

re explicitly contained in the instruction word– Example: X = Y + Z

– With memory speeds (due to caching) approaching the speed of the processor, this gives a high degree of flexibility to the compiler

• Avoid the hassles of keeping items in the register set -- use memory as one large set of registers

– This format is rarely used due to the length of addresses themselves and the resulting length of the instruction words


• 2 address instructions– One of the addresses is used to specify both an o

perand and the result location– Example: X = X + Y– Very common in instruction sets

• 1 address instructions– Two addresses are implied in the instruction– Traditional accumulator-based operations– Example: Acc = Acc + X


• 0 address instructions– All addresses are implied, as in register-based op

erations• Example: TBA (transfer register B to A)

– Stack-based operations• All operations are based on the use of a stack

in memory to store operands• Interact with the stack using push and pop op

erations


• Trade off: Fewer addresses in the instruction results in– More primitive instructions– Less complex CPU– Instructions with shorter length– More total instructions in a program– Longer, more complex programs– Longer execution times


• Consider

Y = (A-B) / (C+D*E)

– 3 address – 2 address


• ConsiderY = (A-B) / (C+D*E)

– 1 address


– 0 address• Convert to postfix (reverse Polish) notation• Y = AB-CDE*+/

PUSH APUSH BSUBPUSH CPUSH DPUSH EMPYADDDIVPOP Y


Addressing Modes (1/12)

• Once we have determined the number of addresses contained in an instruction, the manner in which each address field specifies memory location must be determined

• Want the ability to reference a large range of address locations

• Tradeoff between– Addressing range and flexibility– Complexity of the address calculation


• Immediate Mode– The operand is contained within the instruction its

elf– Data is a constant at run time– No additional memory references are required afte

r the fetch of the instruction itself– Size of the operand (thus its range of values) is li

mited


• Direct mode– The address field of the instruction contains the effec

tive address of the operand– No calculations are required– One additional memory access is required to fetch th

e operand– Address range limited by the width of the field that c

ontains the address reference– Address is a constant at run time but data itself can b

e changed during program execution– Some machines use variations of direct addressing:

direct and extended addressing on the 68HC11 -- 8 and 16-bit addresses


• Indirect addressing– The address field in the instruction specifies a me

mory location which contains the address of the data

– Two memory accesses are required• The first to fetch the effective address• The second to fetch the operand itself

– Range of effective addresses is equal to 2n, where n is the width of the memory data word

– Number of locations that can be used to hold the effective address is constrained to 2k, where k is the width of the instruction’s address field


• Register-based addressing modes– Register addressing: like direct, but address field s

pecifies a register location– Register indirect: like indirect, but address field spe

cifies a register that contains the effective address– Faster access to data, smaller address fields in the i

nstruction word


• Displacement or address relative addressing– Two address fields in the instruction are used

• One is an explicit address reference• The other is a register reference• EA = A + (R)

– Relative addressing• A is added to the program counter contents to c

ause a branch operation in fetching the next instruction


– Base-register addressing• A is a displacement added to the contents of th

e referenced “base register” to form the EA• Used by programmers and O/S to identify the s

tart of user areas, segments, etc. and provide accesses within them


• Indexing– Essentially the same impact as base addressing– Our book says that the A field is a memory addres

s and the referenced register contains the displacement value that is added to A

• This is not necessarily the case! “Indexing” as used and defined by Motorola for the 68HC11 is exactly as our author defines base addressing


– Better distinction of the base and indexing might be who / what does the reference.Examples:

• Indexing is used within programs for accessing data structures

• Base addressing is used as a control measure by the O/S to implement segmentation


• Pentium and PowerPC addressing– Text shows 9 addressing modes for the Pentium

• Range for simple modes (e.g., immediate) to very complex modes (e.g., bases with scaled index and displacement)

– The PowerPC, in contrast has fewer, simpler addressing modes



Endian Wars (1/3)• Architects must specify how data is stored (its byte or

dering) in memory and registers– This leads to the “endian wars”

• Big endian• Little endian

• Consider the hex value $12345678 and how it is stored in memory starting at address $100– Big endian stores most significant byte in the lowe

st address:100 12101 34102 56103 78

– Little endian stores the word in reverse:100 78101 56102 34103 12

• Observations:– In storing several data items into a memory seg

ment, each item will have the same address (big or little endian does not change this)

– Endianness does not effect the ordering of items in a data structure

– No general consensus as to which is “best”• Little endian: Intel X86, Pentium, VAX• Big endian: S370, Motorola 680x0, RISCs

Endian Wars (2/3)

– No real advantage in one style over the other• Decision is based on supporting previous mach

ines in many cases– Biggest problems:

• Data transfers between machines of different endianness

– Must go though a format conversion process

• Manipulation of individual bytes (bits) of multibyte word

Endian Wars (3/3)

Instruction Formats (1/7)

• The instruction format defines the layout of instruction word in terms of its constituent parts

• Most basic issue is the instruction length– Longer instruction lengths permit more opcodes,

addressing modes, addressing ranges, etc.– Longer does not imply a significant increase in fu

nctionality, however– Instruction lengths are equal to the basic memory

transfer data size or a multiple of that size• If the memory system retrieves 32 bit words, in

structions should be 32 bits (or 64)

• Allocation of bits– Tradeoff between number of opcodes supported (rich ins

truction set) and the power of the addressing capability


PDP-8: 12-bit fixed length variable format

• PDP-10: 36-bit fixed length fixed format– Stressed orthogonality, completeness, and direct a

ddressing– Trade off ease of programming with increased H/W

expense


• PDP-11: variable length variable format– 16-bit word length minicomputer– Variable length instructions to provide flexibility

-- more opcodes and memory addressing modes• Cost of the flexibility is a significant increase in

the CPU complexity


Figure 11.6 Instruction formats for the PDP-11

PowerPC format

Figure 11.9 PowerPC instruction formats

Summary (1/2)• In this section, we have looked at the instruction s

et of the machine– Content

• types of information contained in them• Functional completeness

– Addressing in instructions• Number of addresses included and the impact

on the program• Addressing modes -- how is the effective addre

ss determined

– Instruction format• Size and amount allocated to different fields• Fixed and variable formats• Complexity

Summary (2/2)

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L/O/G/O The Instruction Set Chapter 9 CS.216 Computer Architecture and Organization