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EE141 – Fall 2005Lecture 15
Logical EffortLogical EffortRatioedRatioed LogicLogic
EE141 2
Administrative Stuff
Project• Check the web page for latest clarifications
OH today 1-3pm, 511 Cory
2
EE141 3
Schedule
Last lecture• CMOS Logic Optimization• Logical Effort
Today• Logical Effort Wrap-up• Ratioed Logic• Pass Transistor Logic
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Concept of Logical Effort
Normalize gate delay to an inverter
gategategate PFOLED +⋅=
+⋅= gate
in
out
INV
gate
INV
gate
CCDelay
γττ
τ
LogicalEffort
Fanout“Electrical Effort”
ParasiticDelay
INVpINVINV t ,0=⋅γτ
gatepgategate t ,0=⋅γτ
INVINVg
INV
INV
gate
gateg
gate
invg
gateggate
INV
gate PCC
CC
CC
CRCR
γγττ
⋅=⋅=⋅⋅
⋅=⋅
,
int,
int,
int,
,
int,
,
,
3
EE141
DEF: Logical effort is the ratio of the input capacitance to the input capacitance of an inverter delivering the same output current
1: Calculating Logical Effort
Inverter:Cin = 3LE = 1 (def)
NAND2:Cin = 4LE = 4/3
NOR2:Cin = 5LE = 5/3
Reference
EE141
DEF: Parasitic delay is the ratio of intrinsic capacitance at the output and intrinsic capacitance at the output of an equivalent inverter
2: Calculating Parasitic Delay
Inverter:Cint = 3P = 1 (def)
NAND2:Cint = 6P = 2
NOR2:Cint = 6P = 2
Reference
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EE141
1
2
3
4
5
6
1 2 3 4 5
parasitic delay
effortdelay
Electrical effort: FO = Cout/Cin
Nor
mal
ized
del
ay: D
2-inp
ut NAND
invert
er LE = P =D =
LE = P =D =
4/3
1 1FO + 1
2(4/3)FO + 2
LE and P from Simulation Data
Dgate = LE·FO + P = Effort Delay + Parasitic Delay
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Estimate the delay of a fanout-of-4 (FO4) inverter:
Logical Effort: LE =
Electrical Effort: FO =
Parasitic Delay: P =
Stage Delay: D =
1
Cout/Cin = 4
pinv = 1
LE·FO + P = 5
D
Warm-up Example
5
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Multistage Networks
Stage effort: SEi = LEi·FOi
Path electrical effort: FOpath = Cout /Cin
Path logical effort: LEpath = LE1LE2…LEN
Branching effort: Bpath = b1b2…bN
Path effort = LEpath·FOpath·Bpath
Path delay D = ΣDi = ΣPi + ΣFOi·LEi
( )∑=
⋅+=N
iiii FOLEPDelay
1
Forget thisfor now
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Optimum Effort per Stage
PathEffortFOLESE N =⋅=∏When each stage bears the same effort:
N PathEffortSE =*
( ) PSENPFOLED iii +⋅=+⋅=∑ *min
Minimum path delay
Fanout of each stage: ii LESEFO *=Complex gates should drive smaller load!!!
6
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Gate Sizing Example (1/3)
FO
From: David Harris
First Compute Path Effort
∏ ⋅= FOLEPathEffort
90400201
34
35
101 =
×
×
×
=
zyz
xyx
The optimal stage effort is:
45.190400*
4/1
=
=⋅= FOLESE
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Gate Sizing Example (2/3)
FOWe can now size the gates, since for all of them:
We have:*SE
CLEC outin ⋅=
8.1345.1
201 =⋅=z
7.1245.13
4=⋅=
zy
5.1445.13
5=⋅=
yx
1045.1
1 =⋅=xCin
7
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Gate Sizing Example (3/3)
FO
The total normalized delay is (assuming Pinv=1):
8.11)1221(45.14*4 =++++⋅=+= ∑PSED
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Add Branching Effort
Branching effort:
pathon
pathoffpathonC
CCb
−
−− +=
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515
15
90
90
LE =FO =PE =SE1 =SE2 =PE =
190/5 = 1818 (wrong!)(15+15)/5 = 690/15 = 636, not 18!
Introduce new kind of effort to account for branching:
• Branching Effort:
• Path Branching Effort:
Con-path + Coff-path
Con-pathb =
Π biB =
Now we can compute the path effort:• Path Effort: PE = ∏LE·FO·B
Branching Example 1
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Multistage Networks
Stage effort: SEi = LEi·FOi
Path electrical effort: FOpath = Cout /Cin
Path logical effort: LEpath = LE1LE2…LEN
Branching effort: Bpath = b1b2…bN
Path effort = LEpath·FOpath·Bpath
Path delay D = ΣDi = ΣPi + ΣFOi·LEi
( )∑=
⋅+=N
iiii FOLEPDelay
1
Branching
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EE141
Select gate sizes y and z to minimize delay from A to B
Logical Effort: LE =
Electrical Effort: FO =
Branching Effort: B =
Path Effort: PE =
Best Stage Effort: SE =
Delay: D =
(4/3)3
Cout/Cin = 9
2•3 = 6
∏LE·FO·B= 128
PE1/3 ≈ 5
3•5 + 3•2 = 21
Work backward for sizes:
5z =9C•(4/3)
= 2.4C
5y =3z•(4/3)
= 1.9C
Branching Example 2
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Handling Wires & Fixed Loads
CL
Cwire
∑=
+
+⋅+=
N
i iin
wireiinii C
CCLEPDelay
1 ,
1,
stage i
stage i+1
FOi
10
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Logical Effort “Design Flow”
Compute the path effort: Path Effort = ∏ LE·FO·B
Find the best number of stages: N* ~ log4(PathEffort)
Compute the stage effort: SE* = (PathEffort)1/N
Working from either end, determine gate sizes:
Reference: Sutherland, Sproull, Harris, “Logical Effort,” (Morgan-Kaufmann 1999)
*SECBLEC out
in ⋅⋅=
Ratioed LogicRatioed Logic
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VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
FVSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Ratioed Logic
Goal: reduce the number of devices over complementary CMOS
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VDD
VSS
PDNIn1In2In3
F
RLLoadResistive
Ratioed Logic
N transistors + Load
VOH = VDD
VOL = RPDN / (RPDN + RL)VDD
Asymmetrical response
Static power consumption
tpLH = 0.69 RLCL
12
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VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
DepletionLoad
PMOSLoadVT < 0
Active Loads
Depletion load NMOS Pseudo-NMOS
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VDD
A B C D
FCL
With long channel devices
Pseudo-NMOS
22
|)|(22
)( TpDDpOL
OLTnDDn VVkVVVVk −=
−−
−−−=
n
pTDDOL k
kVVV 11)(
VOH = VDD (similar to complementary CMOS)
(assuming that VT = VTn = |VTp|)
Smaller area and load but static power dissipation!!!
13
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Pseudo-NMOS VTC
0.0 0.5 1.0 1.5 2.0 2.50.0
0.5
1.0
1.5
2.0
2.5
3.0
W/Lp=4
W/Lp=2
W/Lp=1W/Lp=1/2
W/Lp=1/4
Vin [V]
V out
[V]
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Improved Loads
A B C D
F
CL
M1M2 M1 >> M2Enable
VDD
M1 >> M2
Adaptive Load
14
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VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
Improved Loads (2)
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B
A A
B B B
Out
Out
DCVSL Example
XOR-XNOR gate
15
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DCVSL Transient Response
0 0.2 0.4 0.6 0.8 1.0-0.5
0.5
1.5
2.5
Time [ns]
A B
A B
A,BA,BV
olta
ge [V
]
AND-NAND gate
PassPass--Transistor Transistor LogicLogic
16
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Pass Transistor Logic (PTL)
Switch
Network
OutOut
A
B
B
BInpu
ts
N transistorsNo static power consumption
Allows primary inputs to drive S and D terminals!(idea: reduce the number of transistors)
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Example: AND Gate
B
B
A
F = AB
0
A B F0 0 00 1 01 0 01 1 1
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A = 2.5 V
B
C = 2.5V
CL
A = 2.5 V
C = 2.5 V
BM2
M1
Mn
NMOS-only Switch
VB does not pull up to 2.5V, but to 2.5V – VTn• Threshold voltage loss causes static power consumption• NMOS has higher threshold than PMOS (body effect)
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NMOS-Only Logic
0 0.5 1 1.5 20.0
1.0
2.0
3.0
Time [ns]
xOut
In
Volta
ge [V
]
VDD
In
Outx
0.5µm/0.25µm0.5µm/0.25µm
1.5µm/0.25µm
18
EE141 35
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
X
Solution 1: Level Restoring Transistor
Advantage: Full swingRestorer adds capacitance, takes away PDN current at XRatio problem
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Restorer Sizing
0 100 200 300 400 5000.0
1.0
2.0
W/Lr =1.0/0.25 W /Lr =1.25/0.25
W/Lr =1.50/0.25
W/Lr =1.75/0.25
Time [ps]
3.0
Vol
tage
[V]
Upper limit on restorer sizePass-transistor PDN can have several transistors in stack
19
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Out
VDD
VDD
2.5V
VDD
0V 2.5V
0V
Watch out for leakage currents
Solution 2: Single Transistor Pass Gate with VT=0
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A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=A⊕ΒÝ
F=A⊕ΒÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-TransistorNetwork
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
Complementary Pass Transistor Logic (CPL)
20
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A B
C
C
A B
C
C
BCL
C = 0 V
A = 2.5 V
C = 2.5 V
Solution 3: Transmission Gate
• Bidirectionalswitch
• Rail-to-rail switching
• Requires two transistors
• More control signals needed
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Vout
0 V
2.5 V
2.5 VRn
Rp
0.0 1.0 2.00
10
20
30
Vout, V
Res
ista
nce,
ohm
s
Rn
Rp
Rn || Rp
Resistance of Transmission Gate
off
sat
sat
lin
Vout: 0 → 1
21
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GND
VDD
In1 In2S S
S S
Pass Transistor based Multiplexer
A M2
M1
B
S
S
S F
VDD
F A S B S= ⋅ + ⋅
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AF
A
B
BM1
M2
M3/M4
Transmission Gate XOR
• 6 transistors only
• 12 transistors in CMOS
“on” forB = 1
“on” forB = 0
B
B
22
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V1 Vi-1
C
2.5 2.5
0 0
Vi Vi+1
CC
2.5
0
Vn-1 Vn
CC
2.5
0
In
V1 Vi Vi+1
C
Vn-1 Vn
CC
InReqReq Req Req
CC
(a)
(b)
C
Req Req
C C
Req
C C
Req Req
C C
Req
CIn
m
(c)
Delay in Transmission Gate Networks
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Delay Optimization
Delay of RC chain
Delay of buffered chain
2)1(69.069.0
0
+== ∑
=
nnCRkCRt eq
n
keqp
bufeqp tmnmmCR
mnt
−+
+
= 12
)1(69.0
bufeq tmnmnCR
−+
+
= 12
)1(69.0
eq
bufopt CR
tm 7.1=
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Transmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry
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Summary
Ratioed Logic• Reduced # of devices (reduced area)• Static power, increased NML
DCVSL• Differential outputs, reduced # of devices• Doubles the # of wires, increased Pdynamic
Pass-Transistor Logic• Modular design (the same gate topology…)• Need level restoration
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Next Lecture
Dynamic logic
CMOS logic• Properties