49
Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Review-II Wang Jiang Chau Grupo de Projeto de Sistemas Eletrônicos e Software Aplicado Laboratório de Microeletrônica – LME Depto. Sistemas Eletrônicos Universidade de São Paulo

Logic Synthesis in IC Design and Associated Tools Review-II

  • Upload
    mabli

  • View
    23

  • Download
    0

Embed Size (px)

DESCRIPTION

Logic Synthesis in IC Design and Associated Tools Review-II. Wang Jiang Chau Grupo de Projeto de Sistemas Eletrônicos e Software Aplicado Laboratório de Microeletrônica – LME Depto . Sistemas Eletrônicos Universidade de São Paulo. Data Structures. - PowerPoint PPT Presentation

Citation preview

Page 1: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Logic Synthesis in IC Design and Associated Tools

Review-II

Wang Jiang Chau

Grupo de Projeto de Sistemas Eletrônicos e Software Aplicado

Laboratório de Microeletrônica – LMEDepto. Sistemas EletrônicosUniversidade de São Paulo

Page 2: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Data Structures

Data Type: integer, boolean, etc.

Set of values that objects can assume, their common

data representation and set of operations on them.

Abstract Data Type (ADT): graphs, trees, lists

Mathematical model with defined operations

Data Structures: arrays, pointers

Data types and their relationships, used to implement ADTs

Obs. Very common The term Data structure is used to mean ADT

Page 3: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Abstract Data Types (ADTs)- 1

We know what a data type can do How it is done is hidden for the user

The concept of abstraction means:

With an ADT, users are not concerned with how the task is done but rather with what it can do.

Page 4: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Mathematical model with associated operations. The implementation is not defined Two ADTs with the same model, but with different

set of operations are considered distinct ones (the implementation may be different depending on the set of operations

Lists, stacks, queues, graphs, trees, heaps

Abstract Data Types (ADTs)- 2

Page 5: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

List ADT A sequence of zero or more elements

A1, A2, A3, … AN

N: length of the list A1: first element AN: last element Ai: position i If N=0, then empty list Linearly ordered

Ai precedes Ai+1

Ai follows Ai-1

Page 6: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Operations

printList: print the list makeEmpty: create an empty list find: locate the position of an object in a list

list: 34,12, 52, 16, 12 find(52) 3

insert: insert an object to a list insert(x,3) 34, 12, 52, x, 16, 12

remove: delete an element from the list remove(52) 34, 12, x, 16, 12

findKth: retrieve the element at a certain position

Page 7: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Implementation of a List

Choose a data structure to represent the list ADT E.g. arrays, records, etc.

Each operation associated with the list is implemented by one or more subroutines

Two standard implementations for the list ADT Array-based Linked list

Page 8: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Lists with Arrays

Elements are stored in contiguous array positions

Page 9: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Array Implementation

Requires an estimate of the maximum size of the list waste space

printList and find: O(n) findKth: O(1) insert and delete: O(n)

e.g. insert at position 0 (making a new element) requires first pushing the entire array down one spot to make room

e.g. delete at position 0 requires shifting all the elements in the list up one

On average, half of the lists needs to be moved for either operation

Page 10: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Lists with Pointers (Linked Lists) Ensure that the list is not stored contiguously

use a linked list a series of structures that are not necessarily adjacent in

memory

Each node contains the element and a pointer to a structure containing its successor

the last cell’s next link points to NULL

Compared to the array implementation, the pointer implementation uses only as much space as is needed for the elements currently on the listbut requires space for the pointers in each cell

Page 11: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Linked Lists

A linked list is a series of connected nodesEach node contains at least

A piece of data (any type) Pointer to the next node in the list

Head: pointer to the first nodeThe last node points to NULL

A

Head

B C

A

data pointer

node

Page 12: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Pointer Implementation Requires no estimate of the maximum size of the list

No wasted space printList and find: O(n) findKth: O(n) insert and delete: O(1)

e.g. insert at position 0 (making a new element) Insert does not require moving the other elements

e.g. delete at position 0 requires no shifting of elements

Insertion and deletion becomes easier, but finding the Kth element moves from O(1) to O(n)

Page 13: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

The Stack ADT

The Stack ADT stores arbitrary objects

Insertions and deletions follow the last-in first-out (LIFO) scheme

Think of a spring-loaded coin dispenser

Main stack operations: push(object): inserts an element object pop(): removes and

returns the last inserted element

Auxiliary stack operations:

object top(): returns the last inserted element without removing it

integer size(): returns the number of elements stored

boolean isEmpty(): indicates whether no elements are stored

Suited to arrays (the top element is the kth one) !!

Page 14: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

The Queue ADT The Queue ADT stores arbitrary

objects Insertions and deletions follow the

first-in first-out (FIFO) scheme Insertions are at the rear of the

queue and removals are at the front of the queue (think of a line in a cashier)

Main queue operations: enqueue(object): inserts an element

at the end of the queue object dequeue(): removes and

returns the element at the front of the queue

Auxiliary queue operations: object front(): returns the

element at the front without removing it

integer size(): returns the number of elements stored

boolean isEmpty(): indicates whether no elements are stored

Exceptions Attempting the execution of

dequeue or front on an empty queue throws an EmptyQueueException

Suited to pointers (both ends need to be controlled) !!

Page 15: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Graph ADT A graph is a pair (V, E), where

V is a set of nodes, called vertices E is a collection of pairs of vertices, called edges

Example: A vertex represents an airport and stores the three-letter airport code An edge represents a flight route between two airports and stores

the mileage of the route

ORD PVD

MIADFW

SFO

LAX

LGA

HNL

849

802

13871743

1843

10991120

1233337

2555

142

Page 16: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Edge Types

Directed edge (arc) ordered pair of vertices (u,v) first vertex u is the origin second vertex v is the destination e.g., a flight

Undirected edge unordered pair of vertices (u,v) e.g., a flight route

Directed graph all the edges are directed e.g., route network

Undirected graph all the edges are undirected e.g., flight network

ORD PVDflight

AA 1206

ORD PVD849

miles

Page 17: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Operations

Vertices and edges are positions store elements

Accessor methods endVertices(e): the two

endvertices of e opposite(v, e): the vertex

opposite of v on e areAdjacent(v, w): true iff

v and w are adjacent replace(v, x): replace

element at vertex v with x replace(e, x): replace

element at edge e with x

Update methods insertVertex(o): insert a

vertex storing element o insertEdge(v, w, o): insert

an edge (v,w) storing element o

removeVertex(v): remove vertex v (and its incident edges)

removeEdge(e): remove edge e

Iterator methods incidentEdges(v): edges

incident to v vertices(): all vertices in

the graph edges(): all edges in the

graph

Page 18: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Graphs with Arrays

SFO

ORD

LAX

DFW

MIA

PVD

1 1 1 1 11 1 11 1 1

1 1 11 1

1 1

ORD PVD

MIADFW

SFO

LAX

LGA

HNL

849

802

13871743

1843

10991120

1233337

2555

142

Edge connectivity Vertices

Page 19: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Array Implementation

Requires an estimate of the maximum size of the vertices waste space (besides memory size is quadratic to the

number of vertices) areAdjacent: O(1) IncidentEdges: O(n) insert and removeVertex: O(n)- similar to lists, but

both arrays must be re-arranged

Page 20: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Graphs with Arrays of Lists

type lisgraph= array [1, 2, …, nnodes] of recordvalue: informationneighbors: linked_list

Node[4]= {value=DFW;neighbors= {LAXORDLGAMIA}

Obs. record structure

Page 21: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Array of Lists Implementation

Requires also an estimate of the maximum size of the vertices waste space

A graph with few edges favors this scheme areAdjacent: O(n) IncidentEdges: O(k) (depends on the size of the lists) insert and removeVertex: O(n), but only one array

must be re-arranged

Page 22: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Rooted Tree ADT

A tree is a collection of nodes The collection can be empty (recursive definition) If not empty, a tree

consists of a distinguished node r (the root), and zero or more nonempty subtrees T1, T2, ...., Tk, each of whose roots are connected by a directed edge from r

Page 23: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Terminology

Root: unique node without a parent Internal node: node with at least

one child (A, B, C, F) External node (a.k.a. leaf): node

without children (E, I, J, K, G, H, D)

Ancestors of a node: parent, grandparent, great-grandparent, …

Descendant of a node: child, grandchild, great-grandchild, etc.

Depth of a node: number of ancestors

Height of a tree: maximum depth of any node (3)

subtree

A

B DC

G HE F

I J K

Subtree: tree consisting of a node and its descendants

Page 24: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Operations We use positions to abstract

nodes Generic methods:

integer size() boolean isEmpty() Iterator elements() Iterator positions()

Accessor methods: position root() position parent(p) positionIterator children(p)

Query methods: boolean isInternal(p) boolean isExternal(p) boolean isRoot(p)

Update method: object replace (p, o)

Additional methods may be defined by data structures implementing the Tree ADT

Page 25: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Binary Tree ADT

A binary tree is a set T of nodes such that either T is empty, or T is partitioned into three disjoint subsets:

A single node r, the root Two possibly empty sets that are binary trees, called

left and right subtrees of r

Page 26: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Binary Trees - Example

Operations are similar to the general trees’ ones !!

Page 27: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Binary Search Trees

A binary search tree A binary tree that has the following properties for

each node n n’s value is greater than all values in its left subtree TL

n’s value is less than all values in its right subtree TR

Both TL and TR are binary search trees

Page 28: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Binary Search Trees - Example

Alphabetical ordering !

Page 29: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Array Implementation - 1

An array-based representation of a complete tree A binary tree is represented by using an array

of tree nodes If the binary tree is complete and remains

complete, then, a memory-efficient array-based implementation can be used

Requires the creation of a free list which keeps track of available nodes

Page 30: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Array Implementation - 2

Page 31: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

A very simple way to implement a tree is to have each node store a reference to its left and right children

An alternative form is to have each node store a reference to its parent

Could also be used to store information about cities on roads, circuits on a board, etc.

Pointer Implementation - 1

Page 32: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Pointer Implementation - 2

Page 33: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Greedy Algorithms

Algorithm is greedy if : it builds up a solution in small steps it chooses a decision at each step myopically to

optimize some underlying criterion

Analyzing optimal greedy algorithms by showing that: in every step it is not worse than any other algorithm,

or every algorithm can be gradually transformed to the

greedy one without hurting its quality

Page 34: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Minimum Spanning Tree Problem A minimum spanning tree is a least-cost subset of the

edges of a graph that connects all the nodes

1

23

4

5

6

3 3

33

2

2

2

4

4

4

Edge Connected Components - {1},{2},{3},{4},{5},{6}Edge Connected

Components - {1},{2},{3},{4},

{5},{6}6-5 (2)

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

5-3 (2)

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

5-3 (2) {1},{2},{4},{3,5,6}

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

5-3 (2) {1},{2},{4},{3,5,6}

4-3 (2)

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

5-3 (2) {1},{2},{4},{3,5,6}

4-3 (2) {1},{2},{3,4,5,6}

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

5-3 (2) {1},{2},{4},{3,5,6}

4-3 (2) {1},{2},{3,4,5,6}5-4 (3)

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

5-3 (2) {1},{2},{4},{3,5,6}

4-3 (2) {1},{2},{3,4,5,6}5-4 (3) rejected

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

5-3 (2) {1},{2},{4},{3,5,6}4-3 (2) {1},{2},{3,4,5,6}5-4 (3) rejected3-2 (3)

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}

5-3 (2) {1},{2},{4},{3,5,6}4-3 (2) {1},{2},{3,4,5,6}5-4 (3) rejected3-2 (3) {1},{2,3,4,5,6}

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}5-3 (2) {1},{2},{4},{3,5,6}4-3 (2) {1},{2},{3,4,5,6}5-4 (3) rejected3-2 (3) {1},{2,3,4,5,6}3-1 (3) {1,2,3,4,5,6}

Edge Connected Components

- {1},{2},{3},{4},{5},{6}

6-5 (2) {1},{2},{3},{4},{5,6}5-3 (2) {1},{2},{4},{3,5,6}4-3 (2) {1},{2},{3,4,5,6}5-4 (3) rejected3-2 (3) {1},{2,3,4,5,6}3-1 (3)

Page 35: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Greedy Algorithm – General Model

Set C of candidates (not used) Solution Set S=

While S final_solution and C {

x is a “maximized” element of C; select (x)

C C-{x}

If (S {x}) is acceptable then SS {x}

}

If S= final_solution then return (S) }

else return (there is no solution)

Page 36: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Divide and Conquer

A divide and conquer algorithm consists of two parts: Divide the problem into smaller subproblems of the

same type, and solve these subproblems recursively Combine the solutions to the subproblems into a

solution to the original problem

Traditionally, an algorithm is only called “divide and conquer” if it contains at least two recursive calls

Page 37: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Quick Sort:

Partition the array into two parts (smaller numbers in one part, larger numbers in the other part)

Quicksort each of the parts

No additional work is required to combine the two sorted parts

D & C- Example and Counter-example

Binary tree Look-up: Compare the key to the value in the root

If the two values are equal, report success If the key is less, search the left subtree If the key is greater, search the right subtree

This is not a divide and conquer algorithm because, although there are two recursive calls, only one is used at each level of the recursion

Page 38: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Traversing Graphs and Trees- DFS A depth-first search (DFS)

explores a path all the way to a leaf before backtracking and exploring another path

For example, after searching A, then B, then D, the search backtracks and tries another path from B

Node are explored in the order A B D E H L M N I O P C F G J K Q

N will be found before either I or J

L M N O P

G

Q

H J K

FED

B C

A

I

Page 39: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

How to Depth-First Search

Start at root_node (any first node if graph) If (node marked) then dfs(node)

// mark is important in graphs

dfs (v)

mark v;

for each node w adjacent to v

if (w marked) then dfs(w);

Page 40: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Traversing Graphs and Trees- BFS

A breadth-first search (BFS) explores nodes nearest the root before exploring nodes further away

For example, after searching A, then B, then C, the search proceeds with D, E, F, G

Node are explored in the order A B C D E F G H I J K L M N O P Q

J will be found before NL M N O P

G

Q

H JI K

FED

B C

A

Page 41: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

How to Breadth-First Search

Start at root_node (any first node if graph) If (node marked) then bfs(node)

// mark is important in graphsbfs (v)

ENQUEUE (v, Q) ; // Q is a queue

while (Q )

u FIRST(Q);

DEQUEUE (u, Q);

for each w adjacent to u

if (w marked) then

mark w; ENQUEUE (w,Q)

Page 42: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Exploring Graphs-1

Node processing first Left node (and descendents)

processing Other children node (and

descendents)

processing

Sequence of processing:

A, B, D, E H, I, J, C, F, G

Pre-order traversal (with dfs)

G

H J

FED

B C

A

I

Page 43: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Exploring Graphs-2

Left node (and descendents) processing first

Other children node (and descendents) processing

Node processing

Sequence of processing:

D, H, I, J, E B, F, G, C, A

Post-order traversal (with dfs)

G

H J

FED

B C

A

I

Page 44: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Exploring Graphs-3

Left node (and descendents) processing first

Node processing Other children node (and

descendents) processing

Sequence of processing:

D, B, H, E I, J, A, F, C,G

In-order traversal (with dfs)

G

H J

FED

B C

A

I

Page 45: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Branch and Bound Algorithms

Branch and bound algorithms are generally used for optimization problems As the algorithm progresses, a tree of subproblems is formed The original problem is considered the “root problem” A method is used to construct an upper and lower bound for a given

problem At each node, apply the bounding methods

If the bounds match, it is deemed a feasible solution to that particular subproblem

If bounds do not match, partition the problem represented by that node, and make the two subproblems into children nodes

Continue, using the best known feasible solution to trim sections of the tree, until all nodes have been solved or trimmed

Page 46: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Branch and Bound Algorithms- Example

Traveling salesman problem: A salesman has to visit each of n cities once each, and wants to minimize total cost traveled

0 14 4 10 20

14 0 7 8 7

4 5 0 7 16

11 7 9 0 2

18 7 17 4 0

1 2 3 4 5

1

2

3

4

5

Cost of a direct travel from one city to another:

Departing from 1 and arriving in 5 : 20

Departing from 5 and arriving in 1 : 18

Page 47: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example- Computing Partial Costs-1

To specify partial paths To explore the most promising conditions first Define the probable minimal cost for arriving Define the probable minimal cost for departing

1

2

3

OBS.From A to B, half of the value depends on the arrival at B and half on the departure froma A

42

42

52

72

42

42

442

22

522

42

Page 48: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example- Computing Partial Costs-2 Suppose the journey starts at city 1 The initial cost (actually eual for any starting city is 40/2 = 20

Next step- computing any one of the possible paths: 12: (in this case, we know that (13,4,5), (3,4,52) and (21) are not possible anymore

and we re- compute the nodes costs Cost= 14 (2) +17 (others) = 31

1

2

3

42

N.A.

72

72

42

442

22

522

42

N.A.0 14 X X X

X 0 7 8 7

4 X 0 7 16

11 X 9 0 2

18 X 17 4 0

1 2 3 4 5

1

2

3

4

5

Page 49: Logic Synthesis in IC Design and Associated Tools Review-II

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example- Computing Partial Costs-3

1Bound 20

1,2Bound 31

1,3Bound 24

1,4Bound 29

1,5Bound 41

1,3,2Bound 24

1,3,4Bound 30,5

1,3,5Bound 40,5

1,4,2Bound 40

1,4,3Bound 41,5

1,4,5Bound 29

1,4,5,2Bound 30

1,4,5,3Bound 481,3,2,4

Bound 371,3,2,5

Bound 311,3,2,5

Bound 31

1,4,5,2Bound 301,3,2,5

Bound 31