CAMBRIDGE INSTITUTE OF TECHNOLOGY, BANGALOREDEPT. OF COMPUTER SCIENCE & ENGINEERING

LESSON PLANCLASS: III SEM SECTION: A

FACULTY: K. Sivani

SUBJECT:Logic Design

SUB CODE:06CSE33

OBJECTIVE: This subject is being taught to the student of III Semester CSE, with a view to enable him/her to understand the Architecture of the Computer, working of its various basic Components and the storage units, the Processor, Hard Disks also it gives a fair exposure to Logic Circuits and their Minimization; various integer and floating point operations, counters and Registers.

PREREQUISITE(s):A Basic Knowledge in Fundamentals of working of Computer and its Components, a Higher Level Programming Language like C and Engineering Mathematics-I and II to solve problems associated with the Subject.

EXPECTED OUTCOME: A student after undertaking this subject; he/she will be able to appreciate the need for learning about Architecture of the Computer and its internal working along with its various components and will be able to design the optimized circuits given some basic GATES to perform various operations.

IT IS BASIC SUBJECT FOR: IV Sem CSE: Microprocessors, Computer Organization; VIII Sem CSE: Advanced Computer Architecture.

SUBJECT APPLICATIONS: Embedded Systems, VHDL.S.No.

Lesson

Planned Date

ActualDate

Taken

DeviationDue to

(CL/UPL/OOD

/HOL/Other)

Remarks(Other)

1 Digital Logic: Overview of Basic Gates and Universal Logic Gates,

14.08.2013

2 AND-OR-Invert Gates, Positive and Negative Logic, Introduction to HDL

16.08.2013

3 Combinational Logic Circuits: Boolean Laws and Theorems, Sum-of-products Method

17.08.2013

4 Truth Table to Karnaugh Map, Pairs, Quads, and Octets

21.08.2013

5 Karnaugh Simplifications, Don’t Care Conditions, Product-of-sums Method

22.08.2013

6 Product-of-sum Simplification, Simplification by Quine-McClusky Method

23.08.2013

7 Hazards and Hazard Covers , HDL Implementation Models

24.08.2013

8 Data-Processing Circuits: Multiplexers, Demultiplexers,

28.08.2013

9 1-of-16 Decoder, BCD-to-Decimal Decoders 29.08.2013

10 Seven-segment Decoders, Encoders 30.08.2013

11 EX -OR gates, Parity Generators and Checkers, Magnitude Comparator

31.08.2013

12 Read-only memory, Programmable Array Logic,

04.09.2013

13 Programmable Logic, Troubleshooting with a Logic Probe,

05.09.2013

14 HDL Implementation of Data Processing Circuits

06.09.2013

15 Arithmetic Circuits: Binary Addition, Binary subtraction

07.09.2013

UNIT TEST – I (08/09/2013 to 10/09/2013)16 Unsigned Binary Numbers, Sign-Magnitude 11.09.2013

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Numbers

17 2’s Complement Representation, 2’s Complement Arithmetic

12.09.2013

18 Arithmetic Building Blocks, The Adder-Subtractor

13.09.2013

19 Fast Adder, Arithmetic Logic Unit, Binary Multiplication and Division

14.09.2013

20 Arithmetic Circuits using HDL 18.09.2013

21 Clocks and Timing Circuits: Clock Waveforms, TTL Clock, Schmitt Trigger

19.09.2013

22Mono stables with Input Logic, Pulse-forming Circuits

25.09.2013

23 Flip-Flops: RS Flip-flops, Gated Flip-flops, 26.09.2013

24 Edge-triggered RS, D,JK Flip-flops, Flip-flop timing, JK Master-slave Flip-flops

27.09.2013

25 Switch Contact Bounce Circuits, Various Representations of Flip-flops,

28.09.2013

26 Analysis of Sequential Circuits, Conversion of Flip-flops – a synthesis example

03.10.2013

27 HDL implementation of Flip-flop 04.10.2013

28 Types of Registers, Serial In-Serial Out,Serial In-Parallel Out, Parallel In-Serial Out

05.10.2013

29 Parallel In-Parallel Out, Applications of Shift Registers,Register Implementation in HDL

09.10.2013

30 Counters: Asynchronous Counters, Decoding Gates,

11.10.2013

31 Synchronous Counters, Changing the Counter Modulus,

12.10.2013

UNIT TEST – II (13/10/2013 to 15/10/2013)32 Decade Counters, Presettable Counters 16.10.2013

33 Counter Design as a Synthesis Problem, A Digital Clock,

17.10.2013

34 Counter Design Using HDL 18.10.2013

35 Design of Sequential Circuit: Model Selection, State Transition Diagram,

19.10.2013

36 State Synthesis Table, Design Equations and Circuit Diagram,

25.10.2013

37 Implementation using Read Only Memory, Algorithmic State Machine

26.10.2013

38 State Reduction Technique, Analysis ofAsynchronous Sequential Circuit

30.10.2013

39 Problems with Asynchronous Sequential Circuits

31.10.2013

40 Design of Asynchronous Sequential Circuit 02.11.2013

41 D/A Conversion and A/D Conversion: Variable, Resistor Networks, A/D Accuracy and Resolution

06.11.2013

42 Binary Ladders 07.11.2013

43 D/A Converters, D/A Accuracy and Resolution,

09.11.2013

44 A/D Converter-Simultaneous Conversion, A/D Converter-Counter Method

13.11.2013

45 Continuous A/D Conversion, A/D Techniques 14.11.2013

46 Dual-Slope A/D Conversion 15.11.2013

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47 Digital Integrated Circuits: Switching Circuits, 7400 TTL

16.11.2013

48 TTL Parameters, TTL Overview, 20.11.2013

49 Open-collector Gates, Three-state TTL Devices,

27.11.2013

50 External Drive for TTL Loads, TTL Driving External Loads

28.11.2013

51 74C00 CMOS, CMOS Characteristics 29.11.2013

52 TTL-to-CMOS Interface, CMOS-to TTL Interface

30.11.2013

PREPARATORY EXAMINATION (01/12/2013 to 06/12/2013)

ABBREVIATIONS: CL: Casual Leave; UPL: Unplanned Leave; OOD: On Office Duty; HOL: Unscheduled Holiday

Assignments and Mini Project

Assignment – ISubmit By: 01/09/2013

Assignment – IISubmit By: 05/10/2013Assignment – III

Submit By: 25/10/2013

Mini ProjectSubmit By: 10/12/2013

Literature to be Referred for the Course:

Book Type Code Title & AuthorPublication Information

Edition Publisher Year

Text Books T1Digital Principles and Applications By Donald P Leach, Albert Paul Malvino & Goutam Saha 6th

Tata McGraw Hill

2006

Reference Books

R1Fundamentals of Digital Logic with Verilog Design By Stephen Brown, Zvonko Vranesic -- TMH 2006

R2Fundamentals of Logic Design By Charles H. Roth 5th Thomson 2004

R3

Digital Systems Principles and ApplicationsBy Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss

10thPHI/Pearson Education

2007

Faculty in-charge HOD CSE(K. Sivani ) (Dr.)

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