Library Explorer and Part Developer Tutorialstatistics.roma2.infn.it/~sabene/CADENCE MANUALS/pl_tut.pdf · Introduction January 2002 14 Product Version 14.2 PADS dB-in translator

Library Explorer and Part DeveloperTutorial

Product Version 14.2January 2002

1999-2002 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

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Disclaimer: Information in this publication is subject to change without notice and does not represent acommitment on the part of Cadence. The information contained herein is the proprietary and confidentialinformation of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customerin accordance with, a written agreement between Cadence and its customer. Except as may be explicitly setforth in such agreement, Cadence does not make, and expressly disclaims, any representations or warrantiesas to the completeness, accuracy or usefulness of the information contained in this document. Cadence doesnot warrant that use of such information will not infringe any third party rights, nor does Cadence assume anyliability for damages or costs of any kind that may result from use of such information.

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Library Explorer and Part Developer Tutorial

Contents

1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Audience Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Pre-requisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Using the Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Chapter Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2Library Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Library Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Physical Organization of Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Lib-Cell-View Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Category (.cat) Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3Working with a Library Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Types of Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Library Management Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

As a Librarian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28As a Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Library Project Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Using Library Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

January 2002 3 Product Version 14.2


Creating a Library Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Steps: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Creating Libraries in the Build Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Viewing by Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Copying Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Viewing Footprints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Verifying Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Overview of Types of Verifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Deleting Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4Creating Parts With Pins Split Across Symbols. . . . . . . . . . . . . . . 49

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Part Creation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Creating a Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Starting Part Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Setting up Part Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52



Entering Part Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Entering Logical Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Intermediate Saving of Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Continuing Pin Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Creating Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Creating Split Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Saving Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Verifying Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76View Verification Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Instantiation and Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Viewing the Part in Concept HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Exporting Parts to the Reference Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5Modifying a Split Part. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Importing a Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86



Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Setting Up Part Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Opening an Existing Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Modifying Pins List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Modifying Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Modifying Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Viewing the Bits of a Vector Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6Creating a Multi-Section Symmetrical Part . . . . . . . . . . . . . . . . . . . 104

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Starting Part Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Setting Up the Part Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Entering Part Properties and Logical Pins Information . . . . . . . . . . . . . . . . . . . . . . . . . 107Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107



Intermediate Saving of Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Creating Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110


Creating Multiple Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Creating Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Copying Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Creating HAS_FIXED_SIZE Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7Modifying Multi-Section Symmetrical Parts . . . . . . . . . . . . . . . . . . 130

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Importing a Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Launching Part Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Setting Up the Part Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131


Modifying Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Deleting Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Deleting Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134



Modifying Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Modifying Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

8Creating Asymmetrical Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Entering Part Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Configuring Pin Name Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144


Entering Logical Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Creating Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Creating Multiple Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Creating Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Saving Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Verifying Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Steps: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162



Alternate Method of Creating an Asymmetrical Part . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

9Modifying Asymmetrical Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Importing a Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Setting up Part Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165


Opening the Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Modifying Logical Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Modifying Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Updating Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Saving Modified Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Adding Symbol Pin Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Changing Symbol Pin Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182



Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

10Handling Pin Texts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Adding Libraries to a Library Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187


Working with Unassociated Pin Texts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

11Data-Managed Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Overview of Data-Managed Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Pre-requisites for Creating a DM Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199Creating a Data-Managed Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

12Using XML to Create Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Importing Part Data from an XML Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Symbol Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217



Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

13Creating Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219Creating and Applying a Part Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Using Part Template to Create Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223Verifying Parts Against Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Property Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224Pin Load Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224Symbol Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

14Extracting Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Extracting Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229


Modifying Template Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233



Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

15Creating VHDL Wrappers and Map Files . . . . . . . . . . . . . . . . . . . . . 235

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Creating a VHDL Wrapper/Map File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16Creating Verilog Wrappers and Map Files . . . . . . . . . . . . . . . . . . . . 245

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245Creating a Verilog Wrapper/Map File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Index.............................................................................................................................. 251



1Introduction

Overview

In the 14.0 release, Cadence has introduced two new tool suites:

■ PCB Librarian

The PCB Librarian tool suite contains the following tools:

❑ Library Explorer

❑ Part Developer

❑ Allegro Librarian

■ PCB Librarian Expert

The PCB Librarian Expert tool suite contains the following tools:

❑ Library Explorer Expert

❑ Part Developer Expert

❑ Concept HDL

❑ Checkplus HDL

❑ CAE Views

❑ EDIF Schematic, symbol, and netlist reader/writer

❑ Verilog Model Library

❑ Allegro PCB (includes Allegro Librarian)

❑ General bi-directional mechanical interface (ver14)

❑ IDF bi-directional mechanical interface (version 2 and 3)

❑ IGES bi-directional electrical translator (level 5)


Library Explorer and Part Developer TutorialIntroduction

❑ PADS dB-in translator (version 4, 6 and PowerPCB version 3)

❑ PCAD dB-in translator (version 8)

❑ Zuken-Redac Cadstar dB-in translator (Cadstar 7.6 and Maxi)

This tutorial demonstrates the major features of the Library Explorer and Part Developertools. Using the Library Explorer and Part Developer, you can create and manage librariesand parts in an easy and effective manner. You can create several different type of parts suchas asymmetrical parts and large pin count parts.

In addition, if you have the Library Explorer Expert and Part Developer Expert, you canmaintain versions of libraries and parts. You can also create parts from XML datasheets andcreate and implement templates for creating parts.

Audience Profile

The intended audience profile for this tutorial are people who maintain and modify digitallibraries for design entry.

Pre-requisites

The tutorial assumes the familiarity with the following products:

■ Project Manager

■ Concept HDL

■ Allegro

How to Use this Tutorial

This tutorial provides a hands-on-exercise on creating libraries and parts. To gain the mostfrom this tutorial, you should try out all the steps as documented in the tutorial. The tutorial isbased on data provided through datasheets in PDF and XML format. The tutorial has 16chapters. The first 9 chapters cover the features which are common to both standard andexpert versions of the Library Explorer and Part Developer tools. The chapters 10 to 16contain the features that are exclusive to the expert version of the Library Explorer and PartDeveloper tool.



Using the Samples

The tutorial works with the samples which are installed along with the software. The samplesare stored in the following location <your_install_dir>/share/fet/examples/pcblibex. The name of the file is pl_db.zip for Windows NT platform and pl_db.t.Zfor UNIX platforms. You need to extract the samples from the compressed file.

When you extract the sample files, it will create the tutorial_project_data directory.This directory has the following subdirectories that are required for the successful completionof the tutorial.

Chapter Summaries

The tutorial is divided into 16 chapters. Each of these chapters detail the steps involved increating the different types of parts. Although the steps are similar, each of these chapterscover some of the unique features of Part Developer. Therefore, you should go through thetutorial completely to benefit from the powerful Library Explorer and Part Developer tools.

Following is a brief summary of the chapters in the tutorial:

Chapter 2, “Library Basics,”, covers the physical organization of a part library. This chapteralso covers the different views of a part.

Chapter 3, “Working with a Library Project,” describes the types of projects, the librarymanagement use models and the library development methodology. You also learn how tocreate a library project and work in it.

Directory Contents

datasheets Contains the datasheets for the parts that you will be creating whilecompleting the tutorial

footprints Contains the Allegro footprints

lcx Contains the lcx library that will be used as a reference library

old_parts Contains the parts created in older versions of Part Developer

test Contains a sample library project named test.cpm

lsttl Contains the ls00 and ls01 parts of the lsttl library. It also contains thecategory file for the lsttl library



Chapter 4, “Creating Parts With Pins Split Across Symbols,” details the methodology andsteps involved in creating a part with pins split across symbols. This chapter also details themethod to verify parts and importing them to the reference area.

Chapter 5, “Modifying a Split Part,” covers the steps involved in modifying a part which haspins split across symbols.

Chapter 6, “Creating a Multi-Section Symmetrical Part,” describes the methodology andsteps involved in creating a multi-section symmetrical part.

Chapter 7, “Modifying Multi-Section Symmetrical Parts,” details the methodology and stepsinvolved in modifying a multi-section symmetrical part.

Chapter 8, “Creating Asymmetrical Parts,” covers the methodology and steps involved increating asymmetrical parts.

Chapter 9, “Modifying Asymmetrical Parts,” describes the steps involved in modifying anasymmetrical part.

Chapter 10, “Handling Pin Texts,” details the methodology followed by Part Developer tohandle pin texts for a part.

Chapter 11, “Data-Managed Projects,” describes the methodology and steps involved increating and working with data-managed projects.

Chapter 12, “Using XML to Create Parts,” details the steps involved in creating parts fromXML datasheets.

Chapter 13, “Creating Templates,” covers the steps in creating part templates. This chapteralso covers the steps involved in using the templates to create parts.

Chapter 14, “Extracting Templates,” describes the steps in extracting template informationfrom a part. This chapter also details the steps involved in modifying the extracted templates.

Chapter 15, “Creating VHDL Wrappers and Map Files,” details the steps involved in creatingand verifying a VHDL wrapper and map file.

Chapter 16, “Creating Verilog Wrappers and Map Files,” details the steps involved in creatingand verifying a Verilog wrapper and map file.



2Library Basics

Objective

In this chapter, you will:

■ Understand the physical organization of a library

■ Understand the different views of a part

Overview

Libraries are a collection of parts. To enable you to understand the library storage and itsorganization, a sample lsttl library containing the ls00 and ls01 parts are provided. Thissample library is stored in the tutorial_project_data location.


Library Explorer and Part Developer TutorialLibrary Basics

Library Concepts

Physical Organization of Libraries

Each library is a directory and each part of a library is a directory. The part directories arestored under the library directory. For example, the library lsttl is stored in a directorycalled lsttl. The part ls00 and ls01 are subdirectories in the lsttl directory.

Information about a part, such as packaging and graphical information, are stored in differentviews. A view is nothing else, but a directory under the part. Each part can have many viewslike chips, entity, sym_1 etc. The information about a view is stored in one or more filesunder the view directory. For example, the chips view (the chips directory under the part)contains the chips.prt file. This file has the information about the physical packagesassociated with the part.

Note: You can see the set of Cadence-supplied libraries in <your_install_dir>/share/library.

The following section describes the views in more detail.



Lib-Cell-View Architecture

Views

Symbol (sym) View

The sym_1 and the sym_2 directories represent the symbol view of the part. The symbolview is the graphical representation of a part in a Concept-HDL drawing. Each part can haveone or more symbol views that are in effect different graphical representations.



Figure 2-1 Examples of Symbol Views

Different symbol views are stored under directories named sym_1, sym_2 and so on. Theactual information about each symbol is stored in the symbol.css file stored within thesym_n subdirectories.

Package (chips) View

The package view or the chip view stores the package information, such as pin names, pinnumbers, footprints and electrical information, for a part. This view connects the logical viewof a component to its physical view.

Pin information, such as pin names, types, loading and physical numbers, is stored in thechips.prt file located in the chips subdirectory. To see the contents chips.prt file ofthe ls00 part, open it through any text editor such as notepad or vi.

Displayed below is a partial screen shot of the chips.prt file for the ls00 component.

lsttlls00

sym_1master.tagsymbol.css

sym_2master.tagsymbol.css



Figure 2-2 The ls00 chips.prt file

The chips.prt file is divided into primitives where each primitive represents theinformation for a specific package such as DIP, SOIC etc. The primitive is itself divided into apin and a body section.



The pin section defines the logical to physical pin mapping. It also contains information on pinnames, pin types, pin loading values and physical pin numbers. The low asserted pins aresuffixed with either a ‘*’ , ‘_N’ or a ‘-’ sign.

Of special interest is the PIN_NUMBER property which is present for each logical pin of apart. The general syntax is

PIN_NUMBER = (pin number,pin number,.....,pin number)

The number of comma separated entries describes the number of slots in a part. If the logicalpin has a corresponding physical pin for the slot, it is filled with the physical pin number.Otherwise, the pin number is substituted with the value 0.

For ls00, A, B and Y are the logical pins. By looking at the PIN_NUMBER entry, you canidentify that the part has four slots. Also, since all the logical pins are present across all theslots, the PIN_NUMBER entry for each logical pin has a physical pin in all the four slots.

The body section of the chips.prt file contains the power pins information as well as theproperties that are associated with a package, such as JEDEC_TYPE etc. These propertiesare necessary and are used during different stages of the PCB Design front-to-back flow.More information about properties is available in PCB Systems Properties Reference.

For more information on the chips.prt file, see Concept-HDL Libraries Reference.

Entity View

The entity view is stored in the entity subdirectory. This view contains a Verilog module anda VHDL entity declaration. Both of them describe the list of ports found on the part. This viewis used when you create Verilog and VHDL wrapper and map files for simulation. For moreinformation about simulation views, see the Concept-HDL Libraries Reference.

Part_Table View

The Part_Table view stores the Physical Parts Table (.ptf) file. The Physical Parts Table (.ptf)file stores the packaging properties for a part in the library. This file contains information aboutparts such as package types, manufacturers, part numbers and any custom properties.



For example, displayed below is a typical entry from a .ptf file.

In the above part table file, the following things are of importance:

■ A unique part number is assigned based on package style.

■ An Allegro package symbol name is assigned based on package style.

Note: The JEDEC_TYPE property may also be defined in the chips.prt file. However, thepart_table view has the priority.

■ A part description is added

The PACK_TYPE property is a key property (it is on the left hand side of the equal sign). Thisimplies that every 74LVT574 in the schematic must have the PACK_TYPE property assigned.However, if an 74LVT574 is found that does not have a PACK_TYPE property value of eitherDIP, SOIC or LCC, the Packager-XL will abort. To set a default PACK_TYPE value, use theOPT statement as follows:

:PACK_TYPE (OPT = ‘LCC’) = PART_NUMBER | JEDEC_TYPE | DESCRIPTION;

When a 74LVT574 part in the schematic fits the key property description (has a PACK_TYPEproperty value of either DIP, SOIC or LCC), then the injected properties (they are all on theright side of the equal sign) are added to the packager netlist files (specifically thepstchip.dat file).

Each cell in a library containing logical parts should have a corresponding .ptf file. You canplace all the files in a single directory which will later be read by Packager-XL duringpackaging. You should maintain packaging information such as Allegro footprint(JEDEC_TYPE), VALUE, TOLERANCE, and PWR_RATING in this file.

FILE_TYPE = MULTI_PHYS_TABLE;

PART ‘74LVT574’

CLASS = IC

:PACK_TYPE = Part_NUMBER | JEDEC_TYPE | DESCRIPTION;

DIP = CDS123 | DIP20_3 | FLIP_FLOP

SOIC = CDS456 | SOIC20 | FLIP-FLOP

LCC = CDS789 | LCC20 | FLIP-FLOP

END_PART

END.



Simulation View

When a symbol view is saved to the disk, an entity view is automatically created. In the entityview is a Verilog and VHDL file that contains the names of all the pins on the symbol (knownas a module). The simulation view maps the symbol (or module) to a simulation model. Thename of the module is mapped to the name of the simulation model. The pin names in themodule are mapped to the port names in the simulation model. The file in this view containsonly mapping data. The actual model is stored in an HDL model library (for example,veriloglib).

During simulation, the Verilog or VHDL file in the schematic view is used as the netlist. Eachpart in this netlist has an entity and a simulation view.

Verilog-XL replaces the parts in the netlist with the simulation models as defined by thewrapper or a map file.

Depending upon whether a Verilog or a VHDL based flow is used, and whether map files orwrappers are used, it is suggested that the following directories store the simulation views:

■ vlog_map stores the map file that is used by Verilog during simulation

■ vlog_model stores the wrapper file that is used by Verilog during simulation

■ vhdl_map stores the map files that is used by VHDL during simulation

■ vhdl_model stores the wrapper file that is used by VHDL during simulation

Note: Unlike other views, simulation views can have user-defined directory names. However,it is suggested that you use the names mentioned above to ensure consistency and uniformityof understanding.

Category (.cat) Files

In addition to the supported views, you can also create a category file (.cat) within eachlibrary, to organize the parts into functional groups, such as BUFFER, CLOCK-DISTRIBUTION and so on. The category files are located within each library. This is anoptional file. The file is named as library_name.cat such as lsttl.cat for the lsttllibrary.

Summary

In this chapter, you learned about the physical organization of a part library. You also learnedabout the different views of a part. In the next chapter, you will learn how to create and workwith a library project.







3Working with a Library Project

Objective

In this chapter, you will learn to:

■ Identify the types of projects.

■ Understand the library management use models.

■ Understand the library development methodology.

■ Create a library project using Library Explorer.

■ Create a new build library.

■ View the categories in which a library is categorized.

■ Import a part from the reference area to the build area.

■ Copy parts across libraries.

■ View footprints.

■ Verify parts.

■ Delete a part from a build library.

Types of Projects

There are two types of projects:

■ Design Projects

You need to create a design project to design and develop PCB boards. Design projectsare created using Project Manager.

■ Library Projects


Library Explorer and Part Developer TutorialWorking with a Library Project

You need to create a library project to create and manage libraries of parts. Theseparts are used in the design projects. The person who creates and manages a libraryproject is called a librarian.

Library Management Use Model

PCB Librarian suite provides you the following tools to perform library creation andmanagement tasks:

■ Library Explorer

■ Part Developer

■ Part Table Editor

Depending upon whether you are a librarian or a designer, you can use the tools to performspecific tasks.

As a Librarian

Use Library Explorer to:

1. Create or open a library project which provides you with a build area where you can buildand modify libraries and parts.

2. Import reference libraries or parts you wish to modify into the build area.

3. Create any new libraries or cells.

4. Launch Part Developer to create or edit views.

5. Verify libraries.

6. Export new or modified libraries and parts to the reference library location.

7. Clean up the build area when finished.

Use Part Developer to:

1. Create or modify symbol, package, simulation views and part table views.

2. Verify the part.

Use Part Table Editor to:

1. Create or modify a part table.



2. Verify a part table.

3. Add new parts to a part table.

As a Designer

As a designer, you can do the following:

1. Create a design project using Project Manager.

2. Specify the project libraries while creating the project.

Now if you want to either create a new part or modify existing parts in the project libraries,you can launch the Part Developer tool. When you launch the Part Developer tool, it willdisplay the project libraries thus enabling you to modify and create new parts only inthem.

Note: Library Explorer will not be available on a project created through Project Manager aslibrary management oriented tasks like creating new libraries and categories, copyinglibraries and so on, should only be done by a librarian.



Library Project Concepts

A library project is a project that provides you with an environment in which to build andmanage libraries and parts. A library project is created using the Library Explorer tool.

Displayed above is a typical Library Explorer window after a library project is created oropened. Similar to the Windows Explorer, the Library Explorer window is divided into twopanes.

The left pane is further divided into two areas, namely the build area and reference area.These two areas are accessible by the two tabs, Build and Ref. These are automaticallycreated when a new library project is created. The build area is the area for your private librarydevelopment needs. That is, it is the work area on which you can create, modify and manageyour libraries and parts.

The entries in the build area are controlled through a file called the cds.lib file. Thecds.lib file is a text file and contains the mapping of the library name as visible in the buildarea to its actual physical location. This file is created automatically when a library project iscreated. The cds.lib file is in the same location as the project file. For example, in the abovescreenshot, the library project test stored in the tutorial_project_data is opened in

Build Tab

Reference Tab



Library Explorer. The actual lsttl library is stored in thec:\tutorial_project_data\test\lsttl location, and the cds.lib fi;e contains thefollowing entry:

DEFINE lsttl c:\tutorial_project_data\test\lsttl

The Ref tab represents the reference area for the library project. The reference area storesthe parts that have been verified by the librarian and made available for use by the designers.The list of libraries in the reference area are stored in the library list file named refcds.lib.

The refcds.lib file is similar to the cds.lib file and is stored in the same location asthe project file. As with the cds.lib file. the refcds.lib file contains the mapping of thelibrary name as visible in the reference area to its actual physical location.

By default, when you create a library project, the standard libraries provided by Cadence andstored in the <your_install_dir>/share/library can be added as referencelibraries in your library project. You can also add your own libraries as reference libraries.

When you create and verify a library in the build area, you can export it to the reference areaso that other users can also use it. Usually, only the librarian should have permissions toexport the libraries to the reference area.

To create a new reference library, you must first create the library and it constituent parts inthe build area, verify them and then export the build library into the reference area.

Similarly, to modify, rename, or delete a reference library, you must import it into your buildarea, make the necessary changes, and export it back to the reference area.

Using Library Explorer

Overview

Now, you will create a library project and name it tutorial_project.cpm. This libraryproject should be created in the tutorial_project directory. After you create the libraryproject, you will import a part that is categorized as a DECODER from the lcx referencelibrary to you build area. Then, you will copy the part from one build area library to another.Next, you will view the associated footprint of the part from within Library Explorer. Finally, youwill verify the part.



Creating a Library Project

The first step in working with libraries is to create a library project. In this section, you will learnhow to create a library project using Library Explorer.

Task Overview

Create a library project. The library project should be named tutorial_project.cpm.This project should be created in the tutorial_project directory. Thetutorial_project_data directory contains the lcx library which will be used as thereference library.

Steps:

1. Invoke the command shell of your computer.

2. Create a directory called tutorial_project.

3. In the command prompt, type libexp and press Enter.

The Library Explorer Product Choices dialog box appears. This dialog box displaysthe product suites for which you have the licences. The availability of tools and featuresof the tools are dependent on the choice of the product suite. For example, if you choosePCB Librarian, you can access the Library Explorer and Part Developer tools, but nottheir expert features such as data management and template creation.



4. Select the PCB Librarian option and click OK.

The Library Explorer window appears on the background with a Getting Started dialogbox on the foreground. In this dialog box you can choose to either open an existing buildarea or create a new build area.

5. Since you are going to create a new library project, select the Create a new Build Areaoption and click OK.



The New Project Wizard appears. This wizard enables you to quickly create a libraryproject. You will need to provide several information as you proceed with the wizard tosuccessfully create the project. First, you need to specify the project name and location.

6. Enter tutorial_project in the Project name text box and press Tab.

7. Click the Browse button and browse to the tutorial_project directory.

8. To continue, click Next.

The Select libraries page of the wizard appears. In this page, you select all the librariesyou want as reference libraries. The reference libraries will appear in the Ref tab ofLibrary Explorer window.

Note that by default, all the Cadence supplied libraries appear in the wizard page, andunless you explicitly remove them, get added as reference libraries to your project.



To add more libraries, either add them or import from another cds.lib file. If you importfrom another cds.lib file, all the libraries listed in the cds.lib are added as referencelibraries.

For this project, you will remove the lcx library from the Cadence supplied libraries andadd the lcx library from the tutorial_project_data location.

9. To remove the lcx library from the Cadence supplied libraries, select the lcx library andclick Remove.

10. Next, to add the lcx library from the tutorial_project_data location, click Add.



The Choose Directory dialog box appears.

11. To begin the process of adding the lcx library to your reference library list, browse to thetutorial_project location.

The contents of the tutorial_project_data directory appears.

12. To add the lcx library as a reference library, double-click on the lcx folder and click OK.

The lcx library gets added to the list of reference libraries.

13. Click Next.



The Summary page of the wizard appears.

14. To complete the creation of the project, click Finish.

After the project has been created, the Library Explorer message box appears.

15. Click OK.



The tutorial_project library project is created and appears in the Library Explorerwindow.

Caution

The tutorial_project_lib library appears in the Build tab. Do not delete thislibrary. This library contains the origin symbol which is required by theCadence tools. Physically, the library is named worklib and created in theLibrary Project location. The cds.lib file displays the worklib as the<projectname>_lib in the Build area.

Next, you will create a new library in the build area. Such libraries are called build libraries.



Creating Libraries in the Build Area

You create libraries in the build area to store user created parts. You have full control over thelibraries in the build area. Other than creating new parts, you can also copy parts from otherlibraries in the build area and import libraries from the reference area into your build area.

Task Overview

Create a library in the build area. Name the library my_library.

Steps

1. Before creating the build library, ensure that the Build tab is selected.

2. To begin creating a new build library, choose File > New > Build Library.

A new build library, named new_library is created.

3. To rename the library to my_library, type my_library press Enter.

The name of the library changes to my_library.

Next, you will identify decoder component in the lcx library and import it to the build area.This is a two step process. First, you need to identify which component in the lcx library is aDECODER and then you need to import it to the build area.

Viewing by Categories

You can categorize parts of your libraries. Normally the categorization is done as per thefunctionality of the part such as FLIP-FLOP, DECODER etc.

To view library in terms of its component categories, you select the category view. This viewis available through Library Explorer.

Task Overview

View the part categories of the lcx library.



Steps

1. To display the reference libraries, select the Ref tab.

2. Select the lcx library.

3. To view the categories, select View > Categories.

4. Double-click on the lcx library.

The Library Explorer view changes to show the categories into which the library isdivided.

5. To see the component that is classified as DECODER, select the DECODER folder inthe lcx library entry.

The lcx library has only one 3-TO-8 decoder is available.

6. To see the part that is classified as the 3-TO-8 DECODER, double-click on the 3-TO-8folder.

The contents of the 3-TO-8 folder appears on the right pane. The part number is LCX138.Now, you need to import this part to your build area.



7. To import a part into the build area, you need to revert back to the part view. To revert tothe part view, select View > Categories.

The Library Explorer reverts to the part view.

8. Right-click on the lcx138 component.

9. Choose Import.

The part gets imported to the build area. It is important to remember that when youimport a part, the complete library structure is created in the build area. Therefore, in thebuild area, you will see the lcx library under the Build Area Libraries, which will haveonly the lcx138 part.

10. To view the imported part in the build area, click on the Build tab.

The build area of the tutorial_project library project appears.

11. Double-click on the lcx library.

The lcx138 component appears in the right pane.

You successfully imported the lcx138 component to the build area. Next, you will copy thelcx138 part to the my_library build library.

Copying Parts

Library Explorer provides a Windows Explorer type ability to copy and paste parts from onelibrary to another.

Task Overview

Copy the lcx138 component from the lcx library to my_library.

Steps

1. Right-click on the lcx138 component in the Build area.

The short-cut menu appears.

2. Choose Copy.

3. Right-click on my_library.

4. Choose paste.



The lcx138 part is copied from the lcx build library and copied to the my_library buildlibrary. Similarly, using the short-cut menu, you can cut, delete, and rename components.

5. Now, rename the part to my_lcx138.

Next, you will view the footprints associated with this component.

Viewing Footprints

Using Library Explorer, you can view the footprints for a part. The footprints are used in theAllegro design.

Task Overview

View the footprints of the my_lcx138 part.

Steps

1. Right-click on the my_lcx138 part in the my_library build area.

2. Choose View Footprint.

The Physical Properties dialog box appears. The dialog box contains the differentphysical footprints for the packages in my_lcx138 part.

3. To close the dialog box, click Close.

4. Next, rename the part back to lcx138.

Next, you need to verify the part to ensure that the part can be used in a design.



Verifying Parts

Overview of Types of Verifications

From Library Explorer, you can run a set of checks. These are:

View Verification

The view verification check does the following checks:

■ Symbol origin is centered.Checks whether the origin always lies within the symbol and the symbol outline is at adistance less than the maximum allowed offset from the origin.

■ Tristated pins have input and output loads defined.Checks the presence of pin properties OUTPUT_LOAD and INPUT_LOAD for every tri-state pin. The presence of a tri-state pin is denoted by the property OUTPUT_TYPE=TS,TS.

■ Mandatory properties present in package file.Checks whether the properties named BODY_NAME, PART_NAME, CLASS, andJEDEC TYPE are present in the packages.

■ Consistent symbol name in symbol and package file.Checks whether the cell name is the same as BODY_NAME property in the chips.prt file.

■ Consistent symbol and package in pin list.Checks whether the pins are the same across symbol and package views.

Instantiation and Packaging

In this check, the parts are instantiated on a design sheet using Concept-HDL. One designsheet is created for each package type. All the cells supporting a particular package type areinstantiated on the sheet of that package type. For each such created design sheet, a .cpmfile is made and saved in the working directory.

Next, Packager-XL is invoked to package each of the designs. Then, the following checks areperformed:

■ Checks the hdldir.log, pxl.log and edbconfig.log files for errors.

■ Checks whether the schematic view has non-zero verilog.v and .sir files.

■ Checks whether the packaged view has non-zero .dat files.



■ If the netrev option ia checked (from the Options button), then Allegro is invoked tocreate an empty board and netrev. The board is then upreved with the netlist, and aphysical view is created. After creating a physical view, the presence of the netrev.lstand .brd files in the physical view is checked. Finally the reports of the result arereported in a log file.

■ Reports the result of the test on the library in a report file called ftb.rep. The report fileis created in the current working directory.

■ Declares the test library as passed, if the Concept-HDL and the PXL run are successful.

■ Reports the nature of a failure in the ftb.rep file, if any errors occur in the Concept-HDL run or at the Packager-XL run.

If the Use project ptf files for verification option is checked, all the .ptf files are loadedas specified in the ptfdirective file, and scanned for rows corresponding to the part concerned.If the rows have the given PACK_TYPE property as the key property, then all the other keyproperties get added to the part. The properties that are being added are checked to ensurethat the properties are not duplicated in the corresponding symbol.css file.

The designs are then packaged and the o/ps is checked. If the o/ps are successful, the designis netreved from the created .pst file.

The following tasks are also performed:

■ Checks whether pack_type is present in .ptf files, but not in the chips.prt file.

■ Ensures that if the PACK_TYPE property on it is conflicting, then the symbol is notinstantiated for a particular pack type. In other words, it skips the parts if the PACK_TYPEproperty on it is in conflict.

■ It checks if pack type is a part of the primitive name in the chips.prt file.

To switch on/off the options mentioned above, you have the following check boxes:

■ Use Project .ptf files for verification

If you select this rule, part table files are used in instantiation and packaging. If no parttable files are specified in the project file, the cell-level .ptf file is used by default.

■ Use allegro board (netrev)

If you select this option, the part or library is verified for the complete Front to Back flow.

■ Generate Pass/Fail report

This option is enabled only if you select a library.



Note: If you select the Generate Pass/Fail option, each part is verified separately. This isa time consuming process.

Advanced View Checks

Select this option to launch CheckPlus. You can run your own custom-defined checks usingCheckPlus.

VHDL Compilation

Note: This check is available only in the expert version of Library Explorer.

You use the VHDL Compilation option to compile the generated VHDL wrapper. You canuse either NCVHDL or CV to compile the wrapper. You can specify the tool to compile theVHDL wrapper in the Enter command in the VHDL compilation dialog box. This dialogbox is displayed when you click the Options button in the Verifications dialog box.

Verilog Compilation


You use the Verilog Compilation option to compile the generated Verilog wrapper. You canuse NCVERILOG to compile the wrapper. You can specify the tool to compile the Verilogwrapper in the Enter command for Verilog compilation dialog box. This dialog box isdisplayed when you click the Options button in the Verifications dialog box.

Verify with Templates


You use the Verify with Templates option to verify a part against a template. The verificationis done only for those values that exist in the template file as well. The output is displayed ina dialog box. The output is divided into two sections, Overview and Details.

In the Overview section, the overview of the differences are displayed. In the Detailssection, each of the differences in the logical, physical and symbol levels are detailed.

Task Overview

For the lcx138 component in the my_library build library, run only the View Verificationcheck with all the options.



Steps

1. Select the lcx138 part in the my_library build library.

2. Choose Tools > Verify.

The Verification dialog box appears.

3. Select the View Verification option.

4. To ensure that all the part will be checked for all the options of the View Verificationcheck, click Options.

The View Verification dialog box appears. Ensure that all the options are checked.

5. Click OK.

The View Verification dialog disappears.

6. To start the verification process, click OK.

The Verification Results message box appears. It should report no errors.

7. Click OK.

8. Click Close to close the Verification dialog box.

Deleting Parts

Library Explorer provides you with a Window Explorer type interface for deleting parts.

Task Overview

Delete the lcx138 part from the my_library build library.

Steps

1. Right-click on the lcx138 part.

2. Choose Delete.



The Confirm Folder Delete dialog box appears.

3. Since the part is to be deleted only from the build area, click Yes.

The lcx138 part gets deleted from the my_library build library.

Summary

You covered a lot in this chapter. In this chapter, you learned about the types of projects. Youlearned the library management use models and the library development methodology. Youalso learned how to create a library project and work in it. In the next chapter, you will learnto create a part with pins split across multiple symbols.





4Creating Parts With Pins Split AcrossSymbols

Objective

To become familiar with the methodology and steps involved in creating a part with pins splitacross symbols.


■ Understand the methodology involved in creating parts.

■ Setup Part Developer to assign properties globally to all symbols and packages of a newpart.

■ Do intermediate saves while creating a part.

■ Create a part with pins split across symbols.

■ Access Allegro footprints to specify JEDEC_TYPE property.

■ Extract pin numbers from the Allegro footprint.

■ Verify parts using View Verification check.

■ Create a new reference library.

■ Export the part to the new reference library.

Part Creation Methodology

Part Developer enables you to create and modify symbol, package, and part table views ofparts in Concept-HDL libraries. You should follow the sequence of steps listed below toensure an effective use of the Part Developer tool.

1. Refer to the datasheet. The datasheet contain all the information that you require tocreate parts.


Library Explorer and Part Developer TutorialCreating Parts With Pins Split Across Symbols

2. Configure Part Developer to correctly interpret the pin names.

3. Enter the logical pin information. Logical pins are the pin names as they appear on thedatasheet.

4. Specify the values in the Setup Options for creating a part. These values are dependenton the values in the datasheet and the standards you follow. These values includeproperties that are to be placed on the symbols, pins and packages, the placement andload values of the pins, the format of the symbols as they will appear in Concept-HDL,the format of the low asserted pins, and the interpretation of the pin names.

5. Create the packages for the part.

This creates the chips view for the part.

6. Create the symbols for the part.

This creates the symbol views.

7. If required, create the simulation views. This involves creating the Verilog and the VHDLwrappers and map files.

8. Verify the parts that you have created for use in the design flow.

Creating a Part

Task Overview

Create the N87C196NT part in the my_library build library. Set up Part developer to:

■ Add the property Library_Name with the value my_library to all the packages andsymbols.

■ Display the pin texts in 0.6 grid size.



The relevant part of the datasheet is stored in the tutorial_projects/datasheetslocation. A snapshot of the datasheet is displayed below:

Starting Part Developer

Since the part has to be created in the my_library build library, ensure that my_library isselected in Library Explorer. To launch Part Developer:

1. Choose Tools > Part Developer.



The Create/Open Part dialog box in the Part Developer window appears.

2. Since you need to set up Part Developer to add global properties, click Cancel.

The blank Part Developer window appears.

Setting up Part Developer

Task Overview

Set up Part Developer to associate and display a property Library_Name with the valuemy_library for all packages and symbols. Also, all the packages should have theBODY_NAME property with value as ? and the symbols should display pin text in 0.6 grid size.

Steps

1. Choose Tools > Options.



The Part Developer Setup Options dialog box appears. By default, the Properties tab isselected. The Library_Name property and its value will be entered in this tab.

2. Enter Library_Name in the Property Name column.

3. Click the corresponding cell in the Value column.

4. Enter my_library.

5. To display both the property name and its value in the symbol, select Both from theVisible drop-down list box.

6. To associate the property with both symbols and packages, select Package checkboxin the Package group box.

Note: The Symbol checkbox is selected by default.

7. Click Add.

The property will get added to all the symbols and packages created in this session ofPart Developer.

8. Next, enter BODY_NAME in the Property Name column.

9. Enter ? as its value.

10. Since the BODY_NAME property is to be added only to the packages, deselect theSymbol check box.

11. Click Add.

12. Next, configure Part Developer to display the pin text in 0.6 grid size. Click the Symboltab.



13. Click in the Pin Text Size text box.

14. To display the pin notes in 0.6 grids, enter 0.6.

After you configure the properties, the next step is to configure the format.

Configuring Format Options

The Format options page helps you to determine the way in which you will read and write lowasserted pins, and how the asymmetrical parts, sizeable pins and vector pins are displayedwhen a part is read into Part Developer.

Following is a description of the two group boxes that constitute the Format page.

■ Low Asserted Pin Syntax.

The setting in this group box determines the pin names that Part Developer will treat aslow asserted while reading a part. You also specify the notation that Part Developershould use to write a low asserted pin into the symbol and the chips.prt file. You canchoose to display the pins with following notations as low asserted pins on the symboland then write them to the symbol file in one of the following ways:

❑ Either with a asterisk (*) or _N suffix: In this case any pin which has either a * or _Nin its name is read as a low asserted pin. You can then determine whether you wantto write the low asserted pin into the symbol file with either the '*' or '_N' suffix.

❑ With a star (*) notation: In this case, the pins with a * are read as a low asserted pin.The pin is written back to the symbol file with the * suffix.

❑ With a _N notation: In this case, the pins with _N are read in a low asserted pin. Theyare written into the symbol file with the _N notation.

Note: Select the Use minus [-] sign for low asserted pins in Packageview to ensure that the pins that are considered low asserted are written into the chipsfile with a minus [-] sign. If you leave this unchecked, and depending on which pins youtreat as low asserted, they will get written into the chips.prt file with the same suffixas they are written into the symbol file (basically, either ‘*’ or ‘_N’).

Caution

You must follow a standard convention for reading and writing the lowasserted pins, otherwise the associated pin texts might get lost. Forexample, while creating a part, you decide on writing the low assertedpins with _N assertion. As a result, all the low asserted pins of the symbolhave _N appended to them. Now to modify the part, you load the part back



into Part Developer and change the low assertion write back option to *.Now when you save the part, the associated pin text will be lost. This isbecause when saving, Part Developer tries to associate pin names withpin texts and fails to find a pin with name, say A*, on the symbol (sincethe symbol has A_N) and as a result it doesn’t write any PIN_TEXTproperty for low asserted pins.

■ Chips File Reading Options

The options in this group box determines how Part Developer reads the chips.prt filefor displaying the following:

❑ Asymmetrical parts

Asymmetrical parts have multiple functionality. Corresponding to each functionality,there is a pin list. All sections or slots that have the same functionality have the samepin list. The slots that have the same functionality form one group. Depending on thepart, there may be multiple groups. You can choose to display the pin numbers insuch a way that the group numbers are also visible. You can do this by selecting theUse group format for reading asymmetrical parts check box.

❑ Sizeable pins

Sizeable pins can be displayed in Part Developer in one of the following ways: SlotNumber-Base Name or Base Name - Slot Number. In the Slot Number - Base Nameformat, the numeric part is treated as the slot number while the alphanumeric stringpart is treated as the base name. For example, if the pin name given is 1A, it is takenas base name A and slot number 1.

In the Base Name- Slot Number format, the alphanumeric string part is treated as abase name and numeric part is treated as a slot number. For example, if the pinname entered is A1, it is treated as a sizeable pin with base name A and slot number1.

❑ Vector pins

Vector pins can be displayed in Part Developer in one of the following ways: BitNumber - Base Name or Base Name - Bit Number. In the Bit Number - Base Nameformat, the numeric part is treated as the bit number while the alphanumeric stringpart is treated as the base name. For example, if the pin name given is 1A, it is takenas base name A and bit number 1.

In the Base Name - Bit Number format, the alphanumeric string part is treated as abase name and the numeric part is treated as a bit. For example, if the pin nameentered is A1, it is assigned the base name A and the bit number 1.



Task Overview

Configure Part Developer to write low asserted pins with ‘*’ suffix.

Steps

1. Select the Format tab.

The Format property page appears.

2. Ensure that the Suffix ‘*’ and Suffix ‘_N’ option for reading and Suffix ‘*’ for writing isselected. This is the default selection and suffices for most of the part creation scenarios.

After you configure the Format options, you need to configure the pin nameinterpretations.



Configuring Pin Name Interpretation

Overview

Logical pin names appear in the datasheets in following four patterns:

■ Alphanumeric String (for example, A, B, and EN)

■ <Alphanumeric String><Numeral> (for example, A0, A1)

■ <Numeral><Alphanumeric String> (for example 0A, 1A)

■ <Numeral><Alphanumeric String><Numeral> (for example 1A1, 1A2)

Note: Any string that is flanked by alphabets on both sides is treated as an alphanumericstring. For example, A, A1A.

Alphanumeric String

Usually, scalar pin names, such as A, B, EN, A1A and so on appear in data sheets asalphanumeric strings. Any alphanumeric string that is not flanked by numerals falls into theAlphanumeric string category. These pins are always treated as scalar pins.

<Alphanumeric String>< Numeral>

Data sheets use the alphanumeric string numeral names for representing vector bits orsizeable pins. For example, the names A0, A1, A2..A7 specify an 8-bit vector bus. Here,A is the base name and 0-7 is the bit range. Similarly, the names B1, B2, B3, B4 specifythe sizeable pin B in a part with four slots. The pins can be interpreted in the following ways:

Base Name: The entire alphanumeric string is treated as the base name and it is treated asa scalar pin.

Base Name-Bit: The alphanumeric string part is treated as a base name and the numeric partis treated as a bit number. For example, if the pin name entered is A1, it is assigned the basename A and the bit number 1.

Base Name-Slot: The alphanumeric string part is treated as a base name, and the numericpart is treated as a slot number. For example, if the pin name entered is A1, it is treated as asizeable pin with the base name A and the slot number 1.



Numeral Alphanumeric String

Sometimes data sheets may also use numeral alphanumeric string names for representingvector bits, sizeable pins, or a scalar pin belonging to a slot group. For example, the names0A, 1A, 2A..7A specify an 8-bit vector bus or the names 1B, 2B, 3B, 4B specify asizeable pin B in a part with four slots. Similarly, the scalar pins 1OE and 2OE are used to showthat the pin is in two slot groups. The pins will be interpreted in one of the following ways:

Base Name: The entire alphanumeric string is treated as a base name and taken as a scalarpin.

Bit-Base Name: The numeric part is treated as the bit number while the alphanumeric stringpart is treated as the base name. For example, if the pin name given is 1A, it is taken as thebase name A and the bit number 1.

Slot-Base Name: The numeric part is treated as the slot number while the alphanumericstring part is treated as the base name. For example, if the pin name given is 1A, it is takenas the base name A and the slot number 1.

Group-Base Name: The numeric part will be treated as group number while alphanumericstring part will be treated as base name. For example, if the pin name given is 1A, it will betaken as the base name A and the group number 1.

<Numeral>< Alphanumeric String>< Numeral>

Usually, data sheets use the <numeral>< alphanumeric string>< numeral> notation forrepresenting sizeable pins belonging to different groups. For example, if a part has 8 slotswith slots 1 to 4 in one group and 5 to 8 in another group, then a sizeable pin A of that partappears on the data sheet as following:

1A1, 1A2, 1A3, 1A4

2A1, 2A2, 2A3, 2A4

You can enter these pins in two steps:

■ enter 1A1- 1A4 and

■ enter 2A1-2A4

These pins can be interpreted in the following ways:

Base Name: The entire alphanumeric string is treated as a base name.



Slot-Base Name: The starting numeral is treated as the slot number while the rest of thename is treated as base name. For example, if the name is 1A1, it is taken as pin A1 in theslot as1.

Bit-Base Name: The starting numeral is treated as bit number while the rest of the name istreated as a base name. For example, if the name is 1A1, it is taken as pin A1 and the bitnumber 1.

Group-Base Name-Slot: The starting numeral is taken as a group number and the endnumeral is treated as a slot number in that group. So, if the pin name is 1A1, it is taken asbase pin A, slot 1, and group 1.

Group-Base Name-Bit: The starting numeral is taken as the group number and the endnumeral is treated as the bit number. Therefore, if the pin name is 1A2, it is taken as base pinA, bit 2, and group 1.

Base Name-Slot: The end numeral is treated as slot number while rest of the alphanumericstring is taken as the base name. For example, if the pin name is 1A1, it is treated as basepin 1A in slot 1.

Base Name-Bit: The end numeral is treated as bit number while rest of the alphanumericstring is treated as base name. For example, if the pin name is 1A1, it is treated as base pin1A, and bit 1.

Group-Base Name: The starting numeral is taken as the group number while the rest of thename is treated as a base name.

Task Overview

The N87C196NT has scalar pins. You will configure the pin interpretation to accept all pinsas scalar pins. For this, you need to setup the pin interpretation defaults as Base Name.

Steps

1. Click Edit in the Pin Name Interpretation group box in the Logical Pins dialog box.



The Pin Name Interpretation tab of the Part Developer Setup Options dialog boxappears.

2. Select Base Name in all the three sections.

3. Click OK.

This will set up Part Developer to interpret all pins as scalar pins.

After you set up Part Developer, you begin the process of creating the parts.



Entering Part Properties

Task Overview

The N87C196NT part should have the following properties:

■ Part Name should be N87C196NT

■ Physical Part Name should be the same as part name.

■ Part Type should be IC.

Steps

1. Click Create New in the Create/Open Part dialog box.

The New Part Properties dialog box appears. Notice that the my_library build libraryis selected by default.

2. Enter N87C196NT in the Part Name field.

Note: The Physical Part Name field also gets filled in automatically as you enter the partname field. This field is used as the PART_NAME property in the chips.prtfile.

3. Click OK.



The Logical Pins dialog box appears.

Entering Logical Pins

Task Overview

Enter the pin information as given in the datasheet into Part Developer. Open the datasheetand go to the pin descriptions table. The datasheet is located in the tutorial_project/



datasheets location. The pins will be entered in the same sequence as they appear in thedatasheet.

Steps

1. The first few pins in the Pin Descriptions table are power pins. To enter a power pin,select POWER from the Pin Type drop-down list box.

2. Enter Vcc, Vss,Vss1, VREF, VPP, ANGND in the Pin Name text box.

Important

Note that the Pin Descriptions table has multiple entries for the Vss1 power pin. InPart Developer you need to enter the name only once in the logical pins list. Laterwhen creating packages, you can associate multiple physical pins to a power pin.

3. To add the pin to the logical pin list, click Add.

The power pins gets added to the logical pins list.

4. Next, to enter an input pin, select INPUT from the Pin Type drop-down list box.

5. Enter XTAL1 in the Pin Name text box and click Add.

6. The next couple of pins in the Pin Descriptions table are output pins. To enter an outputpin, select OUTPUT from the Pin Type drop-down list box.

7. Enter XTAL2, P2.7 in the Pin Name text box and click Add.

8. The next pin in the table RESET which is an active low input pin. Select INPUT from thePin Type drop-down list box.

9. Enter RESET in the Pin Name text box.

10. To make an pin active low, select the Active Low check box and click Add.

11. The next couple of pins are input pin, but not active low. Therefore deselect the ActiveLow check box.

12. Enter P5.7, NMI in the Pin Name text box and click Add.

13. Next, to enter the P5.1 output pin, select OUTPUT from the Pin Type drop-down listbox.

14. Enter P5.1 in the Pin Name text box and click Add.

15. The next two pins in the table are active low input pins. Select INPUT from the Pin Typedrop-down list box.



16. Enter EA, HOLD in the Pin Name text box.

17. Select the Active Low check box and click Add.

18. The next two pins in the table, HLDA and BREQ are active low output pins. Therefore,select OUTPUT from the Pin Type drop-down list.

19. Enter HLDA, BREQ in the Pin Name text box and click Add.

20. The next four pins in the table are active high output pins. Therefore, deselect the ActiveLow check box.

21. Enter P5.0, P5.3, P5.2,P5.5 in the Pin Name text box and click Add.

22. The next pin (P5.6) in the Pin Descriptions table is an input pin. Therefore, select INPUTfrom the Pin Type drop-down list box.

23. Enter P5.6 in the Pin Name text box and click Add.

24. Next few pins in the table are bidirectional pins. To enter a bidirectional pin, select BIDIRfrom the Pin Type drop-down list box.

When creating large parts, it is a good idea to keep saving pin information every once ina while. For this, you do an intermediate save.

Intermediate Saving of Parts

When you save a part in Part Developer, several pre-save checks are run. So if you try to savean incomplete part, you might get some errors and the part will not get saved.

Therefore, to save a work-in-progress part, you should use the intermediate save feature ofPart Developer.

To save the part information in an intermediate save file:

1. Close the Logical Pins dialog box.

2. Choose File > Intermediate Save.

The Save As dialog box appears.

3. Enter n87c196ntin the File Name field and press Enter.

You successfully saved the part in an intermediate file.

After you do an intermediate save, you can continue entering more pins.



Continuing Pin Entry

1. Right-click on the Logical Pins entry in the tree view.

2. Choose Edit Pin List.


3. Enter P5.4,P6.2,P6.3, EPA0-EPA9 in the Pin Name text box and click Add.

4. The next four pins are input pins. Select INPUT from the Pin Type drop-down list box.

5. Enter ACH4-ACH7 in the Pin Name text box and click Add.

6. The next four pins in the datasheet are bidirectional pins. Select BIDIR from the PinType drop-down list box.

7. Enter P6.4-P6.7 in the Pin Name text box and click Add.

8. The next few pins are output pins. Select OUTPUT from the Pin Type drop-down listbox.

9. Enter P2.0-P2.1,P4.0-P4.7 in the Pin Name text box and click Add.

10. Next four pins in the table are bidirectional pins. To enter a bidirectional pin, select BIDIRfrom the Pin Type drop-down list box.

11. Enter A16-A19in the Pin Name text box and click Add.

12. The next pin is an active low output pin. Select OUTPUT from the Pin Type drop-downlist box.

13. Enter INTOUT in the Pin Name text box.

14. Select the Active Low check box and click Add.

15. The final eleven pins in the table are bidirectional pins. To enter a bidirectional pin, selectBIDIR from the Pin Type drop-down list box.

16. Enter P2.2, SLP0-SLP7 in the Pin Name text box.

17. Deselect the Active Low check box and click Add.

18. To accept the entries and close the Logical Pins dialog box, click OK.

After the logical pins have been entered, you create the packages.



Creating Packages

Task Overview

Create the PLCC package for the N87C186NT part.

Steps

1. To begin the process of creating packages, choose File > New > Package.



The New Package dialog box appears. By default, the General tab is selected.

2. Since the N87C196NT part comes in PLCC package, enter PLCC in the SpecifyPackage Type text box.

3. Click Specify Footprint.



The Physical Property dialog box appears.

You need to specify the JEDEC_TYPE value for the package. The value for theJEDEC_TYPE property will be picked up from the Allegro footprints of standardpackages provided by Cadence.

4. Click in the cell under the Value column next to the JEDEC_TYPE entry.

5. To select the appropriate value for the JEDEC_TYPE property, click Browse.



The Footprints dialog box displays. This has the complete list of footprints supplied byCadence.

6. Select plcc68 and click OK.

You selected the value for the JEDEC_TYPE property.

7. To close the Physical Properties dialog box, click OK.

Next, you need to update the value of the BODY_NAME property to be the same as thepart name. This is a standard requirement for your parts to be usable in the design flow.

8. To change the value of the BODY_NAME property, double-click on the Value column.

9. Enter N87C196NT as the value for the BODY_NAME property.

10. Next, you need to enter the physical pins and map them to the logical pins that youentered earlier. To get to the page where you enter physical pins, click the Physical PinMapping tab.

You can either add the physical pins manually, or extract them from the footprint. Toensure correctness of the entered physical pins, you should always extract the pins fromthe footprint.

11. To extract the pins from the footprint, select the Extract from Footprint option.



12. Click Pin Numbers.

The Part Developer message box appears. This message box states that all pin numbersextracted from the footprint will be added as unmapped pins to the package.

13. Click OK.

The 68 physical pins listed in the footprint get added as physical pins. Note that the pinnumbers are not in a sorted order.

14. To sort the physical pins, click on the Number column heading.

Next, the physical pins need to be mapped to the logical pins. The general method tomap a physical pin with logical pin is to select both the pins and click on the Map button.



15. As per the datasheet, physical pin 1 is mapped to logical pin P5.4. Therefore, select 1 inthe Physical Pins list, and select P5.4 in the Logical Pins list.

16. To map the selected pins, click Map.

The physical pin 1 is mapped to the logical pin P5.4.

Note: Whenever you map a physical pin to a logical pin, the pin number moves from thePhysical Pins list to the Logical Pins list and the next pin number in the list gets selectedin the Physical Pins list. This eases the pin mapping as you do not explicitly need to selecta physical pin to map to a logical pin. You can select the logical pin that you want theautomatically selected physical pin to be mapped to, and map it.

17. To map pin number 2 to logical pin P5.6, select P5.6 in the Logical Pins list.

18. Click Map.

19. Similarly, see the datasheet and map the first 10 physical pin numbers.

Note: Other than single pin mappings, you can also select multiple physical pins to bemapped to multiple logical pins. To ensure that pin mappings are done correctly, you mayneed to sort the pins in either ascending or descending order.

The physical pins 11-14 will be mapped to the logical pin A19-A16 by using this method.To select multiple pins, press CTRL + Click on the pins to be selected.

Currently, the logical pins are listed in the order of A16-A19. If you multi-select the pinsand do the mapping, the pin number 11 will get mapped to logical pin A16 and so on.However, what is required is that the pin number 11 be mapped to logical pin A19.Therefore, first the order of the logical pin needs to be reversed.

20. To change the sorting order of the pins 11-14, select the pins and right-click.

21. Choose Sort Descending.

The pins 11-14 are sorted in descending order.

22. To map pin number 11 - 14 to logical pins A19-A16, first select the pin numbers 11,12,13and 14 in the Physical Pins list.

23. Next, select A19,A18,A17,A16 in the Logical Pins list.

24. Click Map.

25. Similarly map the other physical pins to their corresponding logical pins.

26. When you get to pin number 68, you will get an error message saying that this pin hasalready been mapped. This is situation where there are two physical pins (34 and 68) for



a power pin (VSS1) of the same name. To handle such situation, Part Developer allowsyou to replicate the power pin.

27. To replicate the VSS1 power pin, right-click on VSS1.

28. Select Replicate.

The Replication Factor dialog box displays. In this dialog box you can determine thenumber of replicated power pins. The default value is one.

29. Since only one more VSS1 power pin is required, click OK.

30. Map the physical pin 68 to the replicated VSS1 power pin.

31. To complete the creation of the package, click OK.

After you create a package, the next step is to create symbols for the part.

Creating Split Symbols

You can create symbols with pins split across them for reasons such as:

■ Reflect the way the parts functionality is used in a schematic.

■ Enable a more manageable display for large pin count parts.

Task Overview

Create two symbols for the N87C196NT part where the pins are split across the symbols.Symbol 1 should have the following pins:

■ XTAL1, XTAL2, RESET*, NMI, EA*, P4.0 - P4..7, A16-A19, SLP0-SLP7, Power Pins

Symbol 2 should have the remaining pins.



Steps

Part Developer provides a Symbol Creation Wizard which enables you to efficiently andcorrectly create symbols.

1. To begin creating the symbols, choose File > New > Symbol.

The Split Symbol page of the Symbol Creation Wizard appears. By default, the AllPins option is selected.

2. To create two symbols, select the Split Pins across symbols option.

3. By default, the value in the Number of symbols is two. Since the pins are to be splittedinto two symbols, there is no change required for the Number of symbols field. Tocontinue, click Next.



The Pin Selection page of the Symbol Creation Wizard appears. This page displaysthe list of available logical pins and gives the choice to associate a logical pin with aparticular symbol.

The following pins should be added to the first symbol:

■ XTAL1, XTAL2, RESET*, NMI, EA*, P4.0 - P4..7, A16-A19, SLP0-SLP7

The remaining pins should be on the second symbol.

4. To add the above mentioned list of pins on the first symbol, select the correspondingcheck box under the sym_1 heading for each pin. For example, to add the XTAL1 pin onthe first symbol, select the checkbox under sym_1 heading next to XTAL1 entry.

5. Similarly, associate the other pins to the second symbol.




The Summary page of the Symbol Creation Wizard appears. This page displays thelist of symbols and the pins associated with each symbol.

7. Check the summary page and click Finish.

The Symbol Creation Wizard creates the two symbols by splitting the pins across thesymbols.

Saving Parts

Task Overview

Save the N87C196NT part.



Steps

➤ To save the part, choose File > Save.

The Part Developer Errors dialog box appears. It should show no errors.

Next, you will verify the part for its validity.

Verifying Parts

The parts that you created should be error free and usable in the design flow. Part Developerprovides you with robust verification tools which ensure that the parts are correct and usable.

Task Overview

Verify the N87C196NT part for cross view errors and instantiation and packaging errors. Thisis done by running the View Verification and Instantiation and Packagingchecks.

View Verification Check

The view verification check does the following checks:

■ Symbol origin is centered.Checks whether the origin always lies within the symbol and the symbol outline is at adistance less than the maximum allowed offset from the origin.



■ Tristated pins have input and output loads defined.Checks the presence of OUTPUT_LOAD and INPUT_LOAD pin properties for every tri-state pin. The presence of a tri-state pin is denoted by the OUTPUT_TYPE =TS,TS pinproperty.

■ Mandatory properties present in package file.Checks whether the BODY_NAME, PART_NAME, CLASS, and JEDEC_TYPEproperties are present in the packages.

■ Consistent symbol name in symbol and package file.Checks whether the symbol text is the same as BODY_NAME property in thechips.prt file.

■ Consistent symbol and package in pin list.Checks whether the pins are the same across symbol and package views.

Instantiation and Packaging

In this check, the parts are instantiated on a design sheet using Concept-HDL. One designsheet is created for each package type. All the cells supporting a particular package type areinstantiated on the sheet of that package type. For each such created design sheet, a .cpmfile is made and saved in the working directory.

Next, Packager XL is invoked to package each of the designs. Then, the following checks areperformed:

■ Checks the hdldir.log, pxl.log and edbconfig.log files for errors.

■ Checks whether the schematic view has non-zero verilog.v and .sir files.

■ Checks whether the packaged view has non-zero .dat files.

■ If the netrev option is checked (from the Options button), then Allegro is invoked tocreate an empty board and netrev. The board is then upreved with the netlist, and aphysical view is created. After creating a physical view, the presence of the netrev.lstand .brd files in the physical view is checked. Finally, the reports of the result arereported in a log file.

■ Reports the result of the test on the library in a report file called ftb.rep. The report fileis created in the current working directory.

■ Declares the test library as passed, if the Concept-HDL and the Packager-XL run aresuccessful.

■ Reports the nature of a failure in the ftb.rep file, if any errors occur in the Concept-HDL run or at the PXL run.



If the Use project ptf files for verification option is checked, all the .ptf files are loadedas specified in the ptf directive file, and scanned for rows corresponding to the partconcerned. If the rows have the given PACK_TYPE property as the key property, then all theother key properties get added to the part. The properties that are being added are checkedto ensure that the properties are not duplicated in the corresponding symbol.css file.

The designs are then packaged and the o/ps is checked. If the o/ps are successful, the designis netreved from the created .pst file.

The following tasks are also performed:

■ Checks whether pack_type is present in ptf files, but not in the chips.prt file.

■ Ensures that if the PACK_TYPE property on it is conflicting, then the symbol is notinstantiated for a particular pack type. In other words, it skips the parts if the PACK_TYPEproperty on it is in conflict.

■ It checks if pack type is a part of the primitive name in the chips.prt file.

To switch on/off the options mentioned above, you have the following check boxes:

■ Use Project ptf files for verification

If you select this rule, part table files are used in instantiation and packaging.

If no part table files are specified in the project file, the cell-level ptf is used by default.

■ Use allegro board (netrev)

If you select this option, the part or library is verified for the complete Front to Back flow.

■ Generate Pass/Fail report

This option is enabled only if you select more than one part or when you select a library thathas more than one part.

Note: If you select the Generate Pass/Fail option, each part is verified separately. This is atime consuming process.

Steps

1. To begin the process of verifying the part, choose Tools>Verify.




2. To do the verification of the stand-alone views and cross-view checks, select the ViewVerification option. This is selected by default.

3. To ensure that all the checks that View Verification does are selected, click Options.

The View Verification dialog box appears.

By selecting the options in this dialog box you can determine which of the ViewVerification checks will be run on a part. Since for N87C196NT all the checks should berun, ensure that all the checks are selected.

4. Click OK.



The View Verification dialog box closes.

5. To run the View Verification check on the part, click OK.

The Verification Results dialog box appears. It should show that all the checks havepassed.

Next, check the part for instantiation and packaging errors.

6. Select the Instantiation and Packaging radio button.

7. To run this check to verify the packaging of the parts, click Options.

The Instantiation and Packaging dialog box appears.

8. Ensure that the Use project ptf files for verification and Upto allegro board (netrev)options are unchecked.

9. Click OK.

The Verification Results dialog box appears. It should show that all the checks havepassed.

Congratulations. You have successfully created the N87C196NT part.



Viewing the Part in Concept HDL

After you create the part, you can view it in Concept HDL by launching Concept HDL fromwithin Part Developer.

Task Overview

View the N87C196NT in Concept HDL.

Steps

1. Select the symbol sym_1 in the tree view.

2. Choose Tools > ConceptHDL.

An error message pops-up informing you that Concept HDL is not part of the PCBLibrarian tool suite. Click OK to destroy the message box.

The Concept-HDL Product Choices dialog box appears. This dialog box lists all theproduct suites that have Concept-HDL licence.

3. For this example, select the PCB Librarian Expert suite.

4. Click OK.



Concept-HDL launches displaying the selected symbol and its properties.

A partial view of the symbol with the properties is also displayed below:

After you create a part and verify it, you should export the part back into the reference area.



Exporting Parts to the Reference Area

Task Overview

Export the N87C196NT part which you created in the my_library build library to thereference area.

Steps

1. Since parts (and libraries) can only be exported from within Library Explorer, go to theLibrary Explorer window.

2. Right-click on the n87c196nt part in the my_library build library.

3. Select Export from the pop-up menu.

The Export Destination dialog box appears.

4. Notice that although you selected only the N87C196NT part for export, the SourceLibrary column displays the build library name in which the part is stored. This isbecause when you select to export a part, the complete library structure is exported.That is why you need to specify the destination library. You need to determine thedestination library into which you want to export the part. The destination library caneither be one of the existing reference libraries or you can create a new reference libraryaltogether. In this example, you will create a new reference library calledmy_reference_library and store it in the c:\my_reference_libs directory. Youwill need to create this directory outside Library Explorer.

5. To create a a new reference library, click New Ref Lib.



The New Reference Library dialog box appears.

In this dialog box you enter the name of the reference library and its location.

6. Enter my_reference_libs in the Name of the new library field.

7. To change the reference library location, click Browse.

8. Select the my_reference_libs location and click OK.

The New Reference Library dialog box disappears.

Now, you need to select the my_reference_libs from the Destination Library dropdown list box in the Export Destination dialog box.

9. To see the list of available reference libraries, click the down arrow in the DestinationLibrary list box.

10. Select my_reference_libs and click OK.

The Library Explorer dialog box appears. It should show that the export wassuccessful.

11. Click OK.

12. To verify that the new reference library and the exported part shows up in the Ref area,click the Ref tab.



13. Browse and view the contents of the my_reference_libs reference library. It shouldshow the N87C196NT part that you exported from the my_library build library.

Once you export a part to the reference library, you can delete the part from the buildlibrary.

14. To begin the process of deleting the N87C196NT from build area, click the Build tab toview the build area.

15. Select N87C196NT in the my_library build library.

16. Press Delete.

The Confirm Folder Replace dialog box appears.

17. Click Yes to delete the part from the build area.

You deleted the part from the build area.

Summary

In this chapter you learned about the methodology and steps involved in creating a part withpins split across symbols. In the next chapter, you will learn to modify the part that you createdin this chapter.



5Modifying a Split Part

Objective

To become familiar with the steps involved in modifying a split part.


■ Import a part.

■ Setup Part Developer to view the part data in the same format as you had entered.

■ Add/delete logical pins.

■ Add/remove power and NC pins.

■ Modify packages and symbols by resplitting the pins across symbols.

■ View the symbols in Concept-HDL and snap the new pins to the boundary of the symbol.

■ Verify the part.

■ Export the part after modification.

Importing a Part

When you want to modify a part in the reference library, you need to import the part into yourbuild area. After the part has been imported, you can use Part Developer to modify the partas required.

Task Overview

Import the N87C196NT part from the my_reference_library reference library into thebuild area.


Library Explorer and Part Developer TutorialModifying a Split Part

Steps

1. To begin the process of importing the N87C196NT part into the build area, you need toselect the part in the reference area. Click Ref tab to display the reference area.

2. Browse the reference area libraries and select the my_reference_library referencelibrary.

The contents of the my_reference_library appear in the right-pane of the LibraryExplorer window.

3. To import the N87C196NT part, right-click on N87C196NT and select Import from thepop-up menu.

The Library Explorer message box appears. It should report that the import operationwas successful.

Setting Up Part Developer

The settings in the Format tab of Tools > Setup options in Part Developer determines howthe information about a part is interpreted when it is read into Part Developer. It determineswhether the pins that have the suffix * or _N or both are to be interpreted as low asserted pins.It also determines the format in which different kind of pins, such as scalar, sizeable, andvector, are shown when a saved part is read in Part Developer. Therefore, it is necessary toensure that the format options are set up properly for the part that you want to open.

Task Overview

Open the N87C196NT part in Part Developer. Ensure that the pins with suffix * are read in aslow asserted since that is how you had configured Part Developer to represent low assertedpins while creating the part. Since for the N87C196NT part, the logical pins are all scalar, theother options in the Format page will have no effect.



Steps

1. Launch Part Developer by choosing Tools > Part Developer.

2. To verify and set up the values of the Format option before opening the part, click Cancelin the Create/Open Part dialog box.


The Part Developer Setup Options dialog box appears.

4. Click Format.

The Format page appears.

5. Ensure that under the Reading option, the check box next to the Suffix ‘*’ and Suffix‘_N’ is selected. This ensures that the pins with the suffix * and _N will be read in as lowasserted pins.

6. Click OK.

Next, you need to open that part.

Opening an Existing Part

Task Overview

Open the N87C196NT part stored in the library named my_library.

Steps

1. Choose File > Open.

The Open Part dialog box appears.

2. Choose my_reference_libs from the Library drop-down list box.

3. Choose N87C196NT from the Cell drop-down list box and click OK.

The part will open in Part Developer.

Next, you will add some logical pins and NC pins to the part.



Modifying Pins List

Task Overview

Remove the scalar pin P2.2 and add the vector pins ZZ1-ZZ16 to the part. Ensure that thepins ZZ1-ZZ6 are interpreted as vector pins.

Steps

1. To modify the logical pin list, right-click on the Logical Pins entry in the tree view.

2. Choose Edit Pin List.

The Logical Pins dialog box displays.

3. To modify the pin interpretation, click Edit in the Pin Pattern Interpretation group box.

The Pin Name Interpretation page of the Part Developer Setup Options dialog boxappears.

4. To ensure that the pins ZZ1-ZZ16 are interpreted as bits of a vector pin, select theBaseName-Bit option.

5. Click OK.

6. Enter ZZ1-ZZ16 in the Pin Name field.

7. Click Add.

The pins ZZ1-ZZ16 will get added to the logical pins list as vector pins. Next, you needto delete the pin P2.2.

8. Right-click on the pin P2.2.

9. Select Delete.

The P2.2 pin will get deleted from the logical pins list

10. To accept the changes, click OK.

Next, you need to update the package to synchronize it with the modified pin list.



Modifying Packages

Task Overview

Modify the plcc package to reflect the changes done in the logical pins list. Mark the physicalpin that was associated with the deleted logical pin P2.2 as NC. Also, change the value of theJEDEC_TYPE property from plcc68 to plcc84.

Steps

1. Right-click on the N87C196NT_PLCC package in the tree view.

2. Choose Properties.

The Package Properties dialog box appears.

3. Since more pins have been added, the value of the JEDEC_TYPE property needs to beupdated.To select a new value for the JEDEC_TYPE property, click Specify Footprint.

The Physical Properties dialog box appears.

4. To modify the value of the JEDEC_TYPE property, click Browse.

The Footprints dialog box appears.

5. From the displayed list of footprints, select plcc84 and click OK.

The value of the JEDEC_TYPE property changes from plcc68 to plcc84

Next, you need to update the physical to logical pin mapping for the package.

6. Click Physical Pin Mapping.



Notice that the physical pin 43 which was mapped to the logical pin P2.2 is nowunmapped and moved under the physical pins list. You need to mark this pin as NC.

7. To mark the physical pin number 38 as NC, select the NC check box next to the pin.

Next, you need to add the physical pin numbers for the logical pins ZZ1-ZZ16. For this,you will again extract the physical pins from the footprint.

Note: When you re-extract pin numbers from a footprint for an existing package, then allthe pin numbers present in the package, but not present in the footprint are removed fromthe package. The mappings for pin numbers present on the package, and also presenton the footprint are preserved. The rest of the pin numbers on the footprint are added asunmapped pins.



8. To extract the physical pin information, click Pin Numbers.

A confirmation box appears.

9. Click Yes.



The additional pin numbers get extracted from the footprint and added to the physicalpins list.

Next, you need to map the physical pins 69-84 to the logical pins ZZ1-ZZ16.

10. To map the physical pins 69-84 to the logical pins ZZ1-ZZ16, multiselect the physicalpins.

Note: To ease the pin mapping procedure, you can sort the physical pin list by eitherclicking on the Numbers column heading in the Physical Pins list or by right-clicking onthe multiselected physical pins and then choosing either the Sort Ascending or SortDescending option.

11. Next, multiselect the logical pins ZZ1-ZZ16 and click Map.



This maps the physical pins 69-84 to the logical pins ZZ1-ZZ16.

12. To accept the changes, click OK.

Next, you need to modify the symbols.

Modifying Symbols

Overview

Modify split symbols, implies one of the following tasks:

1. Creating new symbols.

To create additional symbols, you need to resplit the pins across a larger number ofsymbols. For example, if you have two symbols for a part and want to create a third one,you will need to specify that you need three symbols and resplit the pins across them.Part Developer provides you with a Symbol Modification Wizard to enable you to resplitthe pins across the symbols.

2. Copying symbols.

You may want to make copies of a symbol to create a flat symbol from a sizeable symbol.However, for parts with split symbols, you cannot simultaneously have both sizeable andflat symbols. You can have either a symbol with all the vector pins/sizeable pinsexpanded or a symbol with the vector/sizeable pins contracted.

3. Deleting Symbols

When deleting split symbols, one of the following is possible:

❑ Deleting all the symbols.

❑ Decrease the number of symbols by resplitting the pins across a smaller number ofsymbols. A Symbol Modification Wizard helps you in effortlessly decreasing thenumber of symbols and resplitting the pins across the smaller number of symbols.

4. Adding Logical Pins

If you add pins to the logical pins list, you cannot globally add them to all the symbols.You need to run the Symbol Modification Wizard to add the logical pins to the requiredsymbol.

Note: You should map the added logical pins to physical pin numbers in the packagebefore you run the Symbol Modification Wizard.



5. Modifying/ Deleting Logical Pins

If you add or delete a logical pin and then try to save the part, it will ask you whether youwant to regenerate the symbols on which the pins have been added or from where thepins have been deleted. If you choose to regenerate the symbols, they will lose theirexisting shape and get saved as rectangular symbols.

Task Overview

Modify the split symbols of the N87C196NT part. Create a third symbol and modify theexisting symbols so as to have the vector pins ZZ1-ZZ16 on sym_1 and the power pins andNC pin on sym_3.

Steps

1. To begin the process of modifying the split symbols, right-click on any one of the existingsymbols.

2. Select Modify Pin List.

The Split Symbol Modification wizard appears.

3. Since you need to create three symbols, specify the value in the Number of splitsymbols field as 3 and click Next.

The second page of the Split Symbol Modification Wizard appears. Notice that thelogical pin P2.2 which was deleted from the logical pins list is automatically deleted fromthe symbols. Also, the pin ZZ1-ZZ16 are added to the pin list. Since they are bits of avectored pin, there is a single entry ZZ in the matrix corresponding to the vectored pin.



The pins that are currently present in the symbols sym_1 and sym_2 are checkedappropriately.

4. Modify the pin list to add the pin ZZ to sym_1 and move the power and the NC pins tothe sym_3.

5. Click Next.

The Summary page of the Symbol Modification Wizard appears.



6. To complete the symbol modification, click Finish.

You successfully modified the symbols and created the third symbol. From sym_1 youdeleted the pin P2.2 and added the vector pin ZZ1-ZZ16. From sym_2, you moved thepower pin to sym_3, and you created the third symbol sym_3 that has the power and theNC pins.

7. Save the part by choosing File > Save.

A message box appears asking you whether new rectangular symbols should be createdfor the modified symbols or whether the existing shape of the symbols should bepreserved. The second option implies that new pins will be added away from theboundary of the symbol. You will need to manually snap the pins to the symbol boundary



in Concept HDL. This functionality is provided to enable addition of pins to existing partswithout destroying the symbol graphics.

8. To retain the shape of the symbols, click OK.




9. Click OK.

Next, you need to view the symbols in Concept-HDL.

10. To view sym_1 in Concept HDL, select sym_1.

11. To launch Concept HDL on sym_1, choose Tools > ConceptHDL.



Concept HDL launches on sym_1. Notice that the vector pins ZZ1-ZZ16 is added awayfrom the symbol graphics.

Next, you need to attach the ZZ vector pins to the symbol outline.

12. Click on pin name ZZ <16 1> on the symbol.

The ZZ<16 1> will be surrounded by a rectangle displaying that it has been selected.

13. Next, press Ctrl and click on the dot, the signal and the pin text ZZ <16 1> entries. Thiswill select all the entries.



14. Right-click on the selection.

15. Select Group of Objects.

This will group the pin name, dot, signal, and pin text together.

16. Right click on the group, and select Move.

17. Move the selected object to wherever you want to place it on the symbol body and clickonce.

You successfully moved the vector pins to the symbol graphics.

18. Close Concept HDL.

Next, you need to ensure the validity of the parts by running the View Verification checkon the part.

19. To run the checks, choose Tools > Verify.

20. Choose View Verification and click OK.

The View Verification check should pass. Next, you will view the bits of the vector pinZZ1-Z16.

Viewing the Bits of a Vector Pin

When you add a vector pin, by default, it appears as pin_name<n..1> format in thesymbols. For example, the vector pins ZZ1-Z16 will appear as ZZ<16..1> in the tree view.However, you can expand the vector pins to view all the bits of the vector pins.

Task Overview

Expand the bits of the ZZ<16..1> of the N87C196NT part.

Steps

1. Expand the sym_1 symbol in the tree view.

2. Right-click on the vector pin ZZ<16..1>

3. Select Expand to Bits.



The vector pins gets expanded to display all the pins of the vector pin ZZ<16..1>

Summary

In this chapter you learned about the steps involved in modifying a split part. In the nextchapter, you will learn to create a multi-section symmetrical part.





6Creating a Multi-Section SymmetricalPart

Objective

To become familiar with the methodology and steps involved in creating a multi-sectionsymmetrical part.


■ Set up Part Developer to apply properties globally to all symbols and packages andinterpret the logical pins in a manner that is most appropriate for the part that is to becreated.

■ Create packages by using the different methods supported in Part Developer.

■ Create symbols.

■ Create a HAS_FIXED_SIZE symbol.


■ Export the part.

Overview

A part in which the pin list that appears in the datasheet (called the logical pin list) is the sameacross the packages and sections (or slots) is known as a symmetrical part. The genericcomponent LS00 (a quadruple 2-input positive-NAND gates symmetrical part) present in theSN5400, SN54LS00, SN54S00, SN7400, SN74LS00, and SN74S00 components will beused as an example while detailing the steps to create a symmetrical part. This will be createdin a build library named my_ library. This part has four independent 2-input NAND gates and


Library Explorer and Part Developer TutorialCreating a Multi-Section Symmetrical Part

comes in DIP, SOIC, Ceramic Chip Carrier (CCC) and Ceramic Flat Packages (CFP). Thepinouts for the specific packages are displayed below:

Note: In the diagram displayed above, the following representations are used for thepackages.

Starting Part Developer

Task Overview

Create the LS00 part in the my_library build library.

Steps

Since the part has to be created in the my_library build library, ensure that my_library isselected in Library Explorer. To launch Part Developer:


J Package DIP Package

W Package Ceramic Flat Package (CFP)

N Package SOIC Package

FK Package Ceramic Chip Carrier (CCC)




2. Since you need to set up Part Developer before you create the part, click Cancel.


Setting Up the Part Developer

The first step in creating parts using Part Developer is to set up Part Developer to ensure thatthe pin names are interpreted correctly. To know more about pin name interpretations, seeConfiguring Pin Name Interpretation on page 57.

Task Overview

LS00 is a four-slot part. The datasheet for LS00 has the pin names in<Numeral><Alphanumeric> pattern. Therefore, configure Part Developer to interpret the pinsin the Slot-BaseName format.

Steps



2. Click Pin Name Interpretation.

The Pin Name Interpretation property page appears.



3. Since the pin name is represented in LS00 as <Numeral><Alphanumeric> and the parthas four slots, select the Slot-Base Name option in the Pin Name Interpretation tabin the Part Developer Setup Options dialog box.

4. Click OK.

The next step is to enter the part properties such as the part name, and the logical pininformation.

Entering Part Properties and Logical Pins Information

Task Overview

Create the LS00 part and enter the part properties and the logical pins for the part. You willcreate the SN5400 implementation of LS00.

Steps

1. Choose File > New > Part.

The New Part Properties dialog box appears. You need to specify the properties for thenew part in this dialog box.

2. Select the library name as my_ library.

3. Specify the part name as LS00.

4. Specify the physical part name as SN5400.

5. Specify the part type as IC.



The completed dialog box should look appear as following:

6. Click OK.




7. Select the pin type as INPUT.

Note: This is selected by default.

8. Enter the logical pin names for input pins as 1A-4A, 1B-4B.

9. Click Add to add the specified pin names to the logical pin list.

10. Repeat the step 8 and 9 for the different pin types. For LS00, to enter output pins, selectpin type as OUTPUT, enter 1Y-4Y as the pin names, and click Add. Repeat for GNDand VCC pins.

The loaded Logical Pins dialog box for LS00 should appear as following:

11. Click OK to accept the entries of the Logical Pins dialog box.

A Part Developer Warnings message box appears. The warning message states thatwhen you enter logical pins, they are entered in the slot range 1 to n, but when youreopen the part, the slot ranges will appear as 0 to n-1. For example, for LS00, the slot



ranges entered was 1-4. However, after you create the part and reopen it in PartDeveloper, the slot ranges will appear as 0 to 3. Therefore, pins 1A-4A will appear as 0A-3A and so on.

12. Click OK.

The next step is to create the packages for the part. But, before you create the packages youwill save the information that you have so far entered.

Intermediate Saving of Parts

When you save a part in Part Developer, several pre-save checks are run. So if you try to savean incomplete part, you might get some warnings and the part will not get saved.

Therefore, to save a work-in-progress part, you should use the intermediate save feature ofPart Developer.

To save the part information in an intermediate save file:

1. Choose File > Intermediate Save.

The Save As dialog box appears.

2. Enter ls00 in the File Name field and press Enter.

You successfully saved the part in an intermediate file.

Creating Packages

Task Overview

Create the packages for the LS00 part.



Steps

1. Choose File > New > Package.

The New Package dialog box appears. The General tab is selected by default.

Note: Alternately, the New Package dialog box can be displayed by the RMB menuoption on a “Packages” tree item.

2. Select the Specify Package Type field.

3. Enter the package type as DIP.

4. Enter the equivalent packages, as CFP and click Add.

5. To enter the value for the JEDEC_TYPE property, click Specify Footprint.

The Physical Properties dialog box displays.

6. Click Browse.



The Footprints dialog box appears. The footprints are displayed from the<your_intall_dir>/share/pcb/pcb_lib. The footprint information itself iscontained in the *.dra and *.psm files.

7. Select dip14_3 as the JEDEC_TYPE value.

8. Click OK.

9. Click OK.

You entered the value for the JEDEC_TYPE property. Next, you need to update theBODY_NAME property.

Tip

You can also enter your own footprint information. This can be done either bymanually typing in the value of the JEDEC_TYPE property or by updating theenvironment variable PSMPATH, or by adding new directories which Part Developerwill scan for displaying the footprints. The environment variable PSMPATH stores thepath to the footprint files. To set up the PSMPATH environment variable:

a. Click Allegro Setup.

The User Preferences Editor dialog box appears.



b. Click the Design_paths entry in the Categories list.

c. Click the browse button (the button with three dots) next to the psmpath entry underPreference.

The Physical Paths dialog box appears. You can set up your preferences for location offootprints in this dialog box. You can see the current value of the PSMPATH environmentvariable by selecting the Expand check box.

a. To add new footprints, click on the New button. It is the button with a dotted outline.

A new blank line is added with a browse button.

b. Browse and select the footprints directory in the tutorial_project_data directory.

c. Click OK.



The new footprints are added.

a. Click OK.

b. Click OK again to close the Allegro Setup dialog box.

c. To verify, click Browse button in the Physical Properties dialog box.



The Footprints dialog box appears. Notice that the first entry in the footprints list isplcc84. This entry is coming from the plcc84.dra file located in thec:\tutorial_project_data\footprints directory.

10. Click on the value column of the BODY_NAME property in the Additional Propertiessection.

11. Enter LS00 and click on the Physical Pin Mapping tab.

Footprint information fromc:\tutorial_project_data\footprint location



The Physical Pin Mappings page appears. This page enables you to add physical pinsand map them to the logical pins..

12. To get the physical pin list from the footprint, ensure that the Extract from Footprint isselected, and click Pin Numbers.

A message box appears informing you that all pin numbers extracted from the footprintwill be added as unmapped pins to the package.

13. Click OK.

This lists all the extracted physical pins under the Physical Pins list in the Physical PinMapping property sheet.



Note that the Physical Pins list is not sorted. To sort it on numeric order, click theNumber column heading.

Next, you need to map the physical pins to the logical pins.

14. As per the datasheet, physical pin 1 is mapped to the logical pin 1A. Therefore, select1A in the Logical Pins list and 1 in the Physical Pins list and click Map.



This maps the physical pin 1 to the logical pin 1A. Similarly, map the other logical pins tothe respective physical pins. After the mappings, the Physical Pin Mapping sheetshould appear as following:

15. Click OK to complete the creation of the package.

Next, you need to create the CCC package.



Creating Multiple Packages

Using Part Developer, you can easily and quickly create multiple packages. You can makecopies of an existing package and then make the necessary changes to quickly get the newpackages.

Task Overview

Create the CCC package for the LS00 part.

Steps

1. Right-click on the SN5400_DIP package in the tree view.

2. Select Copy.

3. Right-click on the Packages entry in the tree view.

4. Select Paste.

A copy of the SN5400_DIP package gets created with the name SN5400_DIP[1]. Youneed to modify the properties of this package to create the CFP package.

5. Right-click on the SN5400_DIP[1] entry in the tree view.

6. Select Properties.

The Package Properties dialog box appears. You need to make the following changesto the current information:

❑ Package Type name

❑ JEDEC_TYPE value

❑ Physical Pin Mappings

First, you will change the package type value.

7. Change the Package Type value from DIP[1] to CCC.

Next, since the CFP package has 20 pins, you need to change the value of theJEDEC_TYPE property from dip14_3 to dip20.

8. To change the footprint information, click Specify Footprint.




9. Click Browse.


10. Select dip20 and click OK.

11. Click OK.

Next, you need to update the pin mappings.

12. To update the pin mappings, click Physical Pin Mapping.

The Physical Pin Mapping property page appears. The DIP package has 14 pins.However, the CCC package has 20 pins. Therefore you need to add the additional 6 pins.You can either add the pins manually or extract it from the footprint.

13. To extract the pin list from footprint, ensure that the Extract from Footprint option isselected and click Pin Numbers.

A message box appears informing that all the pin numbers present in the package, butnot present on the footprint, will be removed from the package. The mappings for pinnumbers present on the package, and also present on the footprint, will be preserved.Rest of the pin numbers on the footprint will be added as unmapped pins.

14. Click Yes.

The added pin numbers get added to the Physical Pins list. Next, you need to modifythe pin list for the CFP. Modification of pin list involves unmapping and remapping thechanged pins.

15. To unmap the pins, click Unmap All.

16. Click Yes.

The physical pins get unmapped and move back to the Physical Pins list. Next, youneed to map the physical pins to the logical pins as per the datasheet.

17. Physical pin 1 is marked as NC in the datasheet. To mark it as NC in Part Developer, clickthe NC check box next to physical pin 1 in the Physical Pins list.



18. Map the physical pin 2 to logical pin 1A.

19. Similarly, map the physical pins to the logical pins as per the datasheet.

The completed pin mappings should appear as following:

20. After you complete the mappings, click OK.

You successfully created the CFP package for the LS00 part. After you create the packagesfor a part, you need to create the symbols for the part.



Creating Symbols

To enable you to create symbols effectively, Part Developer provides a Symbol CreationWizard. The Symbol Creation Wizard guides you through the process of creating symbols.

Task Overview

Create symbols for the LS00 part.

Steps

1. Choose File > New > Symbols.

The Power/NC Pin Selection page of the Symbol Creation Wizard appears. TheSymbol Creation Wizard detects that one package has NC pins whereas the otherpackage does not. The Wizard asks you to determine whether you want to put the powerand NC pins on them. In case you choose to do so, you will need to specify the packagegroup on which you want to base your symbol.



A package group is a collection of packages which have the same logical to physical pinmappings. In this example, you will put the power and the NC pins on the symbol.

2. Choose Yes.

3. Click Next.



The Package Selection page of the Symbol Creation Wizard appears. In this pageyou need to determine on which package group you want to base the symbols.

4. To base the symbol on the SN5400_CCC package, choose SN5400_CCC.

5. Click Next.



The Symbol Kinds page of the Symbol Creation Wizard appears.

6. To create a symbol with logical pins and a symbol with logical and NC pins, check theLogical and Logical + NC check boxes.

Note: Notice that there are options in the Symbol Kinds page that are separated byeither by commas or a + sign. The difference between the two types is that if you selectan option with comma, then two different symbols are created. For example, if you selectthe Logical, NC check box, then two symbols, one with logical pins and another with NCpins gets created. If you select an option with the + sign, then only one symbol getscreated. For example, if you select the Logical +Power option, then only one symbolwith both logical pins and power pins gets created.

7. Click Next.



The Package Types page of the Symbol Creation Wizard appears.

Important

The Package Types page enables you to specify the package type for the symbolsthat you are creating. Depending on the symbols that you have chosen to create,you may face a situation where the logical pin list in the package is not the same asthe logical pin list of the symbol.

For example, for a symbol to contain NC pins (Logical + NC in our case), there must bea package which contains the NC pins as logical pins. This implies that there should bea primitive in the chips.prt file which should have the NC pins in its pin section.

However, when you create packages, Part Developer always puts all the power and NCpins in the body section. Therefore to have Power/NC pins as logical pins, you need toexplicitly move the Power/NC pins upto the pin section.

The Symbol Wizard solves this requirement by letting you create new packages whichcontain the Power/NC pins in the pin section. The information from existing packages is



used to create the new packages. You may choose to follow certain conventions whilenaming your packages, such as L_NC for logical+NC pins on the symbol.

8. To create the corresponding packages, for the Logical + NC symbol, specify the packagetype as L_NC and the Source Package as CCC.

9. Choose Next.

This displays the Summary page. Check the summary to ensure its correctness.

10. Choose Finish to create the symbols.

By default, when you create symbols for a symmetrical part, the symbol is created foronly one section or slot. For LS00, the Symbol Wizard will create a symbol which willrepresent only one section of the four possible sections. However, Part Developerprovides the ability to create symbols which represent more than one section. Suchsymbols are called HAS_FIXED_SIZE symbols. Next, you will make a copy of a symboland make it a HAS_FIXED_SIZE symbol.



Copying Symbols

Task Overview

Make a copy of the symbol sym_1.

Steps

1. Right-click on the symbol sym_1 in the tree view.

2. Select Copy.

3. Right-click on the Symbols in the tree view.

4. Select Paste.

A new symbol sym_3 is created in the tree view. This symbol is a copy of the symbolsym_1.

Next, you will make this symbol a flat symbol.

Creating HAS_FIXED_SIZE Symbols

Normally when you create a multi-section symmetrical part, only one of the section isdisplayed in the symbol. For example, for LS00, only one section containing the logical pinsA, B and Y is displayed in the symbol. However, you may need to create symbols that showmore than one section. You can create such parts by modifying the HAS_FIXED_SIZEproperty of a symbol. Such symbols are called HAS_FIXED_SIZE symbol.

Task Overview

Display all the four sections of LS00 in sym_3 by make the symbol sym_3 aHAS_FIXED_SIZE symbol.

Steps

1. Right-click on sym_3 in the tree view.

2. Select Fixed Size.



The Fixed Size Symbol dialog box appears.

3. To make this symbol represent all the four sections of LS00, change the Size entry to 4.

4. Click OK.

You successfully created a HAS_FIXED_SIZE symbol.

After you complete creating the symbols, you should verify the part to ensure that it ususable and then export it to the reference area. See Verifying Parts on page 76 andExporting Parts to the Reference Area on page 83 for details.

Summary

In this chapter you learned about the methodology and steps involved in creating a multi-section symmetrical part. In the next chapter you will learn to modify the part that you createdin this chapter.



7Modifying Multi-Section SymmetricalParts

Objective

To become familiar with the methodology and steps involved in modifying a multi-sectionsymmetrical part.


■ Import a part from the reference library.

■ Set up Part Developer to view the part data as you had entered it.

■ Delete a package.

■ Delete a symbol.

■ Add a logical pin.

■ Delete a power pin.

■ Modify the packages.

■ Modify the symbols.


■ Export the part.

Importing a Part

When you want to modify a part in the reference library, you need to import the part into yourbuild area. After the part has been imported, you can use Part Developer to modify the partas required. For details, see Importing a Part on page 86.


Library Explorer and Part Developer TutorialModifying Multi-Section Symmetrical Parts

After you import the part into the build area, you open it in Part Developer and make thenecessary changes.

Launching Part Developer



2. Since you need to set up Part Developer before you create the part, click Cancel.


Setting Up the Part Developer

LS00 is a four-slot part. The datasheet for LS00 has the pin names in<Numeral><Alphanumeric> pattern. When creating the part, you had configured the pins tobe interpreted as Slot-BaseName format. Therefore, when reading the part, you shouldensure that the pins are interpreted in the Slot-BaseName format.

Task Overview

Setup Part Developer to interpret the pins in the Slot Number - Base Name format.

Steps





2. Select the Slot Number - Base Name option.

3. Click OK.

You setup Part Developer to read pins of LS00 in Slot-BaseName format. This is thesame format in which you had entered the pin names whine creating the part. Next, youwill modify the pin list.

Modifying Pin List

Task Overview

Add a scalar pin Z to the part. Also, delete the power pin GND from the part.



Steps

1. Right-click on the Logical Pins entry in the tree view.

2. Select Edit Pin List.


3. Enter Z in the Pin Name field.

4. Click Add.

5. To complete the process, click OK.

Next, you need to delete the power pin GND.



6. Expand the Logical Pins entry in the tree view.

7. Right-click on the GND entry in the tree view.

8. Select Delete.

You successfully deleted the GND power pin from the part. Next, you need to modify thepackages and the symbols to reflect that changes in the pin list.

Deleting Packages

Task Overview

Delete the SN5400_L_NC package.

Steps

1. Right-click the SN5400_L_NC package in the tree view.

2. Select Delete.

The SN5400_L_NC package is deleted from the LS00 part. Next, you will delete asymbol of the LS00 part.

Deleting Symbols

Task Overview

Delete the symbol sym_2.

Steps

1. Right-click on the symbol sym_2 in the tree view.

2. Select Delete.

The sym_2 symbol of ls00 part is deleted. Next, you will modify the remaining packagesto add the scalar pin Z.



Modifying Packages

Task Overview

Modify the DIP, CFP packages of the LS00 part.

Steps

1. Right-click on the SN5400_DIP entry in the tree view.






The Physical Pin Mapping property page appears. Note that the power pin GND isremoved from the logical pins list and the physical pin that was mapped to it is movedback to the Physical Pins list.

4. Map the physical pin 7 to the logical pin Z.

5. Click OK.

You successfully updated the DIP package. Similarly update the CFP package. After youmodify the packages, you need to updates the symbols.



Modifying Symbols

Task Overview

You added a scalar pin Z and remove the power pin GND from the part. Modify the symbol toreflect the changes.

Steps

First, you will add the scalar pin to all the symbols. To enable you quickly add a logical pin toall symbols in a sizeable part, do the following:

1. Right-click on the Symbol entry in the tree view.

2. Select Add Logical Pins.

The Add Logical Pins dialog box appears. It displays the logical pin that you can addto all the symbols.

3. Select the pin Z and click OK.

The logical pin Z gets added to all the symbols of the LS00 part.

4. Save the part by choosing File > Save.



A message box appears asking you whether new rectangular symbols should be createdfor the modified symbols or whether the existing shape of the symbols should bepreserved. The second option implies that new pins will be added away from theboundary of the symbol. You will need to manually snap the pins to the symbol boundaryin Concept-HDL. This functionality is provided to enable addition of pins to existing partswithout destroying the symbol graphics. See Modifying Symbols on page 94 for details.

5. To regenerate the symbols, select all the two symbols and click OK.




6. Click OK.

After you modify the symbols, you should verify that the part is error free.

7. To verify the part, select Tools > Verify.

8. Choose View Verification and click OK.

The View Verification check should pass.

Summary

In this chapter, you learned the methodology and steps involved in modifying a multi-sectionsymmetrical part. In the next chapter, you will learn to create an asymmetrical part.



8Creating Asymmetrical Parts

Objective

To become familiar with the methodology and the steps involved in creating an asymmetricalpart.


■ Understand the definition of an asymmetrical part.

■ Understand the methodology involved in creating asymmetrical parts.

■ Manually enter the physical pin information.

■ Create multiple packages.

■ Create multiple symbols.

■ Verify parts.

■ Export a part into the reference area.

Overview

When creating parts, you may come across parts in which the logical pin lists acrosspackages or slots are different. These are called asymmetrical parts. LS241 is such anasymmetrical part.


Library Explorer and Part Developer TutorialCreating Asymmetrical Parts

■ Different logical pin list across slots: Consider the part LS241. The pins appear in thedatasheet as follows:

As displayed, LS241 is an 8-slot part with a low asserted enable signal (G*) and a highasserted enable signal (G). The high asserted enable signal G is present in four slots andlow asserted enable signal G* is present in the remaining four. This divides the part intotwo groups. The first group has G as the enable pin and the second group has G* as theenable pin. Because the functionality of each section in a group is the same and because



of the different assertion signals across the sections, the logical pin list across the sectionor slots are different. The pin entries created will be as follows:

Notice that the pin number G is present in the first four slots and not in the next four. Theslots in which G is not present have 0 as pin numbers.

In this chapter, you will learn to create an asymmetrical part where the asymmetry arises dueto different pin list across slots.

DIfferent pinlist acrossslots



Create the LS241 part. It is an eight slot part with two slot groups, one with low assertedenable signal 1G* and the other with high asserted enable signal 2G. This part comes in DIP,SOIC and CFP packages. The diagram of the LS241 part is displayed below..

Entering Part Properties

1. Choose File > New > Part.

The New Part Properties dialog box appears.

2. Select my_library from the Library Name drop-down list box.

3. Enter LS241 in the Part Name field.

Note: The Physical Part Name field also gets filled in automatically as you enter the apart name field. This field is used as the PART_NAME property in the chips.prt file.

4. Click OK.

The Logical Pins dialog box appears. Next, you need to configure the pin nameinterpretation for the logical pins.



Configuring Pin Name Interpretation

Need for Configuring Pin Name Interpretation

As displayed, the LS241 component is an eight slot part with two slot groups, one with lowasserted enable signal 1G* and the other with high asserted enable signal 2G. In thedatasheet the pins are present in <Numeral><Alphanumeric String><Numeral> format suchas 1A1, 1A2 and in <Numeral><Alphanumeric String> format such as 1G* and 2G. Here theleading numeral represents the group, the alphanumeric string represents the base nameand the trailing numeral represents the slot number. Therefore the pins need to be interpretedas Group-Base Name-Slot and Group-Base Name respectively.

Alternately, you can also enter the pins in the BaseName-Slot format, that is, as A1-A8, B1-B8 etc. See Alternate Method of Creating an Asymmetrical Part on page 162 for details.

Task Overview

Configure the pin interpretation to interpret <Numeral><Alphanumeric><Numeral> pins asGroup-BaseName-Slot and <Numeral><Alphanumeric> as Group-BaseName.

Steps

1. Click Edit in the Pin Name Interpretation group box in the Logical Pins dialog box.



The Pin Name Interpretation tab of the Part Developer Setup Options dialog boxappears.



2. Select Group-Base Name [G-BN] and Group-Base Name-Slot [G-BN-S].

3. Click OK.

You successfully setup Part Developer to interpret pins as Group-BaseName-Slot andGroup-Base Name. Next, you need to enter the logical pins as they appear in thedatasheet.

Entering Logical Pins

Task Overview

Enter the pin information as displayed in the diagram into Part Developer. The pins will beentered in the same sequence as they appear in the diagram.



Steps

1. Select INPUT from the Pin Type as Input.

2. Enter 1A1-1A4, 2A1-2A4 in the Pin Name text box.

3. Click Add.

4. Enter 1G in the Pin Name text box.

5. Click Add.

6. Enter 2G in the Pin Name text box.

7. Select the Active Low check box.

8. Click Add.



9. Similarly, add the 1Y1-1Y4, 2Y1-2Y4 as the output pins and VCC and GND as the powerpins.

The filled up Logical Pins dialog box for LS241 part is displayed below:

10. To accept the entries and close the Logical Pins dialog box, click OK.

After the logical pins have been entered, you need to create the packages.



Creating Packages

Task Overview

Create the DIP package for the LS241 part. Modify the value of the BODY_NAME propertyto LS241. The logical to physical pin mappings are as following:

Steps

1. To begin the process of creating packages, choose File > New >Package.

The New Package dialog box appears. By default, the General tab is selected.

2. Enter DIP in the Specify Package Type field.

3. To update the value for the JEDEC_TYPE property, click Specify Footprint.



The Physical Property dialog box appears. You need to specify the value of theJEDEC_TYPE property for the package. The value for the JEDEC_TYPE property willbe picked up from the Allegro footprints of standard packages provided by Cadence.

4. To select the appropriate JEDEC_TYPE, click Browse.

The Footprints dialog box appears. This has the complete list of footprints supplied byCadence.

5. Select dip20.

6. Click OK.

7. Next, click in the Value column next to the ALT_SYMBOLS property.

8. Click Browse.


9. Select dip20_3.

10. Click OK.

You selected the value for the JEDEC_TYPE and ALT_SYMBOLS properties.

11. To specify the value for the BODY_NAME property, enter LS241 as the value.

12. Next, you need to enter the physical pins and map them to the logical pins that youentered earlier. To get to the page where you enter physical pins, click the Physical PinMapping tab.

You can either add the physical pins manually, or extract them from the footprint.Extracting the pins from footprint is useful when you are dealing with large pin countparts. For this example, you will add the pins manually.



13. To add the pins manually, select the Add Manually option.


The Add Physical Pin Numbers dialog box appears. You add the physical pin numbersthrough this dialog box.

15. Since the part has 20 pins, enter 1-20 in the Numeric field and click OK.



The physical pins get added to the Physical Pins list in the New Package dialog box.

Next, the physical pins need to be mapped to the logical pins. The general method tomap a physical pin with logical pin is to select both the pins and click on the Map button.

16. As per the datasheet, physical pin 1 is mapped to logical pin 1G. Therefore, select 1 inthe Physical Pins list, and select 1G in the Logical Pins list.

17. To map the selected pins, click Map.

The physical pin 1 is mapped to the logical pin1G

Note: Whenever you map a physical pin to a logical pin.The pin number moves from thePhysical Pins list to the Logical Pins list and the next pin number in the list gets selectedin the Physical Pins list. This eases the pin mapping effort as you do not need to explicitly



select a physical pin to map to a logical pin. You can simple select the logical pin that you wantthe automatically selected physical pin to be mapped to, and map it.

18. To map pin number 2 to logical pin 1A1, select 1A1 in the Logical Pins list.

19. Click Map.

Similarly, map the remaining pins.



After the mappings are done, the New Package dialog box should appear as displayedbelow.

20. Click OK to complete the process of creating the DIP package.



Creating Multiple Packages

Task Overview

Create the CCC package for LS241. The package information is displayed below:

You can create multiple packages in two ways:

■ By creating a fresh package.

■ By making a copy of an existing package and then making the necessary changes. Thismethod helps you save time while making multiple packages for a part. For this example,you will make a copy of the DIP package and then make the necessary changes for theCCC package.

Steps

1. Right-click on the LS241_DIP package in the tree view.

2. Select Copy.

3. Right-click on Packages.

4. Select Paste.



A copy of the LS241_DIP is made with the name as LS241_DIP[1]. You need to changethe properties of this package.

5. Right-click on LS241_DIP[1].



7. Enter CCC in the Specify Package Type field.

8. To specify the correct footprint for CCC type package, click Specify Footprint.


9. To display the list of available footprints in Allegro, click Browse.

The Footprints dialog box displays.

10. Select flat20 and click OK.

11. Since there are no alternate symbols for the CCC package, remove the value for theALT_SYMBOLS property.



12. Click OK.

Next, you need to change the logical to physical pin mapping information for the CCCpackage.

13. Click the Physical Pin Mapping tab.

The Physical Pin Mapping tab page appears. This page displays the current logical tophysical pin mappings. You need to update the mapping information for the CCCpackage.

Notice that there is no difference in the pin mappings between the DIP and the CCCpackage, therefore there is no need to make any changes in the Physical Pin Mappingproperty page.

14. To complete the creation of the CCC package for LS241, click OK.

After you create the packages, the next step is to create symbols for the part.

Creating Symbols

Part Developer provides a powerful Symbol Creation Wizard which enables you to quicklyand efficiently create symbols for a part.

Task Overview

Create symbols for the part.

Steps:

1. To begin creating the symbols, select File > New > Symbol.

The Select Sections page of the Symbol Creation Wizard appears. This pageinforms you that there are two groups which exist for the packages. You need to



determine the groups for which you want to create the symbols. You can select either oneof the groups or both. You will create a symbol based on both the slot groups.

2. Click Select All and click Next.

The Symbol Kinds page of the Symbol Creation Page appears. In this page you candetermine the types of symbols you want for the part. For this example, you will createthe following symbols:

❑ A symbol with only logical pins



❑ A symbol with logical and power pins

3. Note that, by default the Logical option is selected. This will create the symbol with onlylogical pins. To create the symbol with both logical and power pins, select theLogical+Power option and click Next.

The Package Types page of the Symbol Creation Page appears. This page displaysthe symbols that you want to make and the packages that correspond to the symbols.You will notice that the value of the Package Type field next to the Logical symbol isfilled with the DIP,CCC values whereas next to the Logical + Power symbol, the valueof the Package Type field is empty.

This happens because when you create a package using Part Developer, the power andNC pins are always put in the body section of the chips.prt file. However, when youwant a symbol to show the power and/or NC symbol, the power/NC pins mustnecessarily be in the pin section of the chips.prt file. Since currently there are no



packages that have the power/NC pins on the pin section, the value of the PackageType next to the Logical + Power symbol appears blank.

To enable the creation of a symbol which can display both the logical and power/NC pinson the symbol, you need to create a new package that will have the logical as well as thepower/NC pins on the pin section. You can do this by entering a package name in thePackage Type field next to the Logical + Power symbol and specify a source packagefrom which this package will be created. When you specify the source package, PartDeveloper uses the information from the source package and creates the section for thepackage in the chips.prt file.

4. Enter lp in the Package Type field next to the Logical + Power symbol entry.

5. Select DIP as the source package and click Next.



The Summary page of the Symbol Creation Wizard appears. Notice that four symbolswill be created. This is because Symbol Wizard creates one symbol for each of the slotgroups in the part.

6. To complete the process of creating the symbols, click Finish.

Saving Parts

Task Overview

Save the LS241 part.



Steps

➤ To save the part, choose File > Save.


Verifying Parts

The parts that you created should be error free and usable in the design flow. Part Developerprovides you with robust verification tools which ensure that the parts are correct and usable.

Task Overview

Verify the LS241 part for errors across the different views.

Steps:

1. To begin the process of verifying the part, choose Tools > Verify.

2. To do the verification of the stand-alone views and cross check view, select the ViewVerification option.

3. Click OK.

The Verification Results dialog box appears. The verification should not report anyerrors.

Congratulations. You have successfully created the LS241 part.

After you create a part and verify it, you should export the part into the reference area andthen delete it from the Build area. See Exporting Parts to the Reference Area on page 83 fordetails.

Alternate Method of Creating an Asymmetrical Part

In parts such as LS241, if you choose to use the BaseName-Slot notation for entering thelogical pins then there has to be a mechanism to determine to which slot groups do the scalarpins G and G* belong. This ability is provided by the Expand to Slots function. To do so:

1. Setup Part Developer (Tools > Options > Pin Name Interpretation) to interpret<Alphanumeric String><Numeral> logical pins as BaseName-Slot.



2. Enter the logical pins, as A1-A8, B1-B8, Y1-Y8, G, and G*.

Note: Note the difference in the logical pin naming. If you had chosen the Group-BaseName-Slot interpretation instead of the BaseName-Slot interpretation, the pinswould have been entered as 1A1-1A4, 2A1-2A4, 1B1-1B4, 2B1-2B4, 1Y1-1Y4, 2Y1-2Y4,1G and 2G*.

3. Create a new package.

4. Enter/extract the required physical pins.

5. Associate the logical pins to the physical pins except G and G*.

6. Right-click on G.

7. Select Expand to slots.

This will expand the scalar pin G across all the slots in the part. For LS241, the scalarpin G will get expanded to all the eight slots, G<1>..G<8>.

Similarly, expand the other scalar pin G*.

8. Since G is common across the first four slots, map the physical pin 1 to G<1>..G<4>.Leave the remaining slots empty.

Similarly, map the physical pin 19 to the G*<5>..G*<8> slots.

9. To complete the process, click OK.

After you create the packages, the remaining steps in creating an asymmetrical parts are thesame as described in the example before.

Summary

In this chapter you become familiar with the methodology and steps involved in creatingasymmetrical parts. In the next chapter, you will learn to modify the part that you created inthis chapter.



9Modifying Asymmetrical Parts

Objective

To become familiar with the methodologies and steps involved in modifying asymmetricalparts.


■ Import a part from the reference library.

■ Set up part developer to read-in asymmetrical parts as they were entered.

■ Add logical pins.

■ Modify the packages.

■ Modify the symbols.

■ Add package pin properties.

■ Add symbol pin properties.

■ Change the blank pin spacings for a symbol pin.


Overview

In this chapter, you will import the LS241 part into the build area and modify it.

Importing a Part

The first step in modifying a part in a reference area is to import it into the build area. To seethe steps, see Importing a Part on page 86.

After you import the part, open the part in Part Developer to modify it.


Library Explorer and Part Developer TutorialModifying Asymmetrical Parts

Setting up Part Developer

Before opening a part, you should configure Part Developer to ensure that the part is read incorrectly. The Format tab is divided into two group boxes:

■ Low Asserted Pin Syntax.

The setting in this group box determines the pin names that Part Developer will treat aslow asserted while reading a part. You also specify the notation that Part Developershould use to write a low asserted pin into the symbol and the chips.prt file. You havethe following options:

❑ Either with a asterisk (*) or _N suffix: In this case any pin which has either a * or _Nas a suffix in its name is read as a low asserted pin. You can then determine whetheryou want to write the low asserted pin into the symbol file with either the '*' or '_N'suffix.

❑ With a star (*) notation: In this case, the pins with a * suffixed in their names are readas a low asserted pin. The pin is written back to the symbol file with the *.

❑ With a _N notation: In this case, the pins with _N as suffix are read in a low assertedpin. They are written into the symbol file with the _N notation.

Note: Select the Use minus [-] sign for low asserted pins in Packageview to ensure that the pins that are considered low asserted are written into thechips.prt file prefixed with a minus [-] sign. If you leave this unchecked, then the lowasserted pins are written into the chips.prt file with the same notation as they werewritten into the symbol.css file.

■ Chips File Reading Options

The options in this group box determines how Part Developer reads the chips.prt filefor displaying the following:

❑ Asymmetrical parts

Asymmetrical parts have multiple slots which have different functionality.Corresponding to each functionality, there is a pin list. All sections or slots that havethe same functionality have the same pin list. The slots that have the samefunctionality form one group. You can choose to display the pin numbers in such away that the group numbers are also visible. You can do this by selecting the Usegroup format for reading asymmetrical parts check box.



If this option is checked, you can see the groups to which each of the pin in a packagebelongs. For example, displayed below is the expanded pin list of the SOIC package ofthe LS241 part, where the group format is used to read the asymmetrical part.

Group Number



The same part is displayed again. This time, the group format has not been used to readthe asymmetrical parts (the Slot-Base Name format has been used). Notice that thegroup information is not displayed in the expanded package pin list.f

❑ Sizeable pins

Sizeable pins can be displayed in Part Developer in one of the following ways: SlotNumber-Base Name or Base Name - Slot Number.

In the Slot Number - Base Name format, the numeric part is the slot number whilethe alphanumeric string part is the base name. For example, if a pin A is present inslots 1,2,3,4, it will be displayed as 1A, 2A,3A,4A.

Slot Number



In the Base Name- Slot Number format, the alphanumeric string part is base nameand numeric part is treated as a slot number. For example, if a pin A is present inslots 1,2,3,4, it will be displayed as A1, A2,A3,A4.

❑ Vector pins

Vector pins can be displayed in Part Developer in one of the following ways: BitNumber - Base Name or Base Name - Bit Number. In the Bit Number - Base Nameformat, the numeric part is the bit number while the alphanumeric string part is thebase name. For example, if a vector pin A has two bits, it is displayed as A<Size2..0>.

In the Base Name - Bit Number format, the alphanumeric string part is the basename and the numeric part is the bit.

For reading in the LS241 part, ensure that the Use group format for reading asymmetricalparts is selected. This is required because you had used the group format while creating thepart.

Task Overview

Set up Part Developer to read in the LS241 part in the same format as you had created it.

Steps

1. Launch Part Developer.

2. Select Tools > Options.


3. Click Format.

The Format property page appears.

4. Ensure that the following options are selected:

❑ In the Low Asserted Pin Syntax group box, Suffix ‘*’ and Suffix ‘_N’ is selected.This will ensure that the pins in the symbol file which have either * or _N as the suffixare read in as low asserted pin.

❑ Use minus [‘-’] for low asserted pins in Package view is selected. This willensure that the low asserted pins are written back into the chips file with the ‘-’ sign.

❑ Use group format for reading asymmetrical parts is selected. This ensures thatthe part is loaded with the group information.



5. Click OK.

Next, you need to open the part to modify it.

Opening the Part

Task Overview

Open the LS241 part.

Steps

1. Select File > Open

The Open Part dialog box appears.

2. Select my_reference_libs from the Library drop-down list.

3. Select ls241 from the Cell drop-down list.

4. Click OK.

The LS241 part launches in Part Developer. Next, you will add a logical pin to the part.

Modifying Logical Pin List

Task Overview

Add logical pins 1K and 2K to the LS241 part.

Steps

1. To add the logical pins 1K and 2K to the LS241 part, right-click on the Logical Pins entryin the tree view.

2. Select Edit Pin List.


3. Enter 1K, 2K in the Pin Name field.



4. Click Add.

5. Click OK.

This adds the logical pins 1K and 2K to the logical pins list. Next, you need to update thepackages and symbols to reflect this change.

Modifying Packages

Task Overview

Update the packages to add the new logical pin. Also add a property my_prop with the valueABCD to the packages. Updating the packages involves the following tasks:

■ Adding the physical pins for the new logical pins

■ Mapping the physical pins to the new logical pins

■ Updating the footprint information, i.e. the JEDEC_TYPE and ALT_SYMBOL values.

■ Adding the additional properties

■ Saving the packages

Note: Although in this section you will be adding the physical pins manually and thenupdating the value for the JEDEC_TYPE property, it is not the recommended way. This styleis covered only to show the possible ways in which you can use Part Developer. Therecommended way to modify packages is to first update the value of the JEDEC_TYPEproperty, then extract the footprint information and change the pin mappings if required.

Steps

1. Right-click on the LS241_DIP package in the tree view.






The Physical Pin Mapping property page appears. Note that the logical pins 1K and2K appear in the Logical Pins list.

Next, you need to add the physical pins for the added logical pins.

4. To manually add the pins, select the Add Manually option.




The Add Physical Pin Numbers dialog box appears. Since the package alreadycontains 20 pins, you need to add 2 more pins for the additional two logical pins.

6. Enter 21-22 in the Numeric field.

7. Click OK.



The physical pins get added to the Physical Pins list.

Next, you need to map the physical pins to the logical pins.

8. To map the logical pin 1K to the physical pin 21, select the pins and click Map.

9. Similarly, map logical pin 2K to physical pin 22.

Next, you need to update the value of the JEDEC_TYPE property for the package.

10. Click General.

The General property page appears.

11. Click Specify Footprint.




12. To update the JEDEC_TYPE property value, click Browse.


13. Select dip22_3 and click OK.

Next, you need to update the ALT_SYMBOLS value.

14. Click on ALT_SYMBOLS.

15. Click Browse.


16. Select dip22_4 and click OK.

17. Click OK.

You successfully modified the footprint information. Next, you need to add the my_propproperty to the package and add ABCD as its value.

18. Double-click in the blank cell under the BODY_NAME property in the AdditionalProperties section.

19. Enter my_prop and click on the column under Value.

20. Enter ABCD as the value.

21. To complete the process of updating the package, click OK.

You successfully updated the DIP package of the LS241 part. Similarly update the otherpackages. After you update the packages, you need to update the symbols.

Updating Symbols

Task Overview

Update the symbols to add the new logical pins to the symbol drawing.

Steps

For asymmetrical parts, you need to update the symbols individually.

1. To update sym_1, right-click on the sym_1 entry in the tree view.



2. Select Modify Pin List.

The Symbol Modification Wizard appears.

This page informs you that the selected symbol is based in the DIP, CCC packages andasks you whether you want change the package association for the symbol. By default,No is selected.

3. Since you do not need to change the package association, click Next.



The next page of the Symbol Modification Wizard appears.

This page displays the different slot groups that exist for the package. You need todetermine the slot group on which you want to base the symbol.

4. To update the symbol for the first slot group, select Groups 1 and click Next.



The Summary page appears.

The Summary page displays the pins that will be visible in sym_1 and the package thesymbol is associated with.

5. Click Finish to complete the process of updating the symbol.

Similarly update the other symbols for the part. After you update the packages and thesymbol, you need to save the part.

Saving Modified Part

Task Overview

Save the modified LS241 part.



Steps

1. Choose File > Save.

A message box appears asking you whether new rectangular symbols should be createdfor the modified symbols or whether the existing shape of the symbols should bepreserved. The second option implies that new pins will be added away from theboundary of the symbol. You will need to manually snap the pins to the symbol boundaryin Concept-HDL. This functionality is provided to enable addition of pins to existing partswithout destroying the symbol graphics.

2. To regenerate symbols, select the regenerate option for all the symbols.

3. Click OK.

The Part Developer Errors dialog box appears. It should show no errors. Next, you willadd some properties to the symbol and package pins.



Adding Symbol Pin Properties

Task Overview

Add the property my_pack_pin_prop to the pin 1G in the LS241_DIP package. The valuefor the property should be my_prop_value.

Steps

1. To associate a pin property to the LS241_DIP package, expand the package in the treeview.

The expanded view of the LS241_DIP package appears.

2. Right-click on the pin 1G.




The Package Pin Properties dialog box appears. You can set the pin specificproperties for a package through this dialog box.

4. To enter the my_pack_pin_prop property, click Additional.



The Additional property page appears. You enter the additional properties for a packagepin in this property page.

5. Enter my_pack_pin_prop under the Name column and click under the Value column.

6. Enter my_prop_value and click OK.

You successfully entered a package pin property. Next, you will add a symbol pinproperty.



Changing Symbol Pin Properties

Task Overview

Do the following changes to the pin G of symbol sym_1:

■ Change the blank pin spacing of pin G to leave 5 stub pin stubs before the pin G.

■ Add a symbol pin property my_symbol_pin_prop to the logical pin G in sym_1. Thevalue of the property should be my_symbol_prop_value. Set up the property so thatboth the pin property name and its value is visible and left-aligned.

Steps

1. To associate a pin property to the sym_1 symbol, expand sym_1 in the tree view.

2. Right-click on G.




The Symbol Pin Properties dialog box appears. You specify all the symbol pin specificproperties through this dialog box.

4. Enter 5 in the Before field of the Blank Pin Spaces group box. This will result in 5 pinstubs being left blank before the pin G in the symbol sym_1. This feature is useful incases where you want to keep a certain amount of gap between two types of pins suchas an address bus and a scalar pin in a symbol.

5. To enter the my_symbol_pin_prop property to the symbol pin, click Additional.



The Additional property page appears. You enter all the symbol pin related propertiesthrough this page.

6. Enter my_symbol_pin_prop under the Name column and click under the Valuecolumn.

7. Enter my_symbol_pin_prop_value.

8. Select Both from the Visible column.

9. Click OK.

You successfully added a symbol pin property. Now save the part.

After you modify a part, you should verify the part for correctness. See Verifying Parts onpage 76 for details. After you verify the part, you should export it to the reference area.See Exporting Parts to the Reference Area on page 83 for details.

Note: After you export a part to the reference area, you should delete the part from the buildarea.



If you view the symbol in Concept-HDL, it should display as following:

Summary

In this chapter you learned to modify an asymmetrical part. In the next chapter you will howPart Developer handles pin texts.



10Handling Pin Texts

Objectives

In this chapter, you will be able to:

■ Understand the methodology involved in handling pin texts.

Methodology

In parts created in earlier versions of Part Developer, the pin text was stored as a note in thesymbol file and not as a pin property. Therefore, there was no direct association of the pin textwith the pin. In the new release of Part Developer, pin texts are stored as properties on thepin.

In the new Part Developer, the following methodology is implemented:

■ For new parts, the pin text is stored as the PIN_TEXT property. This property isassociated with the pin.

■ When parts created in an earlier version of Part Developer or Concept-HDL are loadedin Part Developer, it is likely that the pin texts on symbols are not stored as properties onthe pin. In this case, Part Developer will automatically assign the pin texts to the pins andyou will be prompted to save the part. However, before saving the part, you should verifythat the pin texts are mapped correctly by launching the Associate Pin Text dialog boxand checking the pin texts corresponding to the pins.

■ In case there are some texts that are still unassociated, you should decide whether youwant to retain or remove the text. In case there are any unassociated pin text left on thesymbol, a warning will be given during the saving of the part. You can choose to eitherretain the unassociated text in the symbol or remove them from the symbols. You maywant to retain the unassociated texts if they are symbol texts and not pin texts.

The next time you load such parts, the pin texts will be associated with the pins as pinproperties.


Library Explorer and Part Developer TutorialHandling Pin Texts

To understand this feature, you will open the parts provided in the old_parts libraryunder the tutorial_project_data directory. To open the parts of the old_partslibrary, you need to do the following:

❑ Add the old_parts library to the tutorial_project library project.

❑ Launch Part Developer on the parts of the old_parts library.

Adding Libraries to a Library Project

You can add your own libraries to an existing library project by modifying the cds.lib file ofthe project. You can modify the cds.lib file from within Library Explorer.

Task Overview

Add the old_parts library to the tutorial_project library project.

Steps

1. Launch Library Explorer and open the tutorial_project library project.

2. Choose Edit > Modify Library List.

The cds.lib file appears.

3. Add the following line:

DEFINE old_parts c:\tutorial_project_data\old_parts

4. Save the file and close it.

5. Choose View > Refresh.

The old_parts library gets added to your library project. Next, you will launch PartDeveloper on the parts of the old_parts library to understand how Part Developerworks with parts where the pin texts on symbols are not stored as properties on pins..

Working with Unassociated Pin Texts

To understand the how Part Developer deals with older parts, you will open the following partsof the old_parts library:

■ 3807



This is a part with a 10 bit vector pin O and a scalar pin IN. Each bit of the vector pinhas a pin note associated with it, such as O1, O2 etc. The original symbol isdisplayed below:

■ 803237_50hz

This is a part with 20 logical pins, 4 power pins and two ground pins. The sym_1 isdisplayed below:



Note that some of the pins have two pin texts associated with them, such as LOWBATTERY and EXTERNAL ADJ is associated with the BATT_EXT pin.

Task Overview

Open the 3807 part in the old_parts library and associate the pin texts as pin properties.

Steps

1. In the Library Explorer window, select the 3807 part in the old_parts library.


Part Developer launches on the 3807 part with a message box saying that the pin textsin the symbol are not stored as properties of the pin. This happens because currently thepin texts are not associated to the pins as pin properties.

3. Click OK.

The part opens in the Part Developer with the warning that some text in sym_1 could notbe associated with any pin. You should use the Associate Pin Text option to associate



the text properly. This happens because part Developer tries to associate the pin texts tothe existing pins of the part and finds some text that it fails to associate with any pin.

4. Click OK.

5. To display the Associate Pin Text dialog box, right-click on sym_1 in Part Developertree view.

6. Select Associate Pin Text.

The Associate Pin Text dialog box appears. Since Part Developer has the limitationthat for a vectored pin, bit specific property values are not allowed. So the pin texts for allthe bits are constrained to be the same. Therefore, in the Associate Pin Text dialog box,



only pin O10 gets associated with the vector pin O and rest of the notes are left asunassociated text.

7. Change the pin text associated to the vector pin O from O10 to O. This is requiredbecause Part Developer follows the convention of always adding the range notation (<0>etc.) for pin texts for a vectored pin.

8. Click OK.

Next, you need to remove the unassoicated text as they have no relevance for thesymbol. To remove the unassociated pin texts, you need to save the part.




The Retain Unassociated Text dialog box appears.

10. To remove the unassociated text, select the Remove Unassociated Text checkbox.

11. Click OK.

A message box appears. It should show no errors.

12. Click OK.

13. Launch Concept HDL on the sym_1.

Note that the bits of the vector pin now have O<n> as the pin text associated withthem.For example, bit 1 has the pin text O<1>.

14. Close Concept-HDL and Part Developer.

Next, you will open the 803237_50hz part.

Task Overview

Open the 803237_50hz part in Part Developer.



Steps

1. In Library Explorer, select the 803237_50hz part.


Part Developer launches on the 803237_50hz part with a message box saying that thepin texts in the symbol are not stored as properties of the pin.

3. Click OK.

The part opens in the Part Developer with the warning that some text in sym_1 andsym_2 could not be associated with any pin. You should use the ‘Associate Pin Text’option to associate the text properly.

4. Right-click on sym_1 in the Part Developer tree view.

5. Select Associate Pin Text.

The Associate Pin Text dialog box appears. It is important to remember that althoughPart Developer tries to associate pin texts to pins, three things could happen:

❑ Wrong pin text is associated with a pin.

❑ Some pin texts are left unassociated

❑ Pin with multiple pin texts have only one pin text associated with them. Theremaining stay as unassoicated.

Therefore after the Associate Pin Text dialog box is opened the first time, you shouldverify the pin texts against the symbol and fix the inconsistencies.

In the 803237_50hz, all the three inconsistencies are present. Note that the pins 5VA,8VA, 5VB and 8 VB have incorrect pin texts. Pins such as Z_AMP_IN have no pin textsassociated with them. And pins such as BATT_EXT which had multiple pin texts have



only one pin text associated with them. The remaining pin texts are left as unassoicated.Therefore, you need to fix these inconsistencies.

First, fix the incorrect pin text issue.

6. Edit and change the pin text entry next to pin 5VB from VB to 5VB.

Similarly change the other incorrect pin texts. Next, map the pin texts to the pins whichhave been left blank.

7. Select Z_AMP_IN in the Pin Name column and Z AMP IN in the Pin Text column andclick Map.

This maps the Z AMP IN pin text to the Z_AMP_IN pin. Similarly, map the GAIN BLOCKINPUT, EXTERNAL BIAS, V REF IN, LOOSE LEAD and LOW BATTERY pin texts.

Finally, you need to determine whether you want to add the pin texts to the pin that hadmultiple pin texts.

8. The pin BATT_EXT had two pin texts, LOW BATTERY and EXTERNAL ADJ. PartDeveloper only associated LOW BATTERY pin text to the BATT_OUT pin and left theother pin text as unassociated pin text. In case you want to add it, you will have to editthe LOW BATTERY pin text and type the remaining pin text by hand.



After you have completed updating the pin text association for sym_1, you should verifyand update the pin texts for sym_2.

Note: It is important to remember that the part name that appears in the symbol is thesymbol text stored in the symbol file and can be edited only through the SymbolProperties dialog box.

Next, you need to delete the unassoicated pin texts. To remove the unassociated pintexts, you need to save the part.


The Retain Unassociated Text dialog box appears.

10. To remove the unassociated text, select the Remove Unassociated Text checkbox.

11. Click OK.

A message box appears. It should show no errors.

12. Click OK.

13. Launch Concept HDL on the sym_1 and verify that the pin texts are associated properlyas pin properties.

14. Close Concept HDL and Part Developer.

Summary

In this chapter you learned how Part Developer handles pin texts. This chapter also concludesthe functionality that is available in Library Explorer and Part Developer if you have the PCBLibrarian licence. In the next chapter you will learn to create and work in data-managedprojects.



11Data-Managed Projects

Objective

To become familiar with the methodologies and steps in creating and working with data-managed projects.


■ Understand the methodology of a data-managed project.

■ Setup the environment variables necessary to launch Library Explorer in the data-managed mode.

■ Execute the script to setup areas needed to work in data-managed mode.

■ Create the data-managed project using Library Explorer.

■ Join a data-managed project.

■ Checkout a part and modify it.

■ Checkin the modified part.

Overview of Data-Managed Project

Overview

You can create data-managed (DM) projects in Library Explorer only if you have the PCBLibrarian Expert licence. DM projects allow teams of library developers to work on projects.The Project Leader can create a new DM project and the team members can then join in.Version control of data is supported. The Library Explorer tool provides the interface formanaging library data through checking-in and checking-out of data.

A project comprises of the following storage areas:


Library Explorer and Part Developer TutorialData-Managed Projects

■ Vault or Repository

This is the location where all checked-in data resides. Users (team members and theProject Leader) can check out data, work on it, and check in data back into the repository.Each project has its own repository. Multiple projects cannot share a repository.

■ Integration area (Integ area)

This is the location where all the verified libraries and parts are stored. The ProjectLeader checks out data from the repository, validates it, and updates the integration areawith libraries for the designers. This area serves as the access point for designers.

■ Local work areas/build areas

These are the local work areas owned by individual team members. The team membercan check out data from the repository into the local work area, work on it, and check thedata back in to the repository. Team members can also create new libraries and cells andcheck them into the repository.

The creation of a new project would typically be a one time operation because all thelibraries can be managed by one project. For specific reasons such as to have separateteam members for different projects, the Project leader might decide to create more thanone project, and distribute the libraries to be managed among these projects.



The following figure illustrates the use model of a DM project

Project Leader

■ Create Project

■ Modify Project

■ Update integ area

■ Create work area (optional)

If work area is created:

■ Check out from repository

■ Check in to repository

■ Join Project

■ Check out from repository

■ Check in to repository

PL updatesthe integ area

Repository

Integ Area

Project Leader

Team Members

Designers



Pre-requisites for Creating a DM Project

Library Explorer enables you to create a DM project. However, before creating a project, thefollowing needs to be done by the Project Leader. They are:

1. In UNIX, set the umask appropriately, by running the command umask 002. This isrequired so that everybody in the group has permissions to make modifications in therepository. For NT, set up the appropriate share permissions (i.e. read, write) on thefolders corresponding to the repository and the integration area. This permission isrequired for all users.

2. Set the following variables:

❑ TZ = GMT

This sets the time zone. This is required by VersionSync to execute properly.

❑ GDM_MAIL_HOSTNAME = <your_mailserver_name>

This setting is required for Part Developer to send mails to team members askingthem to join the project.

3. Decide on the libraries that need to be managed and the integration area.

4. Decide on the location of the vault or the repository for the project.

5. Decide on the location of the local workarea.

6. After you have decided the libraries to be managed and the locations, you need to runthe vssetvault script in a command window. This script sets up the vault, integrationarea, and local workarea appropriately. Currently, data-managed functionality is beingprovided with the version control system called VersionSync. The script that needs to berun for setting things up is called vssetvault and for UNIX, should exist in<install_dir>/tools/bin (if the VersionSync kit has been installed).

Before you create or join a DM project in NT, you should do the following:

1. Provide write access to the repository and the integration area to all the members of theproject team.

2. Put the following entry as the first entry in your PATH environment variable:

<your_install_dir>/vs_nt

This entry ensures that the diff executable in the vs_nt directory is the one that ispicked up by the tool.



The vssetvault script takes two parameters, the path to your repository and the path toyour integration area or the local build area.

The vssetvault script has to be run twice. In the first instance, the script prompts for thepaths to the repository and the integration area. The syntax for running the command for thefirst time is:

vssetvault <path of the repository> <path of the integ area>

In the second instance, specify the path for the repository and the local work area. When yourun it the second time, the syntax is:

vssetvault <path of the repository> <path to your local build area>

For example, if you want to create the repository in x:\gdm_projects\repositoryand the integration area in x:\gdm_projects\integ, you will have to specify thefollowing command at the command prompt:

vssetvault x:\gdm_projects\repository x:\gdm_projects\integ

This will create the repository and integ folders under x:\gdm_projects andpopulate the integration area with the two files, .VSVAULT and cdsinfo.tag. The.VSVAULT file contains the path to the repository, and the cdsinfo.tag file contains theentry for the type of version control tool used. In case of vssetvault, the entry will beDMTYPE vs

To create a local build area, for example localbuildlib under x:\gdm_projects, givethe command:

vssetvault x:\gdm_projects\repositoryx:\gdm_projects\localbuildlib

This will create a folder named localbuildlib under x:\gdm_projects and populate itwith the .VSVAULT and cdsinfo.tag files.

For the librarian and the members, ensure that mapping to the repository and the integrationarea is the same. For example, if the project leader creates the repository and the integrationarea in F:\rep and F:\integ respectively, then all the team members should also havethe mapping to repository and integration area as F:\rep and F:\integ respectively.

Once you have run the vssetvault script, you are ready to create a DM project. When youcreate a new project, you are the project leader for that project. You create a new project tospecify the integration area, repository, and work area. You should also define the referencelibraries that are to be managed and the team members who will work on the project.

You can define the libraries that are to be managed by specifying the paths to these librariesor by including cds.lib file that has the paths to these libraries.



Creating a Data-Managed Project

Task Overview

Create a new DM project as a project leader and name the project my_dm_project.

Note: All the screenshots are based on the assumption that the data-managed project iscreated in D:\gdm_projects

Steps

The first task in creating a DM project is to set the environment variables.

1. Set the following environment variables:

❑ TZ=GMT

❑ GDM_MAIL_HOSTNAME = <your_mailserver_name>

Next, you need to create the necessary directory to create and store the project.

2. Create the gdm_projects directory under D:\.

After you create the directory, you need to run the vssetvault script to set up theenvironment for creating a DM project.

3. Run the vssetvault script to mark the respective directories as integration area,repository and local work area. The commands are:

vssetvault d:\gdm_projects\repository d:\gdm_projects\integ

vssetvault d:\gdm_projects\repository d:\gdm_projects\local_area

This sets up the following project directory:

Directory Name Purpose

d:\gdm_projects\integ The location of the integration area(reference area) for the tutorial.

d:\gdm_projects\repository The location of the repository for thetutorial.

d:\gdm_projects\local_area The location of the project leader’s localwork area for the tutorial.



Next, the library project needs to be created.

4. If you are in UNIX, launch Library Explorer by typing the following command in thecommand window

libexp &

If you are in NT, launch Library Explorer by doing the following steps:

a. Choose Start > Run.

The Run dialog box appears.

b. The executable for Library Explorer is libexp. To run the executable, type libexpin the Run dialog box.

The Library Explorer Product Choices dialog box appears.

5. To launch Library Explorer from the PCB Librarian Expert suite, select PCB LibrarianExpert.

6. Click OK.

The Getting Started dialog box appears.

7. To create a new managed library project, select the Create a new Managed LibraryProject radio button.

8. Click OK.



The Project Type page of New Project Wizard appears. In this page, you determinewhether or not to create a managed project.

9. To create a data-managed project, ensure that the DM option is selected.

10. Click Next.

The Create Options page of New Project Wizard appears. In this page, youdetermine whether to join an existing DM project as a team member or to create/managea project as the project lead. If you select the team member option, you can join anexisting DM project. If you decide to join as a project lead, you need to determine whetheryou want to create a new project from scratch or use an existing location containing yourlibraries as the integration area.

For the tutorial, you will be the project lead and create a new project.

11. To create a new project as the project lead, select the Administrator/project lead radiobutton.

Notice that by default the New checkbox is selected.

12. Click Next.



The Project Name and Location page of New Project Wizard appears. In this page,enter the project name and the location to the integration area.

13. Enter my_gdm_project in the Project name field.

Next, the location of the integration area needs to be specified.

14. Browse and select the D:\gdm_projects\integ as the integration area.

15. Click Next.

The Libraries page of New Project Wizard appears. In this page, you can add thelibraries that you want to manage to your project. You can add the libraries by eitherphysically selecting the library folders, or by importing a cds.lib file. If the libraries are



not in the integration area, then the selected libraries will get copied into the integrationarea.

For the tutorial, a sample library lcx is provided under thex:\tutorial_project_data\lcx folder.

16. To add the lcx library, click Add.

The Choose Directory dialog box appears.

17. Select the lcx library from x:\tutorial_project_data\lcx.

18. Click OK.



The selected library is added.

19. Click Next.



The Project Team page of New Project Wizard appears. In this page enter theinformation pertaining to the project team members. A mail is sent out to each memberwhose email has been provided in the E-mail column.

20. Enter the team member’s details. For demonstrative purposes, we have used VishalKumar as team member.


The Create Work Area page of New Project Wizard appears. In this page you needto specify the path to the local work area for yourself. This is optional. You may choosenot to create a local work area for yourself.

For the tutorial, the local work area which was created in the beginning of the tutorial willbe used.



22. To select the local_area as the local work area, click the Browse button and select theD:\gdm_projects\local_area directory.

23. Click Next.



The Summary page of New Project Wizard appears.#

24. Click Finish.

A message box will appear informing you that mail have been sent.

25. Click OK.

The project will be created, and displayed in the Library Explorer window.

Next, you will checkout the lcx00 component from the reference area into the build area.

26. Choose File > Check Out.

The Check Out (Read Only) dialog box appears. You can select the parts that you wantto checkout through this dialog box. Note that, by default the checkout is read-only.However, you can also checkout parts in a read/write mode. For completing the task inthis chapter, you need to checkout the lcx00 part in read\write mode.

27. To checkout the part in read/write mode, click Options.



The Checkout Options dialog box appears.

28. Select the Check out Read/Write option.

29. Click OK.

You configured Library Explorer to checkout the parts in read/write mode. Next, you needto select the part that you want to check out.

30. Click on the lcx00 checkbox.

31. Click OK.

The Library Explorer message box appears informing that the check-out operation wassuccessful.

32. Click OK.

Important

You can see the DM status of any library or part by right-clicking on the library/partand selecting the GDM Status option.



A GDM Status message box appears (sample shown below) appears informing you theDM status of the part.

Next, modify the part and add a symbol property my_prop with value my_val.

33. You use Part Developer to modify parts. See the earlier chapters to know more aboutmodifying a part.

Next, you need to checkin the part.

34. To checkin the part, select File > Check In.



The Check In dialog box appears.

35. To simultaneously update the integration area so that the modified part is also availableto the designers, select the Update integ area checkbox.

Note: When you checkin a part, Part Developer automatically increments the version numberof the part.

36. Click OK.

A message box appears informing that the check-in was successful. This creates theversion 1.2 of the part.

37. Click OK.

38. Next, you will check-out the version 1.1 of the part. It is important to remember that youcan only checkout older versions in read-only mode.

39. To check-out an older version, select File > Check Out

40. To checkout the part in read/write mode, click Options.



The Checkout Options dialog box appears.

41. Select the Update with tag option.

42. To checkout the version 1 of the part, enter 1 in the Repository Tag Name field.

43. Click OK.

44. Click OK.

A message box appears informing that the check-in was successful. The first version ofthe part is checked out. Remember that it is checked out in read-only mode.

Summary

In this chapter you learned about the methodology of a data-managed project. You alsolearned the steps involved in creating and working in a data-managed project. In the nextchapter, you will learn to create a part from an XML datasheet.



12Using XML to Create Parts

Objective

To become familiar with the steps involved in using XML datasheets to create parts.


■ Import data into Part Developer from an XML file.

■ Implement post-import corrections.

■ Update the package information.

■ Create symbols.

Importing Part Data from an XML Datasheet

Task Overview

Import the part information for the LS244 component from the XML datasheet named74ls244.zip. It is stored in the tutorial_project_data/datasheets location.

Steps

1. Launch Part Developer and open the tutorial_project.cpm project.

The Create/Open Part dialog box appears.

2. To begin the process of importing form an XML file, Click Cancel.

3. Choose File > Import XML.

The Import from XML to Concept HDL dialog box appears.


Library Explorer and Part Developer TutorialUsing XML to Create Parts

4. Select 74ls244.zip from the tutorial_projects/datasheets location and click Open.

Next, you need to decide whether you want to convert only the master component, oreach alias as individual primitive or each alias as individual cell.

If you choose to convert only the master component, then one Concept HDL part iscreated. The chips.prt file will have only one primitive section with the mastercomponent name as its only entry.

If you choose to convert each alias as individual primitives, then one Concept HDL partis created with each alias appearing as a primitive entry in the chips.prt file. Forexample, if a part has four aliases, the resultant chips.prt file will have four primitives.

If you choose to convert each alias as an individual cell, then as many number of partsas there are aliases will be created. For example, if a part has four aliases, then fourseparate Concept HDL parts will be created.

5. You need to create only the master component. By default, this option is selected.

6. Click OK.

The LS244 part appears in the Part Developer tree view.

After you read-in the part information from the XML datasheet, you need to take care of thefollowing issues:

PIN_TYPE Property

The PIN_TYPE property gets filled in as per the following rules:



■ Passive is interpreted as ANALOG.

■ Rest of the pins are mapped to their corresponding types in Part Developer.

CLASS Property

The CLASS property gets filled in as per the following rules:

■ CLASS property gets the value IC if the Designator element in the XML datasheet hadthe value U.

■ CLASS property gets the value IO if the Designator element in the XML datasheet hadthe value J, JP or SW.

■ CLASS property gets the value DISCRETE for all other values of the Designator elementtype. These values are: C, D, ISO, L, LS, Q, R, T, U, VR, and Y.

Therefore, you may need to check the value of the CLASS property after the data has beenimported from the XML datasheet. If required, change the value of the CLASS property. Thesteps are:

1. Right-click on the part name in the tree view.

2. Select Properties from the shortcut menu.

3. Change the value of the Part_Type field.

DUPLICATE PINS

Often a part may have duplicate pins names such as multiple collector pins in transistor,programmable IO pins in FPGAs etc. In such cases, Part Developer appends an index with‘_’ to the pin name starting from the second occurrence. For example, if there are twocollectors with name C, they will be read-in as C and C_1.

Pins With ‘>’ or ‘<‘

Certain pins have either a ‘>’ or a ‘<‘ symbol in their pin names, such as P>Q or P<Q incomparators. Such pins will be read in with the ‘>’ symbol converted to ‘_GT_’ and the ‘<‘symbol converted to ‘_LT_’ in the pin names. For example, a pin name P>Q will get convertedto P_GT_Q.



Partnames with ‘/’

Some part may have ‘/’ symbol in their part names. The ‘/’ in such part names will getconverted to ‘_’ in the primitive entry of the chips.prt file.

JEDEC_TYPE

When a part information is imported from an XML datasheet, the value of the JEDEC_TYPEproperty is not seeded. You will need to manually specify the value of the JEDEC_TYPEproperty for a part.

NC Pins

E-tools XML datasheets do not contain information about the NC pins. Therefore, when youimport the data from the XML datasheets, NC pins would be absent from the packages. Youcan follow one of the two methods to add the NC pins to the packages:

1. Use the Extract From Footprint option in the Physical Pin Mapping tab of the PackageProperties dialog box, and then mark the required unmapped pins as NC pins.

2. Manually add the pin numbers and mark them as NC pins.

Note: If you use the Extract From Footprints option, you will lose the mappings for thosepins that are mapped to logical pins but not present in the list of extracted pin numbers.

Symbol Interpretation

After you create a part from an XML datasheet, you need to be aware of the following:

■ The origin of the symbol will be at the top left corner of the symbol bounding box and thePART_NAME will be displayed just above the origin.

■ Pin text will appear outside the symbol graphic.

■ In data sheets, the multi-assertion pin names appears as name/name. When such pinsare read into Part Developer from XML, each character in the low asserted part of thename is followed by a ‘\’. For example, RD/WR will be written as RD/W\R\.

■ Sometimes, some of the symbols may appear to have additional height. This is becausewhen a part data is imported from XML, all the power pins are moved to the body sectionof the chips.prt file. This results in the removal of power pins from the symbols.However, the space reserved by the symbol for power pins is not adjusted after the powerpins are moved to the body section.



Once you have taken care of the above mentioned issues, you should verify the part. Onlyafter the verification of the part is complete, you should check-in the part.

Summary

In this chapter you learned to create a part from an XML datasheet. In the next chapter youwill learn to create a part template and apply the template to create parts.



13Creating Templates

Objective

To become familiar with the methodologies and steps involved in creating and using PartTemplates.


■ Create a new template.

■ Apply the template.

■ Create a part with the applied template values.

■ Verify the part against the template.

Overview

Part Developer provides you the ability to set up the part construction rules and propertysetup through the use of Part Templates. Using the templates, you can quickly create partsthat follow your company standards and yet have the flexibility to add properties andbehaviors specific to the part.

Using Part Developer, you can:

■ Create a template.

A template can be created with data such as property names and values, pin positionsand symbol display characteristics. The template is then used to create multiple parts.

■ Create parts using a template.

A template can be selected from the existing list of available templates and parts createdbased on the information stored in the template.

■ Verify parts against a template.


Library Explorer and Part Developer TutorialCreating Templates

Parts can be verified against a selected template or the original template from which thepart was created.

Creating and Applying a Part Template

Overview

Part Developer enables you to create part templates. While creating part templates, you canspecify the following information:

In Packages

■ Package properties

■ Pin load properties

In Symbols

■ Grid size

■ Symbol outline

■ Pin text orientation

■ Pin text size

■ Whether to use pin names for pin text

■ Minimum symbol height

■ Minimum symbol width

■ Symbol properties

■ Symbol pin spacing, both top/bottom and left/right

■ Position of symbol pin types

After you specify the information, you save the information in a .tpl file. This file can thenbe used as a template in later sessions of Part Developer to create parts.



Task Overview

Create a template with the symbol property PART_NAME, a package propertyCREATED_ON . Save the template in mytemplate.pl and apply it.

Steps

1. Launch Part Developer and open the tutorial_project.cpm project.

The Create/Open Part dialog box appears.

2. Click Cancel.

The empty Part Developer window appears.

3. Choose Templates > New.



The New Template dialog box appears. Note that the properties that were set up in theTools > Options appear as template properties.

Next, you need to enter the new template properties.

4. Enter the property name as PART_NAME.

5. Enter the property value as ?.

This will ensure that the property is annotated to the symbol and the value for thisproperty has to be specified by you in Concept-HDL.

6. Select the value of the Visible field as Both.

7. Specify the alignment as Center.

8. Since the PART_NAME property has to appear only on the symbols and not packages,deselect the Package option.

Next, you need to specify the package property CREATED_ON for the packages.

9. Select the next blank line under Property_Name, and enter CREATED_ON as theproperty name.

10. Enter ? as its value.

11. Since the CREATED_ON property is to be applied only to packages, deselect theSymbol checkbox.

12. Click Save.

The Save Part Template dialog box appears.

13. Enter the file name as mytemplate. tpl



14. Click Save.

A Part Developer message box appears.

15. To apply the template, click Yes.

The blank Part Developer window appears with the template applied on it. Basically, theSetup options properties are updated. You can now create parts. The new parts willautomatically contain the properties that you set up through the templates.

In case you want to see the properties that you added using templates, choose Tools >Options.

Using Part Template to Create Parts

You use a part template as the building block in creating one or more parts. To create partsusing a part template, you need to open the part template and apply the template values tothe current session of Part Developer. This overrides the default values specified throughTools > Options. Once you have applied the template, proceed with the creation of parts asdetailed in Chapter 4, “Creating Parts With Pins Split Across Symbols” and Chapter 6,“Creating a Multi-Section Symmetrical Part” and Chapter 8, “Creating Asymmetrical Parts”.

For this chapter, create a simple part with two input pins A, B and an output pin Y. Name thepart mypart and create one package DIP and one symbol with logical pins for it. Enter ? asthe JEDEC_TYPE value.

Next, you will verify the part against the template that you created.

Verifying Parts Against Templates

To ensure that the parts are conforming to your standards, Part Developer enables you toverify a part against a template. The verification is done only for those values that exist in thetemplate file. The output is displayed as a report that can be saved as a .rep file. Theverification is done as per the following rules:



Property Checks

The property check is done on all packages for the following:

■ All properties listed in the template for a package must exist in each package of the part.

■ The value of the property in each package must match the value in the template unlessthe value in template is "?" or blank.

Pin Load Checks

This is done on all pins in all packages as per the following rules:

■ If PINUSE="UNSPEC" exists for a pin, all checks are bypassed on that pin.

■ If a pin type is not determined, it is an error.

■ If a pin type is determined, its load value is checked against the load value of that pintype in the template. An error is generated if the load values don’t match.

■ Error is shown if any of the loads for a pin type is missing.

Symbol Checks

All Symbols are checked for a given part as per the following rules:

■ All symbols must have at least one connection with a line stub or a bubble else an errorstating that check cannot proceed is shown.

■ All lines are assumed to be vertical or horizontal. Arcs are not supported in this release.

■ Each Bubble is interpreted to have two virtual stub lines - horizontal and vertical.

■ No two connections can have the same X, Y coordinates, else error is shown to the user.

■ Location of connections is derived based on the direction of the stubs attached to theconnection. Therefore, only connections that have a stub or a bubble on them arechecked.

■ Stub length is calculated based on the integer average of all stub lengths.

■ The outline of the body is derived by searching for the perpendicular line from the end ofstub. As the stub size varies, the search is made within the range of the stub sizevariance. After getting a single outline, the rest are traced as the ones connected theoutline end points. The procedure is executed recursively for each detected outline.

■ Minimum pin spacing are calculated for all sides (Top, Left, Right, Bottom).



■ For pin texts, the property PIN_TEXT is used. If it is not found, pin texts are searchedfor within 1/3 of the average stub length from the end of the stub for each connection.Also the location (x,y) of the pin note must not be mis-aligned by more than 1/2 pinspacing.

■ Grid is derived by taking the highest common factor of all differences of values of X andY on respective coordinates. Only the connection (Logic) grid is derived. The symbol gridis not derived even though the template mentions it as Symbol Grid.

■ All properties listed in the template for symbols must exist on each symbol in the part.

■ The value of the property in each symbol must match the value in the template unlessthe value in template is "?" or blank.

■ The alignment of the property must match the one specified in template.

■ The visibility of the property must match the one specified in template.

Pin Checks

Each pin is checked as per the following rules:

■ Each pin based on the type as defined in the template must be at the location area insymbol as defined in the template for that type.

■ The text size of the pin must match the size specified in the template.

■ The Use Pin Names For Text is checked only if the template sets it to true.

■ The text style for pin text is checked with value in template. If the style is vertical for topand bottom pins and horizontal for pins on left and right then the style is considered tobe Automatic. The angles of 90 and 270 are considered equivalent and vertical and 0and 180 are considered equivalent and horizontal.

■ All pins with spacing less than the spacing specified in the template are marked aserrors.

Grid Checks

Grid checks are done with the following rules:

■ Conversions are done for calculating and matching the grid values for Inches andFractional (Fractional is currently not supported in Part Developer). This is then matchedwith the template value.



Outline Checks

The outline checks are done with the following rules:

■ All detected Outlines are checked to match the thickness specified in template.

Minimum Size Checks

■ The minimum pin spacing values on the left and right is read for each symbol and verifiedagainst the minimum pin spacing left and right value stored in the template. An error isgenerated if the value in the symbol is less than that of the value stored in the template.

■ The minimum pin spacing values on the top and bottom is read for each symbol andverified against the minimum pin spacing top and bottom value stored in the template.An error is generated if the value in the symbol is less than that of the value stored in thetemplate.

■ The minimum symbol height value is read for each symbol and verified against theminimum symbol height stored in the template. An error is generated if the value in thesymbol is less than that of the value stored in the template.

■ The minimum symbol height width is read for each symbol and verified against theminimum symbol width stored in the template. An error is generated if the value in thesymbol is less than that of the value stored in the template.

The output of the verification is displayed in a dialog box. The output is divided into twosections, Overview and Details.

In the Overview section, the overview of the differences are displayed. In the Details section,the differences are detailed.

Task Overview

Verify the part mypart against the mytemplate.tpl template.

Steps

1. Choose Tools > Verify.


2. Select the Verify with Templates option.

3. Click OK.



The Select Part Template dialog box appears. You need to select the template fileagainst which the verification will be done.

4. Select mytemplate.tpl and click Open.

The verification is run and the differences found are displayed in the Part verificationwith Template dialog box.

Notice that one difference has been found with relation to the symbol properties.

Summary

In this chapter you learned to create a template and apply the template to create new parts.In the next chapter you will learn to extract and modify templates.





14Extracting Templates

Objective

To become familiar with the methodologies and steps involved in extracting and modifyingpart templates.


■ Extract a template from a part.

■ Modify the extracted template.

■ Save the template.

■ Apply the template on a part.

Extracting Templates

If you have a part which has been built in compliance with your company standards, you canextract information from it and create a template. After the template information is extracted,the part is verified against the extracted template information. A verification report isgenerated listing the differences with the extracted values. Template information is extractedas per the following rules:

From Packages

■ All properties found in any of the packages are added to the template with their values.

■ If the property name matches with any of the properties listed below then the value isreplaced with "?":

❑ JEDEC_TYPE

❑ POWER_PINS

❑ NC_PINS


Library Explorer and Part Developer TutorialExtracting Templates

❑ BODY_NAME

❑ PART_NAME

❑ TECH_FAMILY

Pin Load Extraction

Pin Load is extracted from the different pin types. If a pin type is not found on one of thepackages, it is searched in the next package and so on. If a pin type is not found on any ofthe packages, its load is not added to the template. If for any pin type the load extracted is nota standard, i.e., the load is not same for all pins of a type on all packages then the first loadis used.

Symbol Data Extraction

■ All symbols are read for a given part.

■ All symbols must have at least one connection with a line stub or a bubble else an errorstating that process cannot proceed is displayed.

Symbol Property Extraction

■ All properties found in any of the symbol are added to the template with their values.

■ If a property exists both in a package and a symbol, the package property is givenprecedence and its value is extracted.

■ Alignment and visibility are extracted from the symbol and added.

■ If the property differs in value across packages or across symbols to or it differs invisibility or alignment, then the value of the property from the last instance of either thepackage or symbol is extracted.

Symbol Pin Extraction

For each pin the following checks are done:

■ A search is done for the first pin of each pin type and its location value is added to thetemplate.

■ The Use Pin Names For Text option is set to false if a single pin is found to violate thisrule.



■ The Text Style for Pin Notes is interpreted. If the style is vertical for top and bottom pinsand horizontal for pins on left and right then the style is considered to be Automatic. Theangles of 90 and 270 are considered equivalent and vertical and 0 and 180 areconsidered equivalent and horizontal. If it is not consistent for all the instances for a pintype based location then user is warned that this is not a standard.

Grid Extraction

The highest common factor of all differences in X distances and Y distances is taken as theminimum grid unit. It is calculated into template in Inches.

Minimum Size Extraction

■ The minimum pin spacing values on the left and right are read for all the symbols and thesmallest value is extracted to the templates as the minimum spacing value for left andright. If in a symbol, 0 or 1 pin exist on left and right, its value is not extracted.

■ The minimum pin spacing values on the top and bottom are read for all the symbols andthe smallest value is extracted to the templates as the of minimum spacing on top andbottom. If in a symbol, 0 or 1 pin exist on top and bottom, its value is not extracted.

■ The symbol height value is read for all the symbols and the smallest value is extractedto the templates as the of minimum symbol height.

■ The symbol width value is read for all the symbols and the smallest value is extracted tothe templates as the of minimum symbol width.

■ The outline is extracted as thick if all outlines are thick. The outline is extracted as thin ifall outlines are thin. If neither of the cases are true then no extraction is done for thisvalue. If a value is not extracted, a warning is displayed.

Task Overview

Extract template information from the LS244 part that you had created by importing the datafrom an XML datasheet.

Steps

1. Import the ls244 part from the reference area.

2. Launch Part Developer and open the ls244 part

3. Choose Templates > Extract.



The New Part Template dialog box appears. You need to enter the file name into whichyou want to store the template information that will be extracted.

4. Enter fromls244.tpl as the template file name and click Save.

The Extracted Template Values dialog box appears. You can view the extracted valuesin this dialog box.

5. Click OK.

The Extracted Template Values dialog box disappears.

Next, you need to modify the template values.



Modifying Template Values

Overview

After the template information has been extracted into Part Developer, you can modify theextracted information. You can modify the information by editing the template values.

Task Overview

Modify the Pin Text Size value in the fromls244.tpl template file from 0.88 grids to0.50 grids. Save the template file after you have made the necessary changes.

Steps

1. Choose Templates > Edit.

The Load Part Template dialog box appears.

2. Select fromls244.tpl template file and click Open.

The Edit Template dialog box appears.

To make changes to the pin text size, you need to go to the Symbol property page.

3. Click Symbol.

4. Modify the Pin Text Size value to 0.50.

5. Click Save.



The Save Part Template dialog box appears.

6. Enter the name of the modified template file as my_ls244.tpl and click Save.

A Part Developer message box appears asking you whether to apply the template.

7. To apply the template, click Yes.

Summary

In this chapter you learned to extract a template from a part and modify the extractedtemplate. In the next chapter, you will learn to create a VHDL wrappers and map files.



15Creating VHDL Wrappers and Map Files

Objective

To become familiar with the methdologies and steps involved in creating and using VHDLwrappers and map files.


■ Create VHDL wrapper and map file for a part

Overview

Concept HDL generates a netlist that you can use to simulate your logical design using aVerilog or VHDL based simulator. To generate the netlist, it uses the symbol pin names as theinterface ports for each component used in the design. The interface ports of a part may be


Library Explorer and Part Developer TutorialCreating VHDL Wrappers and Map Files

different from the VHDL model’s ports. For example, for the part 74ac74, the interface portsare:



For the same part, the VHDL model’s port names are:

To successfully simulate a design, a mapping is required between the symbol pin names withthe model port names. This making is stored in wrapper and map files. The wrappers or mapfiles can be created using Part Developer.



Creating a VHDL Wrapper/Map File

Task Overview

Create a VHDL wrapper and map file for the 74ac74 part. The VHDL model for the part isprovided in the vhdl_models directory under tutorial_project location. You will needto import the 74ac74 part from the Cadence supplied reference libraries.

Steps

1. Launch Library Explorer and open the tutorial_project.cpm project.

2. Import the 74ac74 part from the 74ac reference library.

3. Open the part in Part Developer.

4. Choose File > New > VHDL Wrapper/Map File.

The VHDL Wrapper/Map file dialog box appears. You enter the path to the VHDLmodel in this dialog box. This can be done by specifying either the actual physical pathto the VHDL model or the Lib:Cell:View structure.

For example, to access the VHDL model stored in x:⁄74ac⁄sn74ac74, you may provideeither the entire physical path or use the lib:cell:view method, i.e. specifysn74ac:sn74ac74::vhdl_lib.

Note: To use the lib:cell:view method, there should be a library entry in the cds.lib fileof the project. For example, to use the sn74ac74 with the lib:cell:view method, thefollowing entry should be present in the cds.lib file:



DEFINE 74ac x:⁄74ac

Since the cds.lib file entry has not been made for the VHDL model, you will use theFile method to specify the path to the VHDL model.

5. Select File.

6. Browse to the location of the VHDL file,c:\tutorial_project_data\datasheets\vhdl_models\74ac74\entity\vhdl.vhd

Next, you need to determine whether to bind the VHDL model and the symbol. That is,determine whether to bind the symbol with one specific architecture (behavior). If youdecide to bind the VHDL model and the symbol, then the binding statement goes into thewrapper. This is an optional step.

Since each view of the model is essentially a specific architecture, selecting the VHDLmodel by using the lib:cell:view method automatically fills in the binding statement. If youspecify the actual physical path to the VHDL model, then you have to explicitly enter thebinding information. If you decide not to enter the binding information during wrappercreation, then the binding information has to be specified later in the simulation flow.However, not providing the binding information in the wrapper provides the freedom touse the same wrapper for different architectures.

For the tutorial, you will leave the binding information empty.



7. Click Port Mapping.

The VHDL Symbol Pin to Model Port Mapping dialog box appears.

8. Select the pin CLK in the Pin List column.

9. Select CLOCK in the Model Port[s] column.

10. Click Map.

The Update pin mode dialog box appears. This appears if you are mapping a symbolpin to a model port of different modes (input to inout, in this case). Similarly, if the typesare different, then the Update pin type dialog box appears. In this dialog box you candetermine whether or not to map the pins of different types. In case you want to suppressthis dialog box, select the Automatically Update pin mode option.

11. Click OK.

Similarly, map the other pins.

12. Click OK.



Next, determine the generics that should be annotated to the symbols.

13. Click Generics.

The Select VHDL Generics dialog box appears.

14. Select the Annotate on Symbol(s) check box next to Size and TP_CLK_MAXgenerics to annotate both the generics on to the symbols.

15. Click OK.

16. To simultaneously create a map file, click Setup.



The Setup for VHDL Wrapper/Map File dialog box appears.

17. Select the Generate Map File option to create the map file.

18. Click OK.

19. Click OK.

This completes the creation of a VHDL wrapper/map file. You should now save the part.The vhdl_wrapper is the VHDL wrapper and vhdl_map is the VHDL map view for thepart.

After you create the wrapper, you can verify it by using any VHDL compiler such asncvhdl. Part Developer provides you an interface to interact with whichever VHDLcompiler you choose to use.

20. To setup a VHDL compiler to compile the wrapper files, choose Tools > Verify.

21. Select the VHDL Compilation option.

22. Click Options.

The Enter command for VHDL compilation dialog box appears.

23. Enter the command for VHDL compiler in this dialog box. By default, Part Developershows ncvhdl.



Note: ncvhdl is not supplied with PCB Librarian Expert product suite and needs to bepurchased separately.

24. If you have a VHDL compiler, click OK.

The wrapper will be compiled and a report about the verification status will be madeavailable to you.

Summary

In this chapter, you learned to create VHDL wrapper and map files. In the next chapter youwill learn to create Verilog wrapper and map files.





16Creating Verilog Wrappers and Map Files

Objective

To become familiar with the methodologies and steps involved in creating Verilog wrappersand map files.


■ Create a Verilog wrapper and map file.

Overview

Concept-HDL generates a netlist that you can use to simulate your logical design using aVerilog or VHDL based simulator. To generate the netlist, it uses the symbol pin names as theinterface ports for each component used in the design. The interface ports of a componentmay be different from the Verilog model’s ports.

Therefore to successfully simulate a design, a mapping is required between the symbol pinsand the model port names. This mapping information is stored in the wrapper and map files.

Creating a Verilog Wrapper/Map File

Task Overview

Create a VHDL wrapper and map file for the 74LS00 part. The Verilog model for the part isprovided in the <your_install_dir>/veriloglib/verilogTTL/74LSTTLdirectory. You will need to import the 74LS00 part from the Cadence supplied referencelibraries.


Library Explorer and Part Developer TutorialCreating Verilog Wrappers and Map Files

Steps

1. Launch Library Explorer and open the tutorial_project.cpm project.

2. Import the 74LS00 part from the Cadence supplied reference library.

3. Open the part in Part Developer.

4. Choose File > New > Verilog Wrapper.

The Verilog Wrappers/Map File dialog box appears.

Note: The Verilog model file can be accessed by specifying either the physical path tothe model file or the lib:cell:view structure. To access the model file by using thelib:cell:view method, ensure that the library definition exists in the cds.lib file.

5. Click browse to choose the Verilog model. For LS00, select the SN74LS00.v file fromthe <your_install_dir>/veriloglib/verilogTTL/74LSTTL directory andclick Open.

Next, you need to map the pin names to the port names.

6. Click Port Mapping.

The Verilog Symbol Pin To Model Port Mapping dialog box appears.

You will notice that under the Pin List entry, there are only pins a, b, y and NCs whereasunder Model Ports there are fourteen pins. This is because the part that you have



created is a sizeable part, and therefore pin names of only one section is visible, whereasthe Verilog model is a flat model and therefore all ports are displayed.

7. Select y from the pin list.

8. Select _1Y from the Model Ports list.

9. Click Map to map the pin to the port.

10. Similarly map a with _1A and b with _1B.

11. Click OK.

Next, determine the parameters to be annotated to the symbol.

12. Click Parameters.



The Select Verilog Parameters dialog box appears.

13. Select the Annotate on Symbols check box for the parameters that are to be annotatedto the symbols.

14. Click OK.

15. To simultaneously create a Verilog map file, click Setup.

The Setup for Verilog Wrapper/Map File dialog box appears.

16. Select Generate Map File to create a Verilog map file.

17. Click OK.

18. Click OK.



This creates the Verilog wrapper for the LS00 part. You should now save the part.

After you create the wrapper, you can verify it by using any Verilog compiler such asncverilog. Part Developer provides you an interface to interact with whichever Verilogcompiler you choose to use.

19. To setup a Verilog compiler to compile the wrapper files, choose Tools > Verify.

20. Select the Verilog Compilation option.

21. Click Options.

The Enter command for Verilog compilation dialog box appears.

22. Enter the command for Verilog compiler in this dialog box. By default, Part Developershows ncvlog.

Note: ncvlog is not supplied with PCB LIbrarian Expert product suite and needs to bepurchased separately.

23. If you have a Verilog compiler, click OK.

The wrapper will be compiled and a report about the verification status will be madeavailable to you.

Summary

In this chapter, you learned to create Verilog wrapper and map files. This chapter concludesthe tutorial. We hope that you would have got enough insights by now to start working withthe library development tools and develop libraries and parts for your design teams.





Index

BBuild area 30

Creating Libraries 39

CCategory

Viewing 39Category File 24cds.lib file 30Copying Parts 41

DData-Managed Projects

Build Area 197Checking Out Parts 209Creating 199, 201Integ Area 197Overview 196Vault 197

FFootprints

Viewing 42

LLib-Cell-View Architecture 19

Entity View 22Package View 20Part Table View 22Simulation View 24Symbol VIew 19

LibrariesPhysical Organization 18

Library ExplorerOverview 17

Library ManagementConcepts 18

Library Management Use Model 28Designer 29Librarian 28

Library ProjectConcepts 30Creating 32

PPart Template

Creating 220Extracting 229Modifying extracted values 233Using 223

PCB Librarian Expert Product SuiteProducts 13

PCB Librarian SuiteProducts 13

Rrefcds.lib file 31Reference area 30

SSymmetrical Part Creation

Example 104

TTutorial Samples 15Types of Projects

Design Projects 27Library Projects 27

VVerification

Against Part Template 223View Verification 43



Verilog Wrapper/Map File 245Creating 245

VHDL Wrapper/Map File 235Creation 238

ViewsEntity View 22Package View 20Part Table View 22Simulation View 24Symbol View 19

XXML

Duplicate Pins 216Importing Part Data 214JEDEC_TYPE 217NC Pins 217Pins with > or 216Post Import Issues 215Symbol Interpretation 217


Documents

Library Explorer and Part Developer Tutorialstatistics.roma2.infn.it/~sabene/CADENCE MANUALS/pl_tut.pdf · Introduction January 2002 14 Product Version 14.2 PADS dB-in translator