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Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint. Li Jiang 1 , Qiang Xu 1 , Krishnendu Chakrabarty 2 , and T. M. Mak 3 1 Deptartment of CS&E, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong - PowerPoint PPT Presentation
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Layout-Driven Test-Architecture Design and Optimization
for 3D SoCs under Pre-Bond Test-Pin-Count Constraint
Li Jiang1, Qiang Xu1, Krishnendu Chakrabarty2, and T. M. Mak3
1Deptartment of CS&E, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
2Deptartment of ECE, Duke University, Durham, NC3Intel Corporation, Santa Clara, CA
Outline
Background Motivation Approach Experiments Conclusion
Background
TSV Technique
Benefit of 3D IC• Interconnect
• Performance
• Power
• Memory Bandwidth
• Heterogeneous Integration
1. Gabriel H. Loh. 3D-Stacked Memory Architectures for Multi-Core Processors. ISCA. 2008
TSV
DeviceLayer
Metal
Layer 1
Layer 2
Background
Pre-bond Test• W2W
• Simplicity of the Manufacturing Process
• Low Yield
• D2D & D2W• Pre-bond Test
• High Yield
Background
Test Architecture Design• IEEE P1500 Standard
• TAM Manner
• TSV
• Pad
• Additional Pad
• Primary Pad
• Routing Model
• TAM Segment
1 2
4 2'
PP1
AP1
3
5TSV
6
TAM1
TAM2
TAM3 TAM2
WrapperPP2
PP3 PP6PP4 AP5
PPi : Primary Pad i APj : Additional Pad j
Legend
AP2
Layer 1
Layer 2
AP6AP4
PP5
1 2
4 2'
PP1
AP1
3
5TSV
6
TAM1
TAM2
TAM3 TAM2
WrapperPP2
PP3 PP6PP4 AP5
PPi : Primary Pad i APj : Additional Pad j
Legend
AP2
Layer 1
Layer 2
AP6AP4
PP5
Background
Test-Pin-Count Constraint• Fine-grained Touchdown Probe Needles Unavailable
• Impossible to fabricate a large number of test pads for pre-bond testing
• Area of Pad
• Probe Force to the
Thinned WaferDevice Layer
Bulk Si
TSV C4 Bump
Cu
Bulk Si
Cu
Cu
Cu
Bond Pad
(a) (b)
Outline
Introduction Motivation Approach Experiments Conclusion
Motivation
Separate Test Architectures for Pre-bond Tests and Post-bond Test
Share the Routing Resources
W1
W2
7109
34
5
2
7
8
11
6
Layer 1
Layer 2
TP1
TSVTP2
TPi : Test Pad i TAM_1 TAM_2 TAM_3
Legend
TP3TP4
TP5
TP671
W3
(a)
C11,1
C42,2
C21,1
C103,2
C52,2
C31,2
C74,1
C93,1
C84,1
TSV
W1W2
Pad
Core ID
Post-bond TAM ID
Pre-bond TAM ID
(b)
w4
w2
w1
Pre-bond Test Pad
C11,1
C21,1
C31,2
C74,1
C93,1
C103,2
C42,2
C52,2
C84,1
Problem Definition
• Given• Set of Cores• Test Parameters (Scan chain, Pattern, Input/Output) of each c
ore• Physical Position of Each Core• Maximum available TAM width
• pre-bond test-pin-count constraintWpre;• Determine
• Number of TAM• Core Assignment• Width of each TAM
• Objectivity• minimize the total test cost
Total Test Cost
Test Cost Model
• Ctotal = CTest-Time * α+ CWire-Length *(1- α)
• CTest-Time = CTest-Chip + Σ CTest-Layer
• CWire-Length depends on routing model
Routing Model• Manhattan Distance
• TAM Segment
• TSP33.S. Goel and E. Marinissen. Layout-driven SOC test architecture design for test time and wire length minimization. In Proceedings IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition, pages 738–743, 2003.
Outline
Introduction Motivation Approach
• TAM Wire Reuse with Fixed Test Architectures
• TAM Wire Reuse with Flexible Pre-bond Test Architecture
Experiments Conclusion
TAM Wire Reuse with Fixed TestArchitectures
Test Architecture Optimization for Both Post-bond Test and Pre-bond Test• Fix the TAM (width, core assignment)
Post-bond TAM Routing Identification of Reusable TAM Segments Pre-bond TAM Routing
TAM Wire Reuse with Fixed TestArchitectures
Post-bond TAM Routing• Construct the Complete Graph
• Sort Edges
• Greedy Choose
• Update the Candidates
Not TSPBA
C
D
E2
5
13
89
46
7
BA
C
D
E2
5
13
89
46
7
BA
C
D
E
(a) (b) (d)
10 10
2
5
13
89
46
7
BA
C
D
(c)
10
E
TAM Wire Reuse with Fixed TestArchitectures
Identification of Reusable TAM Segments• Manhattan Distance and Bounding Rectangles
• Overlapping Bounding Rectangles
• Impact of Relative Slope
C1
C2
C11,1
C22,1
C31,2
(a) (b) (c)
C43,3
C11,1
C22,1
C33,2
(d)
C43,3
C11,1
C22,1
C33,2
A B CSlope<0
Slope<0
Slope<0
Slope<0
Slope<0
Slope>0
TAM Wire Reuse with Fixed TestArchitectures Pre-bond TAM Routing
• Get Possible Reusable Post-bond TAM Segments• Construct Completed Graph Gi for Every Pre-bond TAM i
n the layer, and put all Gi together into SG.• Build List for Each Pre-bond TAM Segment, Store All Pos
sible Reusable Candidates into the List Combined with the Routing Cost after Reuse.
• Sort the list According to the Routing Cost• In Every Iteration,
• Choose the Segment with Least Routing Cost• Move it into EG• Delete this Reused Segment from all other edges in SG• Update the Candidate Segment
• Obtain the Routing Result and its Cost
TAM Wire Reuse with Fixed TestArchitectures
Example
TAM1 (C1,C2) 0 (C1,C2)
TAM1 (C1,C3)
TAM1 (C2,C3)
3 (C1,C2)
3 (C1,C2) 10 (C3,C4) 18 (Ø)
TAM2 (C4,C5) 0 (C4,C5)
Pre-bond TAM Segment
Reusable Post-bond TAM Segments1
2
320 (Ø)
8 (Ø)1
1
10 (Ø)
TAM Wire Reuse with Flexible Pre-bond Test Architecture
Change test architecture for pre-bond tests, further reduce their routing cost
Sacrifice only limited testing time
Test Architecture Optimization for Post-bond Test
Simulated Annealing-Based Core Assignment for Pre-bond Test
Temperature<threshold ?
Finish
Reduce Temperature
Post-bond TAM RoutingHeuristic Based
TAM Width Allocation
Reusable TAM Segments Identification
Greedy ReusedPre-bond TAM Routing
TAM Wire Reuse with Flexible Pre-bond Test Architecture
Outer SA-based Core Assignment• Rules
• Redundancy
• Two ascending order
• If i<j,
keep the smallest core index assigned to TAM i smaller than that assigned to TAM j
• Prove of completeness
(C1,C3),(C2,C4,C5)
(C2,C4,C5),(C3,C1)
(C1,C4,C7,)(C2,C9,C11,C14)(C3,C8)(C5,C6,C10,C12,C13)
TAM Wire Reuse with Flexible Pre-bond Test Architecture
Inner TAM Width Allocation Procedure• Short running time
• Greedy Heuristic
• Close-to-optimal
Solution4
4. S. K. Goel and E. J. Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proceedings IEEE International Test Conference (ITC), pages 529–538, Baltimore, MD, Oct. 2002.
Outline
Introduction Motivation Approach Experiments Conclusion
Experiments Results
Width(bit)
Routing Fix
Time Compensate
Routing Flexible
Routing Fix
Time Compensate
Routing Flexible
16
P22810
-14.70% 1.16% -32.30%
P93791
-8.50% 2.63% -47.34%
24 -9.23% 1.09% -25.50% -12.41% 0.30% -43.55%
32 -10.60% 0.93% -36.90% -7.29% 1.86% -49.39%
40 -18.70% 0.48% -43.40% -9.07% 2.58% -44.54%
48 -8.34% 0.50% -24.90% -13.36% 0.71% -47.76%
56 -8.16% 0.23% -37.30% -12.34% 1.53% -46.23%
64 -6.20% 0.54% -35.80% -10.81% 1.71% -48.80%
Experiments Results
Width(bit)
Routing Fix
Time Compensate
Routing Flexible
Routing Fix
Time Compensa
te
Routing Flexible
16
P34392
-10.29% -0.54% -48.79%
T512505
-10.55% 0% -26.70%
24 -17.59% -0.62% -36.93% -10.57% 0.33% -26.76%
32 -16.95% 0.16% -44.69% -16.37% 0.43% -41.73%
40 -21.23% -2.55% -43.67% -11.61% 1.35% -26.42%
48 -15.16% -0.33% -29.33% -11.61% 0.88% -26.42%
56 -12.91% 15.77% -31.25% -11.61% 0.43% -26.42%
64 -12.91% 11.86% -32.06% -11.61% 1.59% -26.42%
Experiments ResultsTSV
(a) (b)
Outline
Introduction Motivation Approach Experiments Conclusion
Conclusion
Only fabricate a limited number of test pads for pre-bond testing
Dedicated pre-bond and post-bond test architectures to satisfy the given test pad constraint
Novel layout-driven optimization techniques to share the TAM routing resources between pre-bond tests and post-bond test
Thank You
Q & A
