LFZP11x_R5911D

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Relay Types

LFZP 111/2/3/4Optimho Distance Protection

Service M anual

R5911 D

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OPTIMHO DISTANCE PROTECTION

Relay Types: LFZP111LFZP112LFZP113LFZP114

The relays described have the following features:

Revised directional line polarising for the mho characteristic.

Revised guard zone reach and polarising for relays fitted with quadrilateral characteristics.

Metering can now be provided on the latest version (LFZP113).

Improvements to the Loss of Load feature.

Improvements to the blocking scheme when used with duplex communication channels.

Improved phases selector performance for the fault locator.

Publication R4056 Optimho forms part of this service manual:

SERVICE MANUAL

R5911D

AREVA T&D, St Leonards Works, Stafford ST17 4LX, England Tel: +44 (0) 1785 223251 Fax: +44 (0) 1785 212232

Our policy is one of continuos product development and the right is reserved to supply equipment which may vary from that described. ©1997 AREVA T&D

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Service Manual R5911DLFZP11x Issue

Page 1 of 1

Issue control

Issue Date Author Changes

A-C to 1996 Support Engineers OriginationD 1996/97 Publicity/Support Engineers Formatting and changes to

all chapters

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Service Manual R5911DLFZP11x Contents

Page 1 of 1

CHAPTER 1 APPLICATIONS NOTES(R4056K included)

CHAPTER 2 DESCRIPTION TECHNICAL DATA

CHAPTER 3 INSTALLATION AND HANDLING

CHAPTER 4 COMMISSIONING

CHAPTER 5 CUSTOMER VARIANTS

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CHAPTER 1

APPLICATION NOTES

(PUBLICATION R4056 INCLUDED)

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OPTIMHOStatic Distance Protection Relays

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OPTIMHOStatic Distance Protection Relays

Features

• Full scheme distance relays with18, 12, 9 or 6 measuring units.

• Phase and ground distance orphase distance protection.

• Single or multiple zones.

• Optional directional earth faultprotection.

• Typical operating time: one cyclefor three phase faults.

• Optional fault location includesmutual compensation on selectedmodels.

• Optional data recording for postfault analysis and instrumentationfunctions.

• Eight independent groups of settings can be stored in therelay.

• A second blocking scheme isavailable on selected models foruse with signalling equipment.

• Integral user interface for easyaccess to relay setting and faultrecords.

• Provision for remotecommunications via modems.

Benefits

• Wide model range for accuratematching to applications.

• Remote interrogation reducesneed for site visits.

• Precise fault location, even ondouble-circuit lines together withfault information reduces outagetime.

• Accurate fault informationprovides for in-depth faultanalysis.

• Changes to alternative groups of settings can be accomplishedwith a single command.

• Self diagnosis reducesmaintenance costs.

• Vertical case option eases retrofitproblems.

• Will interface with existingscheme logic.

• Fulfils basic SCADA role at noextra cost.

Figure 1: Optimho (Type LFZP) relays

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Summary Chart

Transmission and Sub-transmission Backsub transmission and distribution upmain protection main protection only

LFZP Model 111 112 113 114 121 122 123 131 132 151

Phase distance • • • • • • • • • •

Ground distance • • • • • • • •

DEF • • • • • •Fault location • •

Fault location with mutual compensation • • • • • • •

Overhead lines • • • • • • • •

Underground cables • •

Open delta/3 limb VTs • •

No. of distance elements 18 18 18 12 12 12 12 9 6 6

Independent zones Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1

Z2 Z2 Z2 Z2 Z2 Z2

Z3 Z3 Z3 Z3 Z3 Z3 Z3 Z3

Reach stepped zones Z1X Z1X Z1X Z1X Z1X Z1X Z1X Z1X Z1X

Z1Y Z1Y Z1Y Z1Y Z1Y Z1Y Z1Y Z1Y Z1Y

Z2 Z2 Z2

Reversible zones • • •

Single pole tripping • • • •

VT supervision • • • • • • • •

3 phase fuse blow supervision • • • • • • • •

Power swing blocking • • •

Loss of load trip feature • • • • • • •

No. of output contacts 24 24 24 24 16 16 16 16 16 8

Basic • • • • • • • • • •Z1 Extension • • • • • • •

Acceleration • • •

PUR • • • •

PUR Unblock • • • •

Schemes POR1 • • • • • •

POR1 Unblock • • • • • •

POR2 • • • •

POR2 WI Trip • • • •

POR2 Unblock • • • •

POR2 WI Trip Unblock • • • •

Blocking • • • •

Blocking 2 • • • •

Z1, Z1X, Z1Y, Z2 Phase m m m m m m c f f

Distance Z1, Z1X, Z1Y, Z2 Ground q/m m m m q/m m c

Characteristic Z3 Phase L L L N N N P N

Z3 Ground Q/L L L D/N N N N

Negative sequence volts • • • • • •

DEF Zero seq current • • • • • •

polarising Zero seq volts • • • •Zero seq volts+current • • • •

• = standard, • = optional, m = shaped mho, f = fully crossed polarised mho, q = quadrilateral,c = shaped mho for cables, D = offset quadrilateral, N = offset lenticular, Q = D/rev q, L = N/rev m, P = N/rev f.For further information see Page 6.

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Applications of Optimho

Optimho is produced in severalmodels, each suitable for a specificrange of applications. The moresophisticated models have featuresand functional abilities which canfulfil the most exacting duties.These can include ehv applicationsdepending on the fault clearancetime required. The more basicmodels have reduced hardware andsoftware to suit the simplerrequirements of sub-transmissionand distribution systems.

Optimho complements the wellestablished Micromho andQuadramho, enhancing the alreadyoutstanding family of distanceprotection available from AREVA

T&D.The range of applications includes:

– main and back-up protection of overhead lines and undergroundcables including transformerfeeders.

– back-up protection of transformers, auto-transformersand shunt reactors (LFZP 151)

– protection of solid or resistance

earthed systems.– Three-pole or single-and-three-

pole tripping, with or without theaid of a signalling channel.

– single zone relays used inmultiple zone schemes to provideultra-high reliability by additionalredundancy of protection(LFZP 121, 122 or 132 with onezone enabled).

– on-site replacement of obsolescent electro-mechanical orswitched static distance relays.

– protection of systems with open-delta line voltage transformers or3– phase 3– limb line voltagetransformers (LFZP 131 or 132).

– phase selection to allow, forexample, a power line carrierphase comparison scheme (suchas P10) to carry out single phasetripping (LFZP 114).

Principles of Operation

All models of Optimho are fullscheme distance relays which havea full set of measuring elements foreach main zone of protection.Compared with the switched type of scheme, the full scheme systemimproves reliability by avoiding theneed to rely on phase selectionhardware or software and byremoving dependence on a singlemeasuring unit. Full scheme distancerelays are better able to cope withinter-circuit faults on double circuitlines and evolving faults.

The measuring element uses a micro-controller to produce a directsoftware equivalent of the hardwarephase comparator used in

Optimho’s forerunners, Micromhoand Quadramho. This phasecomparator design is well tried,having accumulated nearly tenthousand relay years of successfuloperating experience over the lastdecade at locations throughout theworld.

Many of the other hardware andsoftware features of Quadramhohave been retained and further

enhanced in Optimho, ensuring thehighest standards of reliability.

Optimised Performance with Distorted Signals

The phase comparators and leveldetectors use logic processing toachieve immunity from maloperationdue to noise, such as harmonicdistortion, travelling wave effects,high and low frequency capacitor

voltage transformer transients andcurrent transformer saturation.Operation of the phase comparatorsand level detectors can only occur if the input signals are dominated bypower frequency components.Filters are used to insure thisdominance and to optimiseoperating times.

Hardware Structure

All models are built up from a smallrange of standard printed circuitboards used as modular buildingblocks.

All models use the same relay case,power supply unit, and front panel.

The relay hardware is bus-structuredto allow printed circuit boards to beplugged into the case in differentcombinations. (See Figure 2).

The hardware uses multiplemicrocontrollers to perform ascomparators, level detectors, etc.A main microcontroller uses thedigital bus to read outputs from thesubsidiary microcontrollers, readsignals from the outside world via

optically coupled isolators,communicate with the user interfaceand perform scheme logic, serialcommunications, monitoring andoutput contact functions. Settings,indications, and fault records arestored in a type of memory which isunaffected by loss of dc supply.The layout of the relay case followsthe ‘quiet region’ arrangementintroduced in Micromho andQuadramho, with measurement and

control boards located in ascreened compartment and fed withsignals from the outside world viascreened isolation devices andfilters. See Figure 3.

A vertical aspect, panel mountedversion can be used for replacingobsolescent electromechanicaldistance relays in narrow panels,with the minimum of paneldisturbance.

Integral User Interface

All relay settings and records areaccessible from the integral userinterface shown in Figure 4.

The liquid crystal display (LCD)indicates how the relay initiated thelatest trip. The faulty phase andzone are indicated for trips initiatedby the distance elements. The latestalarm condition is also indicated.

If indications are present when thesupply is lost, they are automaticallyreinstated when the supply isrestored.

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The date and time of the fault,location (if available), and more,are displayed by pressing READ.After the indications have beenread, they can be cleared bypressing RESET, and the READ keycan then be used to step through allthe relay settings displayed insequence.

The cursor and SET keys, and the

two test sockets, are only accessibleafter removing the transparent frontcover. The keys are used to selectfrom a menu of options displayedon the LCD in English, and to enternew settings into temporarymemory. The menu has a simplestructure, allowing rapidfamiliarisation.

The SET key is used to transfertemporary entries to the permanentmemory which determines relayaction. Accidental changes areprevented by allowing SET to beoperative only at certain points inthe menu after appropriatewarnings have been displayed.

Figure 3: Mechanical layout of LFZP

Figure 4: User interface on front panel

User interface

8 Output relays

Statusinputs

8 Output relays

8 Output relays

Trips.alarms,etc.

A n a l o g u e b u s

Main controller board+ Schemes, settings,

comms, monitoring diagnostics

Fault location board+ Fault data and instrumentation

Level detector board+ AC supply supervision

Zone 1 and 2 board(Alternatively zones 1, 2 and3)

+ Additional reach – stepped zones

Zone 3 board+ Power swing blocking

DEF board

Quadrilateral

ground fault board

Settings fromdigital bus

Optional boards shown inbroken outline

AC inputs

Analogueinput

module

RS232C serial link to remote terminal

D i g i t a l b u s

VA VB VC

ΙA ΙB ΙC

ΙN

Ιp

VN

7 Optical isolators

Output auxiliaryrelays andstatus input

optical isolators

Fully screenedpower supplyunit enclosureTerminal blocks

Terminal block Analogueinput module

Measurementand control

boards in fullyscreened

compartment

User interfaceon hinged front

panel

DISTANCEPROTECTION

SET

RESET ACCEPT/READ

RELAY AVAILABLE

PARALLEL

SERIAL

TRIP

ALARM

2 x 16 characterliquid crystal display Light emitting diodes

Test sockets7 Keys – only RESET and ACCEPT/READaccessible with front cover in place

Figure 2: Electrical structure of LFZP

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Menu Options

The menu holds an extensive rangeof options, including:

– viewing records of the LCDindications from the last fourfaults.

– printing records or settings on aportable printer plugged into theparallel test socket

– entering a relay identificationcode for use on printouts.

– comprehensive test options suchas: monitoring test points on theparallel socket; blocking outputcontacts (the relay inoperativealarm contact closes when theoutput contacts are blocked);simplified on-load directionaltesting; and closing selectedoutput contacts (for instance tocarry out a circuit breaker test)

– setting up the baud rate andprotocol for the serialcommunications.

Settings

The setting options allow the user toselect functions to suit each

application. The available optionsdepend upon the model of Optimho, but usually include:

– scheme type

– which distance zones areenabled (up to 5 zones)

– whether ground fault timedelayed zones (if fitted) areenabled

– direction of reach-stepped zonesor of Zone 3 (if fitted)

– whether start indications arerequired for remote faults whichdo not result in a trip.

– eight independent groups of settings which are stored in therelay memory and are selectablefrom the menu.

The menu is adaptive; for example,if Zone 2 is not required and hasbeen disabled, its time setting is

automatically removed from themenu.

Schemes Available

The scheme selection varies with themodel of Optimho. Most modelshave basic distance with up to 3independent zones available,designated Z1, Z2 and Z3.Additional zones 1X and 1Y areobtained, if required, by steppingthe reach of the Zone 1 elementsafter time delays started by theZone 2 and/or Zone 3 elements.On some models Zone 2 is obtainedby stepping the reach of Zone 1,while on some other models, Zone 3is omitted.

Models offering selectable,permissive overreach andunblocking schemes are completewith current reversal guard logic

and open breaker echo logic.Models having independent Zone 1,Zone 2 and Zone 3 have additionalpermissive overreach andunblocking schemes with weakinfeed logic, also the blockingscheme. These schemes requireZone 3 to be set reverse looking.

Single phase tripping logic isavailable in some models.

Loss of load accelerated trippingfeature is available on some modelsfor use with 3 pole tripping.

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Distance Characteristics

The phase comparator is arranged to produce several types of distancecharacteristics for the different models of Optimho. For further information seeSummary, Page 3.

Characteristic Descriptiontype

m Partially cross polarised shaped mho with partialsynchronous polarising for 3-phase faults. Expansionunder fault conditions is more than adequate to cover arcand tower footing resistance for most systems, withexcellent phase selection. See Figure 5.

f Fully cross polarised (or quadrature polarised) mho withpartial synchronous polarising for 3-phase faults.Similar to type m above but used where only phase faultprotection is required.

c Self polarised mho, with a small proportion of crosspolarising: used for ground fault protection of

underground cables at high and medium voltages.q Quadrilateral with adaptive reactance measurement to

avoid overreach or underreach for resistive faults withprefault load. The directional measurement is partiallycross polarised. The resistive reach setting is variable upto 150Ω (1A relay) or 30Ω (5A relay). The quadrilateralis used instead of type m above to cover ground faultresistance on overhead lines shorter than 15km, onresistance neutral systems, or on systems with high groundresistivity. See Figure 6.

D Offset quadrilateral: as type q but with reverse reach for

busbar back-up protection in Zone 3 time.N Offset lenticular with a variable aspect ratio set to avoid

load encroachment on long lines. A circular offset settingfor shorter lines is included. The reverse reach is used forbus back-up protection in Zone 3 time. Reach steppedzones whose timers are started by Zone 3 automaticallyavoid load encroachment if Zone 3 is shaped to avoid theload impedance. See Figure 7.

Q Selectable between type D and reverse type q.

L Selectable between type N and reverse type m.

P Selectable between type N and reverse type f.

Figure 5: Resistive expansion of partially cross-polarized mho under f ault conditions for solidly grounded systems

X

Numbers are source impedance/relay setting ratios

24 60

12610

R

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Remote Communications

All the options available on themenu are also available from alocal or remote terminal via anRS232C serial communication port.Sockets are provided on both thefront and the rear of the relay fortemporary or permanent connectionrespectively. The socket on the rearcan also interface with a modem forcommunication over a suitable link,for instance a telephone line.

The facility to bulk transfer settings,event records and meteringinformation (providing a faultlocator is fitted) is available usingAREVA T&D based software

‘Opticom’.

By using KITZ 103 interface unit, theOptimho can be interconnected torelays in the AREVA K range.The interconnection is via ashielded, twisted wire pair knownas K-Bus. Up to 32 relays may beconnected in parallel across the bus.The K-Bus is connected through asecond KITZ protocol convertoreither directly or via a modem to theRS232 port of the pc. The K-Bus isRS485 based and runs at

64 kbits/s.From the same pc, Opticom 100(version 5.0 and higher) and anyCourier based Access Softwarepackages can be used tocommunicate with the Optimho.

The KITZ 103 and the LFZP act as asingle slave device over K-Bus, seeFigure 8.

For more detailed information on theapplication of Optimho over K-Bus,

including modem connections, baudrates, bit framing and the use of Courier features, reference shouldbe made to the following servicemanuals:

KITZ 101/102Interface Unit R8521

KITZ 103K-Bus to Optimho Interface R8532

OptiCom 100/140Settings Databaseand File Transfer R5928

Figure 6: Quadr ilateral ground fault characteristics

Figure 7: Lenticular Zone 3

Z one 3

Z one 2

Z one 1

Z one 3 r ev er se

D i r e c t i o na l l i ne

Z o ne s 1 & 2

R

L H R

e s i s t i v

e r e

a c

h

X

R H

R e s i s t i v

e r e

a c

h

X

Zone 3

Zone 3reverse

a

b

0.410.67

1.00Aspect ratios a/b

Loadarea

R

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Polarising

The partial cross polarising signalused in various distancecharacteristics is a square wave

derived from a healthy phasereference and 16% of the amplitudeof the prefault voltage. This wave isadded to the faulty phase voltage,and dominates it for close-upunbalanced fault conditions.This provides a clear directionalreference even in the presence of capacitor voltage transformertransients.

The partial synchronous polarising is

similar to partial cross polarising butis effective for 3-phase faults.Synchronous polarising is derivedfrom prefault voltage and isavailable for 16 cycles after faultincidence to cover breaker failureprotection time.

Several cycles must elapse fromsystem energisation beforesynchronous polarising is available,so switch-on-to-fault logic isarranged to provide protection forclose-up 3-phase faults during thisinitial period.

Directional Earth FaultProtection(not available in all models)

The directional earth fault protection(DEF) has these features selectablevia the user interface:

– time delayed tripping, eitherdefinite time or inverse definiteminimum time using a selection of built-in IEC or American curves.See Figure 9.

– instantaneous high-set tripping,available if the model of Optimhohas no Zone 1 instantaneous

ground fault elements fitted.– aided tripping via permissive

overreach, unblocking, orblocking schemes (depending onthe model), which work inconjunction with the distancescheme, sharing the samesignalling channel.

– choice of polarising for thedirectional element:

negative sequence voltage

derived from internal filters(compared against negativesequence current).

zero sequence current from aseparate current input

zero sequence voltage (in somemodels) derived internally fromVA, VB and VC.

dual zero sequence current and

voltage (some models only).The overcurrent elements use zerosequence current as the operatingquantity irrespective of the type of polarising used for the directionalelement.

The negative sequence filters areself-adaptive to system frequency,allowing greater sensitivity than ispossible with fixed filters tuned tothe nominal system frequency.

A magnetising inrush currentdetector is provided to preventmaloperation when energising in-zone transformers. The circuit usesthe principle of detectingzeros in the current lasting for aquarter-cycle or more. This methodis inherently unaffected by currenttransformer saturation, unlikesecond harmonic restraint.

Figure 8: Typical application diagram: KBUS/LFZP 100 (Optimho) Interface Type KITZ 103

Auxiliarysupplyvoltage

KITZ101/102KBUS/IEC 60870 Interface+

_

Screen

Screen

All points are internally connected

2 TX3 RX 7 Signal GND 1 Protective GND

IBM or compatible P.C.(For pin assignmentnumbers see table)

Auxiliarysupplyvoltage

12

150R

KITZ103 KBUSLFZP 100 (Optimho)

Interface

LFZP 100 (Optimho) Relay +_

All points are internally connected

2371

2 TX3 RX

7 Signal GND 1 Protective GND

12

*

54

56

150R

Typical ‘K’series relay

When Fitted

Terminals

Screen Link

56

54

Typical ‘K’series relay

Terminals

(Rear Port)

Table showing connections between KITZ 103 serialport and LFZP 100 (OPTIMHO) rear serial port.(For reference only. Please refer to PC user manualwhere available).

KITZ 103 LFZP 100 (OPTIMHO) rear serial port type

25 pin ‘D’ male connector (DTE) KITZ 103 25 pin ‘D’ male connector (DTE)

1 – Protective ground 1 – Protective ground

2 – Transmitted data 2 – Received data

3 – Received data 2 – Transmitted data7 – Signal ground 7 – Signal ground

Connector shell to cab le screen Connector shell to cable screen

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Fault Location, FaultData Recording andInstrumentation(not available in all models)

The fault location algorithm includescompensation for infeed into aresistive fault from remote source

with prefault load flow. Readout of the fault location can be selected tobe in kilometres, miles or percent of line length.

Some versions of the fault locatorcan be mutually compensated if required. This feature can not beused if zero sequence currentpolarising is required for the DEF.

The fault location board alsocomputes prefault and fault voltagesand currents phase-by-phase.These values, together with negativeand zero sequence current andvoltage can be read out to allowanalysis of the power systemnetwork as it was at the time of

fault. The duration of the fault is alsodetermined.

At any time under healthy live lineconditions, the line voltages,currents, watts and vars can becalculated on demand. These valuescan be compared with otherinstrumentation for accuracy.

As the fault location hardware islargely separate from that of thedistance measuring elements,protection accuracy can be cross-checked with fault location accuracyduring secondary injection tests.

All voltages and currents are givenwith phase angle relative to prefault

VA, and rms amplitudes in primaryor secondary terms.

Figure 9: DEF Protection time delay trip times

10

1

0.1

O p e r a t i n g T i m e t ( s e c o n d

s )

1 5 100

O p e r a t i n g T i m e t ( s e c o n d

s )

Current (Multipule of Ιs)American curves

Current (Multipule of Ιs)IEC curves

100

Curve 5 US moderate inverse

Curve 6 US standard inverse

Curve 7 US very inverse

Curve 8 US extremely inverse

Curve 1 S tandard inverse: t = 0.14Ι0.02 –1

Curve 2 Very inverse: t = 13.5Ι–1

Curve 3 Ex treme ly inverse: t = 80Ι2–1

Curve 4 Longtime earth fault: t = 120Ι

–1

5

0.5

10 50

50

1 5 10010 50

Curve 5

Curve 6

Curve 7

Curve 8

Curve 4

Curve 1

Curve 2

Curve 3

10

0.1

100

5

0.5

50

1

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Figure 10: 50Hz operating times (MHO characteristic)

Figure 11: 60Hz operating times (MHO characteristic)

Figure 12: 50Hz operating times (quadrilateral characteristic)

0.03

OperatingTime(s)

0.04

0.02

0.00

0.01

Fault location (% of relay setting)

20 40 60 800 100

0.03

OperatingTime(s)

0.04

0.02

0.00

0.01


20 40 60 800 100

Source impedenceRelay setting = 1

Minimum

MeanM a x i m u m

Mean

Minimum

MaximumSource impedence

Relay setting = 30

0.03

OperatingTime(s)

0.04

0.02

0.00

0.01


20 40 60 800 100

Ma x i mu m

0.03

OperatingTime(s)

0.04

0.02

0.00

0.01

Fault location (% of relay setting)20 40 60 800 100

Source impedenceRelay setting

= 30Source impedence

Relay setting= 1

Maximum

M e a n Me an

M in im um

M in imum

0.03

OperatingTime(s)

0.04

0.02

0.00

0.01


20 40 60 800 100

M a x i m u m

M e a n

M in imumMinimum

0.03

OperatingTime(s)

0.04

0.02

0.00

0.01

Fault location (% of relay setting)20 40 60 800 100

Source impedenceRelay setting = 30 Source impedenceRelay setting = 1

Maximum

M e a n

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Self-Monitoring and Voltage TransformerFuse/MCB Supervision

Optimho has comprehensivecontinuous self-monitoring. If afailure occurs, an alarm is issued byclosing the relay inoperative alarmcontact and extinguishing the relayavailable LED. Diagnosticinformation is automatically

displayed if the failure is such that itdoes not disable the main processorand LCD.

Monitoring of the analogue circuitsincludes (i) the dc supply and allinternal dc power supply rails, and(ii) the ac supplies and internalanalogue voltage and currentcircuits (the latter only if the modelof Optimho has voltage transformersupervision).

The VT supervision logic can be setto block relay operation in the eventof failure of a VT fuse. The VTsupervision logic can be selectedvia the menu to self reset, or toremain sealed in until the resetbutton is pressed. All models havean optically coupled isolator tomonitor the auxiliary contact of aminiature circuit breaker if the VTsupplies are protected by an MCBinstead of fuses. Energising the

optical isolator blocks relayoperation.

Figure 13: 60Hz operating times (quadrilateral characteristic)

In addition, an optional externaldevice for monitoring 3 phase fuseblow via the RELAY BLOCKED opto-isolator is available.

Monitoring of the digital circuitsincludes (i) bus communications(ii) checking of RAM and EEPROMand (iii) watchdog circuits for everymicrocontroller. In the event of failure, trip signals originating fromthe affected part of the relay are

blocked.In models with quadrilateral groundfault characteristics, remedial actionis performed if the quadrilateralmeasuring circuits fail.The alternative shaped mho groundfault measuring elements, located ona different board, are automaticallybrought into action to restore theground fault protection. On powersystems where most faults areground faults, this capabilityconsiderably increases the overallavailability of the relay.

0.03

OperatingTime(s)

0.04

0.02

0.00

0.01


20 40 60 800 100

0.03

OperatingTime(s)

0.04

0.02

0.00

0.01


20 40 60 800 100

Source impedenceRelay setting

= 30Source impedence

Relay setting= 1

Minimum

Ma x imum

M e a n

Max imum

Mean

Minimum

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Contact Arrangements

Most models are pre-programed togive a choice of at least two outputcontact arrangements. One of theseis arranged to give direct access tothe relay’s measuring units via theoutput relay contacts, so that acustomer’s existing protectionscheme can be operated inconjunction with Optimho if required. The other arrangementstake advantage of the Optimho’sown integral scheme logic.

Other Options

To be specified with order.

A facility to control the setting groupselected via five optical isolators is

available on all models.A facility to control the setting groupselected via three optical isolators isavailable on all models. Full schemeoptions are provided and threesetting groups are available.

Selection Chart 1

START

Ground Fault Distance?

Yes No

No

Either of the following:*voltage transformer supervision?*power swing blocking?

Yes

Any of the following:*week infeed POR unblocking scheme?*blocking scheme?*back-up for reverse faults?

Yes No

LFZP 132With DEF

OK for open-deltaOr 3–limb VTs

Optional fault locaton

LFZP 131With DEF

OK for open-deltaOr 3–limb VTs

Optional fault locaton

Yes No

Quadrilateral groundfault elements?

No

Any of the following?*weak infeed POR/unblocking scheme?*blocking scheme?*back–up for reverse faults?*power swing blocking?

Yes

LFZP 121Optional fault

location

Yes No

LFZP 112Optional DEF.

Optional fault locator


Optional fault locator

Any of the following:*single pole tripping?*permissive undereach scheme (PUR)?*permisssive overreach Scheme (POR)?

*unblocking scheme?*power swing blocking?

No

Quadrilateral groundfault elements?


Optional fault location

Yes No

Yes

In some models specified above, it will be necessary to disable unwanted zonesand facilities with settings on the menu.


location

DEF Scheme?Go tochart 2

Undergroundcables?

No

Yes

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Selection Chart 2

Selection Chart 3


START

Yes No

Go to chart 1

LFZP 113Optional fault location

Optional DEF

LFZP 123Optional fault location

No DEF

Yes No

Underground cables?

Any of the following?*single pole tr ipping? * blocking scheme?*PUR scheme? * power swing blocking?*POR scheme? * c apacitor voltage*unblocking scheme? transformers?

START

Any of the following:*single pole tripping?*power swing blocking?*DEF?

Either of the following:*offset characteristic?*power swing blocking?

LFZP 112Optional DEF.Optional fault

location

No

No

Yes

Yes No

Yes No

Offset characteristic

LFZP 151No faultlocation

LFZP 114Optional DEF.Optional fault

location


location

Either of the following:*offset characteristic?*power swing blocking?

YesLFZP 131with DEF.

Optional faultlocation

LFZP 132with DEF.

Optional faultlocation

Offset characteristic?

No

Any of the following:*ground fault distance?*voltage transformer supervision?*power swing blocking?

Single Zone Distance?

Yes

Go to chart 1


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Figure 14: Case connection diagram for relay inputs

A

BCPhase rotation

Direction of power flow for operation

P2 P1

S2A

B

C

A B C

N

a b c

Fusesor MCB

DEF current polarisation when required

S2

P1P2

2A27 2A28

2A25 2A26

2B27 2B28

2B25 2B26

2B23 2B24

2B21 2B22

2A23 2A24

2A21 2A22

2A11 2A12

2A9 2A10

2A7 2A8

2A5 2A6

2A3 2A4

2A1 2A2

MMLGTest block orEquivalent

LFZP 11119

20

21

22

23

24

25

26

15

16

17

18

27

28

+

2B13 2B14 2A13 2A14

2B 9 2 B1 0

2B7 2B8

2B1 2B2

2B5 2B6

2B11 2B12

2B3 2B4

15 70

19 74

3 58

11 66

78

7 62

23 82

A13

CRX

COX

RZ1X

CB AUX

MCB

IPD

R1

17

1

9

13

5

21

External resistor boxrequired for 220/250V

supply only

2A17

2B17

2A 18

2B18

49

77

DC supply

Signal receive

Channel out of service

Rest zone 1 extension

Breaker open

Relay blocked

Inhibit PSB, DEF, WI.

Reset indications

Signal send51

2B20 2B 19

2A 20 2A 19

79

84

64

80

68

60

72

76

14 2A16 2A15 2B16 2B15

–

a

b

c

Fusesor MCB

Alternative voltagetransformer connectionfor LFZP 131 & 132

Test block LFZP

15

16

17

18

Any Trip

S1

Opto–isolator inputs when required:

CRX Open contac t from signalling channe l

COX Close contact f rom s ignall ing channel

RZIX Open contact f rom auto–reclose relay

CBAUX Closed circuit breaker contacts connectedin series to indicate all poles open. Requiredwith busbar VT or if the weak infeed or echofeature of POR scheme are required

MCB Closed contact from minature circuit breakerrequired when no VT fuses are used

RI Open contact to reset visual indications

IPD Open contac t from auto–reclose re layrequired with single phase tripping if PSBor DEF options are used. Opto must beenergised during single pole dead times

For the unblocking mode of operation use CRX forthe unblock frequency (trip frequency) and RZIX

for the block frequency (guard frequency)

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Technical Data

Ratings

AC voltage Vn: 100 to 120V rms phase-phase

AC current In: 1A or 5A rms per phase

Frequency f n: 50Hz or 60Hz

Operating frequency range: 47 to 51Hz or 56.4 to 61.2 HzDC Supply Vx(1): For switched mode dc/ac/dc power

supply unit, available in three versions:

Nominal Operative Maximumrange withstand

48/54V 37.5 to 60V 64.8V

110/125V 87.5 to 137.5V 150V

220/250V 175 to 275V 300V

There is negligible change of accuracy with change of voltage within the operative range of the relay.

DC supply Vx(2): For optically coupled isolators.Supply options are the same as Vx(1).External resistor box provided for 220/250V version(see Figure 16).

Maximum overload ratings

AC voltage: 1.2Vn for measuring accuracy1.5Vn continuous withstand2.5Vn withstand for 10s.

AC current: 2.4In continuous withstand100In withstand for 1s (In = 1A)80In withstand for 1s (In = 5A)

Burdens

AC voltage circuits: 0.1 VA per phase at Vn

AC current circuits: 0.08 VA per phase (In = 1A)0.5 VA per phase (In = 5A)

DC supply (1): 18W under healthy live lineconditions at Vx(1) 28W maximum

DC supply (2): 10mA per energised opticallycoupled isolator at Vx(2).

Distance elements

Range of positive sequence settings referred to line VT and CT secondaries:

All employed zones except reverse Zone 3:

Overhead line models 0.2 to 250Ω (In = 1A)0.04 to 50Ω (In = 5A)

Underground cable models 0.1 to 125Ω (In = 1A)0.02 to 25Ω (In = 5A)

Reverse Zone 3

Overhead line models 0.04 to 250Ω (In = 1A)

0.008 to 50Ω (In = 5A)

Underground cable models 0.02 to 125Ω (In = 1A)and LFZP 151 0.004 to 25Ω (In = 5A)

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Reach setting method is by digitally controlled analogue attenuators.Attenuation factors KZPh and KZN operate on current signals and arecommon to all zones.

Attenuation factors KZ1, KZ1X, KZ1Y, KZ2, KZ3 and KZ3’ operate onvoltage signals and are specific to Zone 1, Zone 1X, Zone 1Y, Zone 2,Zone 3 forward and Zone 3 reverse respectively. The positive sequencereach for Zone 1 is given by:

Zone 1 = KZ1. KZPh.5/In for overhead line models.

Zone 1 = KZ1. KZPh. 5/2In for underground cable models.

Either KZ1 or KZPh is set to 1.000. To obtain the formula for each of theother zones employed, replace KZ1 by the appropriate attenuation factor forthe zone.

Extra settings for ground fault distance:

Residual compensation factor:

KZN=

ZL0 – ZL1 KZPh 3ZL1

Where ZL0 and ZL1 are the phasor values of zero and positive sequence

impedance of the protected line.Quadrilateral resistive reach settings:

Right hand reach = KR.5/In

Left-hand reach = KR.6/In (LFZP 111)

Left-hand reach = KR.5/In (LFZP 121)

Range of factors: KZPh 0.040 to 1.000 in steps of 0.001

KZN 0.000 to 1.360 in steps of 0.001

KZ1KZ1X

KZ1Y 1.00 to 49.98 steps of 0.02KZ2KZ3

KZ3’ 0.2 to 49.9 in steps of 0.1

KR 1 to 30 in steps of 1

Range of setting of Zone 3 lenticular aspect ratio:

a/b = 1.00, 0.67 or 0.41

Characteristic angle settings:

θ Ph = arg ZL1 to nearest available setting.

θ Ph = 50° to 85° in 5° steps (overhead line models)θ Ph = 45° to 80° in 5° steps (LFZP 113 only)

θ Ph = 20°, 25°, 30°, 35°, 40°, 50°, 60° or 70° (LFZP 123 only)

Vectorial residual compensation for ground fault distance:

θ N = arg (ZL0 – ZL1) to nearest available setting

θ N = 50° to 85° in 5° steps (overhead line models)

θ N = –45°, –35° and –25° to 80° in 5° steps (LFZP 113 and 123 only)

Note: LFZP 113 is not designed to be used with a ground fault loop setting(2ZL1 + ZL0) /3 with an argument less than 30°.

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Minimum operating values of the distance measuring elements forall types of fault:

Voltage: zero

Current: 0.05In/KZPh.

Accuracy: Reach: ±5% at 2In and 20°C

Dynamic range: up to 25In for faultlocator and instrumentation up to

56In for distance protectionCharacteristic angle: ±2°

Resetting ratio: 105%

Timer ranges: Zone 1X timerZone 1Y timer each timer 0.10s to 9.98sZone 2 timer in steps of 0.02sZone 3 timer

Scheme co-ordination timers used in permissiveoverreach, unblocking and blocking schemes:

TP

TD 0 to 98ms in steps of 2msTDW

Timer accuracy: ±1% of setting and ±3ms.

Operating time: Typical relay operating times for Zone 1 are shown inFigures 10 to 13.

Mho characteristic (type m, f or c) 50Hz minimum: 14mstypical: 18ms

60Hz minimum: 12mstypical: 16ms

Quadrilateral characteristic (type q) 50Hz minimum: 16ms

typical: 23ms60Hz minimum: 15ms

typical: 20ms

Reset time: The trip contacts are sealed in for 60ms following theinitial contact closure. Thereafter, the maximum resettime is 35ms.

Power swing blocking

Power swing detected by transit time of impedance between Zone 6 andeither Zone 2 or Zone 3 as selected. Zone 6 is offset mho or offset lenticular,with the same range of forward and reverse reach settings and aspect ratios

as Zone 3.Zone 6 timer range: 20ms to 90ms in steps of 5ms

Power swing detection regimes:

(i) detection disabled.

(ii) detection indicated only.

(iii) indication plus blocking of any one or moreselected zones.

Blocking disabled if a ground fault or (if DEF fitted) a phase fault occursduring a power swing.

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Directional earth fault

Directional measuring elements: one forward-looking, one reverse-looking:

Current sensitivity determined by current level detector:0.05In to 0.80In in steps of 0.05In

Sensitivity of polarising quantity is 1V residual voltage of 1.5% polarising current, as appropriate, depending uponthe type of polarising selected.

Characteristic angle θG = 10° to 80° in 10° steps.Instantaneous trip (available only if no Zone 1 ground fault distanceelements fit):

Setting range: 0.2In to 30In in steps of 0.05In

Accuracy: ±5% at f n, 20°C

Aided trippingscheme: Scheme co-ordination timers:

TPG 0 to 98ms in steps of 2msTDG

High set current level detector 0.05In

to 0.80In in steps of 0.05InTime delay trip: Setting Is = 0.05In to 1.20In in steps of 0.05In

Time curves: eight curves and three definite time rangesshown in Figure 9.

Time multiplier: *t = 0.025 to 1.000 in steps of 0.025

Accuracy at f n, 20°C, *t = 1, Is = 0.05In to 0.80In:

Current: +10% – 0%

Operating time: definite time ±3% over 1.3Is to 31Is

curves 1, 2, 4, 5, 6, 7, 8 ±5% over 2Is to 31Is

curve 3 ±7.5% over 2Is to 20Is

Fault location and instrumentation

Fault location positive sequence settings referred to line VT and CTsecondaries:

Range: 0.2Ω to 200Ω (In = 1A)0.1Ω to 100Ω (In = 1A) (113/123)

0.04Ω to 40Ω (In = 5A)0.02Ω to 20Ω (In = 5A) (113/123)

Setting: Zone F = KZF. KZPh.5/In for overhead line models.Zone F = KZF. KZPh.5/2In for underground cable models.

KZPh and residual compensation are common to the distance measuringelements.

KZF range: 1.00 to 40.00 in steps of 0.01.

Line length setting (in miles or km or %)

0.00 to 99.99 in steps of 0.01

100.0 to 999.9 in steps of 0.1

KZM and θM are provided for mutually compensating the fault locator if required:

KZM range: 0.0 to 1.36 in steps of 0.001

θM range: 50° to 85° in steps of 5°

Accuracy ±2% at 2In, f n, 20°C.

Settings to allow for transformer ratios for instrumentation functions:

CT ratio: 1:1 or 10 to 5000: 1 in 10:1 steps

VT ratio: 1:1 or 10 to 9990: 1 in 10:1 steps

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Block or enable reclose logic

A normally-open or normally-closed contact is supplied on most models toblock or enable reclose respectively.

The menu allows the following choices of logic:

Reclose blocked or enabled on:

Zone 1 or aided trip caused by 2 or 3 phase fault

Zone 1 or aided trip cased by 3 phase faultZone 1X and/or Zone 1Y and/or Zone 2 timedelayed trip

Channel out of service

DEF instantaneous and/or aided trip and/or delayed trip.

Voltage transformer (fuse fail) supervision

The voltage transformer supervision (VTS) operates when zero sequencevoltage is detected without the presence of zero sequence current, by meansof the low set neutral level detector. The VTS does not limit the distance relaycurrent sensitivity or operating times for line faults even when the VTS is set to

block relay tripping.

Nominal Vo detector setting 9.5V

The blocking action of the VTS on distance comparators can be removed bymenu selection via the user interface.

Switch-on to fault logic

Menu choices allow instantaneous trip and alarm and indication for faultsoccurring on line energisation, whether bus or line voltage transformers areused:

SOTF enabled either 0.2s or 110s after line de-energised

(110s prevents SOTF action on auto-reclosure).SOTF trip via measuring elements.

SOTF trip via current and voltage level detectors.

Output contacts

Some of the available arrangements are shown in Table 1.

Ratings:

Make and carry 0.2s 7500VA subject to a maximaof 30A, 300V, ac or dc.

Carry continuously 5A ac or dc.

Break ac: 1250VAdc: 50W resistive

25W L/R = 0.04sSubject to a maxima of 5Aand 300V

Durability

Loaded contact 10,000 operations minimum

Unloaded contact 100,000 operations minimum

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High voltage withstand

Dielectric withstandIEC 60255-5:1977 2kV rms for 1 minute between allANSI C37.90:1978 terminals and case earth.

2kV rms for 1 minute betweenterminals of independent circuits,with terminals on each independentcircuit connected together.

1.5kV rms for 1 minute acrossnormally open contacts

High voltage impulseIEC 60255-5:1977 Three positive and three negative

impulses of 5kV peak, 1.2/50µs,0.5J between all terminals and allterminals and case earth.

Insulation resistanceIEC 60255-5:1977 >100MΩ when measured at

500V dc

Electrical environment

DC supply interruptionIEC 60255-11:1979 10ms interruption in the auxiliary

supply under normal operatingconditions, without de-energising.

High frequency disturbanceIEC 60255-22-1:1988 Class III 2.5kV peak between independent

circuits and between independentcircuits and case earth.

1.0kV peak across terminals of thesame circuit.

Electrostatic dischargeIEC 60255-22-2:1996 Class 3 8.0kV – discharge in air with cover

in place

6.0kV – contact discharge withcover removed.

Fast transient disturbanceIEC 60255-22-4:1992 Class IV 4.0kV, 2.5kHz applied directly to

auxiliary supply

4.0kV, 2.5kHz applied directly toall inputs

Radio frequency interferenceEMC compliances Compliance to the European89/336/EEC Commission Directive on EMC isEN50081-2:1994 claimed via the TechnicalEN50082-2:1995 Construction File route.

Generic Standards were used toestablish conformity.

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Atmospheric environment

TemperatureIEC 60255-6:1988 Storage and transit –25°C to +70°C

Operating –25°C to +55°C

IEC 60068-2-1:1990 Cold

IEC 60068-2-2:1974 Dry Heat

Humidity

IEC 60068-2-3:1969 56 days at 93% RH and 40°C

Enclosure protectionIEC 60529:1989 IP50 (dust protected)

Mechanical environment

VibrationIEC 60255-21-1:1988 Response Class 1

SeismicIEC 60255-21-3:1993 Class 1

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Table 1. Standard output contact case terminal connections

Terminal LFZP 111, 112, 113, 114(Note 1) LFZP 121, 122, 123 LFZP 131,132 LFZP 151

29-31 RIA 97Y RIA 97Y RIA 97Y RIA 97Y

29-33 VTS 97X VTS 97X Def Trip 67N VTS 97X

29-35 Dist Trip 21 Z Z1 Dist Trip 21 Trip 94T

37-39 Trip A 94A Trip 94T Trip 94T Trip 94T

41-43 Trip B 94B Trip 94T Trip 94T Trip 94T

45-47 Trip C 94C Trip 94T Trip 94T Trip 94T

49-51 Signal Send 85X Signal Send 85X Signal Send 85X Any Trip 94

53-55 SOTF 98 SOTF 98 SOTF 98 Start 99

30-32 Time delayed 21/67N(T) Z1X + Z1Y(T) Z1X/Z1Y(T) Z1X + Z1Y + Z2(T) Z1X/Z1Y/Z2(T) (Note 2)

30-34 DEF Trip 67N Z2(T) Z2(T) Z3(T) Z3(T) (Note 3)

30-36 Aided Trip 94Y Z3(T) Z3(T) Def(T) 67N(T)

38-40 Trip A 94A Aided Trip 94Y Aided Trip 94Y

42-44 Trip B 94B Trip 94T Any Trip 94

46-48 Trip C 94C Any Trip 94 Signal Stop 85Y (Note 4)

50-52 Bar 96 Bar 96 Bar 96

54-56 Start 99 Start 99 Start 99

57-59 Trip A 94A

57-61 Trip B 94B

57-63 Trip C 94C

65-67 Trip A 94A

69-71 Trip B 94B

73-75 Trip C 94C

77-79 Any Trip 94

81-83 PSB 95

Notes:1. When 3 phase tripping scheme is used,

94A, 94B, 94C and 94 all respond as 94T.

2. Z1X/Z1Y(T) in LFZP 132.

3. Z2(T) in LFZP 132.

4. Trip 94T in LFZP 132.

Key to contact functions.

97Y Relay inoperative alarm. 94Y Aided trip.

97X Voltage transformer supervision 94 Any trip

95 Power swing blocking. 94A Trip pole A of breaker.

21 Distance trip. 94B Trip pole B of breaker.

67N DEF trip. 94C Trip pole C of breaker.

98 Switch on to fault trip. 94T Trip all poles of breaker.

Z1 Zone 1 trip. 96 Block autoreclose.

Z1X(T) Zone 1X time delay trip. 85X Signal send.

Z1Y(T) Zone 1Y time delay trip. 85Y Signal stop.

Z2(T) Zone 2 time delay trip. 99 DEF element operated (forward or reverse)

21/67N(T) Any time delay trip.

or any Zone 1, 2 or 3 element.

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Figure 15a: Arrangement and outline: Optimho panel mounting vertical

Figure 15b: Arrangement and outline: Optimho panel mounting horizontal

T.B.

T.B.

T.B.

25 way 'D' connector detail

14

13

25

1

Terminal block detail

2

27

28 28 way maxEach way accepting:-

2–M4 Ring terminalsor2–4,8 x 0,8Snap-on terminalsor1– Ring+1– Snap-on terminal

1

414.00

177.00

Hingedpanel

Rear view

25 way 'D'connector

Power supplyM4 earth

connections

BoardRef 1234567

89101112137oror

Description

Opto isolatorOutput relayOutput relayOutput relayAssy fault locator module3 Zone gnd fault quadSee below

Level detectorDirectional earth fault1 Zone offset lenticularProcessorAC input 2AC input 12 Zone mho ph & gnd1 Zone mho reversibleZone 3 ph (2 channel)

Board No.

ZJ0133ZJ0140 003ZJ0140 001ZJ0140 002GJ0277 000ZJ0132

ZJ0136ZJ0139ZJ0131ZJ0138ZJ0135ZJ0134ZJ0130ZJ0146ZJ0129

1234

Input/Output

Processing

ACinput

Front view

1213

2956

5784

411.00 362.60

24.20

159.00

168.00

Panel cut-out detail

4 HolesØ4,4

10.00

312.00

32.00

157.00

Bottom view

Front view

1110

9 7 58 6

Ribbon cable


14

13 25

1


2

27 28

28 way maxEach way accepting:-2–M4 Ring terminalsor2–4,8 x 0,8Snap-on terminalsor1– Ring+1– Snap-on terminal

1

T.B. T. B. T. B.

414.00

177.00(4U)

Hinged panel

Front view

32.00 312.00

10.00

157.00

Side view

Rear view

25 way 'D'connector

Power supply

M4 earth connection

BoardRef 123456789

101112

137oror

Description

Opto isolatorOutput relayOutput relayOutput relayAssy fault locator module3 Zone gnd fault quadSee belowLevel detectorDirectional earth fault1 Zone offset lenticularProcessorAC input 2

AC input 12 Zone mho ph & gnd1 Zone mho reversibleZone 3 ph (2 channel)

Board No.

ZJ0133ZJ0140 003ZJ0140 001ZJ0140 002GJ0277 000ZJ0132

ZJ0136ZJ0139ZJ0131ZJ0138ZJ0135

ZJ0134ZJ0130ZJ0146ZJ0129

1 2 3 4

Input/Output

Processing ACInput

Front view (panel removed)

567891011

12

13 29

56

57

84

411.00362.6024.20

159.00 168.00

Panel cut-out detail

4 Holes Ø4,4

Ribboncable

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Figure 15c: Arrangement and outline: Optimho rack mounting

Figure 16: Outline - external component box


14

13 25

1


2

27 28

28 way maxEach way accepting:-2–M4 Ring terminals

or2–4,8 x 0,8Snap-on terminalsor1– Ring+1– Snap-on terminal

1

T.B. T. B. T. B.

483.00

465.10

177.00(4U)

Hinged panel Front view

101.60

37.70

34.00 312.00

10.00

157.00

Side view

Fixing slot10,6 long x 7 wide

1 2 3 4

Input/Output

Processing ACinput

Front view (panel removed) Rear view

25 way 'D'connector

Power supplyM4 earth connection

BoardRef 123456

789

101112137oror

Description

Opto isolatorOutput relayOutput relayOutput relayAssy fault locator module3 Zone gnd fault quad

See belowLevel detectorDirectional earth fault1 Zone offset lenticularProcessorAC input 2AC input 12 Zone mho ph & gnd1 Zone mho reversibleZone 3 ph (2 channel)

Board No.

ZJ0133ZJ0140 003ZJ0140 001ZJ0140 002GJ0277 000ZJ0132

ZJ0136ZJ0139ZJ0165ZJ0138ZJ0135ZJ0134ZJ0130ZJ0146ZJ0129

567891011

12

13

28 way maxEach way accepting:2 - M4 ring terminalsor2 - 4,8 x 0,8 Snap-on terminalsor1 - Ring + 1 - Snap-on terminal

M4 earth connection

155

2

27 28

Perforated cover

Channel used whenmounted in Midosscheme. (See note)

120M4 tapped panel fixing holesscrews not provided10

121

15

36.3

Terminal screws: M4 x 8 brass cheese head

with lockwashers are provided

Note: Where the box is to be fitted into aMidos scheme it should be positionedbetween relays, not at a tier end.

Rack mounting schemes require theaddition of joining strips and spacers.

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Cases

The relay is housed in a multi-module Midos case suitable for rackor panel mounting, as shown inFigure 15.

Weight: 15kg.

Other InformationAn LFZP accessory kit is available tofacilitate commissioning and test.

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Information Required with Order

LFZP model required (see SummaryChart page 3)

Whether DEF required (if optionalfor model selected)

Whether fault location required(if optional for model selected)

Nominal current rating In: 1A or 5A

Frequency f n: 50Hz or 60Hz

Voltage of dc supply Vx(1):48/54V, 110/125V or 220/250V

Voltage of dc supply Vx(2):48/54V, 110/125V or 220/250V

Mounting arrangements: rack, panelhorizontal, panel vertical, semi

projectionWhether the block auto-reclosecontact 96–1 is to be a normally-open or normally-closed contact

Whether the signal send contact85X-1 is to be a normally-open ornormally-closed contact

Advice is available when theinformation requested above isdifficult to specify

Requests for advice should include:– current and voltage transformer

ratios

– positive and zero sequenceimpedances of the protectedfeeder or full details of the feederlengths and construction

– source impedances or fault levelsfor both minimum and maximumplant conditions

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Service Manual R5911DLFZP 11x Chapter 1

Page 1 of 89

Section 1. GENERAL INTRODUCTION

For the protection of high voltage transmission lines and underground cables, aselection of four Optimho distance models are available in order to provide a widerange of relay characteristics and options. Three models are for the protection of overhead transmission lines, two with 18 comparators and up to five zones of protection and one with 12 comparators and up to four zones of protection. The fourthmodel is for the protection of underground cables, with 18 comparators and up to fivezones of protection. All models are provided with single and three phase tripping.

Section 2. RELAY CHARACTERISTIC

The correct relay model selection for the preferred relay characteristics and options isshown on the Selection Chart in the form of a flow-chart, which clearly identifies therelay type reference and the optional facilities that are available. All models areprovided with Power Swing Blocking and Voltage Transformer Supervision, exceptmodel LFZP114, which is provided with Voltage Transformer Supervision only.

Section 3. LFZP111 MODEL (18 COMPARATORS)

It is a general purpose relay, normally recommended for the protection of any lengthtransmission line, where the values of arc-resistance and tower footing resistancerequired to be measured are outside the reach of the mho characteristic.

As shown in Figure 1, this relay has partially cross-polarised shaped mhocharacteristics for the Zone 1 and Zone 2 phase units. This type of characteristic has a'shield' shape when plotted on the impedance plane, exhibiting a strong resistiveexpansion under fault conditions for tolerance of arc-resistance. A digitally generatedsynchronous memory system is used for partial polarisation on three phase faults, toprovide similar strong resistive expansion and to ensure directional response forclose-up faults.

The Zone 1 and Zone 2 earth fault units have quadrilateral characteristics, withindependent settings for reach at the relay characteristic angle and resistive coverage.

The quadrilateral characteristic gives extra tolerance to the measurement of highresistance faults, where the expansion of the mho shielded characteristic may be foundinadequate.

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Page 2 of 89

Z3'

Z1

Z1X

Z1Y

Z2

Z3

X

X

Z2

Z1Y

Z1X

Z1

Z3'

(a) WITH OFFSET ZONE 3

(b) WITH REVERSE ZONE 3

Z2

Z1Y

Z1X

Z1

Z3'

X

R

R

X

Z3'

Z1

Z1Y

Z2

Z3

Z1X

PHASE FAULTS GROUND FAULTS

PHASE FAULTS GROUND FAULTS

Figure 1 LFZP 111 Relay characteristics

8/9/2019 LFZP11x_R5911D



Page 3 of 89

To avoid any problem of overreach or underreach on resistive earth faults when thereis an infeed to the fault from a remote source, the reactance line of the Zone 1quadrilateral automatically tilts to compensate for the pre-fault power flow. The Zone 1quadrilaterals are inhibited for double phase to earth faults to eliminate overreach,

tripping being performed via the phase fault units which measure accurately underthese conditions.

The Zone 3 units for phase faults have offset lenticular characteristics which permit therelay to be applied to long heavily loaded transmission lines without encroachmentinto the load impedance. It has a variable aspect ratio, including an offset circularsetting.

For earth faults, the Zone 3 units are offset quadrilaterals similar in design to thequadrilaterals used for Zone 1 and Zone 2. In the scheme, the facility is provided for

the Zone 3 units to be set directionally in the reverse direction for use in the Blockingschemes or in the Permissive Overreach scheme with Weak Infeed.

As an alternative, the earth fault units are provided with mho comparators for Zone 1and Zone 2 and offset lenticular for Zone 3. The choice of relay characteristics beingperformed in the relay menu.

Selection of the quadrilateral characteristic automatically disables the mho/lenticularground comparators, which are only automatically enabled if a failure occurs in thequadrilateral comparators. Thus, the quadrilateral comparators are backed up by the

mho/lenticular comparators. This back-up feature is not available when the selection ismade of mho/lenticular for earth faults.

Section 4. LFZP112 MODEL (18 C0MPARATORS)

This relay is recommended for the protection of medium and long, transmission linesincluding heavily loaded lines, where load encroachment is to be avoided, as shownin Figure 2, this relay has partially cross-polarised shaped mho characteristics for theZone 1 and Zone 2 units. This type of characteristics has a 'shield' shape when plottedon the impedance plane, exhibiting a strong resistive expansion under fault conditionsfor tolerance of arc-resistance.

A digitally generated synchronous memory system is used for partial polarisation onthree phase faults, to provide similar strong resistive expansion and to ensure correctdirectional response for close-up faults.

The Zone 3 units have offset lenticular characteristics, which permit the relay to beapplied to long transmission lines. The lenticular shape has a variable aspect ratio,including an offset circular setting. The Zone 3 may also be set as a reverse lookingshield characteristic for use in the Blocking schemes or for use in the PermissiveOverreach Scheme with Weak Infeed.

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Section 5. LFZP114 MODEL ( 12 COMPARATOR)

It is a cost effective relay recommended for use when the application does not requirea response to faults in the reverse direction. The application of this relay does notextend to busbar back-up and it has no facilities for use in schemes requiring WeakInfeed, Blocking or Power Swing Blocking features.

As shown in Figure 3, this relay has partially cross-polarised shaped mhocharacteristics for Zone 1 and Zone 2 units, which have a 'shield' shape when plottedon the impedance plane, exhibiting strong resistive expansion under fault conditionsfor tolerance of arc-resistance. A digitally generated synchronous memory system isused for partial polarisation on three phase faults, to provide similar strong resistiveexpansion and ensure correct directional response for close-up faults.

Application possibilities without the optional Directional Earth Fault protection includesthe use of phase selector for the Phase comparison scheme P10 to allow single poletripping. Also, with Zone 1 disabled, the relay can be used for back-up protection of shunt reactors, or with the two zones enabled for the protection of power transformersand transformer feeders.

Section 6. LFZP113 MODEL (18 COMPARATORS)

This relay is intended for protection of underground cables feeders and, as shown in

Figure 4, has partially cross-polarised shaped mho characteristics for Zone 1 andZone 2. The relay has a lower minimum impedance setting to cater for the generallylower impedance of cables per unit length and an extended range of residualcompensation setting angles. The Zone 3 has an offset lenticular characteristic with analternative setting for a reverse 'shield' mho characteristic. Directional Earth Faultprotection is available for this model for hybrid systems where the characterisitcs of theoverhead sections dominate. The Fault Locator option is available for this version,primarily for metering purposes (see section 4.5.8 in chapter 2), as its accuracy forpower systems containing cable sections can not be guaranteed.

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Page 5 of 89

R

Z3'

Z1

Z1X

Z1Y

Z2

Z3

X

X

Z2

Z1Y

Z1X

Z1

Z3'

R

PHASE AND GROUND FAULTS





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Page 6 of 89

Z2

Z1Y

Z1X

Z1


R

X


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Page 7 of 89

R

Z3'

Z1

Z1X

Z1Y

Z2

Z3

X

X

Z2

Z1Y

Z1X

Z1

Z3'

R






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Page 8 of 89

Section 7. DIRECTIONAL EARTH FAULTS

Available as an option on LFZP111, 112, 113 and 114, this additional feature asshown in Figure 5 offers instantaneous and time delayed tripping at selectable currentlevels. A choice of an aided tripping scheme, either permissive overreach or blockingis also provided, sharing the same signalling channel as the distance scheme.

When required to co-ordinate with the earth fault distance time delayed zones, theDirectional Earth Fault protection should be set to definite time delayed tripping.However, if co-ordination with the earth fault distance is not required, for example, theearth fault distance time delayed zones are disabled, a choice may be made between8 inverse overcurrent curves.

With the directional earth fault protection fitted and the distance time delayed earth

fault elements disabled, the relay can be used for phase fault distance plus directionalearth fault protection, an arrangement common in many parts of the world. The Zone1 earth fault protection is retained to give independent earth fault protection for faultswithin the protected section. To prevent any possibility of overreach caused by mutualinductance with a parallel line earthed at both ends, the residual compensation maybe set to zero.

The directional element has an in-built choice of polarising signals, which can benegative sequence voltage, zero sequence current, zero sequence voltage and dualzero sequence current and voltage. The negative sequence voltage polarising is

particularly valuable, because it is unaffected by mutual induction from paralleltransmission circuits. Zero sequence voltage polarising is included for compatibilitywith other protection relays. The operating quantity of the directional element caneither be zero sequence current or negative sequence current depending on themethod of polarising the directional element. Thus, with negative sequence voltagepolarisation, the operating quantity is negative sequence current, whereas for zerosequence voltage and/or zero sequence current polarisation, the operating quantity iszero sequence current.

In the scheme, the non-directional earth fault element operates on zero sequencecurrent, irrespective of the method of polarising the directional element. Whennegative sequence voltage polarising is selected, an automatic check is made for thepresence of negative sequence fault current, since zero sequence current can beinduced by a fault in a parallel line.

The sensitivity of the forward looking directional element used in the aided schemes isbased on DEF.F and CRX only. The DEF Forward comparator can be enabled byeither low set or high set (LDLSID or LDHSID) level detectors. DEF reverse sensitivity isbased on the DEF LOWEST (LDLSID).

To guard against incorrect tripping caused by magnetizing inrush currents when

in-zone power transformers are present, a selectable magnetizing inrush guard featureis fitted.

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Page 9 of 89

A

B

DEF F

DEF T BU

DEF T BU

DEF F

DEF R

DEF R

DEF R

DEF R

DEF F

DEF T BU

DEF T BU

DEF F

B

A

PERMISSIVE OVERREACH SCHEME

BLOCKING SCHEME

Figure 5 Simplified representation of scheme

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Page 10 of 897.1 Negative sequence voltage polarisation

It is customary for directional earth fault relays to be operated by zero sequencequantities. However, in multiple earthed systems, where the transmission lines areoperated in parallel, strung on the same tower or on adjacent towers, the circuits are

exposed to electromagnetic induction under earth fault conditions.

In power systems, the zero sequence mutual impedance between parallel circuits ishigh, whereas the positive and negative mutual impedance is low. Consequently, zerosequence current and voltage may be induced in a closed loop of a network by zerosequence currents in an adjacent faulted line, even a line of different voltage, andcause maloperation of directional earth fault relays.

Both zero sequence and negative sequence components are produced by the earthfault, and it is possible therefore to use negative sequence components instead of the

customary zero sequence components to operate the directional element of an earthfault relay, even though the overcurrent element is still operated by zero sequencecurrent.

The directional units of the DEF scheme are provided with this option and the use of negative sequence voltage polarisation is recommended for the following applications:

a) Parallel lines with galvanic isolation but with high mutual coupling, wheremaloperation of directional earth fault relays supplied with zero sequencecomponents has been experienced.

b) Parallel lines where the combination of source and line impedance for adouble phase to earth fault on one line, causes the positive and negativesequence currents in the healthy line to flow in one direction and the zerosequence current in the opposite direction. Thus, resulting in maloperationof zero sequence polarised DEF schemes operating in the PermissiveOverreach mode and sharing with the distance scheme, a commonsignalling channel.

Section 8. SCHEMES AVAILABLE

With the compliment of a signalling channel, models LFZP111, LFZP112 and LFZP113have a selection of twelve schemes, whereas model LFZP114 has a choice of six. Eachbeing suitable for either three phase or single/three phase tripping. The schemesavailable are:

MODELS LFZP111, LFZP112 AND LFZP113

• BASIC DISTANCE Basic Distance

• Z1 EXTENSION Zone 1 Extension

• PUR Permissive Underreach

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• PUR UNBLOCK Unblocking Permissive Underreach

• POR 1 Permissive Overreach

• POR 1 UNBLOCK Unblocking Permissive Overreach

• POR 2 Permissive Overreach with Zone 3 Reversed Reach and Weak Infeed

Echo


with Zone 3 Reversed Reach andWeak Infeed Echo

• POR 2 WI TRIP Permissive Overreach with Zone 3 Reversed Reach and Weak Infeed

Echo and trip

• POR 2 WI TRIP UNBLOCK Unblocking Permissive Overreachwith Zone 3 Reversed Reach andWeak Infeed Echo and trip

• BLOCKING

• BLOCKING 2

MODEL LFZP114

• BASIC Basic Distance

• Z1 EXTENSION Zone 1 extension•

• PUR Permissive Underreach

• PUR UNBLOCK Unblocking Permissive Underreach

• POR 1 Permissive Overreach


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SECTION 9. TRANSMISSION LINES

9.1 Short transmission lines

The coverage of high values of arc-resistance and tower footing resistance will usuallybe a problem for the mho characteristic, but one that can often be solved by the use of the quadrilateral characteristic. There is, however, a limitation to the amount of coverage that a quadrilateral characteristic can achieve, in terms of the length of lineto be protected and where those values fall short of the desired values, as in the caseof extreme high resistive earth faults, the quadrilateral characteristic can becomplemented with the Directional Earth Fault Scheme.

With short transmission lines, load encroachment problems are not common and themho characteristic will generally be found satisfactory for phase faults. For lines shorterthan 10km, overreaching schemes, with independent Zone 1 are invariably more

suitable than underreaching schemes. Also, parallel lines are frequent and thepossibility of current reversals, when the overreaching Zone 2 units are set to morethan 150% of the protected line length, needs to be considered for selection of theappropriate distance scheme.

9.2 Long transmission lines

Load impedance encroachment into the operating characteristic of the distance relaysis usually the main consideration. This is a three phase balanced condition, whichinvariably affects the Zone 3 reach of the distance relay and can be solved by the use

of the lenticular characteristic with a variable aspect ratio.

With long transmission lines, the diameter of the mho circle is sufficiently large tocover high values of arc resistance along the R axis of the impedance diagram. Thus,the mho characteristic, which is faster and simpler to produce, is invariablyrecommended for the protection of phase and earth faults.

When the transmission lines are not provided with earth wires and extreme highvalues of tower footing and arc resistance, well outside the reach of the mhocharacteristic, need to be covered, the distance relays can be complemented with the

Directional Earth Fault Scheme.

Section 10. UNDERGROUND CABLES

Underground cables differ from overhead lines in that their zero sequence impedanceangle can be vastly different from the positive sequence impedance angle. This angledifference between the cable impedances can cause large errors in the measurementof the earth fault units if the relay residual compensation is based on scalarimpedances only. To ensure correct measurement under earth fault conditions, therelay needs to be compensated with both residual and a angular compensation, so

that the measurement is made along the earth loop impedance and not the positivesequence impedance of the cable. These two methods of compensation are providedin the Optimho relay.

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Section 11. CHOICE OF ZONE 1 IMPEDANCE REACH

Although in most applications the reach accuracy of the relay distance comparators is± 5%, greater errors can occur as a result of voltage and current transformer errorsand inaccuracies in line data from which the relay settings are calculated. To preventthe possibility of relays tripping instantaneously for faults in the next line, it is usualpractice to set the Zone 1 reach of the relay to 80% of the protected line section andrely on Zone 2 to cover the remaining 20% of the line. With a signal aided distancescheme arrangement, the Zone 2 distance comparators could provide fast tripping atboth ends of the line for end zone faults.Note Z2 must be set greater than or equal to Z1 when the Quadrilateral characteristicis required.

Section 12. ZONE 1 EXTENSION

When no signalling channel is available and high speed auto-reclose needs to beused, the relay can be set in the Zone 1 extension mode and ensure that the circuitbreakers at the two ends of the line open instantaneously. If the Zone 1 extensionmode is used, it is usual practice to set the Zone 1 extension to 120% of the protectedline length. In Optimho, this is done via the Z1X settings.Note Z2 must be set greater than or equal to Z1X when the Quadrilateralcharacteristic is required.

Section 13. REACH-STEPPED ZONES Z1X AND Z1Y

To cater for the possibility that more than three zones of protection may be required,the relay is provided with the option of one or two additional reach-stepped zones,which are obtained via the Zone 1 comparators by extending their reach from Zone 1to Z1X and/or Z1Y after suitable time delays. The two timers are started by Zone 2and Zone 3 comparators.


As a general rule, the Zone 2 impedance reach is set to cover the protected line plus50% of the shortest adjacent line. The reasoning behind the value of 50% is that Zone2 should be able to cover at least 20% of the adjacent line, even in the presence of typical additional infeed at the remote terminal of the protected line.

One case of additional infeed at the remote terminal occurs when the protected line isparalleled by another line. When a fault occurs in the adjacent line, approximatelyequal currents will flow in each of the parallel lines. The relay on the protected linelooking towards the fault will see an impedance which will be the sum of the protectedline impedance, plus twice the impedance of the adjacent line to the fault. If the Zone2 reach is set to cover 50% of the adjacent line impedance, then in this parallel infeedcase, Zone 2 will effectively cover 25% of the adjacent line.

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Page 14 of 89In most situations, if the relay reaches 20% into the adjacent line, then faults at theremote terminal of the protected line will be well within Zone 2 reach and so fastoperation of the Zone 2 comparators will be achieved. This is important if signal aidedtripping schemes are used.

In some situations where the protected line is long and the adjacent line is short, thena 50% reach into the adjacent line will only be a very small overreach of the protectedline. If the protected line is paralleled by another line, then it may be that the zerosequence mutual coupling between the two lines will be sufficient to prevent the Zone2 comparators from seeing an earth fault at the remote terminal of the line until theremote circuit breaker trips, preventing earth fault current flowing in the healthyparallel circuit. In such a case, the Zone 2 setting may need to be increased slightly, toavoid sequential or time delayed clearance of the fault at the terminal remote from thefault.

In a parallel line situation, a fault on one line which is cleared sequentially can causea fault current reversal in the healthy line. If the Zone 2 settings are greater than 150%of the protected line impedance and the Permissive Overreach, Unblocking orBlocking scheme is used, then a fault current reversal in the healthy circuit could causethat circuit to be incorrectly tripped unless special steps are taken. The PermissiveOverreach, the Unblocking and the Blocking schemes have been designed withcurrent reversal guards to prevent such maloperations. The operation of these currentreversal guards is explained in detail later, when considering some logic timersettings. It is also recommended that Z2 reach is set such that it cannot see through astar-delta transformer located at the remote end of the line.


The Zone 3 forward reach should normally be set to 1.2 times the sum of the protectedline impedance and the impedance of the longest adjacent line in order to provide anoverall time delayed back-up protection. The reverse Zone 3 offset provides back-upprotection for the busbars behind the relay and would typically be set to 25% of theZone 1 setting for short transmission lines (up to 30km) and 10% for long transmissionlines.

When the Blocking or Permissive Overreach with Weak Infeed scheme is being used,Zone 3 is required to provide a blocking function when it operates without Zone 2 toprevent the protection scheme operating for external faults. The reverse Zone 3 reachin this case must be set to reach further than Zone 2 of the relay at the opposite end of the line. It must also ensure that any resistive faults behind the relay that are seen byZone 2 of the remote end relay are also seen by the Zone 3 of the local relay, toprevent tripping of the healthy line for external faults. As a general guide for the aboveapplications, it is recommended that the reverse Zone 3 reach be set directionally inthe reverse direction to the same value as the Zone 2 setting of the remote end relay.However, if preferred, the blocking scheme Zone 3 reach can also be setnon-directionally with an offset.

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Section 16. POWER SWING BLOCKING (PSB)

The Power Swing Blocking feature can be selected by means of the relay menudisplayed on the LCD indicator to any of the following conditions:

a) Power Swing Blocking feature disabledb) Power Swing Blocking feature set to indication onlyc) Power Swing Blocking feature set to indication plus blocking of any

one or more selected zones.

The inner Power Swing Blocking impedance characteristic is formed by the A-B Zone 3or Zone 2 phase fault characteristic. The additional Power Swing Blocking startercharacteristic Zone 6 is set concentric with the Zone 3 characteristic, as shown inFigure 6a, when it is set in the forward direction as an offset lenticular/mho, but it is

set concentric with the Zone 2 mho characteristic, as shown in Figure 6b when theZone 3 is set reverse looking as a directional mho.

If the power system A-B phase impedance locus enters the operating area of the startercharacteristic, which has an adjustable timer setting of 20-90 milliseconds butnormally set at 50 milliseconds, and takes longer than this value to pass into the faultcharacteristic, then the Power Swing Blocking unit will block the selected zones if theA-B phase impedance does eventually pass into the fault characteristic area.

It is important to note that when the Zone 3 is set forward looking, the PSB unit is

controlled by the Zone 3 characteristic, but when the Zone 3 is set reverse looking, thePSB unit is controlled by the Zone 2 characteristic. The purpose of the reverse lookingZone 3 in the blocking scheme being simply to control the signal transmission and inthe Permissive Overreach scheme the Weak Infeed and current reversal guard logic.The reversed looking Zone 3 can be selected to provide time delayed back-up if required.

When the Power Swing Blocking feature is used, it is necessary to ensure that thephase fault characteristic will not allow the starting characteristic to encroach into theminimum load impedance. A minimum of 10% safety margin should be maintainedbetween the Power Swing Blocking starter characteristic and the minimum loadimpedance.

The Power Swing Blocking feature is overridden under the following power systemconditions:

a) In the presence of an earth fault or a phase to phase fault when theDEF option is fitted

b) In the presence of an earth fault when the DEF option is not fitted.

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Page 16 of 89

(a) WITH ZONE 3 FORWARD LOOKING

Z3R Z1 Z2 Z3F Z6FZ6R

Z3R Z6R Z1 Z2 Z6F

(b) WITH ZONE 3 REVERSE LOOKING

Figure 6 Power swing blocking relay

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Page 17 of 89

It is important to note that when Power Swing Blocking and DEF are provided with thedistance scheme, but the DEF is not used, it is essential to set the 3Io (low set) currentlevel detector, which is ganged to the I2 current level detector required to override thePower Swing Blocking unit under fault conditions.

The recommended settings for the Power Swing Blocking characteristic Zone 6 forwardand reverse reach can be obtained from the following expressions:

With Zone 3 set looking in forward direction:Zone 6 forward reach = 1.3 x Zone 3 forward reachZone 6 reverse reach = 0.3 x Zone 3 forward reach + Zone 3reverse reach

With Zone 3 set looking in the reverse direction:

Zone 6 forward reach = 1.3 x Zone 2 forward reachZone 6 reverse reach = 0.3 x Zone 2 forward reach

With these impedance settings, the recommended timer setting TZ6 is 50ms.

When a zone is blocked during a power swing the blocking is performed at the ‘input’to the scheme logic, i.e. the scheme logic effectively does not register operation of theblocked zone. As a consequence, all functions derived from the blocked zones, e.g.signal send, start contacts etc. will also be inhabited during the swing condition.

Section 17. RESISTIVE REACH OF QUADRILATERAL CHARACTERISITC

The resistive reach should be set to cover the desired level of earth fault resistance,which would comprise arc-resistance and tower footing resistance. A 10% impedancemargin should be observed between the resistive reach and the minimum loadimpedance.

In addition, to ensure Zone 1 reach accuracy the resistive reach should not be greaterthan 15 times the Zone 1 ground loop reach, for single-point grounded radialdistribution systems. A maximum of 4 times the Zone 1 ground loop reach is

recommended for multiple grounded systems.

17.1 Automatic compensation of quadrilateral reach line angle

For the quadrilateral earth fault characteristic, the phase current is in phase with theresistive axis of the R-X diagram. The reach line for the Zone 1 characteristic is inphase with the residual or neutral current measured (with a -3° droop). Thus, if there isa difference in angle between the measured phase current and neutral current, thenthe Zone 1 reach line will be at a corresponding angle to the resistive axis. Thisfeature ensures that resistive earth faults on a double-end fed loaded system will notresult in underreach or overreach of the relay.

The Zone 2 and Zone 3 reach lines and the Zone 3 offset lines are in phase with theresultant angle of the measured neutral current, plus the relevant phase current.

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A qualitative analysis of the purpose of reach line compensation for Zone1 is given inFigure 7.

Section 18. CHOICE OF ASPECT RATIO

The Zone 3 aspect ratio of the lenticular characteristic will need to be adjusted when itis envisaged that there will be load encroachment problems on the Zone 3 or PowerSwing Blocking starter characteristic for a long line application. The Zone 3 aspectratio a/b should be set so that with the required Zone 3 forward and reverse reachsettings, the Zone 3 characteristic or, if used, the Power Swing Blocking starter has a10% safety margin separating it from the load impedance region.

Section 19. CHOICE OF RELAY CHARACTERISTIC ANGLES

Maximum accuracy and sensitivity is obtained by setting the relay angle THETA Phequal to or to the nearest setting of the line positive sequence angle /ZL1 and THETAN equal to or to the nearest value of /KN.ZL1 where KN is the residual compensationfactor.

Section 20. ZONE TIME DELAY SETTING

The time settings TZ2 and TZ3 determine the time delay from detection of a fault by therelevant zone to the operation of the trip output unit.

The relay operates for the majority of Zone 1 faults within 16-30 milliseconds. TheZone 2 time delay should be set to allow for the longest Zone 1 operating time, or if applicable the longest aided trip time and the circuit breaker operating times.Generally, a Zone 2 time delay setting of 0.2-0.3 seconds is satisfactory, but longertimes may be required if the Zone 2 overlaps slower forms of protection.

Zone 3 is generally intended to provide back-up protection, even if it is being used asa reverse 'looking' blocking element. It may be overlapping other forms of protectionsuch as Inverse Definite Minimum Time overcurrent relays. The Zone 3 time delay will

depend on the system to which the relay is applied, but in any case it will be longerthan the Zone 2 time delay and will typically have a setting of one second.

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BA

R

(a) PREVENTING ZONE - 1 OVERREACH

R F

FRR

A B

jX

B

x

RA

KRF

PRE-FAULTPOWER FLOW

KRF

A

x

B

jX

R

(b) PREVENTING ZONE - 1 UNDERREACH

PRE-FAULTPOWER FLOW

Figure 7 Principle of Zone 1 reach line angular compensation

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Page 20 of 89

Section 21. SWITCH ON TO FAULT TRIPPING FEATURE (SOFT)

This feature is enabled by the scheme logic when the line circuit breaker has beenopen for a certain time. To determine whether the line circuit breaker is open, the relay"looks" for an "All Poles Dead" condition (voltage and level detectors have reset oneach phase). For the case where a busbar VT is used "pole dead" signals will not beproduced, but a normally closed circuit breaker auxiliary contact can be used via anopto-isolator input, to inform the relay that the circuit breaker is open.

For single pole tripping applications, the circuit breaker auxiliary contacts of eachbreaker pole should be wired in series and connected to the relay, so that the relay ismade aware that all three poles of the breaker are open.

The SOTF feature becomes enabled 200 milliseconds or 110 seconds after the relaydetects the local circuit breaker has opened, depending on the setting of an option in

the relay menu display.

In the majority of applications, the SOTF enable timer will be set to 200 milliseconds,so that the feature will be available as soon as possible after the line becomes dead.With this short time setting, the SOTF feature will be enabled during auto-reclose deadtime, so that upon reclosure a SOTF trip is possible. This is usually advantageous formost distance schemes, since a persistent fault at the remote end of a protected linesection can be cleared instantaneously after reclosure of the local breaker, rather thanafter Zone 2 time delay.

When it is desired that a SOTF trip indication is not given after auto-reclosure, or twoshot auto-reclose is used, then the 110 seconds SOTF enable timer option should beused. This will ensure that the SOTF feature could not be enabled during theauto-reclose dead time. If a SOTF trip was allowed to occur on auto-reclosure, thedistance relay would also give a 'block auto-reclose' signal to the auto-reclose relayand any second auto-reclose shot would be prevented.

SOTF tripping is only possible for the initial 250 milliseconds after the circuit breakerclosure. During this time, an instantaneous trip can occur in line with the selectionmade in the relay menu. The three options available are:

a) Tripping via the operation of any distance comparator.

b) Tripping via the operation of any current level detector provided that itscorresponding voltage level detector has not picked up within 20ms.

c) Tripping via the operation of any distance comparator or any current leveldetector provided that its corresponding voltage level detector has notpicked up within 20ms.

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Page 21 of 89With the relay set to give a SOTF trip for any distance comparator operation, then anyfault existing on the protected line, including a close-up three phase bolted fault wouldbe cleared. For the latter fault, where line voltage transformers are used, there wouldbe no memory voltage to allow Zone 1 or Zone 2 distance comparator operation, butZone 3 will operate if set forward looking as it has an offset to cover the busbars.

When the Zone 3 is set reverse looking, as a directional mho, the SOTF should be setto give a trip via any current level detector as the Zone 3 comparators would notoperate for a close-up three phase fault on the protected line. Faults at the remote endof the line will also be cleared instantaneously by a SOTF trip when the local circuitbreaker is closed.

In some situations, it may be possible for the magnetizing inrush current of bankedtransformers at the end of a line or particularly of teed-off transformers, to causetransient operation of the Zone 3 comparators on line energisation, resulting in anincorrect SOTF trip. In such a situation, the SOTF trip option should be chosen, so that

SOTF tripping will only occur when a current level detector picks up without thecorresponding voltage level detector picking up.

Section 22. SELECTION OF SCHEME LOGIC PROGRAMS

With the relay cover off, the distance scheme logic programs are selected by using thekeypad and liquid crystal display on the front of the relay case. Operation of thehorizontal and vertical keys on either side of the centre SET key will gain access intothe relay menu structure and enable the user to set the relay scheme logic and settings.With the relay cover on, access to the keypad is prevented, but it is possible to read

the relay settings and reset the relay via the two through cover push buttons labelled'ACCEPT/READ' and 'RESET'.

Section 23. SCHEME LOGIC APPLICATION GUIDE

23.1 Basic distance

(See Figure 8)

• Generally applied when no auto-reclose is used

• The scheme can be used without a signalling channel

• The scheme is suitable for single circuit and double circuit lines fed from either oneor both ends

• A major disadvantage is that not all faults within a protected section can be clearedinstantaneously

• It can be provided with up to five zones by the use of three independent zones and

two optional reach-stepped zones

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Page 22 of 8923.2 Zone 1 extension

(See Figure 9)

• Generally applied when no signalling channel is available and high speed

auto-reclose is used

• Normally the Zone 1 comparators reach is extended to overreach the remote endof the protected line by the action of the Z1X reach-stepped zone which is set tocover 120% of the protected line length

• After a fault clearance, the auto-reclose relay gives a reset signal to the zoneextension logic so that the Zone 1 comparators fall back to normal Zone 1 reachsetting of 80% of the protected line

On the basis that most overhead line faults are transient in duration, the scheme willallow fast clearance of most faults along the protected line and also those just outsidethe line. Lack of discrimination is generally accepted as reclosure of the circuitbreakers will take place and the power system network restored if the fault wastransient. In the event of a permanent fault, upon reclosure the faulted line will betaken out of service by the distance protection as in the BASIC scheme.

• The scheme would not normally be used for cable circuits, although its use might beconsidered for hybrid circuits

•

It can be provided with up to five zones by the use of three independent zones andtwo reach-stepped zones

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Page 23 of 89

ZONE 2

ZONE 1Y

ZONE 1X

ZONE 1

BA Z

Z

ZONE 1

ZONE 1X

ZONE 1Y

ZONE 2

ZONE 3

Z1,(Z1X),(Z1Y)

TZ2

TZ3

TZ1Y

TZ1X Z1 Z1X

Z1 Z1Y

RELAY A

TRIP A

Z2

Z3

ZONE 3

Z3

Z2

TRIP B

RELAY B

Z1Y Z1

Z1X Z1 TZ1X

TZ1Y

TZ3

TZ2

Z1,(Z1X),(Z1Y)

1 1

1 1

Figure 8 Basic simplified distance scheme logic

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Page 24 of 89

ZONE 2

ZONE 1Y

ZONE 1XZONE 1

BA Z

ZZONE 1

ZONE 1X

ZONE 1Y

ZONE 2

Z1,(Z1X),(Z1Y)

TZ2

TZ3

TZ1Y

TZ1X

Z1 Z1Y

TRIP A

TZ1X

TZ1Y

Z2

Z3

ZONE 3

ZONE 3

RESET Z1 EXT.

Z1 Z1 EXT,Z1X

Z3

Z2

TRIP B

Z1Y Z1

TZ3

TZ2

Z1,(Z1X),(Z1Y)

RESET Z1 EXT.

Z1X,EXT Z1 Z1

Z1 EXT

Z1 EXT

1 1

11

11

Figure 9 Zone 1 Ext. simplified distance scheme logic

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Page 25 of 8923.3 Permissive underreach scheme PUR

(See Figure 10)

• This scheme requires one signalling channel for both relays as channel is keyed by

the underreaching Zone 1 comparators within their Zone 1 reach only

• Provided the underreaching Zone 1 comparators reach 'overlap', fast clearance of faults along the whole of the protected line will be effected

• If a line terminal is open, then fast tripping will only occur for faults within the Zone1 reach of the closed end relay

• If the signalling channel fails, the line relays will still provide BASIC protection

• Fast clearance will not occur for all faults along the protected line if there is little orno infeed at one terminal

• The aided trip logic is performed via the Zone 2 comparators and the signalreceive input

Send logic Z1Permissive trip logic Z2 + CRX

23.4 Permissive schemes unblocking logic

The permissive tripping schemes (both underreach and overreach) used with PowerLine Carrier may be required to transmit the permissive trip signal via a fault in theprotected line. The signal will, therefore, be attenuated or shorted out by the fault. Thisproblem can be alleviated by using a frequency shift communication channel to enablethe permissive tripping scheme to operate in the unblocking mode.

In the normal state, the communication equipment transmits a continuous guard (block)frequency which is automatically changed to the trip (unblock) frequency under faultconditions when the associated distance scheme comparator operates.

The Permissive tripping schemes are converted from the standard to the Unblockingmode by the addition of the Communication receive logic shown in Figure 11. Thislogic requires a permissive trip signal input CRX and a loss of guard signal input LGSfrom the communication equipment.

When a fault occurs on the protected line and the distance scheme comparator thatcontrols the action of the transmitter operates, it causes the Communication equipmentto change the transmitted signal from the guard to the trip frequency, which whenreceived at the remote end produces a CRX1 output in the unblocking

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Page 26 of 89

ZONE 2

ZONE 1Y

ZONE 1X

ZONE 1

BA Z

Z

ZONE 1

ZONE 1X

ZONE 1Y

ZONE 2

CRX

CTX

&

Z1,(Z1X),(Z1Y)

TZ2

TZ3

TZ1Y

TZ1X Z1 Z1X

Z1 Z1Y

RELAY A

TRIP A TRIP B

RELAY B

Z1Y Z1

Z1X Z1 TZ1X

TZ1Y

TZ3

TZ2

Z1,(Z1X),(Z1Y)

&

CTX

CRXSIGNALLING

CHANNEL

Z2

Z3

Z2

Z3

ZONE 3

ZONE 3

Z1 Z1

1 1

1 1

11

Figure 10 PUR Simplified distance scheme logic

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Page 27 of 89

Figure 11 Unblocking communication receive logic for permissive schemes

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Page 28 of 89

communication receive logic. This signal when passed to the distance scheme logicprovides an immediate trip if the associated Zone 2 comparator had operated.In the Permissive Overreach scheme, this condition will also produce output CRX2 topermit tripping via the DEF scheme, if used to complement the distance scheme for

high resistance faults.

In the event of the permissive trip signal being shorted out by an internal fault, both theguard and the trip signals would be lost. Under this condition, the communicationreceive logic will give a permissive trip output via CRX1 for a short period, lasting fromthe time setting of TDW (0-98 milliseconds) to the time setting of T2 (150 milliseconds)after which the PSD line goes high and the permissive distance scheme is disabled.

The time delay of TDW is necessary in order to prevent the possibility of spurioustripping during transient loss of guard signal (set typically to 10 milliseconds). To

activate the scheme, the guard signal must be present for the time of T1 (200ms).

23.5 Permissive Overreach Scheme POR 1

(Forward Looking Zone 3 Figure 12)

• This scheme requires a duplex signalling channel, using one frequency for eachline end as the channel transmission is controlled by the overreaching Zone 2comparators.

• This scheme may be more advantageous than the permissive underreach schemefor the protection of short transmission lines, as the resistive coverage of the Zone 2comparators would be greater than that of the Zone 1 comparators which wouldbe set to a lower ohmic reach.

• To provide high speed tripping when a line terminal is open, a 'signal echofeature' is included in the scheme logic, which is initiated when a line terminalcircuit breaker is open (circuit breaker auxiliary contact initiation). By this means,the permissive overreach scheme is able to provide fast tripping for any fault alongthe whole length of the line.

• To cater for the protection of parallel lines where the Zone 2 comparators are set toreach longer than 150% of the protected line, current reversal guards TP and TDare used in order to prevent the possibility of maloperation on current reversalsproduced by sequential opening of circuit breakers.

• If the signalling channel fails, the permissive overreach scheme will operate in theconventional basic mode.

Send logic Z2

Permissive trip logic Z2 + CRXOpen terminal echo : CB open + CRX

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Page 29 of 89

ZONE 2

ZONE 1Y

ZONE 1X

ZONE 1

BA Z

Z

ZONE 1

ZONE 1X

ZONE 1Y

ZONE 2

CRX

CTX

&Z1,(Z1X),(Z1Y)

TZ2

TZ3

TZ1Y

TZ1X Z1 Z1X

Z1 Z1Y

RELAY A

TRIP A

CTX

CRX

SIGNALLINGCHANNEL

Z2

Z3

ZONE 3

ZONE 3

&&CB

OPEN

Z3

Z2

TRIP B

RELAY B

Z1Y Z1

Z1X Z1 TZ1X

TZ1Y

TZ3

TZ2

Z1,(Z1X),(Z1Y)&

OPEN

CB

1

1

1

1

1 1

Figure 12 POR 1 Simplified distance logic scheme

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Page 30 of 8923.6 Permissive overreach scheme POR 2

(Reverse Looking Zone 3 Figure 13)

• This scheme requires a duplex signalling channel using one frequency for each line

end as the channel transmission is controlled by the overreaching Zone 2comparators

• This scheme may be more advantageous than the permissive underreach schemefor the protection of short transmission lines, as the resistive coverage of the Zone 2comparators would be greater than that of the Zone 1 comparators which would beset to a lower ohmic reach

• To provide high speed tripping when a line terminal is open, a 'signal echo' featureis included in the scheme logic, which is initiated when a line terminal circuitbreaker is open (circuit breaker auxiliary contact initiation). By this means, the

permissive overreach scheme is able to provide fast tripping for any fault along thewhole of the line

• To cater for high speed current reversals in double circuit lines, when both theprotective relays and the circuit breakers are exceptionally fast, the possibility of maloperation, due to the sequential opening of circuit breakers is prevented by theuse of a reversed looking Zone 3

• To allow fast tripping at the sending end, in the event of a weak infeed at theremote end, a weak infeed logic is used to echo the received signal back if the

reversed Zone 3 has not operated.

• If the signalling channel fails, the permissive overreach scheme will operate in theconventional basic mode, except that the Zone 3 is reversed

Send logic Z2Permissive trip logic Z2 + CRXOpen terminal echo : CB Open + CRXWeak infeed echo : No comparator operation + CRX

23.7 Permissive overreach scheme POR 2 WI Trip

(Reverse Looking Zone 3 And Weak Infeed Trip Figure 14)

• This scheme requires a duplex signalling channel using one frequency for each lineend as the channel transmission is controlled by the overreaching Zone 2comparators

• This scheme may be more advantageous than the permissive underreach schemefor the protection of short transmission lines, as the resistive coverage of the Zone 2

comparators which would be greater than that of the Zone 1 comparators whichwould be set to a lower ohmic reach

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Page 31 of 89

ZONE 2

ZONE 1Y

ZONE 1X

ZONE 1

BA Z

Z

ZONE 1

ZONE 1X

ZONE 1Y

ZONE 2

CRX

CTX

Z1,(Z1X),(Z1Y)

TZ2

TZ3

TZ1Y

TZ1X Z1 Z1X

Z1 Z1Y

RELAY A

TRIP A

SIGNALLING

Z2

Z3

ZONE 3

&

Z3

ZONE 3

&

&

OPENCB CB

OPEN

&

&Z3

&

Z3

Z2

CHANNEL

TRIP B

RELAY B

Z1 Z1Y

Z1X Z1 TZ1X

TZ1Y

TZ3

TZ2

Z1,(Z1X),(Z1Y)

CTX

CRX

1 1

11

Figure 13 POR 2 Simplified distance scheme logic with Zone 3 reversed reach and weak infeed echo

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Page 32 of 89

ZONE 2

ZONE 1Y

ZONE 1X

ZONE 1

BA Z

Z

ZONE 1

ZONE 1XZONE 1Y

ZONE 2

CRX

CTX

&

Z1,(Z1X),(Z1Y)

TZ2

TZ3

TZ1Y

TZ1X Z1 Z1X

Z1 Z1Y

RELAY A

TRIP A

CTX

CRX

SIGNALLINGCHANNEL

Z2

Z3

ZONE 3

&

CB

OPEN

ZONE 3

&

&

Z3

LDOV LDOV

Z3

&

&OPEN

CB

&

Z3

Z2

TRIP B

RELAY B

Z1Y Z1

Z1X Z1 TZ1X

TZ1Y

TZ3

TZ2

Z1,(Z1X),(Z1Y)

&

1

1 1

1

Figure 14 POR 2 WI TRIP Simplified distance scheme logic with Zone 3 reversedreach and weak infeed echo and trip

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Page 33 of 89

• To provide a high speed tripping when a line terminal open, a 'signal echo feature' isincluded in the scheme logic which is initiated when a line terminal circuit breaker is open(circuit breaker auxiliary contact initiation). By this means, the permissive overreachscheme is able to provide fast tripping for any fault along the whole length of the protected

line.

• To cater for high speed current reversals in double circuit lines when both theprotective relays and the circuit breakers are exceptionally fast, the possibility of maloperation, due to the sequential opening of circuit breakers, is prevented by theuse of a reverse looking Zone 3.

• To allow fast tripping at the sending end, in the event of a weak infeed at theremote end, a weak infeed logic is used to echo the received signal back, if thereversed Zone 3 has not operated.

• An additional check that a voltage level detector (LDOV) has reset is necessary to

allow tripping at the weak infeed terminal after a short time delay.

• If signalling channel fails, the Permissive Overreach Scheme will operate in theconventional basic mode, except that the Zone 3 is reversed.

Send logic Z2Permissive trip logic Z2 + CRXOpen terminal echo : CB open + CRX

Weak infeed echo : No comparator operation + CRXWeak infeed trip : No comparator operation + LDOV reset + CRX

23.8 Blocking scheme

(See Figure 15)

• This scheme requires only one signalling channel for both relays.

• It uses a reverse looking Zone 3 to send the carrier signal to the remote end toblock the operation of the overreaching Zone 2.

• The advantage of this scheme is that only one carrier frequency is required toinitiate blocking at both line terminals regardless of which terminal detected thefault to be in the reverse direction and that the blocking signal is transmitted over ahealthy line.

• This scheme will provide similar resistive coverage as the permissive overreachscheme.

• If a line terminal is open, fast tripping will still occur for faults along the whole of theprotected line length.

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Page 34 of 89

ZONE 2

ZONE 1Y

ZONE 1X

ZONE 1

BA Z

Z

ZONE 1ZONE 1X

ZONE 1Y

ZONE 2

CRX

CTX

&

Z1,(Z1X),(Z1Y)

TZ2

TZ3

TZ1Y

TZ1X Z1 Z1X

Z1 Z1Y

RELAY A

TRIP A

CTX

CRXSIGNALLING

CHANNEL

Z2

Z3 Z3

Z2

TRIP B

RELAY B

Z1Y Z1

Z1X Z1 TZ1X

TZ1Y

TZ3

TZ2

Z1,(Z1X),(Z1Y)

&

ZONE 3

ZONE 3

&&

1 1

Figure 15 Blocking simplified distance scheme logic

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Page 35 of 89

• If the signalling channel fails, fast tripping will occur for faults along the whole of the protected line, but also for some faults within the next line section.

• If the signalling channel is taken out of service, the blocking scheme will operate in

the conventional basic mode, except that Zone 3 is reversed.

• Fast tripping will still occur at a strong source line end, for faults along the protectedline section, if there is a weak or no infeed at the other end of the protected line.

Send logic : Reverse Z3 + not Z2Trip logic : Z2 + not CRX

23.9 Blocking 2 scheme

(See Figure 15B)

• This scheme requires only one signalling channel for both relays. The use of aduplex channel requires a larger setting on scheme timer TD.

• It uses a reverse looking Zone 3 to send the carrier signal to the remote end toblock the operation of the overreaching Zone 2.

• The advantage of this scheme is that only one carrier frequency is required to

initiate blocking at both line terminals regardless of which terminal detected thefault to be in the reverse direction and that the blocking signal is transmitted over ahealthy line.

• This scheme will provide similar resistive coverage as the permissive overreachscheme.

• If a line terminal is open, fast tripping will still occur for faults along the whole of theprotected line length.

• If the signalling channel fails, fast tripping will occur for faults along the whole of the protected line, but also for some faults within the next line section.

• If the signalling channel is taken out of service, the blocking 2 scheme will operatein the conventional basic mode, except that Zone 3 is reversed.

• Fast tripping will still occur at a strong source line end, for faults along the protectedline section, if there is a weak or no infeed at the other end of the protected line.

• Dual contact arrangement for start/stop control of the signalling channel. Bothcontacts are normally open.

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Page 36 of 89

ZONE 3

ZONE 2ZONE 1Y

ZONE 1X

ZONE 1

BA Z

Z

ZONE 1

ZONE 1X

ZONE 1Y

ZONE 2

ZONE 3

CRX

CTX

START

STOP

&

Z1,(Z1X),(Z1Y)

TZ2

TZ3

TZ1Y

TZ1X Z1 Z1X

Z1 Z1Y

RELAY A

TRIP A TRIP B

RELAY B

Z1Y Z1

Z1X Z1 TZ1X

TZ1Y

TZ3

TZ2

Z1,(Z1X),(Z1Y)

&

STOP

START

CTX

CRX

SIGNALLINGCHANNEL

Z2

Z3

Z2

Z3

1

1 1

1

1

1

Figure 15B Blocking 2 simplified distance scheme logic

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Page 37 of 89

• Signal transmission is maintained at the sending end to ensure security againstmaloperation durring current reversal conditions.

• May be suitable for use with some electro-mechanical relays but some care is

required in determining compatibility and the settings.

Carrier Send logic : Reverse Z3 + not Z2Carrier Stop logic : Z2 + not TDTrip logic : Z2 + not CRX

Section 24. HIGH RESISTANCE EARTH FAULTS

There is a limit to the amount of arc resistance and tower footing resistance that can be

adequately covered by distance relays, since the coverage is limited by the ohmicreach of the distance relay. If extremely high values of ground fault resistance areexpected, then an optional directional comparison earth fault scheme (DEF) with timedelay back-up features can be added to complement the distance scheme.

24.1 DEF permissive overreach scheme

(See Figure 16)

• The DEF and the distance scheme share a common signalling channel, both

operating in the same mode.

• Separate frequencies are needed for each line end, as the signal transmission isinitiated by the forward looking directional earth fault comparator.

• Time delayed back-up protection provided to cover uncleared earth faults, whichcan be set to provide nine different characteristics for co-ordination with other earthfault relays.

• The DEF scheme provides three phase tripping only, but if the distance scheme has

been selected for single and three phase tripping, any single phase to earth faultseen by both the DEF and the distance scheme will result in a single phase trip viathe distance scheme.

Send logic DEF FTrip logic DEF F + CRX

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Page 38 of 89

CRX

CTX

&

T

TRIP A

CTX

CRX

SIGNALLINGCHANNEL

TRIP

AIDED

DEF F

DEFBU TRIP BU TRIP

DEF

DEF F

AIDED

TRIP

TRIP B

T

&

A

B

DEF F

DEF T BU

DEF T BU

DEF F

RELAY A RELAY B

1 1

Figure 16 DEF permissive overreach scheme

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Page 39 of 8924.2 DEF Blocking Scheme

(See Figure 17)

• The DEF and the distance scheme share a common signalling channel, both

operating in the same mode.

• A common single frequency only is needed, as the signal transmission is initiatedby the reverse looking directional earth fault comparator.

• Time delayed back-up protection is provided to cover uncleared ground faults,which can be set to provide nine different characteristics for co-ordination withother ground relays.

• The DEF scheme provides three phase tripping only, but if the distance scheme has

been selected for single and three phase tripping, any single phase to earth fault'seen' by both the DEF and the distance scheme will result in a single phase trip viathe distance scheme.

Send logic DEF RTrip logic DEF F + not CRX

24.3 DEF blocking 2 scheme

(See Figure 17B)

• The DEF and the distance scheme share a common signalling channel, bothoperating in the same mode.

• A common single frequency only is needed, as the signal transmission is initiatedby the non directional level detector (LDLSI0) and/or the reverse looking directionalearth fault comparator (DEF_R) and stopped by the forward looking directionalearth fault comparator (DEF_F). The use of a duplex channel would require largersettings on scheme timers TPG and TDG.

• Time delayed back-up protection is provided to cover uncleared ground faults,which can be set to provide nine different characteristics for co-ordination withother ground relays.

• The DEF scheme provides three phase tripping only, but if the distance scheme hasbeen selected for single and three phase tripping, any single phase to earth fault'seen' by both the DEF and the distance scheme will result in a single phase trip viathe distance scheme.

• Dual contact arrangement for start/stop control of the signalling channel. Both

contacts are normally open.

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Page 40 of 89

CRX

CTX

&

T

TRIP A

CTX

CRXSIGNALLING

CHANNEL

TRIP

AIDED

DEF F

DEFBU TRIP BU TRIP

DEF

DEF F

AIDED

TRIP

TRIP B

T

&

A

B

DEF F

DEF T BU

DEF T BU

DEF F

DEF R

DEF R

DEF R DEF R

1 1

11

Figure 17 DEF blocking scheme

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Page 41 of 89

LDLS1

CRX

CTX

START

STOP

&

TRIP A TRIP B

&

STOP

START

CTX

CRX

SIGNALLINGCHANNEL

O

DEF T BU

DEF F

DEF R

A

B

DEF R

DEF F

DEF T BU

OLDLS1

OLDLS1 LDLS1O

AIDEDTRIP TRIP

AIDED

DEF F DEF F

DEFBU TRIP

DEFBU TRIP

T T

1

1

1

1

1

1

Figure 17B DEF 2 blocking scheme

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Page 42 of 89

• Signal transmission is maintained at the sending end to ensure security againstmaloperation during current reversal conditions

• May be suitable for use with some electro-mechanical relays but some care is

required in determining compatibility and the settings.

Carrier Send logic : LDLSI0Carrier Stop logic : DEF_F + not TDGTrip logic : DEF_F + not CRX

Section 25. CURRENT REVERSAL LOGIC

In double circuit lines, the fault current distribution changes when circuit breakers open

sequentially to clear the fault. With one terminal line open, the change in currentdistribution can cause the directionally looking distance comparators to see the fault inthe opposite direction to the direction in which the fault was initially detected. This cancause the Permissive Overreach, the Blocking and the DEF schemes to trip the healthyline due to the contact race between one set of directional comparators resetting andthe other set operating.

A typical system configuration that could result in current reversals is shown in Figure18 for a fault on line L1 close to circuit breaker B with all the circuit breakers closed,which after circuit breaker B has opened, causes the direction of current flow in line L2

to be reversed.

25.1 Permissive overreach scheme POR 1

(See forward looking Zone 3 Figure 19)

The current reversal guard incorporated in the scheme logic is initiated when a healthyline relay receives a permissive trip signal, but does not have a Zone 2 comparatoroperated. A delay on pick up TP in the current reversal guard timer is necessary inorder to allow time for the Zone 2 comparators to operate, if they are going to do so

for an internal fault.

Recommended TP setting = 30ms - minimum signalling channel operating time ms.

Once the current reversal guard timer has operated, the healthy line relay D transfertripping is inhibited. The reset of the guard timer is initiated by either the loss of thepermissive trip signal or by the operation of the Zone 2 comparators. A time delay TDfor the reset of the current reversal guard timer is required in case the Zone 2comparator at end D operate before the permissive trip signal from the relay at end Chas reset, which could cause the relays on the healthy line to maloperate.

Recommended TD setting = maximum signalling channel reset time ms + 35ms.

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NOTE HOW AFTER CIRCUIT BREAKER B ON LINE L1 OPENS

A B

C

FAULT

THE DIRECTION OF CURRENT FLOW IN LINE L2 IS REVERSED.

WEAKSOURCE

STRONGSOURCE

L1

L2 D

DL2

L1

FAULT

C

BA

Figure 18 Current reversal in double circuit lines

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Page 45 of 89

The current reversal sequence diagram shows how the relays in the healthy line areprevented from maloperation due to the sequential opening of the circuit breakers inthe faulted line and the instance in the cycle at which it takes place. After currentreversal, the Zone 2 comparators of the relay at D will initiate the transmission of the

permissive trip signal from substation D to substation C and the relay at C will besimilarly prevented from maloperation. The relays at both D and C substations beingenabled once again when the faulted line is isolated and the current reversal guardtimer setting TD has expired.

25.2 Permissive overreach schemes POR 2 and POR 2 WI trip

(Reversed looking Zone 3 Figure 20)

The current reversal guard incorporated in the scheme logic is initiated when the

reversed looking Zone 3 comparators operate on a healthy line. No time delay TP isnecessary with this scheme as the Zone 3 comparators will operate well before thearrival of the permissive trip signal initiated by the Zone 2 comparators at the oppositeend of the line.

Once the reversed looking Zone 3 comparators have operated, the relay D transfertripping is inhibited. The reset of the current reversal guard timer is initiated when thereversed looking Zone 3 resets. A time delay TD is required in case the Zone 2comparators at end D operate before the permissive trip signal from the relay at end Chas reset, which could cause the relays at D to maloperate.


The current reversal sequence diagram shows how the relays in the healthy line areprevented from maloperation due to the sequential opening of the circuit breakers inthe faulted line and the instance in the cycle at which it takes place. After currentreversal, the reversed looking Zone 3 comparators at substation C will operate toinhibit the relays at substation C before the permissive trip signal is received fromsubstation D. The relays at D and C substations being enabled once again, when thefaulted line is isolated and the current reversal guard timer setting TD has expired.

25.3 Blocking scheme

(See Figure 21)

The current reversal guard incorporated in the scheme logic is initiated when theblocking signal transmission started by the reversed looking Zone 3 comparators isreceived on a healthy line to inhibit the aided trip. A time delay TP is needed with theZone 2 comparators in order to allow for the blocking signal transmission time to bereceived in case the reversed looking Zone 3 comparators had operated for anexternal fault.

Recommended TP setting = maximum signalling channel operating time ms + 16ms.

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Page 46 of 89

&

AIDEDTRIP

OTD&

CTX

CRX

Z2

Z3R

CURRENT REVERSAL SYSTEM CONFIGURATION

CURRENT REVERSAL LOGIC

CURRENTREVERSAL

Z3RD

RESET

TD

RESET

CTX

RESETZ2C RESET

TIME

RELAY DENABLED

RELAY DDISABLED

FAULTINCEPTION

CURRENT REVERSAL SEQUENCE DIAGRAM

B

D

C

Z1B

Z3RD

Z2C

CTX

CB OPERATING TIME

R

EL

A

Y

A B

C D DC

BA

FAULT FAULT

L

O

C

A

T

I

O

N

Z2

&

Figure 20 Permissive overreach transfer trip POR 2 current reversal scheme logicreversed looking Zone 3

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Page 47 of 89

&

AIDEDTRIP

0

Td

&CTX

COS

Z2

CRX



CURRENTREVERSAL

Z3RD

RESET

Td

RESET

CTXRESET

Z2C

TIME

RELAY CENABLED

RELAY CDISABLED

FAULTINCEPTION


B

D

C

Z1B

Z3RD

Z2C

CTX

Tp

CB OPERATING TIME

R

E

L

A

Y

A B

C D DC

BA

FAULT FAULT

L

O

C

A

T

I

O

N

0

TP

Z2

Z3R

RESET

Figure 21 Blocking scheme current reversal logic

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Page 48 of 89

When the current reverses and the reversed looking Zone 3 comparators reset, theblocking signal transmission is stopped and the timer TD is started. After time TD, thescheme resets and the relay aided trip is enabled once again.

Recommended TD setting = 20ms - minimum signalling channel reset time ms.

The current reversal sequence diagram shows how the relays in the healthy line areprevented from maloperation due to the sequential opening of the circuit breakers inthe faulted line and the instance in the cycle at which it takes place. After currentreversal, the reversed looking Zone 3 comparators at substation D reset, but those atsubstation C operate to send the blocking signal to substation D and inhibit the aidedtrip. After the faulty line is isolated, the reversed looking Zone 3 comparators will resetand the scheme aided trip restored when the timer setting TD has expired.


(See Figure 21B)

The current reversal guard incorporated in the scheme logic is initiated when theblocking signal transmission, started by the reversed looking Zone 3 comparators, isreceived to inhibit the aided trip. A time delay TP is needed with the Zone 2comparators in order to allow time for the blocking signal transmission to be receivedin case the reversed looking Zone 3 comparators had operated for an external fault.

Recommended TP setting = maximum signalling channel operating time ms + 14ms.

When the current reverses and the reversed looking Zone 3 comparators reset, theblocking signal transmission is maintained by the timer TD.

Recommended TD setting = maximum signalling channel operating time ms + 14ms.

Note: If a simplex channel is used

TD setting = maximum signalling channel operating time ms - minimum signalling channel reset time ms + 14ms.

The current reversal sequence diagram shows how the relays in the healthy line areprevented from maloperation due to the sequential opening of the circuit breakers inthe faulted line and the instance in the cycle at which it takes place. After currentreversal, the reversed looking Zone 3 comparators at substation D reset but the blockis maintained for time TD, in order to allow the relays at substation C to send theblocking signal to substation D and inhibit the aided trip. After the faulty line isisolated, the reversed looking Zone 3 comparators at substation C and the forwardlooking comparators at substation D will reset.

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Page 49 of 8925.5 Directional earth fault scheme POR 1, POR 2

(See Figure 22)

The current reversal guard incorporated in this DEF Permissive Overreach scheme

logic, is similar to the distance scheme with reversed looking Zone 3 comparators POR2, except that the operation of the scheme is controlled by the reversed

&

AIDEDTRIP

TP

0

&STOP CTX

COS

CRX

Z2

Z3R



&

0

TD

START CTX

CURRENTREVERSAL

Z3RD

RESET

TD

RESET CTX

RESET

Z2C RESET

TIME

RELAY CENABLED

RELAY CDISABLED

FAULTINCEPTION


B

D

C

Z1B

Z3RD

Z2C

CTX

TP

CB OPERATING TIME

R

E

L

A

Y

A B

C D DC

BA

FAULT FAULT

L

O

C

AT

I

O

N

Figure 21B Blocking 2 scheme current reversal logic

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Page 50 of 89



CURRENTREVERSAL

DEF RDRESET

TDRESET

CTX

RESETDEF FC

TIME

RELAY DENABLED

RELAY DDISABLED

FAULTINCEPTION


B

D

C

Z1B

DEF RD

DEF FC

CTX

CB OPERATING TIME

R

E

L

A

Y

A B

C D DC

BA

FAULT FAULT

L

O

C

A

T

I

O

N

TDG

0

&

DEF F

CRX

CTX

TRIPAIDED

&

&

DEF R

DEF F

RESET

Figure 22 DEF permissive overreach scheme POR 1, POR 2 current rev. scheme logiclooking directional earth fault comparator, instead of the distance reversedlooking Zone 3 comparators. It uses a separate current reversal guard timer

TDG, but it shares a common signalling channel.

Recommended TDG setting = maximum signalling channel reset time ms + 35ms.

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25.6 Directional earth fault blocking scheme

(See Figure 23)

The current reversal guard incorporated in this DEF Blocking scheme logic is similar tothe distance blocking scheme, except that the operation of the scheme is controlled bythe reversed looking directional earth fault comparator instead of the distance reversedlooking Zone 3 comparators. It uses a separate current reversal guard timer TPG toallow for the blocking signal to be received in the event of an external fault, and asecond timer TDG to maintain the aided trip inhibition until the forward lookingdirectional comparator at the opposite end has reset.

Recommended TPG setting = maximum signalling channel operating time ms + 26ms.

Recommended TDG setting = 20ms - minimum signalling channel reset time ms.

25.7 Directional earth fault blocking 2 scheme

(See Figure 23B)

The current reversal guard incorporated in this DEF Blocking 2 scheme logic is similar

to the distance blocking scheme, except that the operation of the scheme is controlledby both the low set current zero sequence level detector (LDLSI0) and the reverselooking directional element (DEF_R) instead of the distance Zone 3 comparators. Ituses a separate current reversal guard timer TPG to allow time for the blocking signalto be received in the event of an external fault, and a second timer TDG to maintainthe blocking signal until the forward looking directional comparator (DEF_F) at theopposite end has reset.

Recommended TPG setting = maximum signalling channel operating time ms + 4ms.

Recommended TDG setting = maximum signalling channel operate time ms + 14ms.

Note: If a simplex channel is used:

TDG setting = maximum signalling channel operating time ms - minimum signalling channel reset time ms + 14ms.

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&

AIDEDTRIP

0

TDG

&CTX

COS

DEF F

CRX



CURRENT

REVERSAL

DEF RD

RESET

TDG

RESET

CTXRESET

DEF FC

TIME

RELAY C

ENABLED

RELAY C

DISABLED

FAULT

INCEPTION


B

D

C

Z1B

DEF RD

DEF FC

CTX

TPG

CB OPERATING TIME

R

E

L

A

Y

A B

C D DC

BA

FAULT FAULT

L

O

C

A

T

I

O

N

0

TPG

DEF F

DEF R

RESET

Figure 23 DEF blocking scheme current reversal logic

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Section 26. 230KV POWER SYSTEM WORKED EXAMPLE - POR 1 MODE

26.1 Objective

To protect the 100Km double circuit line between Green Valley and Blue Riversubstations using model LFZP112 in the Permissive Overreach mode with forwardlooking Zone 3 comparators as per scheme POR 1 and to set the relay at GreenValley substation (Figure 24).

26.2 System data

Line length: 100Km

Line impedances: Z1= 0.089 + j0.476 = 0.484 /79.4° Ω/Km

Z0 = 0.426 + j1.576 = 1.632 /74.8° Ω/Km

Z0/Z1 = 3.372 /-4.6°

CT ratio: 1,200/5VT ratio: 230,000/115

26.3 Relay settings

It is assumed that the two optional reach-stepped Zones Z1X and Z1Y are not usedand that only a three zone scheme is required.

26.4 Zone 1 reach settings

Required Zone 1 reach is to be 80% of the line impedance between Green Valley andBlue River substations.

Ratio of secondary to primary impedance = 1,200/5 = 0.12 230,000/115

Required Zone 1 reach = 0.8 x 100 x 0.484 /79.4° x 0.12

= 4.64 /79.4° ohms secondary

Relay Zone 1 reach = KZ1 x KZPh x 5/In

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Figure 24 230kV power system worked example: LFZP 112, POR 1

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The relay coarse reach KZPh should be set to the nearest value below the requiredZone 1 reach. It is important to set KZPh as high as possible, since the current settingof the relay current level detectors is inversely proportional to KZPh and it is best tohave the relay sensitivity as high as possible.

KZPh setting 0.040 to 1.0 in steps of 0.001

Therefore, select KZPh = 1.0

KZ1 settings 1.0 to 49.98 in steps of 0.02

Required zone 1 multiplier setting KZ1 =Re Re

/

quired Zone ach

KZPh In

1

= 4.64

Therefore, select KZ1 = 4.64

Relay Characteristic Angle THETA Ph settings 50° to 85° in 5° steps

Therefore, select THETA Ph = 80°

Actual Zone 1 reach settings = 4.64 /80°Ω secondary


Required Zone 2 impedance =(Green Valley-Blue River) line impedance + 50% (Blue River-Rocky Bay)

line impedance

= (100+30) x 0.484 /79.2° x 0.12

= 7.56 /79.4°Ω secondary



Required Zone 2 multiplier setting KZ2 =×

Re Re

/

quired Zone ach

KZP In

2

5

= 7.56


Actual Zone 2 reach setting = 7.56 /80°Ω secondary

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Required Zone 3 forward impedance =(Green Valley-Blue River + Blue River-Rocky Bay) x 1.2

= (100+60) x 1.2 x 0.484 /79.4° x 0.12

= 11.15 /79.4°Ω secondary

Relay Zone 3 forward reach = KZ3 x KZPh x 5/In

KZ3 setting 1.0 to 49.98 in steps of 0.02

Required Zone 3 forward reach setting multiplier KZ3

= Required Zone 3 forward reach KZPh x 5/In

= 11.15

Nearest KZ3 setting 11.14

Actual Zone 3 forward reach setting = 11.14 x 1 x 5/5 /80°

= 11.14 /80°Ω secondary

Required Zone 3 reverse reach impedance = Typically 10% Zone 1 reach

= 0.1 x 4.64 /79.4°

= 0.464 /79.4°

Relay Zone 3 reverse reach = KZ3' x KZPh x 5/In

KZ3' settings 0.2 to 49.9 in steps of 0.1

Required Zone 3 reverse reach setting multiplier KZ3'

= Required Zone 3 reverse reach KZPh x 5/In

= 0.46

Therefore, select KZ3' = 0.5

Actual Zone 3 reverse reach setting = 0.5 /80°Ω secondary

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26.7 Earth fault residual compensation settings

Residual Compensation factor KNZ Z

Z

L L

L

= −0 1

13

ZL0

- ZL1

= (0.426 + j1.576) - (0.089 + j0.476)

= 0.337 + j1.1

= 1.15 /72.9°

KN = °

× = − °

1 15 72 9

3 0 484 79 40 79 6 5

. / .

. / .. / .

Residual Compensation setting KZNZ Z

Zx KZPhL L

L

= −( )0 1

1

3

KZN = 0.79 /-6.5° x 1 /80°

= 0.79 /73.5°

KZN settings 0 to 1.36 in steps of 0.001

Therefore, select KZN = 0.79 and THETA N = 75°

26.8 Power swing blocking

With the Permissive Overreach scheme POR 1, the Power Swing Blockingcharacteristic Z6 is set concentric with the Zone 3 characteristic, so that if themeasured impedance locus travels into the Z6 characteristic, but takes longer thantimer TZ6 setting to pass through into the Zone 3 characteristic, the Power SwingBlocking unit will operate. The Power Swing Blocking unit is arranged to block undercertain system conditions and can be preset to block one or more of the relay zones.The recommended settings for the Power Swing Blocking characteristic Z6 forwardand reversereachsettings (see Section 16) are:

Z6 forward reach = 1.3 x Zone 3 forward reach

= 1.3 x 11.14 /80°

= 14.48 /80° Ω secondary

Z6 forward reach = KZ6 x KZPh x 5/In

KZ6 = 14.48



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Actual Z6 forward reach = 14.48 /80° Ω secondary

Z6 reverse reach = 0.3 Zone 3 forward reach + Zone 3 reverse reach

= (0.3 x 11.14 /80°) + 0.46 /80°

= (3.34 + 0.46) /80°

= 3.8 /80°

Z6 reverse reach = KZ6' x KZPh x 5/In



Actual Z6 reverse reach = 3.8 /80° Ω secondary

TZ6 timer settings 20 to 90ms in steps of 5ms

Recommended TZ6 setting 50ms

26.9 Lenticular characteristic

For applications where there are likely to be problems of load encroachment on therelay Zone 3 characteristic, or even more so if the Power Swing Blocking characteristicZ6 is used, the lenticular shaped characteristic is available for Zone 3 and Zone 6.

The major axis of the lenticular characteristic (b) would be set in accordance with theforward and reverse settings required, but the minor axis (a) can be selected toprovide an aspect ratio (a/b) of 1.0, 0.67 or 0.41. The aspect ratio should be chosento prevent the load impedance encroachment into the relay characteristic with aminimum safety margin of 10%.

An impedance diagram showing the relay characteristics for each zone is given inFigure 24B

26.10 Permissive overreach schemes for POR 2, POR 2 WI trip

When the weak infeed logic is required, the Permissive Overreach scheme POR 2 orPOR 2 WI Trip with reversed looking Zone 3 comparators needs to be selected andthe relay settings for Zone 1, Zone 2 and the Residual compensation would be thesame as for scheme POR 1, but the settings for Zone 3 and the Power Swing BlockingUnit would be different.

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26.11 Reversed Zone 3 setting

When set reverse looking, the Zone 3 comparators must be set as directional mho'sand, therefore, only need to be set in the reverse direction (see Section 15.0).

Required reverse Zone 3 setting = 1.2 x Zone 2 relay setting at opposite end, to covererrors due to relay accuracy's (CT and VT errors).

= (Blue River-Green Valley) line impedance + 50% (Green Valley-Tiger Bay) lineimpedance x 1.2

= ((100 + 40) x 0.484 /79.4° x 0.12) 1.2

= 9.76 /79.4°

Relay reverse Zone 3 reach = KZ3' x KZPh x 5/In

KZ3' setting 0.2 to 49.9 in steps of 0.1

Required reverse Zone 3 reach setting multiplier KZ3'

=×

Re

/

quired reversed Zone reach

KZPh In

3

5

= 9.76


Actual reverse Zone 3 reach = 9.8 /80°Ω secondary

26.12 P ower swing blocking

When the Power Swing Blocking unit is used with the Permissive Overreach schemesPOR 2 because the Zone 3 comparators are set reverse looking, the Zone 6characteristic of the Power Swing Blocking unit has to be set concentric with the Zone

2 characteristic. In the example chosen, for the 100 Km line between Green Valleyand Blue River, the required settings would be:

Zone 6 forward reach = 1.3 x Zone 2 reach

= 1.3 x 7.56 /80°

= 9.82 /80°

Relay Zone 6 forward reach = KZ6 x KZPh x 5/In


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Page 62 of 89Required Zone 6 forward reach multiplier setting

=×

Re Re

/

quired Zone forward ach

ZPh In

6

5

= 9.82


Actual Zone 6 forward reach = 9.82 /80°

Zone 6 reverse reach = KZ6' x KZPh x 5/In


Required Zone 6 reverse reach setting multiplier KZ6'

=×

Re Re

/

quired Zone reverse ach

ZPh In

6

5

= 2.26


Actual Zone 6 reverse reach = 2.3 /80°Ω secondary

26.13 Current reversals

The current reversal logic available with the Permissive Overreach schemes need onlyto be used when the setting of the Zone 2 comparators is greater than 1.5 times theimpedance of the protected line. In the chosen worked example, since the setting of the Zone 2 comparators is only 1.3 times the protected line impedance, the currentreversal logic does not need to be used and the recommended settings for the currentreversal guard timer are:

TP = 98ms and TD = 0

26.14 Check on comparator voltage at Zone 1 reach

Worst condition is with the parallel line out of service and it is assumed that the valuesof maximum and minimum fault levels at Green Valley and Blue River substations arefor single infeed conditions.

Maximum source positive sequence impedance :

230

20002645

2

,. /80= °

= 4.59 + j26.05Ω

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Protected line positive sequence impedance up to Zone 1 reach =

0.8 x 100 x 0.484 /79.4° = 38.72 /79.4°

= 7.12 + j38.06Ω

Overall source to Zone 1 reach positive sequence impedance =

(4.59 + j26.05) + (7.12 + j38.06) = 11.71 + j64.11

= 65.17 /79.6°Ω

Relay voltage for a phase fault at the Zone 1 reach =

115 x 38.72 = 68.32V 65.17

Earth Fault At Zone 1 Reach

Maximum source zero sequence impedance assumed to be equal to the positivesequence impedance

Maximum source earth loop impedance = 4.59 + j26.05Ω

Protected line zero sequence impedance up to Zone 1 reach =

0.8 x 100 x 1.632 /74.8° = 130.56 /74.8°

= 34.23 + j125.99Ω

Protected line earth loop impedance up to Zone 1 reach =

2 x (7.12 + j38.08) + (34.23 + j125.99) = 16.15 + j67.38 3

= 69.29 /76.5°

Overall source to Zone 1 reach earth loop impedance =

(4.59 + j26.05) + (16.15 + j67.38) = 20.74 + j93.43

= 95.70 /77.48°

Relay voltage for an earth fault at the Zone 1 reach =

66.47 x 69.29 = 48.12V 95.70

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For a ±5% reach accuracy with the Zone 1 multiplier set to unity Optimho requires atleast 2.05 volts for earth fault measurement or at least 3.55V for phase fault

measurement. For a ±10% accuracy, the required voltages are 1.04V and 1.8Vrespectively. For Zone 1 multipliers greater than unity, the required relay voltages foraccuracy vary linearly with the multiplier setting.

In this case, the Zone 1 multiplier KZ1 = 4.64

Thus, the required minimum voltages for a ± 5% reach accuracy are:

4.64 x 2.05 = 9.51V for earth faults

4.64 x 3.55 = 16.47V for phase faults

Both voltage requirements are met in this application

26.15 Current transformer requirements

Class X current transformers are required to meet the following specification:

Phase Fault Condition ( )V I 1X

RZ R R VK F R CT L≥ +

+ +

( )V I 1X

RZ R R voltsK F R CT L≥ +

+ +

IF = maximum secondary fault current for a three phase fault at the Zone 1 reach

Neglecting the small infeed from the parallel line

Minimum source positive sequence impedance

= = °230

5000

10 58 802

,

. / Ω

Overall minimum source to Zone 1 reach positive sequence impedance =

(1.837 + j10.419) + (7.12 + j38.06) = 8.957 + j48.479

= 49.29 /79.5°

I AF = ×

× × =

230 10

3 49 29

5

1 20011 238

3

. ,.

XR

= =48 4798 957

5 41..

.

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ZR = Relay burden for a phase fault = =0 5

250 02

.. Ω

RCT = Current transformer secondary winding resistance assumed to be 0.5Ω

RL = Resistance of one pilot cable lead between the current transformers andthe relay, assumed to be 0.25Ω

Current transformer knee-point voltage requirement for a three phase fault at the Zone1 reach point

VK≥ 11.238 (1 + 5.41)(0.02 + 0.5 + 0.25)

≥ 80.69V

Earth Fault Condition

( )V I 1X

RZ R 2RK FE

E

E

RE CT L≥ + + +

IFE = maximum secondary fault current for an earth fault at the Zone 1 reach

Assuming that the zero and positive sources impedances are equal

Minimum source earth loop impedance = 1.837 + j10.419ΩOverall source to Zone 1 reach earth loop impedance =

(1.837 + j10.419) + (16.15 + j67.38) = 17.987 + j77.799

= 79.85 /77Ω

I AFE = ×

× × =

230 10

3 79 85

5

1 2006 937

3

. ,.

XR

E

E

= =77 79917 987

4 32..

.

ZRE = Relay burden for an earth fault = 0.02Ω

Current transformer knee-point voltage requirement for an earth fault at the Zone 1reach point

VK≥ 6.937 (1 + 4.32)(0.02 + 0.5 + 0.5)

≥ 37.64V

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Page 66 of 89It is also required that at the current transformer knee-point voltage, which from theabove calculations should not be less than 80.69 volts, the exciting current should beless than 0.5A.

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26.16 Optional DEF used in POR schemes

If the optional DEF is used in POR1, CTX is based purely on DEF_F, in POR2 CTX isbased on DEF_F + LDHSZ2. DEF reverse sensitivity is based on the DEF LOWSET

(LDLSI0).

Section 27. 132KV POWER SYSTEM WORKED EXAMPLE - BLOCK MODE

27.1 Objective

To protect the 10Km single circuit line between Ironbridge and Windy Hill substationusing model LFZP111 in the Blocking mode and to set the relay at Ironbridge with theQuadrilateral characteristic for earth faults. It is required to measure high resistancefaults which may be resistive up to 50Ω and to complement the distance scheme withthe directional earth fault scheme (see Figure 25).

27.2 System data

Line length: 10Km

Line impedances: Z1 = 0.16 + j0.41 = 0.44 /69° Ω/Km

Z0 = 0.34 + j1.03 = 1.09 /72° Ω/Km

Z0/Z1 = 2.5 /3°

CT ratio: 500/1VT ratio: 132000/110

27.3 Relay settings

It is assumed that the two optional reach-stepped zones Z1X and Z1Y are not usedand that only a three zone scheme is required.

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Figure 25 132kV power system worked example using model LFZP 111 in the blockingmode

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Required Zone 1 reach is to be 80% of the line impedance between Ironbridge andWindy Hill substations.

Ratio of secondary to primary impedance = =500 1

132 000 1100 416

/

, /.

Required Zone 1 reach = 0.8 x 10 x 0.44 /69° x 0.416



The relay coarse reach KZPh should be set to the nearest value below the required

Zone 1 reach. It is important to set KZPh as high as possible, since the current settingof the relay current level detectors are inversely proportional to KZPh and it is best tohave the relay sensitivity as high as possible.

KZ KZPh11 46 69

50 292 69× =

°= °

. /. /

KZPh settings 0.040 to 1.0 in steps of 0.001


Therefore, select KZ1 = 1.0 and KZPh = 0.292

Relay characteristic Angle THETA Ph settings 50° to 85° in 5° steps

Therefore, select THETA Ph = 70°

Actual Zone 1 reach setting = 1.0 x 0.292 x 5 x 70°



Required Zone 2 impedance = (Ironbridge-Windy Hill) line impedance + 50% (WindyHill-Tagus River) line impedance

= (10 + 15) x 0.44 /69° x 0.416

= 4.576 /69°



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Required Zone 2 multiplier setting KZ24 576

0 292 53 143=

× =

.

..


Actual Zone 2 reach setting = 3.14 x 0.292 x 5 /70°



In the Blocking mode the Zone 3 comparators are set looking directionally in thereverse direction.

Required Zone 3 reverse impedance= Zone 2 relay setting at opposite end

= (Windy Hill-Ironbridge) line impedance + 50% (Ironbridge- Trent Bridge) lineimpeadance = (10 + 10) x 0.44 /69° x 0.416

= 3.66 /69°

Relay reverse Zone 3 reach = KZ3' x KZPh x 5/In


Required Zone 3 multiplier setting KZ3' =×

=3 66

0 292 52 50

.

..


Actual reverse Zone 3 reach = 2.5 x 0.292 x 5 /70°

= 3.65 /70°

27.7 Quadrilateral characteristic

For this example, the quadrilateral characteristic has been chosen for earth faults,because the line to be protected is short and very high values of arc-resistance need tobe measured.

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27.8 Resistive reach of earth fault comparators

Required resistive coverage for earth faults = 50 ohms primary

= 50 x 0.416

= 20.8 Ω secondary

Minimum load impedance =×

=110

3 16358 secondary. Ω

There will, therefore, be no problem of encroachment on the earth fault comparatorsoperating zone, if the comparators are set to see 50 ohms primary fault resistance.

Quadrilateral characteristic right hand reach = KR x 5/In

Quadrilateral characteristic left hand reach = KR x 6/In

KR settings 1 to 30 in steps of 1

Select nearest resistive reach setting above the required value

Required KR setting = =20 8

54 16

..

Therefore, select KR = 5

Actual resistive reach = 5 x 5 = 25 ohms secondary

Check on ratio resistive reach /Zone 1 earth loop impedance reach

Zone 1 earth loop impedance reach = + +1 46 1 46 3 65

3

. . .

= 2.19 Ω secondary

Ratio resistive reach/Zone 1 earth loop reach = =25

2 1911 41

..

The above ratio is within the limit of 15 prescribed in Section 17.0

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27.9 Earth fault residual compensation settings

Residual compensation factors KNZ Z

Z

L L

L

= −0 1

13

ZL0

- ZL1

= (0.34) + j1.03) - (0.16 + j0.41)

= 0.18 + j0.62

= 0.64 /73.8°

KN =0 64 73 8

3 0 44 69

. / .

. /

°× °

= 0.48/4.8°

Residual compensation setting KZN

Z Z

Z x KZPhL L

L=

−( )0 1

13

KZN = 0.48 /4.8° x 0.292 /70°

= 0.14 /74.8°

KZN settings 0 to 1.36 in steps of 0.001

Therefore, select KZN = 0.14 and THETA N = 75°

An impedance diagram showing the relay phase and earth fault characteristics foreach zone is given in figure 25B.

27.10 Directional earth fault scheme settings

Mode of operation blocking, sharing the same signalling channel as the distancescheme. It uses one forward looking and one reverse looking directional earth faultcomparator to provide high speed clearance of high resistance faults. Also, it providesdirectional time delayed back-up protection with a choice of time curves to assist with

system co-ordination. No instantaneous directional trip is provided because thedistance scheme is fitted with Zone 1 earth fault measuring comparators. In setting thecurrent level detectors, it is important to note that to allow for relay tolerance and thecapacity current of the protected line, it is essential to maintain a ratio of 1.5 betweenthe setting of the forward looking current level detector at the local end and the reverselooking current level detector a the remote end. For this purpose, it is necessary toconsider the source contribution from each end of the protected line.

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Z3

Z2

Z1

IRONBRIDGE WINDY HILL

5

4

3

2

1Z1

Z2

Z3

1 2 3 4 5R

X

PHASE FAULTS

EARTH FAULTS

1

2

3

4

5

5 10 15 20 25

R

1

2

3

51015202530

Z2

Z1

Z3'

3

2

1

X

Figure 25B 132kV Power system worked example using model LFZP 111 in

the blocking mode relay settings

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The sensitivity of the forward looking directional element is set by either DEF LOWSETor DEF HIGHSET (if aided tripping selected). Reverse sensitivity is set by DEFLOWSET.

( i ) Earth fault at Windy Hill substation busbars fed from Trent Bridge substation

Trent Bridge maximum source impedance = =132

10001742

2

. Ω

Trent Bridge to Windy Hill line positive sequence impedance =

(20 + 10) x 0.44 /69° = 13.2 /69° Ω

Trent bridge to Windy Hill line zero sequence impedance =

(20 + 10) x 1.09 /72° = 32.7 /62° Ω

Arc-resistance = 50 ohms

Minimum earth fault current =( )

3 132 10

3 30 62 30 62 20012

3× ×

+ +. . .

= 875.81A primary

Equivalent CT secondary current = =875 81

5001 75

.. A

( ii ) Earth fault at Ironbridge substation busbars fed from Tagus River substation.

Tagus River maximum source impedance = =132

1500116

2

. Ω

Tagus River to Ironbridge line positive sequence impedance =

(30 + 10) x 0.44 /69° = 17.6 /69° Ω

Tagus River to Ironbridge line zero sequence impedance =

(30 + 10) x 1.09 /72° = 43.6 /72° Ω

Arc-resistance = 50 ohms

Minimum earth fault current =( )

3 132 10

3 292 292 2052

3× ×

+ +. . . ) = 868.36A primary

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Equivalent CT secondary current = =868 36

5001 736

.. A

Directional measuring elements current setting range 0.05In to 0.80In in

steps of 0.05In

( iii ) To set the directional measuring elements at Ironbridge and Windy Hillrelays.

Because the earth fault current is primarily controlled by the arc-resistance,the minimum current seen by the relays at both ends of the protected line ispractically the same. Therefore, in this application, they can be set with thesame current settings, subject to the following constraints:

a) The current setting must be above the maximum zero sequencecurrent unbalance present in the protected line under normaloperating conditions.

b) That the current setting of the forward looking current leveldetector is 1.5 times the reverse looking current level detector.

Therefore, the recommended current settings assuming that themaximum zero sequence current unbalance is 5% would be:

Reverse looking current level detector (3Io Low set) 0.1A

Forward looking current level detector (3Io High set) 0.15A

c) To set the current reversal timer TPG/TDG

Recommended TPG setting = maximum signalling channeloperating time ms + 26ms.

Recommended TDG setting = 20ms - minimum signalling channelreset time ms.

d) Back-up earth fault protection time delay trip

Current setting range 0.05In to 1.20In in steps of 0.05In

Time multiplier setting range 0.025 to 1.0 in steps of 0.025

Number of co-ordination curves available: 8 inverse and 3definite time.

Recommended current setting 0.1A

Operating curve and time multiplier setting to be chosen toco-ordinate with the time delayed protection on the adjacent lines.

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e) Directional element characteristic angle THETA G 10° to 80° in 10° steps tobe set to the source zero sequence impedance angle which in this examplehas been assumed to be 80°.

27.11 Check on comparator voltage for accuracy of Zone 1 phase fault atZone 1 reach

Maximum source positive sequence impedance =

132 80

100017 424 80 3 025 j17159

2 /. / . .

°= ° = + Ω

Trent Bridge to Ironbridge line positive sequence impedance =

20 x 0.44 /69° = 8.8 /69° = 3.153 + j8.215Ω

Maximum positive sequence impedance behind relay =

(3.025 + j17.159) + (3.153 + j8.215) = 6.178 + j25.374

= 26.115 /76.3Ω

Protected line positive sequence impedance up to Zone 1 reach =

0.8 x 10 x 0.44 /69° = 3.52 /69° = 1.261 + j3.28Ω

Overall source to Zone 1 reach positive sequence impedance =

(6.178 + j25.374) + (1.261 + j3.28) = 7.439 + j28.654

=29.60 /75.4°Ω

Relay voltage for a phase fault at the Zone 1 reach =

110 x 3.52 = 13.08V 29.60

Earth fault at zone 1 reach

Maximum source zero sequence impedance assumed to be equal to the positivesequence impedance

Trent Bridge to Ironbridge line zero sequence impedance =

20 x 1.09 /72° = 21.8 /72° = 6.736 + j20.733Ω

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Page 78 of 89Maximum zero sequence impedance behind relay =

(3.025 + j17.159) + (6.736 + j20.733) = 9.761 + j37.892

= 39.129 /75.5°Ω

Maximum earth loop impedance behind relay =

( ) ( )2 617 8 j25374 9761 j37 892

3

× + + +. . . . = 7.372 + j29.546

= 30.45 /76°Ω

Protected line zero sequence impedance up to Zone 1 reach =

0.8 x 10 x 1.09 /72° = 8.72 /72° = 2.694 + j8.293Ω

Protected line earth loop impedance up to Zone 1 reach =

( ) ( )2 1261 j328 2694 j8293

3

× + + +. . . .= 1.738 + j3.857

= 4.23 /65.7°Ω

Overall source to Zone 1 earth loop impedance =

(7.372 + j29.546) + (1.738 + j3.857) = 9.11 + j33.403

= 34.62 /74.7°Ω

Relay voltage for an earth fault at the Zone 1 reach =

63.54.23

34.627.758V× =

For a ± 5% reach accuracy with the Zone 1 multiplier set to unity Optimho requires atleast 2.05V for earth fault measurement or at least 3.55V for phase fault measurement.For a ± 10% accuracy, the required voltages are 1.04V and 1.8V respectively. ForZone 1 multipliers greater than unity, the required relay voltages for accuracy varylinearly with the multiplier setting.

In this case, the Zone 1 multiplier KZ1 = 1.0

Therefore, both voltage requirements are met in this application

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Page 79 of 89


Class X current transformers are required to meet the following specification

Phase Fault Condition

( )V I 1X

RZ R R VK F R CT L≥ +

+ +

IF = Maximum secondary fault current for a three phase fault at the Zone 1 reach.

Minimum source positive sequence impedance= = °132

5 0003 48 80

2

,. /

Overall minimum source to Zone 1 reach positive sequence impedance =

(0.604 + j3.427) + (3.153 + j8.215) + (1.261 + 3.28) =

5.018 + j14.922 = 15.74 /71.4°Ω

I132 10

3 15.74

1

5009.69 AF

3

= ×

× × =

XR

= =14 9225 018

2 97..

.

ZR = Relay burden for a phase fault = 0.08Ω

RCT = Current transformer secondary winding resistance assumed to be 2.5Ω

RL = Resistance of one pilot cable lead between the current transformers andthe relay,assumed to be 0.5Ω

Current transformer knee-point voltage requirement for a three phase fault at the Zone1 reach point

VK≥ 9.69 (1 + 2.97)(0.08 + 2.5 + 0.5)

≥ 118.48V

Earth Fault Condition

( )V I 1X

RZ R 2RK FE

E

E

RE CT L≥ +

+ +

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Page 80 of 89

IFE = Maximum secondary fault current for an earth fault at the Zone 1 reach

Assuming that the zero and positive source impedances are equal

Minimum source earth loop impedance = 0.604 + j3.427Ω

Trent Bridge to Ironbridge earth loop impedance =

( ) ( )2 3153 j8215 676 j20 733

3

× + + +. . . . = 4.355 + j12.387Ω

Overall minimum source to Zone 1 reach earth loop impedance =

(0.604 + j3.427) + (4.355 + j12.287) + (1.738 + j3.857) = 6.697 + j19.671

= 20.78 /71.2°Ω

I132 10

3 20.78

1

5007.34 AFE

3

= ×

× × =

X

R

19.671

6.6972.937E

E

= =

ZRE = Relay burden for an earth fault 0.08Ω

Current transformer knee-point voltage requirement for an earth fault at the Zone 1reach point

VK≥ 7.34 (1 + 2.937)(0.08 + 2.5 + 1)

≥ 103.45V

It is also required that at the current transformer knee-point voltage, which from theabove calculations should not be less than 118.48 volts, the exciting current should beless than 0.1A.

Section 28. FAULT LOCATOR

The distance from the relaying point to the fault can be quickly and convenientlymeasured and displayed by the fault locator unit, when fitted, in the Optimho relay.

The principle of measurement is based on the computation by means of an algorithm,which takes into account the pre-fault load current and the infeed from the remote endand if selected the mutual coupling between parallel circuits.

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Page 82 of 89Fault location is computed when the relay does any start or distance trip (selectable bythe menu) but faults outside the protected line are based on the protected lineimpedance. Faulted phase information is displayed by the distance relay directly onthe LCD. When fault location computation is completed, (this may take severalseconds), the location is displayed by pressing the ACCEPT/READ key and reviewing

the fault record.

When the fault occurs and before the circuit breaker has opened, the fault locatorstores ten cycles of pre-trip and six cycles of post-trip data. The algorithm finds theinstant of fault by scanning the stored faulted phase current data and determines thepre-fault and fault values.

By the user interface, the fault locator can be set in Kilometres, miles, or as apercentage of the protected line length and displayed on the LCD. Likewise, the valuesof primary current and voltage can be expressed in primary values and displayed on

the LCD unit.

28.1 Mutual Compensation

Analysis of an earth fault on one circuit of a double circuit line shows that a distancerelay at one end of a faulted line will tend to overreach while that at the other end willtend to underreach. In most applications the degree of underreach is acceptable, butin cases of long lines with high mutual coupling or where precise fault locationmeasurement is required, mutual zero sequence compensation can be used to improvethe distance measurement. In practice, the positive and negative sequence coupling

between parallel lines is insignificant and only the zero sequence mutual couplingneeds to be considered.

To illustrate the principle involved in the application of mutual compensation, considerthe sequence networks shown in Figure 26 for a double circuit line with an earth faulton line AB and where y is the per unit distance of the fault from end A.

A fault locator at terminal A having zero sequence compensation only will be suppliedwith voltage VR and current IR as given by the expressions:

( ) ( ) ( ) ( )V y Z I y Z I y Z I y Z I

R L1 a1 L2 a2 L0 a0 M0 c0= + + +

For a fully transposed transmission line assume ZL1 = ZL2 then

= + +

+

y Z I I Z

ZI Z

ZIL1 a1 a2

L0

L1a0

M0

L1c0

)I I I I ZZ

1IR a1 a2 a0L0

L1a0= + + +

−

= + +

I I Z

ZIa1 a2

L0

L1a0

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Page 83 of 89

Therefore, the impedance presented to the fault locator is:

Z y Z I I

ZZ I

ZZ I

I I ZZ

IR

L1 a1 a2 L0L1

a0 M0L1

c0

a1 a2L0

L1a0

=+ +

+

+ +

( )( ) ( ) ( )

Z y Z 1Z I

I Z I Z I ZR L1

M0 c0

a1 L1 a2 L2 a0 L0

= ++ +

But Ia1 = Ia2 = Ia0 for an earth fault,

Therefore:

( )Z y Z 1

Z

2Z Z

I

IR L1

M0

L1 L0

c0

a0

= ++

Now, if in addition to the zero sequence compensation, we add to the fault locator themutual compensation:

I I I I ZZ

1 I ZZ

IR a1 a2 a0L0

L1a0

M0

L1c0= + + + −

+

Z

y Z I I ZZ

I ZZ

I

I I ZZ

I ZZ

IR

L1 a1 a2L0

L1a0

M0

L1c0

a1 a2L0

L1a0

M0

L1c0

=

+ +

+

+ +

+

= y ZL1

Which is the correct distance from the fault locator to the fault.

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Page 84 of 8928.2 Mutual input polarity

The polarity of the residual current to be added to the fault locator from the parallelline is shown on the diagram in Figure 27. The star point of the parallel line currenttransformers being connected to the relay terminal number 28 and the residual circuit

connection to terminal 27.

Note: Please note that when Optimho is supplied with both DEF and Fault Locatorthe relay can only be connected to one current input and that the user mustmake the choice via the relay menu for either DEF current polarisation orFault Locator mutual compensation.

C

SOURCE

D

A B

Z

ZZ

Z

L

L

L

ZM

1-yy ( )

S

S1

( )y 1-y L1

L1

L1

Z

Z Z

Z

I a1

I C1

C2I

a2I

Z

ZZ

Z

L2

L2

L21-yy ( )

S2

C0I

a0I

Z

ZZ

Z

L0

L0

L01-yy ( )

S0

M0Z

Figure 26 Sequence networks for an earth fault on a double circuitline with single infeed

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Page 85 of 89

A

B

C

P2 P1

LINE 1

DIRECTION FOR OPERATION

19

20

21

2223

24

25

26

27

28

OPTIMHO

MUTUAL COMPENSATION

MUTUAL COMPENSATION

OPTIMHO

28

27

26

25

24

23

22

21

20

19

LINE 2

P1P2

C

B

A

DIRECTION FOR OPERATION

Figure 27 Optimho fault locator mutual compensation connections

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Page 86 of 8928.3 Fault locator settings

The procedure for setting the Fault Locator can be best illustrated using the 230kVtransmission line in the example shown in Figure 24 where the zero sequence mutualimpedance between circuits is assumed to be 0.1068 + j0.5712Ω/Km.

Line length: 100Km

Line positive sequence impedance: Z1 = 0.484 /79.4°Ω/Km

CT ratio: 1200/5VT ratio: 230,000/115

Ratio of secondary to primary impedance = 0.12

Mutual impedance: ZM0 = 0.1068 + j0.5712

= 0.581 /79.4°Ω/Km

Mutual compensation factor KM = ZM0/3ZL1

= °

× °

0.581 /79.4

3 0.484 /79.4

= 0.4 /0°

Required fault locator setting = Protected line impedance

= 100 x 0.484 x 0.12

= 5.80 secondary Ω

Fault locator setting = KZF x KZPh x 5/In

KZPh = 1 (Optimho selected setting)

Required fault locator multiplier KZF = 5.8

KZF setting 1 to 40 in steps of 0.01

Therefore, set KZF = 5.8

Mutual compensation setting KZM = KM x KZPh

KZPh = 1 /80° (Optimho selected setting)

Therefore KZM = 0.4 /0° x /80°

= 0.4 /80°

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Page 87 of 89

KZM setting range 0 to 1.36 in steps of 0.001.

Therefore, select KZM = 0.4

Mutual compensation angle THETA M setting range 50° to 85° in 5° steps.

Therefore, select THETA M = 80°

Line units setting Kilometres

Line length setting: 0 to 99.99 in 0.01 steps and 100 to 999.9 in 0.1 steps to be setat 100 (corresponding to the protected line length)

VT ratio setting: 1/1 or 10/1 to 9990/1 in 10/1 steps to be set to 2000/1(corresponding to the actual VT ratio)

CT ratio setting: 1/1 or 10/1 to 5000/1 in 10/1 steps to be set to 240/1(corresponding to the actual CT ratio)

Section 29. LOSS OF LOAD ACCELERATED TRIP FEATURE

When only three pole tripping is used and no signalling channel is available, a novel

way to achieve an accelerated trip for unbalanced faults at the end zones of theprotected line is the `Loss of Load feature'.

It is based on the operation of Zone 2 comparators and the resetting of the healthyphase(s) current level detectors. Load current is detected by either the LOW SET or theHIGH SET current level detectors as selected on the relay menu. Before an acceleratedtrip can occur load current must have been present prior to the occurrence of the fault.The loss of load current in the health phase(s) opens a window of 40ms during whichtime an accelerated trip can take place, if the Zone 2 comparators have operated. Theaccelerated trip is delayed by 18ms in order to avoid the possibility of a Loss of Load

trip being produced during the clearance of an external fault due to pole scatteropening of the circuit breaker.

In connection with this feature, it is important to note that the sensitivity of the currentlevel detectors is linked to the setting of the coarse adjustment KZPh and this currentsensitivity varies in the inverse ratio. That is, it is 5%In for the LOW SET and 7.5%In forthe HIGH SET at the reference setting of KZPh = 1 but they vary in accordance withthe expression 0.05In/KZPh for the LOW SET and 0.075In/KZPh for the HIGH SET forother values of KZPh. Also that the Zone 2 comparators are gated with the currentlevel detectors so that on the clearance of external faults, the possible loss of loadcausing all the current level detectors to reset would immediately block the Zone 2

comparator and thus avoid an unnecessary trip. Likewise operation of the Switch on toFault feature (SOTF) or a protection trip via the distance disables the Loss of Loadfeature.

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Page 88 of 89

Although, the main usefulness of the Loss of Load feature is for use with the BASICscheme when no signalling channel is available, it can nevertheless be used in

conjunction with any three pole only tripping scheme to provide high speed back-up

clearance for end zone faults on failure of the signalling channel.

When selected for use with plain or tapped circuits it is essential to note therelationship between the load current and/or standing current and the current leveldetectors should be:

a) That under normal healthy conditions the load current of theprotected circuit is greater than the effective current setting of theselected current level detectors.

b) That under end zone fault conditions the healthy phase(s) standingcurrent is less than the effective setting of the selected leveldetectors.

Loss of Load Accelerated trip logic is:

Zone 2 comparators operation plus resetting of health phase(s) current leveldetectors.

29.1 Current level detectors effective setting

The relationship between the load current and/or standing current and the currentlevel detector effective setting can best be illustrated by the following examples:

Short Transmission Lines

Line length: 5Km

Power system voltage 69KV

Line impedance: Z1 = 0.4 ohm/Km

Line charging current: 0.1A/Km

CT ratio: 500/5VT ratio: 69000/115

Required Zone 1 reach is to be 80% of the line impedance.


69000 1150 1666

/

/.

Required Zone 1 reach = 0.8 x 5 x 0.4 x 0.1666

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Page 89 of 89

= 0.266Ω secondary


The relay coarse reach KZPh should be set to the nearest value below the required

Zone 1 reach. It is important to set KZPh as high as possible, since the current settingof the relay current level detectors are inversely proportional to KZPh and it is best tohave the relay sensitivity as high as possible.

KZ1 x KZPh = 0.266




Low set level detector effective setting = ×

=0 05 5

0 2660 94

.

.. A

Line charging current = × × =5 0 15

5000 005. . A Secondary (negligible)

For the Loss of Load feature to function, the line load current under normal healthyconditions must be greater than the low set current level detector setting of 0.94A

(18.8% of rated current) to satisfy the requirement that load current must have existedprior to the occurrence of the fault.

The current remaining in the healthy phase(s) when the remote circuit breaker is opendue to the internal fault must be less than the low set current level detector setting of 0.94A to allow the level detector(s) to reset, thereby detecting a `loss of load'condition. In this example, this current is the line charging current of only 0.005A.

Long transmission lines

Line length: 150Km

Power system voltage:115KV

Line impedance: Z1 = 0.4 ohm/Km

Line charging current: 0.15A/Km

CT ratio: 1000/5VT ratio: 115000/115

Required Zone 1 reach is to be 80% of the line impedance.


11500 1150 2

/

/.

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Page 90 of 89

Required Zone 1 reach = 0.8 x 150 x 0.4 x 0.2

= 9.6Ω secondary


The relay coarse reach KZPh should be set to the nearest value below the requiredZone 1 reach. It is important to set KZPh as high as possible, since the current settingof the relay current level detectors are inversely proportional to KZPh and it is best tohave the relay sensitivity as high as possible.

KZ1 x KZPh = 9.6




Low set level detector effective setting= ×

=0 05 5

1 00 25

.

.. A

Line charging current = × × =150 0155

10001125 A secondary. .

= 2.25% of rated current

For the Loss of Load feature to function, the line load current under normal healthyconditions must be greater than the low set current level detector setting of 0.25A (5%of rated current) to satisfy the requirement that load current must have existed prior tothe occurrence of the fault. It can be seen that for long lines where KZPh is large, thiscondition is easily satisfied.

The current remaining in the healthy phase(s) when the remote circuit breaker is open

due to the internal fault must be less than the low set current level detector setting of 0.25A to allow the level detector(s) to reset, thereby detecting a `loss of load'condition. In this example, this current is the line charging current of 0.1125A.However, currents other than the line charging current may be present in the healthyphase(s) when the remote breaker opens (for example tapped-off load current). If thehealthy phase current should exceed the low set level detector setting the level detectorsensitivity may be increased by:-

a) Selecting the high set current level detectors, which have 1.5 times the lowset setting.

and/or

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Page 91 of 89b) Decreasing the KZPh setting and adjusting all the distance multipliersto

maintain the required zone reaches.

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Page 92 of 89

Section 30. MULTIPLE SETTING GROUPS

The concept of multiple setting groups is a recent innovation in distance relays, madepossible since all settings are stored in non-volatile (EEPROM) memory, rather thanbeing linked to the position of setting switches, as was the case with earlier relays.Optimho can store up to eight independent groups of settings. The active group isselected either locally via the menu or remotely via the serial RS232 communicationsusing a modem.

The ability to quickly reconfigure the relay to a new setting group may be desirable if changes to the system configuration demand new protection settings.

Typical examples where this feature can be used include single bus installations with a

transfer bus and double bus installations with or without a separate transfer bus, wherethe transfer circuit breaker or bus coupler is used to take up the duties of the by-passedfeeder circuit breaker when both the circuit breaker and the current transformers areby-passed.

In the case of a double bus installation when only two buses are provided it is usualfor bus 1 to be referred to as the main bus and bus 2 as the reserve bus, and for theby-pass circuit isolator to be connected to bus 2 as shown in Figure 28. Thisarrangement avoids the need for a current transformer reversed polarity switch thatwould be required if both buses are to be used for by-pass purposes.

The standby relay, associated with the transfer circuit breaker or the bus coupler, canbe programmed with the individual setting required for each of the outgoing feeders.For by-pass operation the appropriate setting group can be selected as required.

This facility can be extremely usefully in the case of unattended substations were all theswitching can be controlled remotely. Remote control of the relay settings removes theneed for a skilled engineer to travel to site to change the relay settings.

A further use for this novel feature of the relay is the ability to provide alternativesetting for teed feeders or double circuit transmission lines with mutual coupling, foruse when one line is out of service and grounded at both ends.

Similar alternative settings could be required to cover different operating criteria in theevent of the signalling channel or auto-reclose equipment failing, or alternative systemconfiguration (i.e. lines being switched in or out).

All relays leave the factory with all the setting groups programmed the same andsetting group 1 selected. For those users not requiring multiple setting groups it isstrongly recommended that the active setting group number be left unchanged.

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Page 93 of 89

MAIN BUS

RESERVE BUS

21

OPTIMHO

STANDBY RELAY21

FEEDER 1

21

FEEDER 2

Figure 28 Typical double bus installation with by-pass facilities

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CHAPTER 2

DESCRIPTION, TECHNICAL DATA

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ContentsPage 1 of 10

Contents Page

1. INTRODUCTION 1

1.1 General 11.2 Features 11.3 Benefits 21.4 Operating principles 21.5 Hardware structure 22. MECHANICAL LAYOUT 73. OPERATING INSTRUCTIONS 103.1 User interface 103.1.1 Keypad 103.1.2 Serial port 113.1.3 Parellel port 11

3.1.4 Indication LED’s 113.1.5 Relay available LED. 123.1.6 Alarm LED 123.1.7 Trip LED. 123.2 Visual indication of faults or events 143.3 View/scroll settings/data 183.4 Menu system 203.4.1 Default level 203.4.2 Time-out feature. 213.4.3 Multiple setting groups 213.4.4 How settings and records are stored 24

3.4.5 Setting trap 253.4.6 Operating the menu 263.5 Commission tests 363.5.1 Contact control 363.5.2 On load directional test 373.5.3 Power swing test 373.5.4 Monitor option 383.5.5 Output option 393.6 Communications 403.6.1 Access level 403.6.2 Serial Control 403.6.3 Active Port 403.6.4 Baud Rate 413.6.5 Protocol 413.6.6 Control Lines 413.6.7 Communications and multiple setting groups 413.7 Fault Records. 423.7.1 Viewing Fault Records 423.7.2 Clearing Fault Records 433.8 Metering 43

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Contents Page

3.9 Print option 44

3.9.1 Printing to the parallel port 443.9.2 Printing to serial port . 453.10 Identifiers 503.10.1 Group identifier 503.10.2 Software version. 513.10.3 Default display 513.11 Calendar clock 523.11.1 Format 523.11.2 Default time & date 523.11.3 Setting time & date 523.11.4 Clock reference 53

3.12 Settings 533.12.1 Contact configuration 543.12.2 Scheme 543.12.3 Distance 573.12.4 Block autoreclose block auto-reclose 603.12.5 VT supervision 613.12.6 Start indication 613.12.7 DEF 613.12.8 Fault locator 643.13 Serial communications 713.13.1 Introduction. 71

3.13.2 Security 713.13.3 Control of serial communications from the relay menu 723.13.4 Hardware connections 733.13.5 Logon procedure 733.13.6 K-Bus interface 753.13.7 Modem requirements 753.13.8 Recommended modems 753.13.9 Optimho serial communication protocol 763.14 Test features 783.14.1 Contact control 783.14.2 On load dir test 783.14.3 PwrSwg test 793.14.4 Monitor option 793.14.5 Output options 813.14.6 Parallel test socket 834 PRINCIPLES OF OPERATION 864.1 The comparator 864.1.1 Fundamentals of the comparator 864.1.2 Action of the comparator 884.1.3 Exclusion of noise 90

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Contents Pge

4.2 Polarising arrangements 95

4.2.1 Partially cross polarised mho 964.2.2 Synchronous polarising 994.2.3 Offset mho characterisitic 1004.2.4 The lenticular characteristic 1004.2.5 The quadrilateral characteristic 1014.2.6 Two phase to ground faults (quadrilateral characteristic 1024.2.7 The offset quadrilateral 1044.2.8 Operate and polarising signals LFZP11x 1054.3 Level detectors 1204.3.1 Introduction 1204.3.2 Inhibition of the comparator 120

4.3.3 Single pole tripping 1214.3.4 Phase section 1214.3.5 Other level detectors 1224.4 Directional overcurrent ground fault protection (DEF) 1274.4.1 Introduction 1274.4.2 Implementation 1274.4.3 Directional elements 1274.4.4 Level detectors 1284.4.5 Operation in single pole tripping schemes 1284.4.6 Operation with voltage transformer supervision 1284.4.7 Magnestising inrush current detector 128

4.4.8 Polarising 1294.4.9 Negative sequence filters 1294.4.10 Directional overcurrent backup protection 1294.5 Fault locator 1354.5.1 Introduction 1354.5.2 Basic theory for ground faults 1364.5.3 Data acquisition 1384.5.4 Cyclic buffer processing 1394.5.5 Fourier filtering 1414.5.6 Distance to fault calculation 1414.5.7 Mutual compensation 1454.5.8 Metering 1455 SCHEME FUNCTIONS 1505.1 Level detector pole dead logic 1505.2 Voltage transformers supervision (VTS) 1525.2.1 Purpose 1525.2.2 Principle of operation 1525.2.3 Outputs 1525.2.4 Implemetation 1525.2.5 Level detector settings 1545.2.6 Speed of operation 154

Contents Page

5.2.7 Seal-In of block and resetting 154

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5.2.8 Operation for indication only 1555.2.9 Operation with line side voltage 1555.2.10 Operation with busbar voltage transformers 1555.2.11 Operation with single pole tripping 155

5.2.12 Operation during line energisation with a voltage supplyfault present line VTs 156

5.2.13 Operation with weak infeed schemes 1565.2.14 Operation with MCB 1565.2.15 Operation with DEF 1575.3 Comparator level detector checks 1575.4 Swith on to fault logic (SOTF) 1595.5 Power swing blocking (PSB) 1625.6 Standard schemes in optimho distance 1685.7 Basic scheme and loss of load accelerated tripping 1695.7.1 Basic scheme 169

5.7.2 Loss of load acceleated trip feature 1705.8 Zone 1 extension scheme 1745.9 Permissive undereach scheme (PUR) 1745.10 Permissive overreach scheme (POR 1) 1775.11 Permissive overreach scheme (POR 2) 1795.12 Permissive overreach scheme with weak infeed tripping

(POR 2 WI) trip 1835.13 Unblocking permissive trip scheme 1865.14 Blocking schemes 1875.14.1 Blocking scheme 1875.14.2 Blocking 2 scheme 188

5.15 Current reversal logic 1925.15.1 Current reversal POR 1 scheme 1925.15.2 Current reversal POR 2 schemes 1945.15.3 Current reversal blocking scheme 1945.15.4 Current reversal blcoking 2 scheme (Figure 5-20B) 1945.12.5 Current reversal DEF FOR 1, POR 2 schemes 1955.15.6 Current reversal DEF blocking scheme 1955.15.7 Current reversal DEF blcoking 2 scheme 1965.1 Bandpass filter, memory and comparator count control logic 2055.17 Trip latching logic 2055.18 Block auto-reclose logic 2085.19 external fault locator start logic 2086 MODULE AND BOARD DESCRIPTIONS 2116.1 Self-monitoring 2116.1.1 Introduction 2116.1.2 Analogue circuits 2116.1.3 Digital bus intergrity 212

Contents Page

6.1.4 Memory checks-RAM and EEPROM 2156.1.5 Watch-dog monitoring 2156.2 Main microcontroller software 223

6.2.1 Introduction 2236.2.2 Initialisation 223

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6.2.3 Main loop 2246.2.4 Timers 2246.2.5 Input routine 2286.2.6 Output routine 229

6.3 Power supply unit GJ0236 2316.3.1 Introduction 2316.3.2 Operation 2326.4 Main microcontroller board ZJ0138 2346.4.1 Versions 2346.4.2 Introduction 2346.4.3 Operation - computer system 2356.4.4 Main microcontroller 2366.4.5 Slave microcontroller - timers 2366.4.6 Identifier circuit 2366.4.7 Transceiver and latch circuits - external bus control 237

6.4.8 External control lines - RD, WR, RS and R/W 2376.4.9 EEPROM - non-volatile memory 2386.4.10 Serial communication 2386.4.11 Monitor circuits 2396.4.12 Clock reference circuit 2396.4.13 Accessing external memory - bus cycle timing 2406.5 Front Module GJ0240 (board ZJ0137/ZJ0166 2446.5.1 Versions 2446.5.2 Mechanical 2446.5.3 Liquid crystal display 2446.5.4 Keypad operation 245

6.5.5 Address/Data Bus Checking Circuit 2466.5.6 Parallel Port 2466.5.7 Indication LED’s 2496.5.8 Serial port 2496.6 Optical isolator board ZJ0133 2516.6.1 Introduction 2516.6.2 Voltage rating 2516.6.3 Implementation 2516.7 Input module GJ0233 2536.7.1 Introduction 2536.7.2 Voltage input circuits 2536.7.3 Current Input circuits 2556.7.4 Optional current circuits 256

Contents Page

6.7.5 Input module calibration 2576.8 Level detector doard ZJ0136 2636.8.1 Introduction 2636.8.2 Implementation 2636.8.3 Voltage level detectors 2646.8.4 Phase current level detectors 2646.8.5 Neutral current level detectors 264

6.8.6 DEF level detectors (If DEF fitted 2656.9 Zone 1/Zone 2 mho comparator board(ZJ0130) 267

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6.9.1 Introduction 2676.9.2 Operation 2676.10 Zone 3/Zone 6 offset lenticular comparator board (ZJ0131) 2726.10.1 Introduction 272

6.10.2 Operation 2726.11 Zone 1/Zone 2/Zone 3 quadrilateral comparator board (ZJ0132) 2776.11.1 Introduction 2776.11.2 Operation 2776.12 Directional overcurrent ground fault protection board (ZJ0139) 2846.12.1 Introduction 2846.12.2 Comparators 2846.12.3 Comparator input signals 2846.12.4 Directional overcurrent backup protection 2866.12.5 Magnetising inrush current detector 2866.13 Fault Locator module GJ0277 288

6.13.1 Introduction 2886.13.2 80C 186 processor 2886.13.3 Memory 2896.13.4 Data and address line buffering 2896.13.5 Eight channel 12 bit data acrquisition system 2896.13.6 Watch-dog timer and reset circuit 2916.13.7 Eight bit parallel communication to protection 2916.13.8 Mode link connections 2916.10.9 Test serial I/O port 2926.13.10 Test eight bit parallel output port 2926.14 Output relay board ZJ0140 294

6.14.1 Mechanical arrangement 2946.14.2 Circuit operation description 2946.14.3 Noise suppression 2966.14.4 Contact connections to terminal block 2976.14.5 Operating time and power dissipation 2976.14.6 Output option 2976.14.7 Monitor option 297

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7 TECHNICAL DATA 301

7.1 Input ratings 3017.2 Maximum overlaid ratings 3017.3 Burdens 3027.4 Distance elements 3027.4.1 Settings 3027.4.2 Accuracy of distance elements 3057.4.3 Current sensitivity 3057.4.4 Timers 3057.4.5 Polarising 3067.4.6 Operate and reset times 3067.5 Switch on to fault (SOTF) 315

7.6 Voltage transformers supervision (VTS) 3167.7 Power swing blocking (PSB) 3167.8 Block auto-reclose 3167.9 Current transformer requirements 3177.10 Directional earth fault (DEF) 3177.11 Fault location and instrumentation 3217.12 Output contacts 3227.13 Dimensions 3267.14 Serial communications 3267.15 Environmental withstand 3267.16 Mechanical durability 327

7.17 Voltage withstand 3277.18 High voltage withstand 3277.19 Electrical Environment 3278 OPTIMHO DISTANCE RELAY EXTERNAL CONNECTIONS 3288.1 Power supply (Vx1) 3288.2 AC voltage 3288.3 AC current 3288.4 Optical isolators 3288.4.1 Breaker open 3298.4.2 Relay blocked 3298.4.3 Single pole open 3328.4.4 Unblocking schemes 3328.5 Serial communications port 3328.6 Output connections 3338.6.1 Output relays for LFZP111 without DEF 3348.6.2 Output relays for LFZP111 With DEF 3358.6.3 Output relays for LFZP112 without DEF 3368.6.4 Output relays for LFZP112 with DEF 3378.6.5 Output relays for LFZP113 3388.6.6 Output relays for LFZP114 without DEF 3398.6.7 Output relays forLFZP114 with DEF 341

Contents page

8.6.8 Reserved 343

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8.6.9 Abbreviations used in contact names 344

FIGURES

Figure 1-1 Selection chartFigure 1-2 Electrical structure LFZP 11x seriesFigure 2-1 “Quiet”processing areaFigure 2-2 Module earthing arrangementFigure 3-1 Front panelFigure 3-2 Typical fault record print out for relay without fault locatorFigure 3-3 Typical fault record print out for relay with fault locatorFigure 3-4 Data transfer within optimhoFigure 3-5 Operation of setting trapFigure 3-6 Typical settings print out (LFZP 11x with DEF & fault locatorFigure 3-7 Serial communications hardware connections

Figure 4-1 Sequence comparator voltages for mho characteristicsFigure 4-2 Comparator logic variablesFigure 4-3 Action of counter in comparatorFigure 4-4 Effect of high-frequency interferenceFigure 4-5 Effect of exponentialoffsetFigure 4-6 Sequence comparatorFigure 4-7 Action of synchronous polarisingFigure 4-8 Resistive expansion of partially cross - polarised mhoFigure 4-9 Zone 1/1X.1Y/2 polarising arangement LFZP 111/112/113/114Figure 4-10 Comparison of polarised characteristicsFigure 4-11 Critical angle

Figure 4-12 Critical angleFigure 4-13 Synchronous polarising healthy live line conditionsFigure 4-14 Synchronous polarising faulty line conditionsFigure 4-15 Sequence comparator voltages for offset mho characteristicFigure 4-16 Lenticular characteristicFigure 4-17 Lenticular charac eristic block diagramFigure 4-18 Quadrilateral Zone 1Figure 4-19 Behaviour for a-b-g faultFigure 4-20 Guard Zone logicFigure 4-21 Quadrilateral Zone 3Figure 4-22 Level detector gating of distance comparatorsFigure 4-23 Level detectorFigure 4-24 Level detector inhibiting of distance comparatorsFigure 4-25 Biased reference levelFigure 4-26 Biased neutral current level detectorsFigure 4-27 Simplified DEF block diagramFigure 4-28 DEF control & backup logicFigure 4-29 Simplified DEF inhibit and control logicFigure 4-30 Principle of magnetising inrush detectorFigure 4-31 Adaptive negative sequence filtersFigure 4-32 Two machine equivalent circuitFigure 4-33 Superimposed symmetrical components sequence diagram for A-N faultFigure 4-34 Optimho fault locator data selection

Figure 4-35 Optimho fault locator data windowsFigure 4-36 Optimho fault locator selection of fault current zero

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Figure 6-22 Inhibit comparator controller ZJ0131Figure 6-23 Zone 1/Zone 2/Zone 3 quadrilateral ZJ0132Figure 6-24 Directional inhibit and Z1 guard Zone logic ZJ0132Figure 6-25 Sidelines & pole dead inhibits forward & reverse inhibits ZJ0132

Figure 6-26 DEF ZJ0139Figure 6-27 Fault locator ZJ0165Figure 6-28 Output relay board for ZJ0140 & ZJ0140 003Figure 6-29 Output relay board ZJ0140 002Figure 6-30 Output contact connections to terminal blocksFigure 7-1 Zone 1 typical operating timesFigure 7-2 Zone 1 typical operating timesFigure 7-3 Zone 1 typical operating timesFigure 7-4 Zone 1 typical operating TimesFigure 7-5 Zone 1 typical operating timesFigure 7-6 Zone 1 typical operating times

Figure 7-7 Zone 1 typical operating timesFigure 7-8 Zone 1 typical operating timesFigure 7-9 Zone 1 typical operating timesFigure 7-10 Zone 1 typical operating timesFigure 7-11 Zone 1 typical operating timesFigure 7-12 Zone 1 typical operating timesFigure 7-13 Zone 1 typical operating timesFigure 7-14 Zone 1 typical operating timesFigure 7-15 Zone 1 typical operating timesFigure 7-16 Zone 1 typical opearting timesFigure 7-17 IEC Characteristics(time multiplier=1

Figure 7-18 American characteristics (time multiplier=1Figure 7-19 Arrangement & outline panel mounting horizontalFigure 7-20 Arrangement & outline rack mountingFigure 7-21 Arrangement & outline panel mounting verticalFigure 8-1 Typical external connection diagramFigure 8-2 Typical external connection diagram with mutual zero sequence input

Appendix A Optimho menu treeGlossary

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Section 1. INTRODUCTION

1.1 General

Optimho is produced in several models, each suitable for a specific range of applications. The LFZP 11x group of relays provide protection for high voltagetransmission lines and underground cables. Table 1 provides a summary of the featuresof the LFZP 11x series. Selection of the appropriate model for the application involvedmay be aided by the use of the selection chart, Figure 1-1. The complete range of relays is detailed in Publication R4056.

1.2 Features

The LFZP 11X range of the Optimho relays provide the following features :

a) Full scheme distance relay with 18 measuring elements.

b) Phase and ground distance protection.

c) Typical operating time one cycle for three phase faults.

d) Integral user interface for easy access to relay settingand fault records.

e) Provision for remote communication if required.

f) Provision for eight independent groups of settings.

g) Four previous fault records are stored.

h) Optional directional earth fault protection.

i) Optional fault location with data recording for post fault analysisand instrumentation functions.

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1.3 Benefits

a) Wide range (see publication R4056) for accuratematching to applications.

b) Remote interrogation reduces the need for site visits.

c) Fault type / location data reduces outage time.

d) Self diagnosis reduces maintenance costs.

e) Vertical case option eases retrofit problems.

f) Can interface with existing scheme logic.

1.4 Operating principles

All models of LFZP11X are full scheme distance relays, having a full set of measuringelements for each main zone of protection.

The measuring elements use micro controllers to produce a direct software equivalent of the phase sequence comparators used in Optimho's forerunners, Micromho andQuadramho. This phase sequence comparator design is well proven, havingaccumulated several thousand relay years of successful operating experience.

The phase sequence comparators and level detectors use logic processing to achieveimmunity from maloperation due to noise, such as harmonic distortion, travelling waveeffects, high and low frequency capacitor voltage transformer transients and currenttransformer saturation. Operation of the phase sequence comparators and leveldetectors can only occur if the input signals are dominated by power frequencycomponents. Filters are used to ensure this dominance and to optimise the operatingtimes.

1.5 Hardware structure

All models are built up from a small range of standard printed circuit boards used asmodular building blocks. All models use the same relay case, power supply unit, andfront panel. The relay hardware is bus-structured to allow printed circuit boards to beplugged into the case in different combinations.

Figure 1-2 is a schematic representation of the electrical structure of the LFZP 11xseries.

The hardware uses several micro controllers to provide the functions of comparators,level detectors, etc. A main micro controller uses the digital bus to read outputs from thesubsidiary micro controllers, read input signals from the outside world via opticallycoupled isolators, communicate with the user interface and perform scheme logic, serialcommunications, monitoring and output contact functions.

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Settings, indications, and fault records are stored in non-volatile memory, i.e.unaffected by loss of dc supply. The layout of the relay case follows the `quiet region'arrangement introduced in Micromho and Quadramho (see Section 2, MechanicalLayout).

All settings and records are accessible from the integral user interface, or if preferred,by the use of a `dumb' terminal connected to the serial communication socket on therelay front panel. It is also possible to communicate with the relay remotely via the rearmounted modem serial communication socket. (see Section 3.13)

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LFZP Model 111 112 113 114

PhaseDistance ∗ ∗ ∗ ∗

Ground Distance ∗ ∗ ∗ ∗

DEF o o oFault Location with o o o oMutual Com ensation

Overhead Lines ∗ ∗ ∗

Under round Cables ∗

No. of Distance elements 18 18 18 12Z1 Z1 Z1 Z1

Inde endent Zones Z2 Z2 Z2 Z2Z3 Z3 Z3

Reach Ste ed Zones Z1 Z1 Z1 Z1Z1Y Z1Y Z1Y Z1Y

Sin le Pole Tri in ∗ ∗ ∗ ∗

VT Su ervision ∗ ∗ ∗ ∗

Power Switchin Blockin ∗ ∗ ∗

Loss of Load Accelerated ∗ ∗ ∗ ∗

Tri FeatureNo. of out ut contacts 24 24 24 24

SchemesBASIC ∗ ∗ ∗ ∗

Z1 EXTENSION ∗ ∗ ∗ ∗

PUR ∗ ∗ ∗ ∗

PUR UNBLOCK ∗ ∗ ∗ ∗

POR1 ∗ ∗ ∗ ∗

POR1 UNBLOCK ∗ ∗ ∗ ∗

POR2 ∗ ∗ ∗

POR2 WI TRIP ∗ ∗ ∗

POR2 UNBLOCK ∗ ∗ ∗

POR2 WI TRIP UNBLOCK ∗ ∗ ∗

BLOCKING ∗ ∗ ∗

BLOCKING 2 ∗ ∗ ∗

Distance CharacteristicZ1,Z1X,Z1Y,Z2 Phase m m m mZ1,Z1X,Z1Y,Z2 Ground /m m m mZ3 Phase L L LZ3 Ground L L L

DEF PolarisinNe . Se . Volts ∗ ∗ ∗

Zero Se . Currents ∗ ∗ ∗

Zero Se . Volts ∗ ∗ ∗

Zero Se . Volts+Current ∗ ∗ ∗

* = Standard, o = Optional, m = Shaped mho, q = QuadrilateralQ = Offset quadrilateral/reverse quadrilateral

L = Offset lenticular/ reverse shaped mho

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LFZP114

OPTIONAL DEF

OPTIONAL FAULT LOCATOR

NO YES

LOCATOR

NO


OPTIONAL DEF

LFZP112

POWER SWING BLOCKING

BACK UP FOR REVERSED FAULTS?

BLOCKING SCHEME?

WEAK INFEED POR\UNBLOCKING SCHEME?

ANY OF THE FOLLOWING:

OPTIONAL FAULT

OPTIONAL DEF

LFZP111

YES

NO DEF


LFZP113

FAULT ELEMENTS

QUADRILATERAL GROUND

YES YES

CABLES

UNDERGROUND

LINES

TRANSMISSION

OVERHEAD

TYPE OF SYSTEM

START

(BUT SEE SECTION 4.5.1)

Figure 1-1 Selection chart

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Figure 1-2 Electrical structure LFZP 11x series

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Section 2. MECHANICAL LAYOUT

In order to ensure that the distance protection is unaffected by conditions of severe highfrequency interference, such as can occur in a high voltage substation,

certain precautions have been taken in designing the physical layout. These are:-

a) Separation of interface functions from measuring and control functions. Theinterface modules/boards occupy the right and left hand side of the subrackand provide isolation between all connections with the outside world andthe measuring and control circuitry which occupies the central section of thesubrack (see Figure 2-1). The interface modules/boards provide galvanicisolation to 5kV peak and filter out high frequency common-mode andtransverse-mode noise signals. The measuring and control circuits thereforeoperate in a relatively quiet electrical environment. The need for galvanicisolation of circuits in the quiet space is eliminated and so the relay internal

d.c. supply centre rail is connected to the case. The case earth stud is in turnconnected to the relay room earth.

b) Within the ac current and voltage input module, isolating transformers havescreens to minimise primary to secondary capacitance coupling, therebyattenuating common-mode interference.

The efficiency of any screen is defined more by the electrical strength of theconnection to the common rail or earth than by the design of the screenitself, so the transformers are mounted on a metal plate and thetransformer screens are connected directly to this plate by short thick wires.

This ensures a low inductance between the screens and earth. A lowinductance is more important than low resistance because of the high ratesof rise of currents that exist in screen connections under interferenceconditions.

The screen plate itself is connected to the relay case earth by a wide wipingcontact attached to the top of the module frame.

c) Three different categories of currents flow to earth. These are signalcurrents, power supply currents and screen surge currents. To eliminatecross-coupling effects, these are conducted by separate paths to the case

earth stud. For convenience, the signal and power supply earth's areconnected to a common ground plane on the PCB backplane which isemployed to provide interconnection of module signals. The ground planealso affords good screening of the intermodule connections. The groundplane is connected to the relay case at one mounting point. Fig 2-2 showsthe basic schematic of the relay earthing and screening arrangements andpaths of current flow for some typical common mode surges.

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OUTPUT

INPUT/ PROCESSING AC

INPUT

FRONT VIEW (PANEL REMOVED)

Ribboncable

1 2 3 4 56

789

10

11

12

13

Area AreaInterfaceInterface

"Quiet" Area

Figure 2-1 "Quiet" processing area

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Figure 2-2 Module earthing arrangement

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Section 3. OPERATING INSTRUCTIONS

3.1 User Interface

The operator interface of the Optimho LFZP range of relays consists of:

a) A two line by 16 character liquid crystal display (LCD).b) A seven key keypad.c) Two serial communication ports (front mounted designated LOCAL,

rear mounted designated MODEM).d) A parallel printer/test port.e) Three indication light emitting diodes (LED) designated TRIP (red), ALARM

(yellow) and RELAY AVAILABLE (green).

The operator interface is used to enter settings and obtain information from the relay.

The front panel is shown in Figure 3-1.

3.1.1 Keypad

The keypad consists of four cursor (arrow) keys mounted in a cruciform pattern, a RESETkey, a SET key and a ACCEPT/READ key. With the transparent front cover in position,only the RESET and ACCEPT/READ keys can be operated via the push buttons mountedon the transparent front cover.

Removal of the front cover is necessary to gain access to the four cursor keys and theSET key. No aspect of the relay operation can be changed without using these keys,

provided the serial communications facility is not in use.

The function of each cursor key is as follows:

UP arrow key move up in the menu or one step of a setting.DOWN arrow key move down in the menu or one step of a setting.LEFT arrow key move left in menu.RIGHT arrow key move right in menu or execute and confirm

command.

The SET key is used to :

a) Update setting changes.b) Clear fault records.c) Execute certain commission tests.

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The RESET key is used to :

a) Clear LCD and LED indications after a protection trip, start, or powerswing has occurred.

b) Reset the VT supervision alarm contact, LCD and LED indication, andoptional block, after a voltage supply failure has occurred and hassubsequently been corrected.

c) Ignore any newly entered settings.d) Scroll information groups when in View/Scroll mode.e) Log off serial communications.

The ACCEPT/READ key is used to :

a) Page fault data information.B) Accept alarms.

c) Scroll through data contained in information groups when inView/Scroll mode.

3.1.2 Serial port

Each serial port enables communication via a remote terminal or computer. The rear(MODEM) port is provided primarily for communication over telephone networks usinga modem. The front (LOCAL) port is provided primarily for communication via acomputer in order to load settings or extract records.

3.1.3 Parallel port

The parallel port is used for driving a local printer or parallel I/O connectedtest/monitoring equipment.

3.1.4 Indication LED's

The indication LED's work in conjunction with the LCD to display the current status of therelay.

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3.1.5 Relay available LED

Under normal working conditions the RELAY AVAILABLE LED is turned on, indicatingthat the relay is healthy and available for protection operation. If the RELAY AVAILABLELED is off, this indicates one of the following conditions:

a) The on-load directional commission test is active.b) The output option commission test is in use.c) A contacts blocked commission option is selected.d) The Relay Blocked opto-isolator is energised.e) Bulk data transfer over serial communications link is in progress. f) An internal failure has been detected. Operation of the protection may

or may not be allowed, depending on the nature of the failure, seeSections 6.1 and 6.2.

g) VT supervision feature set to BLOCKED with VT fuse fail occurrence.

3.1.6 Alarm LED

The ALARM LED is used to signal either :

a) The occurrence of a fault or event which is displayed on the LCD.b) Detection of an internal failure which may be indicated on the LCD.

Generally the ALARM LED flashes for the above conditions until the alarm is acceptedby pressing the ACCEPT/READ key. If the alarm condition is accepted the ALARM LEDwill turn on permanently. For alarms initiated by faults or events on the power systemthe ALARM LED can be turned off either by :

a) Energising the Reset Indications opto-isolator, orb) Pressing the RESET key, provided the alarm has been accepted, i.e. is

not flashing.

A flashing ALARM LED may, under some conditions, revert to being permanently on oroff for the duration of the condition, these conditions being :

a) On-load directional commission test is active.b) Output option commission test is in use.c) Address/data bus failure.

d) Bulk data transfer via serial communications link in progress.

3.1.7 Trip LED

The TRIP LED is turned on when a protection trip has occurred, it can only be turned off when either :

a) The Reset Indications opto-isolator is energised, orb) The RESET key is pressed, provided the ALARM LED is permanently on,

i.e. alarm has been accepted.

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Figure 3-1 Front panel

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3.2 Visual Indication of faults or events

Faults are defined as any condition which causes a trip. Events are defined as anyconditions which do not cause a trip, i.e., starts, relay blocked, VT fuse failure (providedthe appropriate menu option has been set to block tripping) and a power swing

condition (provided the appropriate menu option has been set to block tripping).

Occurrence of a trip is indicated by the TRIP and ALARM LED's. Information about thelatest zone and phase in which the relay tripped is presented on the LCD , and/orwhether the fault was tripped via the DEF elements if this option is fitted. The displayalso indicates whether the trip was time delayed, or aided. Zone information is notgiven for a distance aided trip. The time and date at which a fault or event occurs ispresented as a second page of LCD information which can be read using theACCEPT/READ key.

A trip produced by the switch on to fault logic is denoted by 'SOTF'. No phase

information is normally given, although if the switch on to fault trip occurred onauto-reclosing on to an earlier trip, the previous faulty phase information is retainedtogether with 'SOTF'.

Occurrence of a fault detected by any Zone 2, Zone 3 or forward DEF comparatoroperation is termed a 'start'. If the menu option to enable start indication is selected, thestart event, together with details of the phases and zone or zones which started, areindicated on the LCD and the ALARM LED is flashed. If the menu option to block startindications is selected, no indication is given for any start event. If the relay goes on totrip because of the continued presence of the fault, the start information on the LCD isreplaced by the trip information previously described.

The internal trip and/or start information, from which the LCD and LED visual indicationis produced, is stored in non-volatile memory. If the dc supply to the relay is switchedoff, the visual indication is only temporarily lost, automatically returning when the dcsupply is restored. The LCD and LED's can only be cleared when either an electricalreset is applied via the Reset Indications opto-isolator, or by the RESET key (provided theALARM LED is not flashing, that is when the fault or event condition has been read andaccepted using the ACCEPT/READ key).

If a subsequent trip (or start, if start indication is enabled) occurs before the LCD andLED information from a previous fault is cleared, only the information about the mostrecent fault is displayed. Information about the last four faults or events displayed by therelay is stored in non-volatile memory within the relay. This data can be viewed from theFAULT RECORDS section of the menu.

For relays fitted with the optional fault locator, an additional 18 pages of LCDinformation is available. The third page gives the fault location as a percentage of theline length, or in miles or in kilometres, together with the duration (period) of the fault.

The remaining 17 pages detail the pre-fault and fault voltage and current values. Forcertain fault conditions the calculated period, pre-fault voltage and/or pre-fault currentmay not be applicable, for these cases 'n/a' is written. Figures 3-2 and 3-3 show typical

fault records. Each page of information can be read in turn by successive presses of the

ACCEPT/READ key. When the last page has been read the display wraps around toshow the first page on the next press of the ACCEPT/READ key. After the third page hasbeen viewed, the ALARM LED stops flashing and from this point it is possible to reset thedisplay by pressing the RESET key. If the fault locator is not fitted or the fault or event

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does not initiate the fault locator measuring elements (i.e. VT fuse fail, power swing,starts (only if blocked), weak infeed trips, or relay blocked), only the first page of faultinformation and the second page of time/date information is available. For these cases,if the fault locator is not fitted; the ALARM LED will stop flashing when the time/datepage is viewed by pressing the ACCEPT/READ key, if the fault locator is fitted; the

ALARM LED will stop flashing when the first page of fault data is reviewed after thetime/date page has been viewed. The fault LCD and LED indications can then becleared by pressing the RESET key, provided the fault or event is not still active.

Detection of a power swing is indicated by the ALARM LED flashing and the message'PwrSwg' on the LCD. If the power swing goes on to cause the relay to trip, the ALARMLED and 'PwrSwg' LCD indications are retained, together with the TRIP LED and the typeof trip on the LCD. Detection of a power swing causes resetting of any previous trip orstart indications. Power swing indications can be suppressed by selecting the 'PwrSwgdetector blocked' menu option.

In the event of operation of the VT supervision feature the ALARM LED flashes, anyprevious fault indication is reset and the message 'V~FAIL' appears on the LCD. If theVT supervision logic has been set to block operation of the relay comparators byselecting the 'TO BLOCK TRIP' VT supervision menu option, the RELAY AVAILABLE LED isextinguished, the Relay Inoperative Alarm contact closes, and the message 'RELAYBLOCKED' appears on the top line of the LCD with the 'V~FAIL' message on the bottomline of the LCD.

Energisation of the Block Relay opto-isolator will cause the ALARM LED to start flashing,reset any previous fault indication, and cause the message 'RELAY BLOCKED' toappear; also the RELAY AVAILABLE LED will extinguish and the Relay Inoperative Alarmcontact will close. In this case, however, when the Block Relay opto-isolator isde-energised, the indications and alarms all self reset.

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Z1YAB

DELAY

1995 Oct. 0613 : 17 : 55

Oldest record

Z1BC

1995 Nov. 1423 : 44 : 31

Z1AN

1995 Dec. 0402 : 05 : 08

Z2BN

DELAY

1995 Dec. 2315 : 34 : 58

Latest record

Figure 3-2 Typical fault record print out for relay without fault locator

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Z1AN

Note, only one record shown.

1995 OCT. 0108 : 54 : 20

LOC.= 60.1 %PERIOD = 45 ms

PRE - FAULT Va63.50 KV / 0.0°

PRE - FAULT Vb

63.50 KV / -120°

PRE - FAULT Vc63.50 KV / 120°

PRE - FAULT Ia1.0 KA / -10.0°

PRE - FAULT Ib1.0 KA / -130.0°

PRE - FAULT Ic1.0 KA / 110.0°

FAULT Va36.73 KV / -1.8°

FAULT Vb63.50 KV / -120°

FAULT Vc63.50 KV / 120.0°

FAULT Vo7.643 KV / 178.9°

FAULT V27.717 KV / -179.9°

Figure 3-3 Typical fault record print out for relay with fault locator

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FAULT Ia3.67 KA / -85.4°

FAULT Ib

1.0 KA / -130.0°

FAULT Ic1.0 KA / 110.0°

FAULT Io1.224 KA / -85.4°

FAULT I21.223 KA / -85.4°

FAULT Im0.223 KA / -85.4°

Figure 3-3 continued .

3.3 View/scroll relay settings/data

Menu scrolling of settings/data is available via the use of the RESET and READ keys. Thescrolling feature is only active when the relay display is at the root or default level, thatis, when the display page shows one of the following :

' '' ' (A blank display)

or '.OPTIMHO ' (User identifier string of up to 32' ' characters)

or 'ACTIVE SETTINGS ' Active setting group selected)'GROUP = 1 '

or 'Please set ' (If clock has not been set)'CALENDAR CLOCK '

or 'PwrSwg TEST ' (If commission test option selected)'ENABLED '

or 'Contacts blocked ' (If commission test option selected)' '

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or 'ERROR# SLOT No 1 ' (Diagnostics message indicates slot'5 6 7 8 9 10 11 ' number of faulty board/s)

or 'ERROR# I~FAIL ' (Diagnostics message if anomalous' ' current condition detected i.e. Neutral

current flowing for no obvious reason)

In order to clarify the setting/data information stored within the relay, the information issegregated and grouped under the following sections :

LAST FAULTLAST FAULT −1LAST FAULT −2LAST FAULT −3METERING (Only if fault locator fitted)IDENTIFIERS

CALENDAR CLOCK COMMUNICATIONSCONTACT CONFIG−

SCHEMEDISTANCEBLOCK AUTO RECLOSEVT SUPERVISIONSTART INDICATIONDEF (Optional for LFZP 111, 112 & 114)FAULT LOCATOR (Optional)

Pressing the RESET key (from one of the above default display pages) will bring up thedisplay :

'View / Scroll ''LAST FAULT '

Repeated presses of the RESET key will scroll through the above list of informationgroups.

To view settings or information contained in each group the READ key is pressed. Thefirst setting of the group is then displayed. Repeated presses of the READ key will scrolleach setting in turn. The order in which settings are presented is as listed in the menutree (Appendix A). When the last setting/data item of a particular group has beenviewed, a wrap around feature will display the first setting/data item on the next pressof the READ key. When the RESET key is pressed the display returns to the root ordefault level. When the last group option (i.e. FAULT LOCATOR, if fault locator is fitted)has been scrolled through using the RESET key, the display returns to the root or defaultlevel.

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3.4 Menu system

The operator interface operates on the tree like menu system shown in Appendix A.Each item in a branch of the menu forms a page of information when it is displayed on

the LCD,

e.g., 'OPTIONS''CALENDAR CLOCK'

is a page of information.

The cursor (arrow) keys are used to move around the menu tree, enabling the user to :

a) Change settingsb) Execute commands

c) Reconfigure the relay during commissioningd) View settings

3.4.1 Default level

The top of the menu tree is designated the default level. When the operator interface isnot in use the liquid crystal display will always show an appropriate default page. Thenormal default or root page will be as selected in the

'OPTIONS ''IDENTIFIERS '

section of the menu. This will be either a blank page, a group identification string of upto 32 characters which has been entered by the user (see Section 3.10) or,the active setting group number selected. Under certain conditions, as indicated below,the root page may be replaced by one of the following default pages which are listed ina hierarchical order, item a) having the highest precedence :

a) 'Serial Comms ' If serial communications is logged on.Note, serial communications can only log onwhen either a root page or one of the defaultpages b) to h) below are displayed.

b) 'Push SET to ' Only if setting changes have been made.'update changes '

or'Push SET to ' Only if active setting group no. has'update group ' been changed.

c) 'Z1 ' Fault or event information.'AN V ∼ FAIL '

d) 'PwrSwg TEST 'If the power swing test commission'ENABLED 'option has been selected.

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e) 'Contacts blocked 'If either the 'contacts blocked' or'the 'contacts blocked except any trip'commission options have been selected.

f) 'ERROR # SLOT No 1 'Diagnostic information, if any faults have

'5 6 7 8 9 10 11 ' been detected.

g) 'ERROR # I ∼ FAIL ' Diagnostic information, if anomalous' condition has been detected .

h) 'Please set ' If power up reset has occurred.'CALENDAR CLOCK '

3.4.2 Timeout feature

If no key is pressed within a 15 minute interval, an appropriate root or default page isautomatically selected.

3.4.3 Multiple setting groups

The currently active working relay settings constitute a setting group. Eight independentsetting groups can be stored within the relays non-volatile (EEPROM) memory. Eachsetting group can be pre-programmed and then selected to become the active workingsetting group by a menu option to select the group number required.

The concept of multiple setting groups is a recent innovation made possible since allsettings are stored in non-volatile (EEPROM) memory, rather than being linked to theposition of setting switches, as was the case with earlier relays. The ability to quicklyreconfigure the relay to a new setting group may be desirable if changes to the systemconfiguration demand new protection settings. For instance, maintenance outage timemay be reduced by substituting a spare relay, pre-programmed with setting groupswhich match a number of different relays, and selecting the setting group required.

Changing setting groups

The active setting group selection is made from the

'OPTIONS ''ACTIVE SETTINGS '

section of the menu. The method used to change any setting within the relay is ageneral one and is applicable to all setting changes, refer to Section 3.4.6 (Operatingthe Menu). Before any setting group change is implemented the user is requested forconfirmation at a 'group trap' page when exiting from the menu back to the defaultlevel.

From the 'group trap' page :

'push SET to ''update group '

the user has the option of :

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a) pressing the SET key to confirm the setting group change, thisreconfigures the relay to the new setting group.

orb) pressing the RESET key to ignore the setting group change.

orc) pressing the RIGHT arrow key to re-enter the menu.

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If the SET key is pressed, the page :

'settings group ''updated '

appears. From this page, pressing the LEFT or RIGHT arrow keys steps the user to :


If the RESET key is pressed, the page :

'settings group ''change ignored '

appears.

From this page, pressing the LEFT or RIGHT arrow keys steps the user to :


If the RIGHT arrow key is pressed, the page :


is stepped to. Notice that the UP/DOWN keys have no effect from this page until thegroup change has been confirmed or ignored by pressing SET or RESET from the grouptrap page. This restriction prevents the settings from within a group being changedwhilst confirmation of a group change is still pending.

Active settings group as a default page

If required, the active settings group page can be displayed as a default page byselecting this option from the DEFAULT DISPLAY section of the IDENTIFIERS section of the menu. This feature may be useful for commissioning purposes in order to easilyconfirm the currently selected setting group.

Factory default settings

All relays leave the factory with the active setting group number set to 1. For those usernot requiring multiple setting groups it is strongly recommended that the active settinggroup number be left unchanged.

Changing or reading active setting group values via remote serial comms.

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The GECA T&D PC based communications program 'Opticom' (Publication numberR-5928) has been specifically developed to run under MS-DOS 3.2 or above tofacilitate remote communications with Optimho. Opticom enables the user to send andretrieve settings and data from a remote relay, it also allows the user to manipulate anyof the relays 8 setting groups.Opticom enables the user to send and retrieve settings

and data from a remote relay, it also allows the user to manipulate any of the relays 8setting groups. For information on the application of Optimho over K-Bus seepublication R8532, KITZ103.

3.4.4 How settings and records are stored

There are 3 distinct areas of memory used to store relay settings and records,these are :

a) Working RAMb) Scratchpad RAM

c) EEPROM (Electrically programmable and erasable ROM)

Working RAM

This area of memory stores all the settings to which the relay is actually set.

Scratchpad RAM

This area of memory holds a temporary copy of all the most recent setting changesmade prior to updating the changes. If these recent setting changes are confirmed, theScratchpad RAM is copied to the Working RAM. If the recent settings changes arecancelled, the temporary Scratchpad RAM copy is over written with a copy of theWorking RAM.

EEPROM

This area of memory is non-volatile, that is, it maintains the information stored within iteven if the dc supply is removed. This area of memory is copied to the Working RAMafter a dc power up, but only written to, and read from, if settings changes are updatedor a fault condition occurs.

Figure 3-4 illustrates how the transfer of settings and records between each area of memory is implemented for each of the following conditions :

a) DC power upb) Updating recent changesc) Cancelling recent changesd) Storing fault records

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3.4.5 Setting trap

In order to implement all setting changes at once, a so called 'setting trap', as illustratedin Figure 3-5, is used. The default display page :

'Push SET to ''update changes '

appears if setting changes have been made, whenever the user exits from the menutree.

At this point the user has three options, these are :

a) Push SET key to update settings changes, this reconfigures the relay tothese changes and stores the changes in working RAM memory and non-volatile EEPROM memory.

orb) Push RESET key to cancel and ignore all recent setting changes, orc) push the RIGHT arrow key to move back into the menu.

If the SET key is pressed, the confirmation display page :

'all changes ''updated '

appears. From this page, pressing the LEFT arrow key returns the user to the rootdisplay or a default display if a default condition is active, pressing the RIGHT arrow keysteps the user to :-

'OPTIONS ''PRINT '

(Note, this page is located in the menu above the setting trap)

If the RESET key is pressed, the display page :

'all changes ''ignored '

appears. From this page, pressing the LEFT or RIGHT arrow keys has the same effect asabove.



is stepped to. Notice that this page is the first page in the menu tree immediately belowthe setting trap. This page is stepped to because at this stage no commitment has been

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taken to update or ignore the setting changes made. The menu sections ACTIVESETTINGS, PRINT, FAULT RECORDS and METERING (if Fault Locator fitted) are alllocated above the setting trap and as such are unavailable until the current changes areeither updated or ignored by pressing SET or RESET at the setting trap.

3.4.6 Operating the menu

The four cursor (arrow) keys are used to navigate around the menu tree. The function of each key is to move the user one step at a time in the direction of the arrow for eachpress of the key. A key press repeat feature will automatically initiate successive keypresses at about a rate of 1 press per second if a key is maintained pressed. Thefollowing examples illustrates how the cursor keys are used to navigate around themenu and change a setting.

Example 1 - Setting contact configuration

From the root or default page,

1) Press RIGHT arrow key to step to :


2) Press DOWN arrow key to step to :

'OPTIONS ''PRINT '


'OPTIONS ''FAULT RECORDS '


'OPTIONS ' (Only if Fault Locator fitted).'METERING '



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'OPTIONS ''CALENDAR CLOCK '


'OPTIONS ''COMMISSION TESTS'


'OPTIONS ''COMMUNICATIONS'


'OPTIONS ''SETTINGS '

(Note, in this instance it would have been quicker to press the UP arrow key from thepage :


since the presentation order of pages in the menu tree automatically wraps aroundfrom bottom to top or top to bottom).


'SETTINGS ''CONTACT CONFIG '


'CONTACT CONFIG- ''URATION NO. 01 '

12) Press RIGHT arrow key to obtain above page with alternating up/down arrowafter CONFIGURATION NO. 01.

Note that settings can only be changed when the alternating up/down arrow isshowing.

13) Press DOWN arrow key to select :

'CONTACT CONFIG ''URATION NO. 02 '

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Note: in this case, Contact configuration No.1 is the actual relay setting held incurrent memory and non-volatile memory. Changing this setting toCONFIGURATION NO. 02 does not change the actual relay setting at thisstage. Instead, the new setting is held in temporary memory and is onlytransferred to the current memory and non-volatile memory if the user

confirms the update of settings, at the setting trap, when exiting the menu. The mechanism used is described in step 17) below.

14) Press LEFT arrow key to remove alternating up/down arrow.

15) Press LEFT arrow key to step to :

'SETTINGS ''CONTACT CONFIG '


'OPTIONS ''SETTINGS '



Note, this is the settings trap default page which appears whenever any setting changeshave been made. At this point the user has the option of :

a) pressing the SET key to confirm the setting changes, reconfigure the relayto these changes and store the changes in the current memory andnon-volatile memory.

orb) pressing the RESET key to ignore setting changes. orc) pressing the RIGHT arrow key to re-enter the menu.

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appears. From this page, pressing the LEFT arrow key steps the user back to the rootdisplay or a default display if a default condition is active, pressing the RIGHT arrow keysteps to :-



'all changes '

'ignored '




is stepped to. Notice that this page is the first page in the menu tree immediately belowthe setting trap. This page is stepped to because at this stage no commitment has beentaken to update or ignore the setting changes made. The menu sections ACTIVESETTINGS, PRINT, FAULT RECORDS and METERING (if Fault Locator fitted) are alllocated above the setting trap and as such are unavailable until the current changes areeither updated or ignored by pressing SET or RESET at the setting trap.

Example 2 - Setting the time and date

When the relay is first powered up the default display page will be :

'Please set ''CALENDAR CLOCK '

provided no higher priority default conditions are active. Since this page will always bedisplayed whenever the relay is powered up the menu treats this condition as a specialcase by stepping the user directly to the CALENDAR CLOCK branch of the menu,instead of the PRINT section, when the RIGHT arrow key is pressed.

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From the default display page :


1) Press RIGHT arrow key to move to :



'CALENDAR CLOCK ''READ TIME & DATE '

3) Press DOWN arrow key to move to :

'CALENDAR CLOCK ''SET TIME & DATE '


'SET TIME & DATE ''SET YEAR 1995 '

5) Press RIGHT arrow key to obtain above page with alternating up/down arrowafter 1995. Note that settings can only be changed when the alternatingup/down arrow is showing.

6) Press UP or DOWN arrow key to increment or decrement the year value.

An acceleration feature is provided to speed up numerical setting changeswhen the UP or DOWN keys are held pressed.

Note, the value 1995 is the actual relay setting held in current memory andnon-volatile memory. Entering a new value does not change the actual relaysetting at this stage. Instead, the new value is held in temporary memory. Anychanges to the time/date values are only transferred to current memory whenthe user steps back to the page :


as described in step 13) below. New time/date values are only transferred to non-volatile memory if the user confirms the update of settings when exiting the menu. Themechanism used is described in step 15) below.

7) When the desired year is obtained, press LEFT arrow key to remove thealternating up/down arrow.

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'SET TIME & DATE ''SET MONTH Jan '

9) Press RIGHT arrow key to obtain above page with alternating up/down arrowafter Jan.

10) Use UP or DOWN arrow keys to change month.

11) When the desired month is obtained, press LEFT arrow key to remove thealternating up/down arrow.

12) Repeat the above procedure to set the DAYS, HOURS, MINUTES andSECONDS values.

13) From the page :

'SET TIME & DATE ''SET SECOND 0 '

press LEFT arrow key to step to :


Note, the time and date is set at this point, i.e. when the LEFT arrow key is pressed tostep back to above page.



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Note: this is the settings trap default page which appears whenever any settingchanges have been made. At this point the user has the option of:

a) Pressing the SET key to confirm the setting changes, reconfigure the relayto these changes and store the changes in non-volatile memory. Note,the actual time/date stored at this point is that time at which the SET keyis pressed, this will be the time/date which was set in the CALENDARCLOCK section plus the time interval that has elapsed prior to the SETkey being pressed. The time/date value stored in non-volatile memory isused on setting printouts to indicate when settings were last updated andis also used to restore an initial time/date value when the relay is

powered up. orb) Pressing the RESET key to ignore setting changes. Note, since the

time/date is a special case, the time/date as set in the CALENDARCLOCK section remains active until the dc supply to the relay isremoved. On power up the relay time/date will default to the time/datewhich was recorded when the SET key was last pressed to updatesettings.

orc) Pressing the RIGHT arrow key to re-enter the menu.



appears.

From this page, pressing the LEFT arrow key steps the user back to the root display or adefault display if a default condition is active, pressing the RIGHT arrow key steps to:



'all changes ''ignored '



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is stepped to. Notice that this page is the first page in the menu tree immediately belowthe setting trap. This page is stepped to because at this stage no commitment has been

taken to update or ignore the setting changes made. The menu sections ACTIVESETTINGS, PRINT, FAULT RECORDS and METERING (if Fault Locator fitted) are alllocated above the setting trap and as such are unavailable until the current changes areeither updated or ignored by pressing SET or RESET at the setting trap.

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Data Transfer when Recording Faults or Events

Data Transfer when Setting Changes Ignored

SCRATCHPAD

MEMORY

RAM

SCRATCHPAD

MEMORY

RAM

EEPROM

MEMORY

MEMORY

WORKING

RAM

MEMORY

EEPROM

MEMORY

Data Transfer on DC Power Up

Data Transfer when Setting Changes Updated

SCRATCHPAD

RAM

MEMORY

RAM

MEMORY

SCRATCHPAD

WORKING

WORKING

RAM

RAM

MEMORY

EEPROM

MEMORY

WORKING

RAM

MEMORY

MEMORY

EEPROM

Figure 3-4 Data transfer within Optimho

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Figure 3-5 Operation of setting trap

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3.5 Commission tests

This section of the menu provides necessary test and monitoring facilities forcommissioning the relay. Refer to Commissioning Instructions and Test Features (Section3.14) for more detailed explanations on the use and implementation of these features.

Options provided are :

a) Contact controlb) On load directional testingc) Power swing testingd) Monitor optionse) Output options

3.5.1 Contact control

Options provided are :

a) 'ALL CONTACTS ' This is the normal working setting'ENABLED '

b) 'ALL CONTACTS ' Operation of all relay functions are as'BLOCKED ' normal except for final trip signals issued

to output trip relays which are blocked.

c) 'CONTACTS ' Operation of all relay functions and'BLOCKED EXCEPT ' 'Any Trip' output relay are as normal'ANY TRIP ' except for final trip signals issued to

output trip relays which are blocked.

Note:

1) The above contact options are only active when the SET key is pressed at thesetting trap page :

'push SET to ''update changes '

to reconfigure the relay with the new settings.

2) Provided no other higher priority default messages are active (see Section3.4.1), the default display page :

'Contacts blocked '' '

is displayed at the default level if either of the contacts blocked options b) or c) hasbeen selected.

3) In the event of a dc power up or software reset the contact control option

selected when settings were last updated is restored.

3.5.2 On load directional test

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This test is only active when the SET key is pressed from the page :

'ON LOAD DIR TEST ''push SET to test '

When the test is actioned, by pressing the SET key, the relay is reconfigured to enable itsmeasuring circuits to respond to the test condition (see Test Features Section 3.14). Also,the RELAY AVAILABLE LED is turned off and Relay Inoperative Alarm contact closes.

One of the following three pages will be displayed :

a) 'Fault seen as ''FORWARD '

b) 'Fault NOT seen '

'as FORWARD '

c) 'Test aborted ''check I &/or V '

Page c) will result if any current or voltage level detectors are not picked up.

Note: if the ACCESS LEVEL (COMMUNICATIONS section) is set to LIMITED theON LOAD DIR TEST option feature is not accessible.

3.5.3 Power swing test

Options provided are:

a) 'PwrSwg TEST''DISABLED '

b) 'PwrSwg TEST''ENABLED '

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Note:

1) The above power swing options are only active when the SET key is pressed atthe setting trap page :


2) Provided no other higher priority default conditions are active (see Section3.4.1), the default display page :

'PwrSwg TEST ''ENABLED '

is displayed at the default level if the that option has been selected.

3) Monitor option number 8 is used to monitor the relay response to this test.

4) In the event of a dc power up or software reset the power swing test optionselected when settings were last updated is restored.

3.5.4 Monitor option

This feature allows the status of various internal signals such as level detectors orcomparators to be monitored as discrete logical values (e.g. 0 or 1) either on the LCDor at the PARALLEL port. Refer to Test Features Section 3.14 for a detailed listing of eachoption.

Monitor signals for the option selected are always sent to the PARALLEL port and appearat pins 2 through to 9, the same signals are displayed on the LCD when the monitoroption page is viewed. When viewed on the LCD or measured on the PARALLEL port,the monitor option selected is always active, there is no need to step back through thesetting trap to action a particular option.

Since monitor option signals are always sent to the PARALLEL port, regardless of thecurrent menu display, it may, depending on equipment available, be moreadvantageous to monitor the port signals rather than the LCD signals.

In the event of a dc power up or software reset the monitor option number displayed isthat option which was selected when settings were last updated.

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3.5.5 Output option

Trip testing on individual or groups of output relays can be performed using this option.Refer to Test Features Section 3.14 for a detailed listing of each output option.

Provided contacts have not been blocked by selecting either of the contact controlcommission test blocking options, trip tests are activated whenever the SET key ispressed from the display page :

'push SET to test ''OUTPUT OPT # xx '

The selected output relay/s will remain energised until the SET key is released. If contacts have been set to blocked, the page :

'Contacts blocked '

' '

is displayed and no contacts are energised when the SET key is pressed.

Note:

1) When the page :

'push SET to test ''OUTPUT OPT # xx '

is displayed the relay is taken out of service, the RIA contact closes and thegreen RELAY AVAILABLE LED is extinguished. The relay is put back in servicewhen the <- key is pressed to return to the page :

'COMMISSION TEST ''OUTPUT OPTION '

2) Since the output test option results in a change of relay status when the relayis taken out of service, the 15 minute time out feature, which normally returnsthe relay display to an appropriate default level, is not applicable.

3) If the ACCESS LEVEL (COMMUNICATIONS section) is set to LIMITED theoutput test option feature is not accessible.

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3.6 Communications

3.6.1 Access level

In applications where remote serial communication facilities are used (see Section

3.13), it may be deemed necessary to provide total security against unauthorised accessin order to prevent any changes being made to relay settings. The ACCESS LEVELsetting, which can be set to LIMITED or FULL, provides this security.

When serial communications is logged on to the MODEM (rear) port and the accesslevel is set to LIMITED, all settings can be viewed but only the time and date settings canbe changed. Also, the CLEAR ALL RECORDS option and the commission options for ONLOAD DIR TEST and OUTPUT OPTION are not available. Alteration of time and datevalues is allowed since it may be necessary to reset the time/date in the event of a dcpower failure.

When the serial communications is logged on to the LOCAL (front) port and the accesslevel is set to LIMITED, all settings can be viewed but only the time and date, andACCESS LEVEL settings can be changed. Also, the CLEAR ALL RECORDS option and thecommission options for ON LOAD DIR TEST and OUTPUT OPTION are not available.

When the serial communications is logged on to the MODEM or LOCAL ports and theaccess level is set to FULL, all settings can be viewed and changed.

3.6.2 Serial control

The serial communications feature allows :

a) Fault records to be viewed remotely,b) Settings to be viewed and changed remotely,c) Bulk transfer of settings, fault records and metering information (if fault

locator is fitted) using GEC ALSTHOM T&D Protection & Control PCbased software Òpticom'

Refer to Section 3.13 for information regarding the implementation and use of theserial communication facility.

3.6.3 Active port

Only one of the serial ports, LOCAL or MODEM, can be active at any one time. Thismenu option is used to select either the LOCAL (front) or MODEM (rear) serial controlport as the active port.

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3.6.4 Baud rate

Separate BAUD rate settings are available for LOCAL and MODEM ports.

These are :

300, 600, 1200, 2400 & 4800.

3.6.5 Protocol

Separate protocols are available to set up the bit framing (DATA, PARITY, STOP) forLOCAL and MODEM ports. Protocols available are :

DATA PARITY STOP 8 NONE 1 8 EVEN 1

8 ODD 1 8 NONE 2 7 EVEN 1 7 ODD 1 7 EVEN 2 7 ODD 2 7 NONE 2

3.6.6 Control lines

This option is only applicable to the MODEM (rear) port. If modem control lines CTS(clear to send), DTR (data terminal ready), RTS (request to send) and DSR (data setready) are required, this option should be set to :

'CONTROL LINES ''IN USE '

If modem control lines are not required, this option should be set to :

'CONTROL LINES ''NOT IN USE '

3.6.7 Communications and multiple setting groups

The branch of the menu tree containing all the communication settings (Sections 3.6.1to 3.6.6) appears in each of the setting group's individual menu trees. However thesesettings are common to all the setting groups and are copied into the other settinggroups when a setting group is updated.

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3.7 Fault records

The most recent four records are stored by the relay, the latest being LAST FAULT andthe oldest being LAST FAULT - 3.

3.7.1 Viewing fault records

Fault (or event) records can be viewed using the VIEW/SCROLL feature (see Section 3.3)or by entering the FAULT RECORDS branch of the menu tree. If a fault record haspreviously been cleared the page :

'No record '' '

is displayed when that fault record is viewed.

Viewing fault records with fault locator not fitted

Each fault record comprises two display pages. The first page contains all informationpertinent to the fault or event (except time/date). The second page displays thetime/date of the fault or event. Figure 3-2 shows a typical fault record.

Viewing fault records with fault locator fitted

The fault record will comprise either 2 or 20 pages depending on whether the fault orevent initiated the fault locator measuring elements (see Visual Indication of FaultRecords, Section 3.2). If the fault locator measuring elements were initiated, the faultrecord will comprise 20 pages, otherwise it will comprise 2 pages.

The first page always contains all information pertinent to the fault or event (excepttime/date) obtained from the distance (and DEF if fitted) measuring elements.

The second page displays the time/date of the fault or event.

The third page displays the fault location (in Km, miles or percent) and the period(duration) of the fault.

The remaining 18 pages display the pre-fault and fault voltage and current values.Figures 3-2 and 3-3 show typical fault records.

Note: For certain fault conditions the calculated period, pre-fault voltage and/orpre-fault current may not be applicable, for these cases 'n/a' is written, referto Section 4.5.4 for further details.

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3.7.2 Clearing fault records

The facility to clear fault records is provided primarily to enable all fault records to becleared subsequent to commissioning. Note that :

a) ALL fault records are cleared by the clear records feature.

b) The clear records facility is only available if the ACCESS LEVEL (inCOMMUNICATIONS section) is set to FULL.

To clear all fault records the SET key is pressed from the display page :

'push SET to ''clear all records '

The confirmation display page :

'all records ''cleared '

appears if SET is pressed.

Note: Fault records can be viewed using the view/scroll feature (see Section 3.3).

3.8 Metering

The metering option is only available on relays which have the optional fault locatorfitted.

Primary three phase voltage and current are measured and displayed in magnitude(rms) and phase angle relative to phase A voltage. Real and reactive powers are alsomeasured.

Note: Measured values are relative to the VT and CT ratios set in the FAULTLOCATOR section of the menu.

Metering can be obtained by using the VIEW/SCROLL feature (see Section 3.3) or byentering the METERING section of the menu tree.

If the fault locator PCB is fitted to the LFZP 113 relay for cable applications, it ispossible to use the metering feature. Although the fault locator will also be available,there will be inaccuracy in fault measurement due to the cable capacitance

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3.9 Print option

The print facility can be used in conjunction with either :

a) A parallel printer plugged into the relay PARALLEL port socket,

orb) Remote or local serial communications equipment connected to theappropriate rear or front SERIAL port socket.

Two menu options are available, these are :

a) Print all settings andb) Print fault records.

Settings are printed in the same order as they appear in the menu tree. Fault records

are printed oldest (least recent) first and latest (most recent) last.

Typical printouts for each option are show in Figures 3-2, 3-3 and 3-6.

3.9.1 Printing to the parallel port

Printing is directed to the PARALLEL port provided serial communications is not loggedon. If serial communications is logged on, printing is only directed to the active SERIALport. The active serial port is selected in the COMMUNICATIONS section of the menu.

Appropriate printer connections for the 25 way PARALLEL socket are detailed in Table3-1.

Note: for correct printer operation pin 10 and pins 12 to 21 should not beconnected.

When the -> key is pressed from the LCD display page :

'push -> to print ''all settings 'or'push -> to print ''fault records '

the relay checks if a printer is connected and is 'on line'. If no printer is connected or theprinter is not 'on line' the LCD will display the page :

'printer not ''ready '

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If a printer is connected and is 'on line' the LCD will display the page :

'printing in ''progress '

and printing will commence. Should the printer run out of paper or go 'off line' whilstprinting is in progress the LCD will display the page :

'printer not ''ready '

When the printer goes back 'on line' the LCD will display the page

'printing in ''progress '

and printing will resume.

Printing can be terminated by pressing the <- key to return the LCD display to the page:

'push -> to print ''all settings 'or'push -> to print ''fault records '

When printing is complete the LCD display automatically returns to the page :

3.9.2 Printing to serial port

Printing is only directed to the active SERIAL port when serial communications is loggedon. If serial communications is not logged on, printing is only directed to the PARALLELsocket. The active serial port is selected in the Communications Section of the menu.

Print format is as shown in Figures 3-2, 3-3 & 3-6.

Appropriate connections for the 25 way SERIAL socket are detailed in Table 3-2.

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When the -> key is pressed from the VDU (visual display unit) display :

'push -> to print ''all settings '

or'push -> to print ''fault records '

printing to the VDU will commence. The display can be halted for viewing using CTRL S(X-OFF), and restarted using CTRL Q (X-ON).

When printing is complete, the page :

'type C to continue '

is displayed. Typing C returns the display to

'push -> to print ''all settings '

or'push -> to print ''fault records '

Hard copy printouts can be obtained by capturing the print information sent to the VDUor computer terminal using the VDU or computer terminal memory and then printingthe captured file information. Formatted printouts are available using GECA s software

package Opticom'.

Note: A time out feature will automatically select X-ON if X-OFF is active for morethan 60s.

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Settings printedon : -

CONTACT CONFIG-URATION No 01

Z1 & Z2 SETTINGKZ1Y = 3.00

ALLOW A/R ONZ1X (T) TRIP

1995 Apr. 0109 : 29 : 36

SCHEME SELECTIONBASIC

Z1 & Z2 SETTINGKZ2 = 3.00

ALLOW A/R ONZ1Y (T) TRIP

Settings lastchanged on : -

DEF ELEMENTSALL BLOCKED

ZONE 3 SETTINGOFFSET

BLOCK A/R ONZ2 (T) TRIP

1991 Apr. 0108 : 33 : 47

LOSS OF LOADFEATURE ENABLED

ZONE 3 SETTINGKZ3' = 2.0

ALLOW A/R ONCHANNEL OUT

Group identifieris : -

LL ENABLED BYLS I LEVEL DET

ZONE 3 SETTINGKZ3 = 5.00

ALLOW A/R ONDEF DELAY TRIP

OPTIMHO TYPE OF TRIP3 POLE ONLY

ZONE 3 SETTINGLENT a/b = 0.41

ALLOW A/R ONDEF AIDED TRIP

DISTANCE18 LFZP 087 A

ZONE 1 TRIPPINGENABLED

SWCH ON TO FAULTENABLED

VT SUPERVISION TO BLOCK TRIP

FAULT LOCATOR10 LFZP 100 A

TIME DELAY TRIPZ1X (T) BLOCKED

SWCH ON TO FAULTENABLED IN 0.2 s

SELF RESETTINGENABLED

CLOCK REF.RELAY CRYSTAL

TIME DELAY TRIPZ1Y (T) BLOCKED

SWCH ON TO FAULTBY LD OR COMP

START INDICATIONENABLED

ACTIVE SETTINGSGROUP 1

TIME DELAY TRIPZ2 (T) ENABLED

PwrSwg DETECTORENABLED

DEF LOW SET3Io = 0.01 In

DEFAULT DISPLAYGROUP IDENTIFIER

TIME DELAY TRIP TZ2 = 0.46 s

PwrSwg DETECTOR TIMING Z6--> Z3

DEF ELEMENTSALL BLOCKED

ALL CONTACTSENABLED

TIME DELAY TRIPZ3 (T) ENABLED

PwrSwg DETECTOR TO BLOCK Z1

REACHKZF = 1.00

PwrSwg testDISABLED TIME DELAY TRIP TZ3 = 0.60 s PwrSwg DETECTOR TO BLOCK Z1X LINE UNITS= 100%

MONITOR 23456789OPT 20 00000000

TIME DELAY TRIPALL G ENABLED

PwrSwg DETECTOR TO BLOCK Z1Y

FAULT LOCATORCT Ratio = 1000 : 1

ACCESS LEVELFULL

BASE SETTINGKZPh = 0.800


FAULT LOCATIONVT Ratio = 1000 : 1

ACTIVE PORTLOCAL

BASE SETTING THETA Ph = 70


MUTUAL COMP .ENABLED

MODEM BAUD RATE 4800 BASE SETTINGKZN = 0.800

PwrSwg DETECTOR TZ6 = 50 ms

MUTUAL COMP .KZM = 0.50

DATA PARITY STOP 7 EVEN 1

BASE SETTING THETA N = 70

PwrSwg DETECTORKZ6 = 6.50

MUTUAL COMP . THETA M = 70

CONTROL LINESNOT IN USE

DIST G CHAR'STICMHO

PwrSwg DETECTORKZ6' = 3.5

LOCAL BAUD RATE2400

Z1 & Z2 SETTINGKZ1 = 1.00

PwrSwg DETECTORLENT a/b = 0.41

DATA PARITY STOP 8 NONE 1

Z1 & Z2 SETTINGKZ1X = 2.00

BLOCK A/R ONZ1 + AT 3Ph/F

Figure 3-6 Typical settings print out (LFZP 11x with DEF & Fault Locator)

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Table 3-1Parallel port pin connections

Parallelport pin

Printerconnections

Function name

1 STB (Pin 1) Printer strobe (Output)2 D0 (Pin 2) Data line D0 (Output)3 D1 (Pin 3) Data line D1 (Output)4 D2 (Pin 4) Data line D2 (Output)5 D3 (Pin 5) Data line D3 (Output)6 D4 (Pin 6) Data line D4 (Output)7 D5 (Pin 7) Data line D5 (Output)8 D6 (Pin 8) Data line D6 (Output)

9 D7 (Pin 9) Data line D7 (Output)10 Do not connect Data line D6 RESET key (Input)11 BUSY (Pin 11) Data line D7 Printer Busy (Input)12 Do not connect Data line D5 READ key (Input)13 Do not connect Data line D4 SET key (Input)14 Do not connect Data line D3 LEFT key (Input)15 Do not connect Data line D2 DOWN key ( Input)16 Do not connect Data line D1 RIGHT key (Input)17 Do not connect Data line D0 UP key (Input)18 Do not connect 5v Monitor (Output)

19 Do not connect 12v Monitor (Output)20 Do not connect -12v Monitor (Output)21 Do not connect 12v (Relay) Monitor (Output)22 0v (Pin 22) 0v23 0v (Pin 23) 0v (Note: All 0v are commoned,24 0v (Pin 24) 0v only 1 connection is25 0v (Pin 25) 0v necessary)


Table 3-2a Serial port pin connections for front (LOCAL) socket

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Serialport pin

Function name

1 0v (Ground)2 TXD (Transmit)

3 RXD (Receive)4 Not connected Refer to Figure 3-7 for5 Reserved, do not connect appropriate connections6 Not connected7 0v (Signal ground)

8 to 24 Not connected25 Reserved, do not connect

Table 3-2b Serial port pin connections for rear (MODEM) socket

Serialport pin

Function name

1 0v (Ground)2 TXD (Transmit)3 RXD (Receive)4 RTS5 CTS6 DSR

7 0v (Signal ground)8 Not connected Refer to Figure 3-7 for9 + 12v appropriate connections10 - 12

11 to 19 Not connected20 DTR

21 to 25 Not connected

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3.10 Identifiers

This section of the menu is used to :

a) Enable the user to enter a unique group identification code which can

be up to 32 characters long.b) Read the factory set software version numbers.c) Select either a blank display or the user set group identification code or

the active setting group number as a root default display.

3.10.1 Group identifier

Each settings group has its own unique GROUP IDENTIFIER, but it is important to notethat the identifier for group 1 is also the code used by the serial communications as alog on password. All relays leave the factory with all the group identifiers set to

'Optimho'.

To change/set the group identifier the user should press the RIGHT arrow key from thedisplay page :

'GROUP IDENTIFIER ''push -> to set '

The display page changes to the group identifier code with an underline cursorpositioned under the first character position of the group identifier code. TheUP/DOWN arrow keys step the character at the cursor position either up or downthrough the ASCII table of characters given in Table 3-3. The RIGHT and LEFT arrowkeys are used to move the cursor position right or left. On pressing the LEFT arrow key,with the cursor at the first character position, the display steps back to the page :

'GROUP IDENTIFIER ''push -> to set '

Any changes to the group identifier code will be updated when the user presses the SETkey at the settings trap position in the menu (see Section 3.4.5).

Note:

1) If the ACCESS LEVEL (COMMUNICATIONS section) is set to LIMITED, thegroup identifier code can be viewed but not changed.

2) Any blank spaces at the end of the group identification code are ignored bythe serial communications when entering the group identifier as a log onpassword.

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3.10.2 Software version

The software version number is factory set and can not be changed by the user.An additional software version number is given for relay versions which have theoptional fault locator fitted.

3.10.3 Default display

The default display is determined by the status of the relay, as detailed in Section3.4.1. If there are no higher priority default conditions active, the default or rootdisplay page will be as selected in this section, this will be either a blank displayor group identification code or active setting group number.

Note: the GROUP IDENTIFIER, SOFTWARE VERSION and DEFAULT DISPLAYcan all be viewed using the View / Scroll feature (see Section 3.3).

Table 3-3Group Identifier character set

The following characters are available:

space , 8 D P Y h t! - 9 E Q ] i u" . : F R ^ j v# / ; G S _ k w$ 0 < H T ` l x% 1 = I U a m y& 2 > J V b n z' 3 ? K W c o ( 4 @ L X d p |) 5 A M Y e q * 6 B N Z f r ->+ 7 C O [ g s

Note:

i) The Y character is shown as \ on the VDU or computerterminal.

ii) The -> character is shown as ~ on the VDU or computerterminal.

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3.11 Calendar clock

The calendar clock feature is primarily provided for time and date stamping of fault records, it is therefore important that the calendar clock be set prior toplacing the relay in service.

3.11.1 Format

The ISO time / date format :

Year Month DayHour Minute Second

is used.

3.11.2 Default time & date

The calendar clock is not battery backed up. In the event of a dc power failure orsoftware reset, the calendar clock will default to the time & date stored in non-volatile memory, this will be the time & date recorded when settings were lastupdated.

A '?' is appended to the defaulted time/date to indicate that the time & datesetting is no longer correct. If at power up, no higher priority default conditionsare active (see Section 3.4.1), the page :


is displayed. In order to reduce the number of key presses required to set theclock the menu steps the user to the page :


when the RIGHT arrow key is pressed.

3.11.3 Setting time & date

The general rule for all relay settings is that settings are only updated when theSET key is pressed at the setting trap page :


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The time and date setting however, is an exception to this rule and is updatedwhen the LEFT arrow key is pressed to step to the page :

'CALENDAR CLOCK '

'SET TIME & DATE '

The method used to set the time/date is described in Section 3.4.6. The '?' symbolis removed from the time & date display when the clock has been set.

3.11.4 Clock reference

In circumstances where the average system voltage frequency is accuratelymaintained at its nominal value, it may be preferable to reference the calendarclock to the system frequency rather than to the internal relay crystal. The CLOCK REFERENCE menu option allows the clock to be referenced to either the relay

crystal or the system voltage frequency.

If the option to reference the calendar clock to the system voltage is selected, andthe system voltage falls to less than about 70% of nominal, the calendar clockautomatically references to the internal crystal until the system voltage rises toabove 70% of nominal.

Note, the Calendar Clock can be viewed using the View/Scroll feature (seeSection 3.3).

3.12 Settings

Settings which relate directly to the relay protection elements are grouped in thisbranch of the menu tree under the following sections:

a) CONTACT CONFIGURATIONb) SCHEMEc) DISTANCEd) BLOCK AUTORECLOSEe) VT SUPERVISIONf) START INDICATIONg) DEF (Optional for LFZP versions 111, 112 & 114)h) FAULT LOCATOR (Optional for LFZP versions 111, 112 & 114)

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3.12.1 Contact configuration

The adoption of a bus oriented system, running under software control, haseliminated the need for fixed hard wired connections to output tripping relays.Each individual output relay has a unique software address, this allows it to be

control LED by the particular scheme software selected and thus allows differentoutput configurations to be implemented.

Output contact configurations are detailed in Section 8.

3.12.2 Scheme

The LFZP 11x range of relays provide an extensive range of scheme options.12 different scheme options are available, these are:

a) BASIC

b) Z1 EXTENSIONc) PUR (Permissive Underreach)d) PUR UNBLOCK (Permissive Underreach Unblock)e) POR 1 (Permissive Overreach 1)f) POR 1 UNBLOCK (Permissive Overreach1 Unblock)g) POR 2 * (Permissive Overreach 2)h) POR 2 WI TRIP * (Permissive Overreach 2 Weak

Infeed Trip)i) POR 2 UNBLOCK * (Permissive Overreach 2 Unblock)

j) POR 2 WI TRIPUNBLOCK * (Permissive Overreach 2 Weak

Infeed Trip unblock)k) BLOCKING *l) BLOCKING 2 *

* (Not available for version LFZP 114)

Scheme options are described in Section 5.6.

Scheme timers

Depending on the scheme selected, up to 3 scheme timers are available, theseare TP, TD and TDW. If the DEF is fitted, an additional 2 timers are alsoavailable, these are TPG and TDG. All timers have a setting range of 0 to 98ms,selectable in 2ms increments.

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Timer TP

This timer is only available if any of the following scheme options are selected:

POR 1

POR 1 UNBLOCK BLOCKINGBLOCKING 2

Timer TD


POR 1POR 1 UNBLOCK POR 2

POR 2 UNBLOCK POR 2 WI TRIPPOR WI TRIP UNBLOCK BLOCKINGBLOCKING 2

Timer TDW


PUR UNBLOCK POR 1 UNBLOCK POR 2 UNBLOCK POR 2 WI TRIP UNBLOCK

Timer TPG

This timer is only available if both DEF ELEMENTS and DEF AIDED TRIP areENABLED and the BLOCKING scheme option is selected.

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Timer TDG

This timer is only available if both DEF ELEMENTS and DEF AIDED TRIP areENABLED and any of the following scheme options are selected:

POR 1POR 1 UNBLOCK BLOCKINGBLOCKING 2

DEF elements

Setting options relating to the DEF are only available if the DEF is fitted. Allelements of the DEF feature can be ENABLED or BLOCKED either in the

'SETTINGS ''SCHEME '

section of the menu tree or in the

'SETTINGS ''DEF '

section of the menu tree. If the DEF elements are set to ALL BLOCKED, all otherDEF element settings (except DEF LOW SET in DEF section of the menu tree) arenot available.

DEF aided trip

Provided DEF elements are ALL ENABLED, the DEF AIDED TRIP can be ENABLEDor BLOCKED. If the DEF AIDED TRIP is set to BLOCKED, DEF AIDED TRIPHIGHSET, TPG and TDG are not available.

The DEF AIDED TRIP is automatically set to BLOCKED if any of the followingschemes are selected:

BASICZ1 EXTENSIONPURPUR UNBLOCK

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DEF aided trip highset

This setting is only available if both DEF ELEMENTS and DEF AIDED TRIP areENABLED and any of the following schemes are selected:

POR 1POR 1 UNBLOCK POR 2POR 2 UNBLOCK POR 2 WI TRIPPOR WI TRIP UNBLOCK BLOCKINGBLOCKING 2

The DEF HIGHSET 3Io setting range is 0.05In to 0.8In, selectable in increments of 0.05In.

Loss of load

This feature can be ENABLED or BLOCKED. If ENABLED a choice can be madebetween using low set current level detectors or high set current level detectors.

3.12.3 Distance

Settings related to the distance measuring elements are grouped under theDISTANCE section of the menu tree, these are:-

TYPE OF TRIPZONE 1 TRIPPING

TIME DELAY TRIPBASE SETTINGDIST G CHAR'STIC (Only available for LFZP 111)Z1 & Z2 SETTINGZONE 3 SETTING (Not available for LFZP 114)SWCH ON TO FAULTPwrSwg DETECTOR (Not available for LFZP 114)

Type of trip

Options available are:

1 OR 3 POLE TRIPPINGor 3 POLE TRIPPING ONLY

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Zone 1 tripping

Zone 1 tripping can be selected to be either ENABLED or BLOCKED.

Time delay trip

Time delayed zones Z1X(T), Z1Y(T), Z2(T), Z3(T) and all ground fault elementscan be selected to be either ENABLED or BLOCKED. Timers TZ1X, TZ1Y, TZ2 and

TZ3, associated with each zone, are only available if their corresponding zone isENABLED. Each timer has a setting range of 100ms to 9980ms, selectable in20ms increments.

Time delayed zone Z3(T) is not available for relay versions LFZP 114.

Base setting

Base settings are KZPh, THETA Ph, KZN and THETA N. KZPh and KZN settingranges for all relay versions are :-

KZPh 0.04 to 1.000 selectable in increments of 0.001KZN 0 to 1.360 selectable in increments of 0.001

THETA Ph and THETA N setting ranges for relay versions LFZP 111, 112 & 114are :

THETA Ph 50° to 85° selectable in increments of 5° THETA N 50° to 85° selectable in increments of 5°

THETA Ph and THETA N setting ranges for relay version LFZP 113 is :-

THETA Ph 45° to 80° selectable in increments of 5°. THETA N -45°, -35°, -25° to 80° selectable in increments of 5°.

Dist G Char'stic (Distance ground fault characteristic)

This option is only available for relay version LFZP 111.

Either MHO or QUADRILATERAL characteristics are available.

Resistive reach factor KR is only available if QUADRILATERAL is selected. KR has asetting range of 1 to 30, selectable in increments of 1.

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Z1 & Z2 setting

The setting range for Zone 1 and Zone 2 reach setting multiplier factors KZ1,KZ1X, KZ1Y and KZ2 is 1 to 49.98, selectable in increments of 0.02.

Zone 3 setting

This option is not available on relay version LFZP 114.

The Zone 3 characteristic can be selected to be either OFFSET or REVERSELOOKING. Setting ranges for Zone 3 settings KZ3', KZ3 and aspect ratio a/b are:

KZ3' 0.2 to 49.9 selectable in increments of 0.1KZ3 1 to 49.98 selectable in increments of 0.02

a/b 1, 0.67 or 0.41

Note: KZ3 and a/b settings are only available if OFFSET characteristichas been selected.

Swch on to fault (Switch on to fault)

This feature can be selected to be either ENABLED or BLOCKED. The following options and settings are only available if switch on to fault isselected to be ENABLED :

a) Switch on to fault ENABLED IN 110s, or Switch on to faultENABLED IN 0.2s

b) Switch on to fault BY COMPARATORS, or Switch on to fault BYLEVEL DETECTORS, or Switch on to fault BY LEVEL DETECTORS orCOMPARATORS

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PwrSwg DETECTOR (Power swing detector)

This option is not available on relay version LFZP 114.

This feature can be selected to be either ENABLED or BLOCKED.

The following options and settings are only available if the PwrSwg DETECTOR isselected to be ENABLED :

a) TIMING Z6-->Z2 or TIMING Z6-->Z3b) TO ALLOW Z1 or TO BLOCK Z1c) TO ALLOW Z1X or TO BLOCK Z1Xd) TO ALLOW Z1Y or TO BLOCK Z1Ye) TO ALLOW Z2 or TO BLOCK Z2f) TO ALLOW Z3 or TO BLOCK Z3g) TZ6

h) KZ6i) KZ6' j) LENT a/b

Factors influencing appropriate selection are discussed in Section 5.5.

Setting ranges for TZ6, KZ6, KZ6' and aspect ratio a/b are:

TZ6 20 to 90ms selectable in increments of 5msKZ6 1 to 49.98 selectable in increments of 0.02KZ6' 0.2 to 49.9 selectable in increments of 0.1a/b 1, 0.67 or 0.41

Note : If the DEF is fitted, THE LOW SET 3Iosetting MUST BE SET if the PSB option isENABLED. Refer to Section 5.5.

3.12.4 Block Autoreclose (Block Auto-reclose)

Several options are available to enable auto-reclose to be either ALLOWED orBLOCKED subject to the option selected, these are :

a) BLOCK A/R ON Z1 OR AT 2&3Ph/F (Block auto-reclose onZone 1 or aided Trip 2&3 Phase faults)

or ALLOW A/R ON Z1 OR AT 2&3Ph/For BLOCK A/R ON Z1 OR AT 3Ph/F

b) BLOCK A/R ON Z1X(T) TRIPor ALLOW A/R ON Z1X(T) TRIP

c) BLOCK A/R ON Z1Y(T) TRIPor ALLOW A/R ON Z1Y(T) TRIP

d) BLOCK A/R ON Z2(T) TRIPor ALLOW A/R ON Z2(T) TRIP

e) BLOCK A/R ON CHANNEL OUT

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or ALLOW A/R ON CHANNEL OUT

f) BLOCK A/R ON DEF DELAY TRIPor ALLOW A/R ON DEF DELAY TRIP

g) BLOCK A/R ON DEF AIDED TRIPor ALLOW A/R ON DEF AIDED TRIP

Note: options f) and g) are only available if the DEF is fitted.

3.12.5 VT supervision

VT supervision can be selected either TO ALLOW TRIP or TO BLOCK TRIP in theevent of a VT fuse failure. SELF RESETTING of the VTS feature can be ENABLED orDISABLED.

3.12.6 Start indication

Start indications can be selected to be either ENABLED or BLOCKED.

In the event of a fault, operation of any comparator or DEF (if fitted and enabled)element will initiate a start indication on the LCD if the start indication option hasbeen selected to be ENABLED.

If the optional fault locator is fitted and start indications are selected to ENABLED,the fault locator measuring elements will be initiated by any start event. If startindications are selected to BLOCKED, the fault locator measuring elements willnot be initiated by any start event.

3.12.7 DEF

DEF is an optional feature for LFZP versions 111, 112 & 114.

Settings related to the directional earth fault measuring elements are groupedunder the DEF section of the menu tree, these are:

a) LOW SETb) ELEMENTS

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Low set

The DEF LOW SET 3Io setting is separate from all other DEF settings which aregrouped under the ELEMENTS section. This arrangement enables the DEF LOW

SET element to be set even if all other DEF elements are DISABLED.

Note : If the DEF is fitted, THE LOW SET 3Iosetting MUST BE SET if the PSB option isENABLED. Refer to Section 5.5.

The DEF LOW SET 3Io level detector has a setting range of 0.05In to 0.8In,selectable in increments of 0.05In.

Elements

All settings other than the LOW SET 3Io setting are grouped under this section,these are :

a) DELAY TRIPb) AIDED TRIPc) POLARISINGd) ANGLEe) MAG INRUSH

None of the above options are available if DEF ELEMENTS are selected to ALLBLOCKED.

Delay trip

This option can be selected to be either ENABLED or BLOCKED.

The following settings are only available if DELAY TRIP is ENABLED :

a) Time delay characteristicb) Time multiplierc) Base setting Is.

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Time delay characteristic

Inverse and definite time overcurrent characteristics are shown in Figures 7-17 &7-18. Four IEC and four AMERICAN inverse time curves are available, also threedefinite time curves are available, these are :

Inverse (IEC): CURVE 1 (Standard Inverse)CURVE 2 (Very Inverse)CURVE 3 (Extremely Inverse)CURVE 4 (Long-time Stand-By Earth Fault)

Inverse (AMERICAN): CURVE 5 (US Moderate Inverse)CURVE 6 (US Standard Inverse)CURVE 7 (US Very Inverse)CURVE 8 (US Extremely Inverse)

Definite time : 2 SECOND4 SECOND8 SECOND

Time mulitiplier

Time multiplier setting (*t) range is 0.025 to 1, selectable in increments of 0.025.

Base setting

Base setting (Is) setting range is 0.05In to 1.2I

n, selectable in increments of

0.05In.

Aided trip

This option can be selected to be either ENABLED or BLOCKED.

The following settings are only available if AIDED TRIP is ENABLED :

a) Highset 3Iob) Timer TPGc) Timer TDG

Highset

Highset 3Io setting range is 0.05In to 0.8In, selectable in increments of 0.05In.

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TPG

TPG setting range is 0 to 98ms, selectable in 2ms increments.

TDG

TDG setting range is 0 to 98ms, selectable in 2ms increments.

Polarising

Four methods of directional polarising are selectable, these are :

a) NEGATIVE SEQ. V (negative sequence voltage)b) ZERO SEQ. I (zero sequence current)

c) ZERO SEQ. V (zero sequence voltage)d) ZERO SEQ. V&I (dual zero sequence voltage & current)

Angle

DEF ANGLE THETA N setting range is 10 to 80 degrees, selectable in incrementsof 10 degrees.

Mag inrush

The DEF utilises a novel measuring circuit to detect transformer magnetisinginrush current. Refer to Section 4.4.7 for details of the measurement technique.

The output from the magnetising inrush detector can be selected to stabilise theDEF measuring circuit when in-zone transformers are connected.

Options available are STABILISER ON or STABILISER OFF.

3.12.8 Fault locator

The fault locator is an optional feature available for LFZP relay versions 111, 112,113 (but see section 4.5.1) & 114.

Reach

The fault locator reach multiplier KZF is adjustable from 1 to 40 in steps of 0.01.

Line units

Line Units can be set to Km, Miles or 100%.

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Line length

If LINE UNITS are set to Km or Miles the LINE LENGTH is adjustable from 0 to99.99 in steps of 0.01, and from 100 to 999.9 in steps of 0.1.

If LINE UNITS are set to 100% the line length is fixed at 100%.

CT Ratio

CT RATIO is selectable as 1:1 or 10:1 to 5000:1 in steps of 10:1

VT Ratio

VT RATIO is selectable as 1:1 or 10:1 to 9990:1 in steps of 10:1

Mutual Comp.

Mutual compensation can be ENABLED or DISABLED. If ENABLED the settingranges of KZM and THETA M are:

KZM 0 to 1.360 selectable in increments of 0.001 THETA M 50° to 85° selectable in increments of 5°

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Table 3-4 Summary table of numeric settings

Setting Minimum Maximum Step

TP 0 98ms 2ms TD 0 98ms 2ms

TDW 0 98ms 2ms TPG 0 98ms 2ms TDG 0 98ms 2ms TZ1X 100ms 9980ms 20ms TZ1Y 100ms 9980ms 20ms TZ2 100ms 9980ms 20ms TZ3 100ms 9980ms 20ms TZ6 20ms 90ms 5msKZPh 0.040 1.000 0.001KZN 0 1.360 0.001KR 1 30 1

KZ1 1.00 49.98 0.02KZ1X 1.00 49.98 0.02KZ1Y 1.00 49.98 0.02KZ2 1.00 49.98 0.02KZ3 1.00 49.98 0.02KZ6 1.00 49.98 0.02KZ3' 0.2 49.9 0.1KZ6' 0.2 49.9 0.1KZF 1.00 40.00 0.01KZM 0 1.360 0.001DEF Low Set 3Io 0.05In 0.8In 0.05In

DEF Highset 3Io 0.05In 0.8In 0.05InDEF MULT * t 0.025 1.000 0.025DEF Base setting Is 0.05In 1.2In 0.05In

THETA G 10° 80° 10° THETA Ph 50° 85° 5° * THETA N 50° 85° 5° * THETA M 50° 85° 5° THETA Ph 45° 80° 5° **

THETA N -45°, -35°, -25°, to 80° in steps of 5° **Baud (Modem) 300, 600, 1200, 2400 & 4800Baud (Local) 300, 600, 1200, 2400 & 4800

CT Ratio 1 : 1 and 10 : 1 to 5000 : 1 in steps of 10 : 1VT Ratio 1 : 1 and 10 : 1 to 9990 : 1 in steps of 10 : 1Z3 Lenticular a/b 1.00, 0.67 & 0.41Z6 Lenticular a/b 1.00, 0.67 & 0.41Line Length 0 to 99.99 in steps of 0.01 plus 100 to 999.9 in steps

of 0.1* LFZP Versions 111, 112 & 114.** LFZP 113

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Table 3-5 Summary of menu option settings

SECTION SETTING

IDENTIFIER DEFAULT DISPLAY Blank displayGROUP IDENTIFIER

ACTIVE GROUPCALENDAR CLOCK CLOCK REFERENCE RELAY CRYSTAL

SYSTEM VOLTAGECOMMISSION ALL CONTACTS ENABLED

BLOCKEDBLOCKED EXCEPT ANY

TRIPPwrSwg TEST DISABLED

ENABLEDCOMMUNICATIONS ACCESS LEVEL FULL

LIMITED

COMMUNICATIONS\SERIAL CONTROL

ACTIVE PORT MODEMLOCAL

DATA PARITY STOP 8 NONE 1 (MODEM)8 EVEN 18 ODD 18 NONE 27 EVEN 17 ODD 17 EVEN 27 ODD 27 NONE 2

CONTROL LINES IN USENOT IN USE

DATA PARITY STOP 8 NONE 1 (LOCAL)8 EVEN 18 ODD 18 NONE 27 EVEN 17 ODD 17 EVEN 27 ODD 27 NONE 2

SETTINGSCONTACTCONFIGURATION

CONTACTCONFIGURATION

RESERVED0102030405(plus any specials)

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Table 3-5 Continued.

Section Setting

SETTINGS\SCHEME

SCHEME SELECTION BASICZ1 EXTENSION

PURPUR UNBLOCK POR 1POR 1 UNBLOCK POR 2POR 2 WI TRIPPOR 2 UNBLOCK POR 2 WI TRIP UNBLOCK BLOCKINGBLOCKING 2(plus any specials)

DEF ELEMENTS ALL ENABLEDALL BLOCKED

DEF AIDED TRIP ENABLEDBLOCKED

LOSS OF LOAD ENABLEDBLOCKEDBY LS I LEVEL DETECTORSBY HS I LEVEL DETECTORS

SETTINGS\DISTANCE

TYPE OF TRIP 1 OR 3 POLE3 POLE ONLY

ZONE 1 TRIPPING ENABLED

BLOCKED TIME DELAYED TRIP Z1X (T) ENABLED

Z1X (T) BLOCKEDZ1Y (T) ENABLEDZ1Y (T) BLOCKEDZ2 (T) ENABLEDZ2 (T) BLOCKEDZ3 (T) ENABLEDZ3 (T) BLOCKEDALL G ENABLEDALL G BLOCKED

DIST GCHARACTERISTIC

MHOQUADRILATERAL

ZONE 3 SETTING OFFSETREVERSE LOOKING

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Table 3-5 continued.

Section SettingSETTINGS\DISTANCE

SWCH ON TO FAULT ENABLEDBLOCKED

ENABLED IN 110sENABLED IN 0.2sBY COMPARATORSBY LEVEL DETECTORSBY LD OR COMP

PwrSwg DETECTOR ENABLEDBLOCKED

TIMING Z6-->Z2 TIMING Z6-->Z3 TO ALLOW Z1 TO BLOCK Z1

TO ALLOW Z1X TO BLOCK Z1X TO ALLOW Z1Y TO BLOCK Z1Y TO ALLOW Z2 TO BLOCK Z2 TO ALLOW Z3 TO BLOCK Z3

SETTINGS\BLOCK AUTORECLOSE

BLOCK A/R ON Z1 + AT 2 &3 Ph/FZ1 + AT 3Ph/FZ1X (T) TRIP

Z1Y (T) TRIPZ2 (T) TRIPCHANNEL OUTDEF DELAY TRIPDEF AIDED TRIP

ALLOW A/R ON Z1 + AT 2 & 3 Ph/FZ1X (T) TRIPZ1Y (T) TRIPZ2 (T) TRIPCHANNEL OUTDEF DELAY TRIP

DEF AIDED TRIPSETTINGS\VT SUPERVISION

VT SUPERVISION TO ALLOW TRIP TO BLOCK TRIPSELF RESETTING ENABLEDSELF RESETTING DISABLED

SETTINGS\START INDICATION

START INDICATION ENABLEDBLOCKED

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Table 3-5 continued.

Section SettingSETTINGS\DEF

DEF ELEMENTS ALL ENABLEDALL BLOCKED

DEF DELAY TRIP ENABLEDBLOCKEDCURVE 1CURVE 2CURVE 3CURVE 4CURVE 5CURVE 6CURVE 7CURVE 8DEFINITE t = 2s

DEFINITE t = 4sDEFINITE t = 8s

DEF POLARISING NEGATIVE SEQ. VZERO SEQ. IZERO SEQ. VZERO SEQ. V & I

DEF MAG INRUSH STABILISER ONSTABILISER OFF

SETTINGS\FAULT LOCATOR

LINE UNITS = Km = Miles

= 100%MUTUAL COMP. ENABLED

DISABLED

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3.13 Serial communications.

3.13.1 Introduction

Optimho Serial communications provides a means to access the relays menu

structure from a remote terminal.

The serial communications feature allows :

a) Event records to be viewed remotely.b) Settings to be viewed and changed remotely.c) Bulk transfer of settings, event records and metering information

(if fault locator is fitted) using GECAM PC based software'Opticom'. (This technique is detailed in a separate publicationnumber R5928.)

The method of use is designed to remain similar to that provided on the relayinput keys by using the numeric keypad normally situated on the right hand sideof the keyboard.

Two RS232 connectors are provided on the relay, one for local use on the front of the relay (designated LOCAL) and the second for remote use on the rear panel of the relay (designated MODEM).

3.13.2 Security

Basic security is provided by the setting group 1 `group identifier' (see Section

3.10.1) which acts as a unique password. (see Section 3.13.5 "Logon procedure".)

In some applications where remote serial communication facilities are used, itmay be considered necessary to provide total security to prevent changes beingmade to relay settings by unauthorised users. The ACCESS LEVEL setting can beset to LIMITED to provide this security.

When using the MODEM port the ACCESS LEVEL setting can only be changedfrom FULL to LIMITED.

When the ACCESS LEVEL is set to LIMITED, all settings can be viewed but only thetime and date settings can be changed. Also, the CLEAR ALL RECORDS optionand the commissioning options for ON LOAD DIR TEST and OUTPUT OPTIONare not available. Alteration of time and date values is allowed since it may benecessary to reset the time/date in the event of a dc power failure.

When the ACCESS LEVEL is set to FULL all settings can be viewed and changedwith the exception that, when using the MODEM port, the ACTIVE PORT LOCALselection is not available , to prevent any user from accidentally selecting LOCALand therefore losing the serial communication link.

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3.13.3 Control of serial communications from the relay menu

Active port

Only one of the serial ports, LOCAL or MODEM, can be active at any one time. This menu option is used to select either the LOCAL (front) or MODEM (rear)serial control port as the active port.

Baud rate

Separate BAUD rate settings are available for LOCAL and MODEM ports. Theseare 300, 600, 1200, 2400 & 4800.

Protocol

Separate protocols are available to set up the bit framing (DATA, PARITY, STOP)for LOCAL and MODEM ports. Protocols available are :-

No of data bits Parity No of stop bits

8 NONE 18 EVEN 18 ODD 18 NONE 27 EVEN 17 ODD 17 EVEN 2

7 ODD 27 NONE 2

Note 1: Where Optimho 100 is used over K-Bus, both the pc and the Optimhomust be matched to the KITZ101/102 and KITZ103 respectively with respect totheir baud rates and bit framing protocols, see publication R5832, KITZ103.

Control Lines

This option is only applicable to the MODEM (rear) port. If modem control linesCTS (clear to send), DTR (data terminal ready), RTS (request to send) and DSR(data set ready) are required, this option should be set to :-

'CONTROL LINES ''IN USE '

If modem control lines are not required, this option should be set to :-

'CONTROL LINES ''NOT IN USE '

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3.13.4 Hardware connections

The hardware connections for the two ports are shown in Figure 3-7. (Options 1and 2). It should be noted that the LOCAL port is considered as a DCE (Datacommunications equipment) whilst the MODEM port is configured as a DTE (Data

Terminal Equipment). This implies that should it be necessary to drive anotherDTE from the MODEM port then the wires between pins 2 and 3 should becrossed. (Figure 3-7 option 3).

In a substation environment it is recommended that the RS232 wires are isolated.An optional optical isolator unit is available as shown in Figure 3-7 option 4.Mounting points are provided on the rear of the relay for this optical isolator unittype GT0022, details of which are available from GEC ALSTHOM T&D Protection& Control, reference publication R-4082B.

3.13.5 Logon procedure

The serial communications may be accessed using either a VT100 (DECCorporation) or ANSI (American National Standards Institution) compatibleterminal or a proprietary VT100 terminal emulation software package running ona personal computer.

The procedure to logon is as follows :

a) Enter the setting group 1 group identifier followed by<CR>. The group identifier acts as a unique password and is not echoedto the screen by the relay.

b) When the relay being addressed successfully receives its group 1group identifier it replies with a prompt "GECAM:".

c) At this stage the relay will recognise the following commands:

LOGON<CR> To enter the settings menu.QUIT<CR> To close communications.

These commands may be either upper or lower case characters but not acombination.

Note: <CR> signifies the keyboards "Enter" or "Carriage return" key.

The command "LOGON" will give the user access to a settings menu similar tothat seen on the relays liquid crystal display. The menu is displayed on two lines inthe top left hand corner of the screen. The seven keys on the front of the relay aresimulated by the numeric keypad normally found on the right hand side of thekeyboard :-

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7 8

↑↑↑↑

9

4

←←←←

5 6

→→→→

1 2

↓↓↓↓

3

Once the settings menu has been entered the arrow keys are used to navigate

around the menu in the normal manner. The allocation of the keys is as follows:

↑↑↑↑ key 8↓↓↓↓ key 2→→→→ key 6←←←← key 4SET key 5RESET key 1ACCEPT/READ key 3

All Print options are redirected to the terminal when serial communications is in

use. The communications software supports a character flow-control protocolknown as Xon/Xoff. (i.e. The screen can be paused by sending an Xoff characterand restarted by sending an Xon character.)

The designated character for Xoff is<Ctrl><S>. The designated character for Xon is<Ctrl><Q>.

Note: <Ctrl><S> signifies to press and hold the "Ctrl" key and press "S" or "s"<Ctrl><Q> signifies to press and hold the "Ctrl" key and press "Q" or "q"

There is a 1 minute timeout on Xoff. (i.e. Xon is automatically reselected if Xoff is

selected for greater than 1 minute.)

Serial Communications will be logged off and a closing message "Serialcommunication has been logged off" sent to the terminal when the key 'Q' or 'q' ispressed.

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If no key is pressed in any 15 minute period the relay will automatically closeserial communications and send the closing message. This timeout ensures that inthe event of a prolonged failure in the communication link the relay is releasedfrom serial communications.

Serial communications will also be logged off if the RESET key on the front of therelay is pressed.

3.13.6 K-Bus interface

The introduction of the KITZ103, a K-Bus to Optimho interface unit, has made itpossible to group as a single network, the LFZP and K-Range relay families. It isstill possible to make a direct connection between a VT 100 type terminal or evena pc emulation to an Optimho to gain access to the relay menu features, butwithin Opticom, the dumb terminal and IEC 870 formatted data options are

mutually exclusive. For more information on the use of Optimho 100 over K-Bus,including modem connections and communication parameter set-ups, seepublications R8532, KITZ103 and R5928, Opticom.

3.13.7 Modem requirements

Due to the wide variety of modems and possible configurations, it is not possibleto specify exact requirements, the user should always refer to the manufacturesmanual for information regarding the use and operation of his modem. As ageneral guide the following suggestions are given to assist the user in configuringhis modems for use with Optimho:

• The modem should be configured to a communications standard whichsupports Full Duplex asynchronous RS-232C communications.

• The modem must support the Hayes AT Command language.

• DTE and DCE devices should be set to operate at the same Baud rate.

• Modems should be configured to ignore DTR.

• The remote modem (relay location) should be set to Auto-Answer.

• Any data compression, error checking, speed buffering or automatic speedchanging should be turned off.

• A 10 bit framing protocol should be used.

3.13.8 Recommended modems

Modems which comply with the above requirements should be suitable for usewith Optimho. However, future GEC ALSTHOM T&D Protection & Control relaysand systems which utilise serial communications (i.e., K range relays) will complywith IEC870 FT1.2 protocol. This protocol has several requirements that restrictthe choice of modems which may be used. This restriction results from the need tosupport an eleven bit asynchronous frame with frames transmitted without idleperiods between characters. To assist customers in their choice of suitablemodems which will operate with Optimho and other GEC ALSTHOM T&D

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Protection & Control relays and systems, the following modems have beenevaluated by GEC ALSTHOM T&D Protection & Control for use with the fullIEC870 FT1.2 protocol, and are recommended for use:

1. Dowty Quattro (BS2422)

2. Motorola Codex 3265 or 3265 Fast

To extend the choice of suitable modems, GEC ALSTHOM T&D Protection &Control have decided to introduce an additional protocol based on IEC870 FT1.2but with parity bit omitted. This protocol is less secure than the FT1.2 frame asone of the error checks is discarded. Other modems may be used provided thefollowing features are available:

1. Must support 11 bit frame (one start bit, eight data bits, evenparity bit and one stop bit). This feature is not required if the10 bit option is chosen.

2. Must be possible to disable all error correction, datacompression, speed buffering or automatic speed changes.

3. Must save all the settings required to achieve connection in non-volatile memory. This feature is only required for modemsat the outstation end of the link.

Notes:

1. The V23 asymmetric data rate (1200/75bps) is not supported .

2. Modems made by Hayes do not support 11 bit characters.

3.13.9 Optimho serial communication protocol

In order to allow party vendors to develop communications equipment for usewith Optimho relays a detailed specification no. 50184.1700.001 is available.

This specification covers all aspects of serial communication as implemented byall standard variants of Optimho relays.

Liability

GEC ALSTHOM T&D Protection & Control Limited accept no liability resultingfrom any consequent mal-operations of Optimho relays pertaining to the use of third party vendors equipment developed to communicate with Optimho relays.

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Relay (Rear)

5

20

7

6

3

4

2

DTE

CTS

DTR

DSR

Common

RTS

TXD

RXD

Modem

5

20

7

6

DCE

3

4

2

different for other terminals

in particular pins 2 and 3

may have to be crossed.

Check the serial interfacing

of the terminal being used.

NB. Pin assigments may be

Common

TXD

Relay (Front)

7

3

2

DCE

RXD

25 Pin

7

Terminal

2

3

DTE

+12v

DTR-12v

Common

RTS

CTS

DSR

RXD

9

Option4

2010

3

4

5

6

7

9

2010

3

4

7

5

6

GECAM

Optical

Isolator

Unit

9 +12v 9

2010

DTR-12v

2010

3

4 RTS

7

5

6

CTS

DSR

Common

RXD 3

4

7

5

6

9 Pin AT

Connector

Terminal

DTE

Relay (Rear)

TXD2

DTE

Option 2b

2

Relay (Front)

DCE

3

7

2

Option 1

RXD

Common

TXD

3

5

2

Modem

2 TXD 2

DCE

Option 3

Common7

DTE

3

2

RXD

TXD

Relay (Rear)

Option 2a

Connector

25 Pin

7

DTE

TXD

RXD 3

2

Terminal

Connector

5

20

6

8

4RTS

CTS

DTR

DSR

DCD

520

6

8

4RTS

CTS

DTR

DSR

DCD

RXD

TXD

Figure 3-7 Serial communications hardware connections.

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3.14 Test features

Optimho has several menu driven features to aid testing and commissioning. These are to be found on the menu under the Commissioning Section and aredescribed in the following sections.

3.14.1 Contact control

This option allows all the relay output contacts to be disabled for example duringcommissioning, and thus prevent tripping of the circuit breaker or remote alarmsbeing sent. A second option allows all contacts except Any Trip to be disabled.

The Any Trip contact can be used for timing or monitoring purposes. If either of these two options are selected the green relay available LED is extinguished andthe relay inoperative alarm contact is closed. Also the default message on thedisplay indicates that the contacts are blocked. The normal setting will be allcontacts enabled.

3.14.2 On load dir test

This option simplifies the on load directional testing of the relay. When the SETkey is pressed to activate the test the following actions occur within the relay.

a) All contacts are blocked, the relay available LED is extinguishedand the Relay Inoperative alarm contact closed.

b) The comparator count control is set to 4.c) The voltage and current bandpass filters are switched in. (Load

currents may be distorted)

d) KZPh is set to maximum. (Gives maximum sensitivity)e) KZ1 is set to infinity. (Makes Zone 1 Directional)f) THETA Ph is set to minimum. (Nearer to expected load)g) Level detectors LDOVA, LDOVB, LDOVC, LDLSA, LDLSB & LDLSC

are checked and if they are not all picked up the message Testaborted is written to the LCD display.

h) If the level detectors are picked up the Zone 1 phase faultcomparators are checked and the appropriate messageFault seen as FORWARD or Fault NOT seen as FORWARD.is written to the LCD display

When the SET key is released to deactivate the test the following actions occurwithin the relay.

a) All settings that have been changed are restored.b) All comparators are reset.c) The contacts are unblocked and the relay is returned to service.

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3.14.3 PwrSwg test

This test simplifies testing of the power swing blocking (PSB) feature. The relayremains in service even when the test is enabled but the default message on thedisplay indicates that the PwrSwg TEST is enabled.

The test is provided to assist with two problems encountered during testing. Onrelays that have optional DEF fitted the PSB Zone 6 comparator is blocked if thenegative sequence current detector (LDLSI2) operates. This would require the PSBto be tested with balanced 3 phase faults which many test sets cannot deliver. Thistest option removes this check thus allowing a AB phase fault to be used.

The second problem with some test sets is that while simulating a power swing atransient pole dead condition may occur with the result that the PSB logic isinhibited for 240ms. The test option removes this check.


This option enables all the input signals to the main microcontroller i.e. status of level detectors, comparators & optical isolators and several internal signals to bemonitored.

Table 3-6 lists all the monitor options which are selected by a number and thecorresponding data which is displayed on the LCD while the monitor option pageis displayed. This information is also available on the parallel socket on the frontof the relay at all times.

The signals on the socket can be used for monitoring or to control timers etc. Thesignal level is 0V corresponding to a 0 on the display or 5V corresponding to a 1.

The relay remains in service when the test options are being used.

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Table 3-6 Monitor options

NB. When using the parallel socket pin 25 is 0V reference.

Test parallel socket pin no. and LCD positionno. 2 3 4 5 6 7 8 90 SLOT 1

DIAGSLOT 5DIAG

SLOT 6DIAG

SLOT 7DIAG

SLOT 8DIAG

SLOT 9DIAG

SLOT 10DIAG

SLOT 11DIAG

1 CpAZ1 CpBZ1 CpCZ1 CpABZ1 CpBCZ1 CpCAZ1 0 02 CpAZ2 CpBZ2 CpCZ2 CpABZ2 CpBCZ2 CpCAZ2 0 03 CpAZ3 CpBZ3 CpCZ3 CpABZ3 CpBCZ3 CpCAZ3 CpABZ6 04 MAG

INRUSHDEF BUSTSRT

DEF T BU

0 CpDEF_F CpDEF_R 0 0

5 OPTO58-60

OPTO62-64

OPTO66-68

OPTO70-72

OPTO74-76

OPTO78-80

OPTO82-84

0

6 LD0VA LD0VB LD0VC LDV0 LDLSA LDLSB LDLSC LDLSN

7 LDLSI0 LDLSI2 LDHSI0 0 LDHSA LDHSB LDHSC LDHSN8

Z1 Z1XT Z1YT Z2T Z3T 0 LDCpABZ6 TZ6

TimedOut

9 0 0 0 0 0 0 SOTF Trip

SOTFEn

10 UPSK2-17

RIGHTSK2-16

DOWNSK2-15

LEFTSK2-14

SETSK2-13

READSK2-12

RESETSK2-10 SK2-11

11 LDCpAZ1 LDCpBZ1 LDCpCZ1 LDCpABZ1 LDCpBCZ1 LDCpCAZ1 0 012 LDCpAZ2 LDCpBZ2 LDCpCZ2 LDCpABZ2 LDCpBCZ2 LDCpCAZ2 0 013 LDCpAZ3 LDCpBZ3 LDCpCZ3 LDCpABZ3 LDCpBCZ3 LDCpCAZ3 LDCpABZ6 014 RL29-31 RL29-33 RL29-35 RL37-39 RL41-43 RL45-47 RL49-51 RL53-5515 RL30-32 RL30-34 RL30-36 RL38-40 RL42-44 RL46-48 RL50-52 RL54-56

16 RL57-59 RL57-61 RL57-63 RL65-67 RL69-71 RL73-75 RL77-79 RL81-8317 Count 4 0 PoleDead C

PoleDead B

PoleDead A

0 0 0

18 0 0 0 0 0 Filter( I )

Ampl.Hyst

Filter( V )

19 Timer 1 Timer 2 DEFAided

DISTAided

DEF_R DEF_F Z3Comp

Z2Comp

20 Z1-REACH

ZIX-REACH

Z1Y-REACH

0 0 0 0 0

21 Timer 1 Timer 2 Any Trip

SignalSend

LGSopto

CRXopto

Z3Comp

Z2Comp

22 Timer 1 Timer 2 Any Trip

SignalSend

LGSopto

CRXopto

DEF-R DEF-F

23 LD0VA LD0VB Any Trip

SignalSend

LDLSA LDLSB Z3Comp

CRXopto

24 EEPROMSettings

0 EEPROMRecords

InternalRAM

ExternalRAM

LCD ANOMAL 0

25 SignalStart

SignalStop

Any Trip

TestPoint

DEF-R DEF-F Z3Comp

Z2Comp

Note: options 26 to 30 inclusive are not used.

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3.14.5 Output options

This option allows each output contact to be closed individually for testing

purposes. The relay is taken out of service indicated by the green relay availableLED being extinguished and the relay inoperative alarm contact closed when themessage push SET to test is displayed. On pushing SET the appropriate contact isclosed.

Table 3-7 relates test numbers to contacts. Test numbers 24 to 27 can be used forcircuit breaker trip tests. For example test 24 is used to simulate a single pole tripon A phase. The test closes all contacts labelled Trip A or Any Trip for theparticular contact arrangement selected. Similarly test 25 simulates a single poletrip on B phase and test 26 a single pole trip on C phase. Test 27 simulates a 3pole trip closing all trip contacts. For 3 pole only tripping schemes tests 24 to 26

are inoperative. If the contacts are blocked as described earlier the message‘Contacts Blocked’ is given on the display.

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Table 3-7 Output test options

Number Contact operated

1 29-332 29-35

3 37-394 41-435 45-476 49-517 53-558 30-329 30-3410 30-3611 38-4012 42-44

13 46-4814 50-5215 54-5616 57-5917 57-6118 57-6319 65-6720 69-7121 73-7522 77-79

23 81-8324 Trip A & Any Trip25 Trip B & Any Trip26 Trip C & Any Trip27 Trip A, B, C, 3Ph & Any Trip

Note: option 24, 25 & 26 only applicable if 1 or 3 pole tripping is selected.

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3.14.6 Parallel test socket

The parallel test socket on the front of the relay has the combined functions of a

parallel printer interface and a test socket. The pin connections are shown in thetable below. A monitor box which converts the 25 way D type connector to 254mm sockets is available as an option.

The output data lines can be used in conjunction with the Monitor optionsdescribed earlier. The output signal level is 0V for logic 0 and 5V for logic 1.

The input data lines can be used to mimic the 7 keys by connecting theappropriate pin (D0 to D7) to 0V (pin 25) to represent a key press.

Other signals allow the internal voltage rails to be monitored.

Table 3-8 Parallel test socket

ParallelPort pin

PrinterConnections

Function Name

1 STB (Pin 1) Printer strobe (Output)2 D0 (Pin 2) Data line D0 Output)3 D1 (Pin 3) Data line D1 (Output)4 D2 (Pin 4) Data line D2 (Output)5 D3 (Pin 5) Data line D3 Output)

6 D4 (Pin 6) Data line D4 Output)7 D5 (Pin 7) Data line D5 Output)8 D6 (Pin 8) Data line D6 (Output)9 D7 (Pin 9) Data line D7 (Output)10 Do not connect Data line D6 RESET key ( Input)11 BUSY (Pin 11) Data line D7 Printer Busy (Input)12 Do not connect Data line D5 READ key (Input)13 Do not connect Data line D4 SET key (Input)14 Do not connect Data line D3 LEFT key (Input)15 Do not connect Data line D2 DOWN key (Input)

16 Do not connect Data line D1 RIGHT key (Input)17 Do not connect Data line D0 UP key ( Input)18 Do not connect 5v Monitor (Output)19 Do not connect 12v Monitor (Output)20 Do not connect -12v Monitor (Output)21 Do not connect 12v(Relay) Monitor ( Output)22 0v (Pin 22) 0v23 0v (Pin 23) 0v (Note: All 0v are commoned,24 0v (Pin 24) 0v only 1 connection is necessary)25 0v (Pin 25) 0v


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The monitor options may also be selected using an appropriate code applied tothe input data lines of the parallel socket as shown in the Table 3-9. This featurecan be used with automatic test sets to select monitor options. Note there will be a20ms delay before the option is available.

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Table 3-9 Monitor options selected by parallel test socket

Code applied to parallel socket Monitoroption

Data line D7 D6 D5 D4 D3 D2 D1 D0 no selectedsocket pin 11 10 12 13 14 15 16 17

1 0 1 0 0 0 0 0 001 0 1 0 0 0 0 1 011 0 1 0 0 0 1 0 021 0 1 0 0 0 1 1 031 0 1 0 0 1 0 0 041 0 1 0 0 1 0 1 051 0 1 0 0 1 1 0 061 0 1 0 0 1 1 1 071 0 1 0 1 0 0 0 08

1 0 1 0 1 0 0 1 091 0 1 0 1 0 1 0 101 0 1 0 1 0 1 1 111 0 1 0 1 1 0 0 121 0 1 0 1 1 0 1 131 0 1 0 1 1 1 0 141 0 1 0 1 1 1 1 151 0 1 1 0 0 0 0 161 0 1 1 0 0 0 1 171 0 1 1 0 0 1 0 181 0 1 1 0 0 1 1 19

1 0 1 1 0 1 0 0 201 0 1 1 0 1 0 1 211 0 1 1 0 1 1 0 221 0 1 1 0 1 1 1 231 0 1 1 1 0 0 0 241 0 1 1 1 0 0 1 251 0 1 1 1 0 1 0 261 0 1 1 1 0 1 1 271 0 1 1 1 1 0 0 281 0 1 1 1 1 0 1 291 0 1 1 1 1 1 0 30

NB: To input a code on pins 10 to 17 logic 1's are not connected andlogic 0's are connected to 0V pin 25. For example to select monitoroption 02 connect input data lines D6, D4, D3, D2 & D0 to 0Vleaving D7, D5 & D1 unconnected.

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Section 4. PRICIPLES OF OPERATION

4.1 The comparator

The important requirements of high speed and high stability have both beensatisfied in the comparator design. Usually these two requirements are incontention because the greater the operating speed, the greater the risk of falseoperation caused by contaminated relay input signals. Signal contamination'sinclude harmonic components, switching surges, lightning impulses, travellingwaves, exponential decays, saturated current transformer waveforms andinterference voltage induced on low voltage wiring due to switching on the highvoltage system.

The comparator resolves the speed/stability contention by checking its own inputsignals to verify that they are dominated by components consistent with power

system frequency waveforms. If verification is obtained the full operating speed isallowed. If verification is not obtained, the comparator demands more databefore tripping can be allowed, thereby automatically extending the signalprocessing time sufficiently to ensure that no maloperation can occur. By suitablefiltering and preconditioning of the comparator input signals, the relay design en-sures that the comparator is able to operate at its highest speed for the majorityof transmission line faults.

The sequence comparator employed in the Optimho range of distance relaysderives its pedigree from Micromho and Quadramho distance protections, andembodies the experience gained in the development and application of these

products.

4.1.1 Fundamentals of the comparator

In the Optimho range the comparators are used to provide a variety of differentcharacteristic shapes, such as quadrilateral, mho, offset mho, lenticular etc. Theeasiest to explain is the mho (or circular), so this will be described first.

For simplicity describing a self polarising characteristic, the comparator inputs areshown in Figure 4-1, such that:

A = V-IZB = V/-90°

and the condition for operation is that A lags B by 0 to 180°.

Since the operation of the comparator is independent of the magnitude of A andB, these two quantities are changed to "square waves", by use of high gainamplifiers, before being supplied to the comparators. The "squared up" signalsconvey the phase angle information of the original signals in a digital form.

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The comparator processes the input "square waves" as logic variables which caneach have a high (H) or low (L) logic state at any time. To facilitate the followingexplanation, signal A will be described as A(H) or A(L) depending on its logic stateat a particular instant of time, and signal B will be described as B(H) or B(L).

There are four possible combinations of logic state:

A(L).B(L)A(L).B(H)A(H).B(H)A(H).B(L)

If both signals have unity mark/space ratios and equal periods but differentphases, then the four combinations will occur in a cyclic manner.

There are only two possible sequences of these combinations, as shown in Figure4-2. These are :

If A leads B:

A(H).B(H), A(L).B(H), A(L).B(L), A(H).B(L), A(H).B(H)

If A lags B:

A(H).B(H), A(H).B(L), A(L).B(L), A(L).B(H), A(H).B(H)

From these the following logic statements can be deduced.

a) If A leads B, then when A changes it acquires the opposite state toB, and when B changes it acquires the same state as A.

b) If A lags B, then when A changes it acquires the same state as B,and when B changes it acquires the opposite state to A.

The comparator processor algorithm scrutinizes the input signals at each changeof state to decide which of the two states is true and thus determine whether thesequence is progressing in a restrain or tripping direction. The comparatoralgorithm can identify the direction of the progression from a single change of logic state of either input, and from any starting point in the sequence.

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The presence of noise can introduce false changes of state unconnected with thetrue signals at the power system frequency. A single change of state matching thetrip sequence does not necessarily represent a fault condition within the protectedsection of line. Greater security is obtained if the criterion for tripping is to receive

a number of successive changes of state each of which matches the trippingsequence. The comparator therefore has a counter for determining whether one,two, three or four such changes have been observed. Each acceptable changematching the tripping sequence adds to the total count (up to a maximum of four), while every change matching the restrain sequence subtracts from the totalcount (down to a minimum of zero).

The criterion for operation for self-polarised characteristics is a count of three. Forpartially cross-polarised characteristics, if the input signals are relatively noise andtransient free, a count of two is sufficient.

The action of the counter for a typical fault within the measuring zone is shown inFigure 4-3.

4.1.2 Action of the comparator

Figures 4-2 and 4-3 show pure power-frequency signals, but it is obvious that thepresence of noise would change the situation. To illustrate the point, Figure 4-4shows a restrain condition of the power-frequency signals, with a burst of high-frequency noise superimposed on a comparator input. Because the noisehappens to coincide with a change of state of the other comparator input, acount-up situation occurs at high frequency. To prevent the comparator incorrectlytripping, the rate of counting up is deliberately limited, preventing a count-up of more than one being registered under these conditions.

The method of restricting the rate of counting up is to set a minimum acceptabletime period between successive count-up occurrences of 0.15 cycles of nominalsystem frequency (0.175 cycles for partially cross-polarised characteristics. If acount-up occurs within this time, then the period is restarted. While this period isrunning the counter cannot be incremented further. Each change of state in arestrain sequence decrements the counter and terminates any time periodrunning, so there is no restriction on the rate of counting down.

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The restriction on the rate of counting up effectively limits the operatingbandwidth of the comparator, eliminating maloperation due to high frequencyinterference. The same restriction also prevents the possibility of transientoverreach occurring when the V-IZ comparator input has an exponential offsetwhich distorts the mark/space ratio of the square wave, as shown in Figure 4-5.

Note that the exponential component of the current does not cause a significantexponential offset in the IZ vector, because the signal is differentiated with a shorttime constant by the current input devices. The voltage supply can have anexponential component which is reflected in the comparator V-IZ input and in thecomparator polarising input of self-polarised relays. Therefore, for self-polarisedcharacteristics a trip output is issued by the comparator when the counter isincremented to three, as shown in Figure 4-6.

For partially cross-polarised characteristics the exponential component in thevoltage is not reflected in the comparator polarising input, since this signal isnormally dominated by healthy phase components. Therefore a trip output is

issued by the comparator when the counter increments to two, subject to :

a) No change of state of a restrain sequence is observed after thecounter has incremented to one or more.

b) That a time of 0.35 cycle of nominal system frequency hasexpired since the counter was incremented to one. Thisensures adequate processing time in the event of disturbancescausing polarising phase shifts.

c) That no inhibit is applied to the comparator whilst count 2 is setwith the 0.35 cycle timer running.

If these criteria are not met, then tripping on count 2 is disabled until thecomparator receives four consecutive down-counts after reaching a count of 0.Whilst tripping on count two is disabled the comparator will issue a trip when thecounter is incremented to three. Figure 4-6 shows a flowchart representation of the comparator logic.

A further safeguard is provided against incorrect directional response caused bycapacitor voltage transformers which have severe transient voltage errors.

The CVTs concerned are those with near system frequency components in theirtransient error waveforms, against which the comparator controls are ineffective.

The safeguard comprises a directional sequence comparator, which compares theIZ vector with the polarising vector. This polarising vector (see Section 4.2) hassufficient synchronous polarising present to mask out the CVT transient from thepolarising signal.

If the directional comparator indicates that a fault lies in the reverse direction of the relay, the main comparator is inhibited (i.e. it treats all counts as if they werein a restrain sequence) thus preventing relay mal-operation.

4.1.3 Exclusion of noise

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The following interfacing and preconditioning measures ensure that the full highspeed performance potential of the comparator is achieved even with severelycontaminated relay input signals.

a) Good physical layout and electrical filtering has been used to

exclude high frequency noise generated in the substation. Therelay terminals and all of the relay modules/boards which interfacewith the outside world are located on the right and left handsides of the relay case. The interface modules/boards provideelectrical isolation to 5kV peak, using isolating transformers withscreens to shunt high frequency currents to earth and so attenuatecommon-mode interference. Transverse mode interference isattenuated by low pass filters. The measuring and control boardswhich occupy the centre portion of the relay case, thereforeoperate in a quiet electrical environment.

b) Other high frequency signals, such as travelling wave effects andother high harmonic frequencies, are attenuated by low passfilters which have a cut-off of approximately 120 Hz.

c) Exponential components of the current supply are attenuated with ashort time constant by the main current input devices of therelay.

d) Coupling capacitor voltage transformer (CVT) transients areprevented from having any effect on the polarising signal by thedominant effect of sound phase polarising or synchronouspolarising (Section 4.2). Alternative band-pass filter outputs areselected at the appropriate time to eliminate excessive effects ofCVT transients in other signals derived from the ac voltagesupply. (See also Sections 5.17 and 6.7)

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Vpol = V -90

IX

characteristicFault inside

characteristic

outside

Fault

Fault on

IR

IZ

V-IZ

boundary

Figure 4-1 Sequence comparator voltages for mho characteristics

OPERATE CONDITION

AB

inputs

RESTRAIN CONDITION

ABLogic states AB AB

Squared

inputs

B = V -90

A = V-IZ

B

A

AB AB AB AB AB AB

B

A

Sine wave

B A

AB AB AB

A B

Figure 4-2 Comparator logic variables

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A

Fault Occurs

Counter

AB

B

AB AB AB

4

12

3

AB AB AB AB AB AB AB AB

Figure 4-3 Action of counter in comparator

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COUNTER 0

1

SQUARED INPUTS

Vpol

V-IZ

B

A

Sinusoidal V-IZ input

A

AS CHANGES SPACED 0.15 < CYCLE

NO SECOND UP-COUNT

0

INTERFERENCE

BURST OF

Figure 4-4 Effect of high - frequency interference

AS CHANGES SPACED <0.15 CYCLE

0

NO SEC0ND UP-COUNT

COUNTER

V-IZ

INPUTS

SQUARED

SINUSOIDAL

INPUT

V-IZ

Vpol

1

0

B

A

FAULT OCCURSOUTSIDE BOUNDARY

OF OPERATION

Figure 4-5 Effect of exponential offset

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Reset Timer 2Restart Timer 1Set all Block registers

Reset outputReset all Count registers

yes

yes

no

yes

yes

yes

high

?

is

no

inhibit input

no

reset inputhigh ?

is

Read inputs

no

is

set ?register count 2

Times are for 50 Hz

register 2

register 3

Reset block

Reset block

register 4

no

Reset block

Reset block

register 1

no

no

no

2) Count 2 trips are blocked if the inhibit input goes high

3) 4 consecutive downcounts are required, after count 1

1) A minimum of 3 counts are required for self polarised

4) No action is taken if both A and B inputs are seen to

5) For cross polarised characteristics T1 = 3.5 mS T2 = 7 mS

register resets, to remove any block on count two tripping

For self polarised characteristics T1 = 3 mS T2 n/a

block registers

set ALL

2

yes

required

are3 counts

?

1

noSET OUTPUT

Set count

register 2

Set count

Set count

Set count

register 1

Start Timer 2

no

4 countsrequired

areyes

?

register 4

no count 4

SET OUTPUT

yes

register set ?

is

register 3

no

no

no

register

set ?

yes

is

register count 3

yes

set ?

yes

iscount 2

yes

is

set ?

count 1register

Timer 1

Re-start

yes

no

OPERATE

finished ?Timer 1

is

no

high

?

isinhibit input

yes

input Bchanged

no

?

A = B

does

?

4

no

?

yes

has

changed?

yes

hasinput A

changed

has

input A or B

count 2

no

set ?register

is

Reset count

register 3

reset timer 2

reset output

Reset count

register 2

register 1

Reset count

Reset count

register 4

yes

register count 4

set ?

isno

yes

yes

register

yes

block registers

register

set ALL

set ?

iscount 3

set ?

iscount 2

no

no

register

set ?

yes

register block 4

is

yes

set ?

yes

block 3is

register block 2

set ?

is

yes

whilst waiting for Timer 2 to finish

Operation on count 2 permitted.

Operation on count 2 not permitted.

yes

characteristics

change together

block 1

set ?register

Finish Timer 1

register

RESTRAIN

set ?

count 1is

no

does

no

?

B = A

no

Timer 2

?

finished

no

is

yes

Notes

yesis

set ?register block 1

is

3

4 countsrequired

areno

yes

?

no

Figure 4-6 Sequence comparator

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4.2 Polarising arrangements

To simplify the description, the mho characteristic has been described in Section4.1.1 as if it were self polarised. In fact, partial healthy phase cross polarising andpartial synchronous polarising components are used. These extra polarising

components are used in order to satisfy the following requirements:

a) To maintain a correct polarising (i.e. directional reference) signalfor the relay comparators under conditions of close up faults ofall types even in the presence of large transient voltage errorsfrom CVTs, so that correct directional response can beensured.

b) To enable fast operating time to be obtained for close up faultsof all types in the forward direction of the relay.

c) To provide expansion of the resistive coverage of the mho forfaults with low infeed currents, where arc resistance may belarge.

Both the healthy phase and synchronous components are square wave signals of amplitude 16% of the peak prefault voltage vectors. Under unbalanced faultconditions, the proportion of healthy phase polarising is enough to overcome theeffects of normal CVT transients. Under three phase fault conditions, the syn-chronous polarising works in a similar way. Figure 4-7 shows that by adding a16% square wave to the CVT error, the correct zero crossings of the polarisingvoltage are restored. The polarising signal is squared up and phase retarded by90° to become input B of the comparator as described in Section 4.1.

The unique shapes of the partially cross polarised mho practical polarcharacteristics, shown in Figure 4-8, have been achieved by suitable choice of thewave shape of the signals involved in the polarising mixing circuits. Inconventional polarising mixing circuits all the signals are sine waves, but in theOptimho the synchronous polarising and sound phase cross polarising compo-nents are square waves. The advantages of these unique polar characteristics areobtained with only one two input comparator, enabling optimum operating timeto be obtained. Due to the partial synchronous polarising component, the resistiveexpansion is maintained for three phase faults. The top line of the expandedcharacteristic is part of a fully cross polarised circle and moves with prefaultpower flow so as to avoid overreach or underreach.

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For the B-C polarising mixing circuit (also shown in Figure 4-9) The A-Gpolarising signal VPol A is level shifted by the action of IC3 to produce the bipolarsignal VPOL A. A set of resistors R8, R9, R10, and R11 are used to mix VPOL Awith VB and VC in such proportions that the peak value of VPOL A corresponds to16% of the peak value of VB-VC at the input of squaring amplifier IC4. The

output VQBC of IC4 is phase shifted through a lagging angle of 90° by a shiftregister and is then supplied to the comparator.

The phase of VQBC is determined largely by the zero crossings of VB-VC underall types of fault conditions except B-C, B-C-G and three phase faults which causethe B-C voltage to collapse. For these conditions of low B-C voltage the VPOL Ainput dominates the phase of the polarising signal. VPOL A in turn is controlled byVA if this fault involves the B-C or B-C-G phases, or by Vmem A if the faultinvolves all three phases. Therefore, if VB-VC collapses below 16%, the B-C unit iseffectively fully cross polarised and consequently the resistive expansion of theimpedance characteristic is greater than for a conventional partially cross polar-

ised relay. Furthermore, the resistive expansion also applies to three phase faults.

The combination of the sine wave faulty phase voltage with the square wave crosspolarising (or synchronous polarising) voltage results in a phase displacement of the resultant polarising signal from its prefault position which is different from thatof a conventional partially cross polarised mho. Figure 4-10 shows therelationship of the phase displacements of the faulty phase and polarising signalsfor Optimho and conventionally polarised comparators, drawn for a typical faultvoltage amplitude. In Optimho the displacement of the polarising signal is zerountil the faulted phase is displaced by more than a critical angle Φ°, the captureangle. Once the critical angle is exceeded, the polarising voltage phasedisplacement rises linearly with the faulted phase voltage displacement.

The explanation for this behaviour is shown in Figures 4-11 and 4-12. Figure4-11, shows an example of the composition of the polarising signal in Optimho.

The faulted phased sine wave is drawn here for a fault voltage of 25%, displacedby 30°

lagging, relative to the prefault values. This signal is summed with the

square wave cross polarising signal whose magnitude is 16% of the prefault sinewave peak voltage. The zero crossings of the resultant signal remain in phasewith those of the cross polarising signal, that is, no displacement from the prefaultposition.

Figure 4-12 shows conditions similar to Figure 4-11, but with the faulted phasevoltage displaced by 60°. Under these conditions the resultant polarising signal isdisplaced by about 20°

from its prefault position, because the faulted phase

displacement exceeds the captive angle by this amount.

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When the displacement of the faulted phase voltage is just equal to the captiveangleΦ°;

Vpk(sinΦ°) = VPol

Captive angleΦ° = sin−1 Vpol

Vpk

provided that Vpk > = VPol

If Vpk < VPol, the sine wave has no effect on the polarising signal, so the

characteristic becomes fully cross polarised.

Since the displacement of the resultant polarising signal is zero if the faultedphase voltage is less than the captive angle, the boundary of the characteristicover this range is the same as that of a fully cross polarised mho (see Figure4-10). For high values of displacement of the faulty phase, the curves of theresultant polarising signal for a conventional partially cross polarised mho and forOptimho are asymptotic. This meansthe reach of Optimho in the capacitive reactance region is the same as for a relaywith 16% sine wave cross polarising (see Figure 4-10).

Although Figure 4-10 is drawn for a constant fault voltage, the principles remainthe same for constant System Impedance Ratio (SIR) conditions. The higher the SIRthe lower the fault voltage and the larger the capture angle. Hence the relaybecomes progressively more cross polarised as the SIR rises, as previously shownin Figure 4-8.

Note : On Optimho 11* version "D", the polarising arrangement for thedirection line has changed - see Figure 4-9. By using the soundphase polarising signal to polarise the direction line, there is improveddirection stability for reverse faults, when importing heavy pre-faultload. On earlier versions of Optimho the directional linepolarising signal was dominated by the faltered phase, or phases.

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4.2.2 Synchronous polarising

The synchronous polarising signal is available for 16 cycles following a threephase close up fault. This time is sufficient to keep the Zone 1 comparators in astable condition for a reverse fault, until the fault is cleared by other protection. In

the case of a forward fault, 16 cycles is more than sufficient to allow Optimho totrip and clear the fault. (or to bring in breaker fail protection if necessary)

Under three phase close up fault conditions, the polarising signal is controlled bythe synchronous polarising signal Vmem A (see Figure 4-9). After 16 cycles thispower system frequency signal is replaced by 0.3% of -IA ZPh. This limits thedirectional sensitivity of the comparator, once the synchronous polarising hasexpired, to approximately 1.3% of rated voltage, for three phase faults.

The synchronous polarising system is implemented as a software control featureof a microcontroller on the Zone 1 / Zone 2 comparator board (see Section 6.9),

and the basis of the system is a set of 64 registers of 8 bits each, which may beimagined as being arranged in a carousel as shown in Figure 4-13. The carouselmay be regarded as rotating anticlockwise under healthy live conditions on thetransmission line.

Phase B voltage is used as a reference signal for prefault phase information, afterbeing squared by a high gain amplifier. The length of one half-cycle is measuredin units of 108µs (the timer interrupt period of the microcontroller) and thenumber of units is stored in a register. When this half-cycle finishes, the carouselis rotated anticlockwise by one register and the length of the next half-cyclemeasured and stored.

This process continues indefinitely, with new data overwriting the old when all 64registers are full.

To generate the synchronous polarising output signals, an examination is made of the data held in the 8th register anticlockwise from the present input register whenthe outputs are connected. This number is then used to determine the length of the output half-cycle required. When the output half-cycle has been produced thepolarity of the output is reversed and another examination is made of the dataheld in the next register anticlockwise from the last one used. The next half-cycle isgenerated accordingly. This process is repeated indefinitely, producing thesynchronous polarising output waveforms.

This method allows the reproduction of the frequency of the input signal VB. Theoutput is phase locked with the input, during healthy line conditions, by effectivelyadjusting the number in the output register by plus or minus one, every fourthoutput edge, to bring the output into phase with VB as closely as possible. Themicrocontroller also produces signals +120° and -120° with respect to VB,thereby providing three synchronous polarising signals Vmem A, Vmem B andVmem C.

When any voltage level detector resets, or any comparator operates, this isdeemed to be a faulty or dead line condition and the memory is allowed to run

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out. Under these circumstances, the direction of rotation of the carousel isreversed (see Figure 4-14) and the output is maintained from data previouslystored, for 32 half-cycles, after which the synchronous polarising output isdisconnected from the polarising mixing circuits. The data in the most recentlyrecorded registers are not used, because distorted voltage may be present in the

period just before the voltage level detector resets, or the comparator operates.During the 32 half-cycles of memory run out, the phase lock is disabled to protectthe synchronous polarising from any undesirable change in frequency.

A period of 25 half-cycles is allowed to occur after all voltage level detectorsbecome operated and all comparators are reset, before the synchronouspolarising is reconnected. Immediately before the synchronous polarising isreconnected, a comparison is made between the number in the current inputregister (equivalent to the elapsed time of the current half-cycle) and the numberin the next anticlockwise register (equivalent to the length of the previoushalf-cycle). The difference in time is effectively put into the output register, so that

when the synchronous polarising is reconnected, the output is in phase with theinput. Therefore, at the instant of reconnection, 16 half-cycles of accuratesynchronous polarising is available for Zone 1 comparator operation. Thismethod ensures that synchronous polarising is available after the expire of theSOTF enable time.

4.2.3 Offset mho characteristic

The offset mho characteristic for Zone 3 (not available on LFZP 114) is producedby the same type of phase comparator as for Zone 1 and Zone 2, but usingdifferent input quantities. (See Figure 4-15) i.e.

A1 = V + IZ' B1 = (V - IZ) /-90°

4.2.4 The lenticular characteristic

An offset lenticular characteristic is available for Zone 3 for long line applicationswhere load impedance may encroach on to an offset mho characteristic. Thelenticular characteristic is produced by the intersection of two circles as shown inFigure 4-16. The two circles are generated by two comparators using the samesignals as for a normal offset circular characteristic, but using different phaseshifts.

The inputs to the comparators then become:

A1 = V + IZ' )) comparator C1

B1 = (V - IZ) /-Φ° ) (main comparator)

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A2 = V - IZ )) comparator C2

B2 = (V + IZ') /-Φ° ) (inhibit comparator)

The intersections of the two circles occur on the characteristic angle of the relay

and determine the forward and reverse reach of the lenticular characteristic. Thereach remains independent of the comparison angles.

The aspect ratio, or ratio of the length of the minor and major axes of thelenticular shape, is determined by the angle Φ. The aspect ratio can be set to0.41, 0.67 and 1.00.

The block diagram is shown in Figure 4-17. The inhibit comparator consists onlyof basic circuitry for determining whether changes of state of the input signalsconstitute an operate or a restrain sequence. There is no counter associated withthe inhibit comparator as its purpose is only to provide a signal for the inhibit

terminal of the main comparator. Therefore the main comparator only producesa trip signal for faults within the lenticular characteristic.

4.2.5 The quadrilateral characteristic

The quadrilateral characteristic, available as an optional characteristic for theground fault comparators on Optimho type LFZP 111, offers an increasedcoverage of fault resistance for short lines with strong infeed, where the resistiveexpansion of the partially cross polarised mho may not be sufficient to cover hightower footing or ground contact resistance.

Only a single main comparator is needed to produce a quadrilateralcharacteristic, thus avoiding the race problems associated with characteristicsproduced by multiple comparators. As shown in Figure 4-18, the maincomparator of Zone 1 produces the top or "reactance" line of the quadrilateralfrom inputs:

A1 = V - IZ andB1 = INR, where INR = (IAR + IBR + ICR) /-3°

The vector INR is obtained from the line currents via three current transactors,after phase shifting (see description GJ0233, Section 6.7). The replica signals arebandpass filtered to remove exponential and high frequency components beforebeing mixed to produce an IR signal representing the residual current component.

The top line moves with active power flow to avoid the overreach or underreachproblems associated with phase current polarised reactance characteristics.

The other three sides of the Zone 1 quadrilateral are formed by three inhibitcomparators, that is, comparators without counters, arranged to inhibit the maincomparator. The main comparator can only count up when the three inhibitcomparators all agree that the impedance is within the operating zone (but seealso Section 4.2.6).

The signals used are as follows:

A2 = IZ ) right hand "resistance" lineB2 = V - IR )

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A3 = V + IR ) left hand "resistance" lineB3 = IZ )

A4 = VPol ) "directional" line

B4 = IZ )

Throughout, V is the faulty phase voltage, VPol is the partially cross polarisedvoltage described under "polarising mixing circuits" and IZ is the residuallycompensated vector (IPhZPh + INZN) from the transactors. The IR signal for theresistance lines is derived from the phase current only, the absence of residualcompensation permitting good phase selection for single pole tripping purposes.

This method of producing a quadrilateral characteristic has several advantagesover other methods:

a) Independent settings for reach and resistance coverage

b) Relay characteristic angle can be set to line angle giving fastestoperating speed for solid faults and optimum control of reachaccuracy

c) Good operating speed over the whole of the characteristic.

4.2.6 Two phase to ground faults (quadrilateral characteristic)

The operation of the quadrilaterial characteristic during two phase to ground

faults presents special problems. This type of fault may be measured in threeways:

a) Operation of the corresponding phase-phase element

b) Operation of the leading ground fault element

c) Operation of the lagging ground fault element

The operation of the phase-phase elements is practically independent of the faultresistance to ground. However, the measurement of the ground fault elementsunder these conditions, is affected by the resistance of the fault to ground. Theeffect being that the leading phase-ground element will tend to overreach and thelagging phase-ground element will tend to underreach.

The effect of arc resistance between phases and to ground can also have theeffect of making the leading phase-ground element underreach and the laggingphase-ground element overreach. (See Figure 4-19).

The amount of overreach, or underreach, depends on the arc and ground

resistances, the prefault load current and the type of polarisation used for the"top" or "reactance" line. In Optimho, the polarisation of the Zone 1 reactance lineis optimised for single phase faults, and a technique is employed to inhibit theoperation of the ground fault comparators for two phase to ground faults. The

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phase fault comparators, with their partially cross polarised shapedcharacteristics, are allowed to operate on two phase to ground faults.

The technique used to prevent operation of the quadrilateral ground faultcomparators is as follows:

The three Zone 1 ground fault comparators each have a corresponding "guard"zone, whose characteristic shape comprises the same side and directional lines asZone 1. The top line of the "guard" zone has ten times the reach of Zone 1 andhas different polarisation (IphZph∠-10°). The "guard" zone is generated entirelyfrom inhibit comparators and so its operating speed is only a fraction of a cycle.Due to the different polarisation employed for the reactance lines, under twophase to ground fault conditions the reactance lines of the Zone 1 and corre-sponding "guard" zone tilt with respect to each other (see Figure 4-19). This actionis used to advantage with the logic of Figure 4-20 to prevent operation of theground fault comparator. The ground fault comparators are allowed to operate if

the corresponding "guard" zone, and no other, operates. For example, for theexternal A-B-G fault condition depicted in Figure 4-19 which is 30% beyond Zone1 reach setting, it can be seen that the B phase Zone 1 reach line tilts such thatthe measured B-G impedance appears within B phase Zone 1 ground faultcharacteristic. The measured B-G impedance is also within the B phase "guard"zone characteristic. This would cause the B phase Zone 1 ground fault element tooperate if it was not for the fact that the measured A-G impedance appears withinthe A phase guard zone characteristic. The operation of the A phase guard zonein conjunction with the B phase guard zone ensures that all ground fault Zone 1comparators are inhibited due to logic action as depicted in Figure 4-20.

The "guard" zone system allows correct Zone 1 operation on single phase faultssince the phase selection properties of the guard zone comparators ensure thatonly the faulty phase guard Zone comparators operate. The 10:1 ratio of the"guard" zone reach for Zone 1 reach ensures that the resistive coverage of Zone 1is not seriously affected by any angular "droop" of the "guard" zone reactance lineunder load exporting conditions, caused by its non optimum polarising quantityfor single phase faults.

With the guard zone set to 10x reach, zone 1 may overreach for phase to phasefaults which occur on the far side of a star/delta transformer at the remote end of the line. If the impedance matrix is unbalanced, a small neutral current may beproduced, possibly high enough to pick up the biased neutral current leveldetector. If the phase of this neutral current is such that the top line of the zonequadrilateral becomes inverted, the guard zone no longer prevents zone 1 fromoverreaching.

To prevent this type of problem the zone 1 quadrilateral is gated with the zone 2quadrilateral of the same phases. Zone 2 has a top line polarised with phase plusneutral current and cannot invert under these circumstances.

Overreach of Zones 2 and 3 under two phase to ground fault conditions is lessserious than overreach of Zone 1 and can be tolerated, provided that gradingproblems between time delayed Zone 2 and Zone 3 back up trips do not occur.

To avoid having to provide guard zones for Zones 2 and 3, the polarising signal(IPhR + INR) for these two zones provides a compromise between single phaseand two phase to ground fault requirements. Any consequent errors are boundedby the accuracy claims for Zones 2 and 3.

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4.2.7 The offset quadrilateral

The offset quadrilateral characteristic of Zone 3 is produced in a similar way to

that of Zones 1 and 2, a further main comparator is used for the reverse reach,having vectors:

A5 = IPhR + INRB5 = V + IZ'

This is shown in Figure 4-21.

The outputs of the Zone 3 forward main comparator and Zone 3 reverse maincomparator are "ORed" to obtain the complete Zone 3 characteristic shape.

The side lines are shared with Zone 1 and Zone 2. The resistive reach of the righthand line is set via an option on the menu. The reach of the left hand line is set tobe 20% larger. This ensures that the reverse resistive coverage of Zone 3 isgreater than the forward resistive coverage of the overreaching Zone 2 elementsat the other end of the line. This will ensure that the protection is stable forexternal resistive faults in the blocking and permissive overreach schemes.

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4.2.8 Operate and polarising signals LFZP 11x

Function I/Ps Mho Quad

Zone 1AA1

B1

VA/K Z1 - IAZPh - INZN

VA+0.16[2VA-VB-VC+0.16VMA]/-90°=Vpol A

As Mho

INR

Zone1 ABA2

B2

(VA - VB)/K Z1 - (IA - IB)ZPh

(VA - VB) + 0.16Vpol C/-90°=Vpol AB

As Mho

As Mho

Zone 1 BA1

B1

VB/K Z1 - IBZPh - INZN

VB+0.16[2VB-VC-VA+0.16VMB]/-90°=Vpol B

As Mho

INR

Zone 1 BCA2

B2

(VB - VC)/K Z1 - (IB - IC)ZPh

(VB - VC) + 0.16VpolA/-90°

=Vpol BC

As Mho

As Mho

Zone 1 CA1

B1

VC/K Z1 - ICZPh - INZN

VC+0.16[2VC-VA-VB+0.16VMC]/-90°=Vpol C

As Mho

INR

Zone 1 CAA2

B2

(VC - VA)/K Z1 - (IC - IA)ZPh

(VC - VA) + 0.16Vpol B/-90°=Vpol CA

As Mho

As Mho

Zone 2 AA1

B1

VA/K Z2 - IAZPh - IN ZN

Vpol A

As Mho

IAR + INR

Zone 2 AB

A2

B2


Vpol AB

As Mho

As Mho

Zone 2 BA1

B1


V pol B

As Mho

IBR + INR

Zone 2 BCA2

B2

(VB - VC)/K Z2 - (IB - IC)ZP

Vpol BC

As Mho

As Mho

Zone 2 CA1

B1


Vpol C

As Mho

ICR + INR

Zone 2 CAA2

B2

(VC - VA)/K Z2 - (IC - IA)ZPh

Vpol CA

As Mho

As Mho

A DirectionalDA1

DB1

-IAZPh - INZN

(VB - VC) + 0.16Vpol A

Vpol A

IA ZPh + INZNA Left Hand

Side Line

DA2

DB2

Not Used

Not Used

VA + IAR

IAZPh + INZN

B DirectionalDA1

DB1

-IBZPh - INZN

VC - VA + 0.16Vpol B

Vpol B

IBZPh + INZN

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B Left Hand

Side Line

DA2

DB2

Not Used

Not Used

VB + IBR

IBZPh + INZN

C DirectionalDA1

DB1

-ICZPh - INZN

VA - VB + 0.16Vpol C

Vpol C

ICZPh + INZNC Left Hand

Side Line

DA2

DB2

Not Used

Not Used

VC + ICR

ICZPh + INZN

AB DirectionalDA1

DB1

-IABZPh

VQC=2VC-(VA+VB)+0.16VmemC

Vpol AB

IABZPhA Right Hand

Side Line

DA2

DB2

Not Used

Not Used

IAZPh + INZN

VA - IAR

BC Directional

DA1

DB1

-IBCZPh

VQA=2VA-(VB+VC)+0.16memA

Vpol BC

IBCZPh

B Right Hand

Side Line

DA2

DB2

Not Used

Not Used

IBZPh + INZN

VB - IBR

CA DirectionalDA1

DB1

-ICAZPh

VQB=2VB-(VC+VA)+0.16VmemB

Vpol CA

ICAZPhC Right Hand

Side Line

DA2

DB2

Not Used

Not Used

ICZPh + INZN

VC - ICR

Zone 3 AA1

B1

(VA/K Z3 - IAZPh - INZN)/-∅

VA/K Z3' + IAZPh + INZN

VA/K Z3-IAZPh-INZN

IAR + INR

Zone 3 ABA2

B2

(VA - VB)/K Z3 - (IA - IB)ZPh/-∅

(VA - VB)/K Z3’+ (IA - IB)ZPh

As Mho

As Mho

Zone 3 BA1

B1

(VA/K Z3 - IBZPh - INZN)/-∅

VB/K Z3’+ IBZPh + INZN


IBR + INR

Zone 3 BCA2

B2

(VB - VC)/K Z3 - (IB - IC)ZPh/-∅

(VB - VC)K Z3' + (IB - IC)ZPh

As Mho

As Mho

Zone 3 CA1

B1

(VC/K Z3 - ICZPh - INZN)/-∅

VC/K Z3' + ICZPh + INZN


ICR + INR

Zone3 CAA2

B2

(VC - VA)/K Z3 - (IC - IA)ZPh/-∅

(VC - VA)/K Z3' + (IC - IA)ZPh

As Mho

As Mho

Zone 3' AA1

B1

Not Used

Not Used

IAR + INR

VA/K Z3' + IAZPh +INZN

Zone 6 ABA2

B2

(VA - VB)/K Z6 - (IA - IB)ZPh/-∅

(VA - VB)/K Z6' - (IA - IB)ZPh

As Mho

As Mho

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Zone 3' BA1

B1

Not Used

Not Used

IBR + INR

VB/K Z3' + IBZPh +INZN

Zone 3'CA2

B2

Not Used

Not Used

ICR + INR

VC/K Z3' + ICZPh +INZN

Zone 3 A INHDA1

DB1

VA/K Z3 - IAZPh - INZN

(VA/K Z3' + IAZPh + INZN)/-∅

Not Used

Not Used

Zone 3 AB INHDA2

DB2


(VA - VB)/K Z3' + (IA - IB)ZPh/-∅

Not Used

Not Used

Zone 3 B INHDA1

DB1


(VB/K Z3' + IBZPh + INZN)/-∅

Not Used

Not Used

Zone 3 BC INHDA2

DB2

(VB - VC)/K Z3' - (IB - IC)ZPh

(VB - VC)/K Z3' + (IB - IC)ZPh/-∅

Not Used

Not Used

Zone 3 C INHDA1

DB1


(VC/K Z3'+ ICZPh + INZN)/-∅

Not Used

Not Used

Zone 3 CA INHDA2

DB2

(VC - VA)/K Z3' - (IC - IA)ZPh

(VC - VA)/K Z3'+ (IC - IA)ZPh/-∅

Not Used

Not Used

A Guard ZoneDA1

DB1

Not Used

Not Used

VA/10K Z1 - IAZPh

IAZPh/-10°

Zone 6 AB INHDA2

DB2


(VA - VB)/K Z6'+ (IA - IB)ZPh/-∅

Not Used

Not Used

B Guard ZoneDA1

DB1

Not Used

Not Used

VB/10K Z1 - IBZPh

IBZPh/-10°

C Guard ZoneDA2

DB2

Not Used

Not Used

VC/10K Z1 - ICZPh

ICZPh/-10°

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CVT ERROR

(BEFORE SQUARING AND

INCIDENCE

FAULT

POLARISING VOLTAGE

16% SYNCHRONOUS

PHASEVOLTAGE

FAULTY

90 PHASE SHIFT)

POLARISING

Figure 4-7 Action of synchronous polarising

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Figures are S.I.R.s

0 1 6 2412 60

Figure 4-8 Resistive expansion of partially cross - polarised mho

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VQBC = (VB - VC) + 0.16VPOL A

VKA = 2VA - (VB + VC) + 0.16Vmem A

Vmem A

VC

VB

VA

-

+

R4

R2

R3

R1

IC1

-90 o

BC Directional polarising

-90 o

-

+

IC4

R11

0V

0V

-

+

-12V

0V

0V

R5

R10

R9

R8

IC3

VPOL A

-

+

0V

R7

R6

IC2

0V

Vpol BC

Vpol A

VQA=2VA-(VB+VC)+ 0.16 Vmem A

A phase directional polarising signal

LFZP11X only

Figure 4-9 Zone 1/1X/1Y/2 polarising arrangement LFZP 111/112/113/114

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140

ANGLE OF PRE-FAULT VOLTAGE

Cross-polarised16% Sinewave

100% Cross-polarised

100% Cross-polarised

16% Sinewave

Cross-polarised

16% Squarewave

Cross-polarised

Faulted voltage = 25%

100% Self-polarisedX

100% Self-polarised

RELATIVE TO PRE-FAULT POSITION

DISPLACEMENT OF FAULTED-PHASE VOLTAGE [ LAG]

40

POLARISING

0 20

20

40

100

120

60

80

60 80 120100

Cross-polarised

COVERAGEEXTRA RESISTIVE

R

16% Squarewave

140

RELATIVE TOPRE-FAULT

RESULTANT

SIGNAL

[ LAG]

ANGLE OF

Figure 4-10 Comparison of polarised characteristics

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Resultant Polarising (before -90 phase shift)

16%A

30

Faulted Phase voltage (-30 displacement)

Cross-polarising voltageB

D

C A

90

A

180 270

D

360 etc.

C16%

16%B

B+

Figure 4-11 Critical angle

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16%

16%

90 180 270 etc.360

16%

A

B

C

D

20

60

Resultant Polarising (-20 displacement)

Faulted Phase voltage (-60 displacement)

B

D

C A +

A

B

Cross-polarising voltage

(Before -90 phase shift)

Figure 4-12 Critical angle

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4TH EDGE AND ADJUSTED + 1 COUNT

'DATA IN' IS MEASURED LENGTH

OF HALF CYCLE IN UNITS OF 108us

SYNCHRONISM CHECKED EVERY

ELAPSED TIME

92 92 93 92 91

ANTICLOCKWISEROTATION

92DATA OUT

DATA IN

92 9392 9192 9192

HALF CYCLE GENERATED

USING 'DATA OUT'

91 92 92

9291

9292

Figure 4-13 Synchronous polarising healthy live line conditions

92

ROTATION

REVERSED

4158 92219392

HALF CYCLE GENERATED

92

USING 'DATA OUT'

DATA OUT

92

9192

92

92 93

Figure 4-14 Synchronous polarising faulty line conditions

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ZI

j I X

V-IZ

-IZ`

(V+IZ`) -90

V+IZ`

V

I R

Figure 4-15 Sequence comparator voltages for offset mho characteristic

COMPARATORINHIBIT

I

(V-IZ) V-IZ

(V+IZ`)

B

AV+ Z`

- I Z`

I

B

IZ

A

COMPARATORMAIN

j I X

R

Figure 4-16 Lenticular characteristic

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0.67

ASPECT

RATIO

a

b= 1.00 0.41

COMPARATOR

LENTICULAR ZONE 3

tan (180 - )ab = 1

2

COMPARATOR

PHASESHIFT

V+IZ' B

INHIBIT

C2

INHIBIT

A

MAIN

C1

V-IZ

A

90= 67.5 45

PHASE

SHIFT

B

LOAD

BOUNDARY

OF

OUTPUT

Figure 4-17 Lenticular characteristic block diagram

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ZI

3

I X

tilt

( see Fig.4-21 )

Left hand sideline

has 20% more

resistive reach

- R

B3= ZI

RIRI

A4= Vpol

II

A3= Vph + Iph 1.2 R

ph

B4= Iph Zph + In Zn

A2= Iph Zph + In Zn

B2= Vph - Iph R

B1= In R

A1= Vph Zph - In Zn

Figure 4-18 Quadrilateral Zone 1

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Z1

A-G GUARD ZONE

QUAD TO TOP LINE

10X Z1ph

R.H. QUAD

TOP LINE OF QUAD

10X Z1ph

ZN(RESIDUAL COMP)

Z1phZ1

B-G GUARD Zone

-10

Zn

Zph

R.H.GUARD ZONE(R.H. QUAD)

Figure 4-19 Behaviour for A - B - G fault

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Guard Zone C

Pole dead C

&

Pole Dead B

Guard Zone A

Pole Dead A

Guard Zone B

&

&

&Inhibit Zone 1 C-G

1=

&

&Inhibit Zone 1 B-G

Inhibit Zone 1 A-G

Figure 4-20 Guard zone logic

B1 = IPhR+INR

has 20% more

resistive reach

Left hand sideline

-IR

B5 = V+IZ`

-IZ`

A5 = IPhR+INR

IR

A3 = V+IR

B3 = IZ

3 tilt

IZ

IX

B2 = V-IR

A2 = IZ

A1 = V-IZ

I

Figure 4-21 Quadrilateral zone 3

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4.3 Level detectors

4.3.1 Introduction

On de-energising a transmission line, line voltage transformers can supply one inputterminal of the comparators with low frequency voltage waveforms, particularly if electromagnetic transformers are connected to the isolated line. To avoid the risk of false operation of the relay comparators caused by the continuing presence of synchronous polarising of the other input of the comparators, phase current leveldetectors are provided. These have a very fast reset time and are used to blockcomparator operation when the line is de-energised as shown in Figure 4-22. Theactual blocking operation is performed under software control in the mainmicrocontroller.

The principle of operation of the current level detectors is explained with the help of

Figure 4-23. If the instantaneous amplitude of the input voltage (VIN) exceeds athreshold setting VREF either on a positive half cycle or on an inverted negative half cycle, a timer T1 is started. If T1 finishes before the non inverted or the inverted inputsignal has fallen below VREF, the input sine wave is known to be greater than thelevel detector setting and the output is set high.

At the same time as the output is set, a second timer T2 is started, whose purpose isto bridge the time interval between the positive and negative half cycles. So while T2is running, the output cannot reset. When the level VREF is exceeded on the next half cycle, the output is kept in the operated state. Only if the threshold level fails to beexceeded on the next half cycle, is the output reset after T2 finishes. The output alsoresets if the input signal becomes a unidirectional signal greater than VREF, afterboth T1 and T2 have timed out. Positive feedback is applied from output to input togive a reset/operate ratio of 0.85 to prevent chatter when the input signal is at thepick-up level.

The current level detectors are designed to restrict the operative range of the relay,preventing excessive sensitivity, although because they have a low setting (5% of rated current at the relay reference setting), this restriction does not constitute anypractical disadvantage. Hence the maximum SIR for ground faults is 126 and forphase faults is 219. The operating time of the level detector circuit is fast enough notto limit the minimum operating time of the relay. The maximum reset time of thelevel detector is less than the fastest practical comparator operating time.

4.3.2 Inhibition of the comparator

With busbar voltage transformers, the comparator returns naturally to a restrainedcondition when the circuit breaker is opened. However, when line voltagetransformers are used the relay must take special measures to ensure thecomparators reset when the line is de-energised.

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In addition to the current level detectors, the relay contains voltage level detectorsoperating on a similar principle, with a setting of approximately 70% of ratedvoltage. If the transmission line is de-energised, the voltage and current level detec-tors of the de-energised poles reset, a "pole dead" signal is produced and after 20ms

is supplied to the "inhibit" terminals of the relevant comparators as shown in Figure4-24. This terminal, when activated, causes the counter of the comparator to registerall changes of state of each input A and B as down counts. The counters of anycomparators which have operated, will be rapidly decremented to zero when thetransmission line is de-energised. The implementation of the "Pole Dead" signals isperformed by software operations in the main microcontroller.

With 3 pole tripping there may be no signal on either input of the comparator duringthe time the line is de-energised. Under these conditions the comparator may remainoperated or partially operated. To ensure a full reset on detecting all the poles aredead all the comparators are reset by the main microcontroller.

4.3.3 Single pole tripping

The level detectors are also beneficial when single pole tripping of the circuitbreakers is required when using line voltage transformers. Following a single phaseto ground fault and a single pole trip, the output of the ground fault comparator isblocked by the resetting of the relevant phase current level detector and thecomparator is forced to count down by the relevant pole dead signal. Thus the relayresets correctly even though the presence of residual current due to load and thepresence of sound phase cross polarising, may appear as an impedance within therelay characteristic.

4.3.4 Phase selection

A problem with full scheme distance relays is that heavy close up single phase faultscan sometimes intrude into the operating characteristics of the phase faultcomparators, causing a three pole trip where a single pole trip would beappropriate. In Optimho a special neutral current level detector is used to block thephase fault comparators to prevent this type of incorrect trip.

This neutral current detector, known as the "high set" (LDHSN), has a setting levelwhich is biased by the maximum amplitude of phase difference current flowing atany time. The three phase to phase signals IA-IB, IB-IC and IC-IA are rectified by aprecision three phase full wave rectifier and a peak level formed by a fast chargeslow discharge smoothing circuit. A fixed proportion of this level is then used as thevalue VREF in a level detector of the type previously described. See Figure 4-25.

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In order to prevent chatter of the output and also to give the level detector aminimum sensitivity under no load or very low load conditions, a fixed minimumreference level is "ORed" with the variable reference.

For practical reasons, an upper limit to the reference level is used to ensure thatunder very heavy fault current conditions the detector will operate correctly and notbe limited by internal power supply rails.

The signal input to the neutral detectors is derived by summing together theindividual phase current signals, in order to maintain the relay sensitivityindependent of residual compensation setting.

A similar "low set" neutral current detector (LDLSN) is used to enable the ground faultcomparators, thereby preventing wrong operation of a ground fault comparatorunder heavy close up phase-phase fault conditions. See Figure 4-26. The low setneutral detector is also used by the Voltage Transformer Supervision feature since it

has a high degree of immunity from operating under unbalanced load conditions.

Biasing the neutral current detector has distinct advantages. The detector can be setsensitive enough to operate for all single phase faults which could cause phase faultcomparator maloperation, without any risk of the detector picking up on neutral spillcurrent during phase to phase faults. Neutral spill current arises from mismatchedcurrent transformers, CT saturation, etc. The biasing also ensures that the phase faultcomparators are generally enabled during two phase to ground faults, permittingthe relay to give its fastest possible three pole trip. For two phase to ground faultswith high resistance in the neutral, only the phase fault comparators are enabled,avoiding possible measuring errors which ground fault comparators can exhibitunder these conditions. For conditions where the fault resistance places the faultimpedance just outside the ground fault comparator characteristic, but with sufficientneutral spill current to still block the phase fault comparators, a special logic featureis employed (see Figure 5-3) whereby if the "high set" detector operates for 35mswithout any Zone 1 or Zone 2 ground fault comparator operating, then the "high set"block of the phase fault comparator is removed.

4.3.5 Other level detectors

A zero sequence voltage detector is used in the voltage transformer supervisionfeature. This is described in the VTS section. Three high set phase current detectorswhich have settings 50% higher than the low sets are used in some schemes, such asthe Blocking scheme and the Permissive Overreach scheme with weak infeed. Theoptional DEF feature uses three additional level detectors, two operating on zerosequence current and one on negative sequence current. These are described in thesection on DEF.

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COMPARATOR

LEVEL DETECTOR

I LOW SET

V POL

POLE DEAD

B

A

INHIBIT

&

OUT

TRIP

V-IZ

Figure 4-22 Level detector gating of distance comparators

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VIN

YESMODULUS OF

IS

START

NO

-Vref

+Vref

T1

T1 T2

SET OUTPUT LOW

RESTORE Vref

IS

START TIMER T1

SET OUTPUT HIGH

RESET TIMER T2

START TIMER T2

LET Vref=Vref*0.9

SET FLAG

YES

TIMER T1NO

RESET?

NO

IS

INSTANTANEOUS

VALUE OF Vin

> Vref?

YES

IS

SET?

FLAG YES

FINISHED?

TIMER T1

YES

HASNO

RESET TIMER T1

RESET FLAG

TIMERS RESET

OUTPUT LOW

Vref NORMAL

FLAG RESET

INITIAL

CONDITIONS

TIMER T2

NO

RUNNING?

Figure 4-23 Level detector

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0

t

22.5msLEVEL DETECTOR

LEVEL DETECTOR

LOW SET CURRENT

VOLTAGEV

I

1TO INHIBIT

COMPARATORS

POLE DEAD

SIGNAL

Figure 4-24 Level detector inhibiting of distance comparators

LDIA

LIMITS MAX VALUE

OF REFERENCE

PRECISION FULL WAVE RECTIFIER

BASE REFERENCE LEVEL

LDIC

LDIB

LEVEL

REFERENCE

FAST CHARGE

SLOW DISCHARGE

Figure 4-25 Biased reference level

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GREATEST PHASE DIFFERENCE CURRENT

Figure 4-26 Biased neutral current level detectors

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4.4 Directional overcurrent ground fault protection (DEF)

4.4.1 Introduction

The directional ground fault (DEF) feature is used to cover high resistance ground

faults. It employs separate forward and reverse looking directional elements, twozero sequence current level detectors and an overcurrent unit.

The directional elements have four types of polarising allowing a choice of zerosequence voltage, zero sequence current, dual zero sequence current and voltage,and negative sequence voltage.

The directional units are used in a number of aided tripping schemes. Theovercurrent unit allows for time delayed backup tripping with a choice of definitetime, inverse IEC or American curves.

Stabilisation against magnetising inrush currents when energising a line with in-zonetransformers is provided.

4.4.2 Implementation

Most of the hardware required to implement the DEF protection is located on theDEF board ZJ0139. The level detectors are on the level detector board ZJ0136 andthe controlling logic is run in the main processor on ZJ0138.

Figure 4-27 shows a simplified block diagram of the hardware. Figure 4-28 showsthe logic equivalent of the software.

4.4.3 Directional elements

The directional elements employ two sequence comparators of the type described inSection 4.1 one being forward looking, the other reverse. The A and B inputs aredependent on the type of polarising selected and are shown in Figure 4-29 for theforward looking element. The inputs are reversed for the reverse looking element.

The directional element inhibit is controlled by the low set zero sequence leveldetector (LDLSI0), and by the high set level detector (LDHSI0)(If the DEF aidedtripping is selected).

The level detectors ensure the comparators are fully restrained under all but faultconditions. Without this check the unbalance in the zero sequence quantities wouldresult in the comparators partially operating and thus less stable.

The directional element has an adjustable characteristic angle THETA G, set via themenu, which covers the range 10° to 80°.

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4.4.4 Level detectors

The level detectors used are similar to those described in Section 4.3. The differenceis that the operate levels are adjustable and settings are provided via the menu.

The operate levels of the DEF low set and the DEF high set zero sequence currentlevel detectors are independent and they determine the sensitivity of the directionalelements.

An additional negative sequence current level detector is employed when negativesequence polarising is used. Its setting is 70% of the DEF low set zero sequence leveldetector, or if DEF aided tripping is enabled, 70% of the lower setting of either thelow set or high set zero sequence level detectors. This ensures that sufficient negativesequence current is present for the comparators to function correctly. For relays withthe power swing blocking feature enabled the setting changes to 100% duringdetected power swings (Section 5.5). This ensures the level detector does not operate

due to large spill currents during the power swing.

4.4.5 Operation in single pole tripping schemes

The DEF cannot give single pole trips but it can be used in conjunction with thedistance comparators in single pole tripping schemes. When a single pole is openthe DEF cannot derive suitable quantities to operate correctly and therefore must bedisabled. The Single Pole Open optical isolator is used for this purpose. To cover thetime difference between the relay issuing a single pole trip and the optical isolatorbeing energised internal logic is used to inhibit the DEF.

In aided schemes with single pole tripping selected the distance comparators aregiven priority to trip single pole were possible. This condition is detected if a singleZone 2 ground fault comparator operates and logic blocks the DEF. This allows thedistance to trip single phase.

4.4.6 Operation with voltage transformer supervision

The DEF directional units are stable to a fault in the ac voltage supply, because thereis no zero sequence current flowing. However if a subsequent transmission line faultoccurs the DEF could maloperate. To prevent this the DEF is inhibited by thesealed-in VTS block signal which occurs 5.5 seconds after detection of the ac supplyfailure. The Block Relay optical isolator also inhibits the DEF.

4.4.7 Magnetising inrush current detector

A magnetising current inrush detector is used to prevent maloperation whenenergising multiple in-zone transformers. The circuit uses the principle of detectingzeros in the current lasting for a quarter cycle or more. See Figure 4-30. Thisdetector is selected or deselected by the menu.

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4.4.8 Polarising

There are four types of polarising selectable via the menu allowing a choice of zerosequence voltage, zero sequence current, dual zero sequence current and voltage,and negative sequence voltage. System operating conditions may determine which

type is required.

The zero sequence voltage is derived internally from the three phase-neutralvoltages. In some system configurations the level of zero sequence voltage producedis insufficient to polarise the directional elements.

Zero sequence current may be used if system configuration allows a suitable currentfrom say the neutral current transformer of a local power transformer with anearthed neutral or the neutral current of an earthing transformer.

In certain systems dual polarising is used if the possibility of low zero sequence

voltage and or loss of current polarising is present.

Negative sequence polarising can be used if zero sequence is not possible or ondouble circuit lines where coupling can cause problems.

It should be noted however that on versions of Optimho fitted with both a DEFelement and a fault locator the DEF zero sequence current polarising input is sharedwith the mutual compensation current input terminals. Thus DEF zero sequencecurrent polarising cannot be used at the same time as fault locator mutualcompensation.

4.4.9 Negative sequence filters

Negative sequence voltage and currents are derived using filters. Most filters areprone to unacceptable errors as the frequency drifts away from the nominal thuslimiting the sensitivity. These errors are overcome by a filter which has 8 centrefrequencies and automatically adjusts itself to the nearest one thus maintainingerrors below the required sensitivity level. See Figure 4-31.

4.4.10 Directional overcurrent backup protection

The overcurrent unit allows for time delayed backup tripping. It is made directionalby the forward looking directional element. A range of sensitivities with a choice of definite time, inverse IEC or American curves are available controlled via the menu.

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Figure 4-27 Simplified DEF block diagram

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Figure 4-28 DEF control & backup logic

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COMPARATOR

COMPARATOR

INHIBIT

INHIBIT

3I 0 -90

3I 0 -90

3I 0 -90

3I 2b -90

DEF AIDED En (menu)

Scheme

All Schemes

Blocking

Blocking

POR 2 WI TRIP

All POR

All POR

DEF_F . LDHSI0

DEF_R

Signal

DEF_F

CpDEF_R

LDLSI0

LDHSI0 &

Current Reversal

Trip

CRX

CRX

Enables overcurrent

&

&

Use

Trip

1

DUAL VOLTAGE & CURRENT

LDLSI0

LDHSI0

LOW SET I0

LEVEL DETECTOR

LEVEL DETECTOR

DEF AIDED EN (menu)

HIGH SET

CpDEF_F

3I0

I0

ZERO SEQ VOLTAGE

ZERO SEQ CURRENT

NEGATIVE SEQ VOLTAGE

POLARISING

1INPUT 2

&

B

A

B

3V2b -THETA G

3VO -THETA G

3VO -THETA G

INPUT 1

INPUT 1

pI

A

+ kI p

DEF_R

DEF_F

OUT

CpDEF_ROUT

CpDEF_F

INPUT 2

Figure 4-29 Simplified DEF inhibit and control logic

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3 Block if gap > 1/4 cycle. Block resets after 2 cycles if no reappearance of gap.

2 Bias of 1/3 peak chosen for immunity to operation on saturated CTs

1 Threshold level 1/3 of peak up to rated current, then fixed at higher currents

Waveform after differentiation

Inrush current waveform

Full wave rectified signal shows gaps

Notes

Figure 4-30 Principle of magnetising inrush detector

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3V2B = -(VAB+VCA 60)

3I2B = -(IAB+ICA 60)

44

Required sensitivity

error

%

42 43

0

2

4

6

8

f Hz

Adaptive filter

45 46 47 48 49 50 51

Graph of % error in V2B against frequency

for balanced inputs

-IBX

10

12

14

-ICX

VB

Signal

Mixing

-IAX

VC

VA

Fixed filter centre 50Hz

Negative Seq Filter

circuit

Controller

Tracking

Frequency

Adaptive 60 deg

Phase advance

Phase advance

Adaptive 60 deg

Negative Seq Filter

circuit

5352

Figure 4-31 Adaptive negative sequence filters

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4.5 Fault locator

4.5.1 Introduction

The Optimho fault locator uses an algorithmic method to provide a distance to faultlocation feature with metering capabilities. The data input to the algorithm is filteredusing established digital signal processing techniques.

The measuring accuracy of the fault locator is ± 2% at 2In, fn, 20°.

The data processed by the algorithm is first acquired by performing analogue todigital conversion on signals provided by the relays internal analogue bus and thenperforming the necessary calculations.

The metering values are continuously calculated, regularly updated and passed to

the relays microcontroller when requested.

Acquired data is written to a buffer until a fault condition is notified by themicrocontroller. This input buffer data is held pending the fault calculation and inputdata is redirected to an alternative buffer.

The fault calculation is initiated by a signal from the relay main microcontroller.When the fault calculation is complete the output information is stored in non-volatilememory and made available to the microcontroller for display on the relay frontpanel.

Where parallel circuits are hung on opposite sides of a route of towers, mutual fluxcoupling alters the impedance seen by the fault locator. In practice the positive andnegative sequence coupling is insignificant and the effect on the fault locator of thezero sequence mutual coupling can be eliminated by using the mutual compensationfeature provided.

It should be noted however that on versions of Optimho fitted with both a DEFelement and a fault locator the mutual compensation current input terminals areshared with the DEF zero sequence current polarising input. Thus DEF zero sequencecurrent polarising cannot be used at the same time as fault locator mutualcompensation.

The fault locator is optional on the underground cable version of the relay (type LFZP113) where it is recommended that it is used for metering purposes only (see Section4.5.8) since fault location accuracy cannot be relied upon for this application.

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4.5.2 Basic theory for ground faults

A two-machine equivalent circuit of a faulted power system is shown in Figure 4-32.

From this diagram :

Vp = mIpZr + IfRf (equation2.1)

This equation shows that the calculation of m, the distance to fault, based onmeasurements of Vp and Ip at the local relay terminals is distorted by the IfRf term.

This term is related to the current infeed from the remote terminal and cannot bereadily measured. However its effect can be minimised as follows:

The real and imaginary components of these vectors (with respect to an arbitraryvector reference) vary with time as:

Vp[cos(ωt+s)+jsin(ωt+s)] = mZrIp[cos(ωt+e)+jsin(ωt+e)] +Rf If [cos(ωt+d)+jsin(ωt+d)].

where d is the angle of the fault current.s is the angle of Vp.

and e is the angle of IpZr.

By evaluating equation 2.1 at the instant in time when the fault current passesthrough zero and considering only the real components, then the Rf If termbecomes zero i.e. t = ((π/2)-d)/ω and the equation simplifies to:

Vpcos(((π/2)-d) + s) = mZrIpcos(((π/2)-d) + e)

Therefore the fault location m can be calculated if the angle of the faultcurrent d is known.

Estimating d the phase of the fault current If

The fault vector If is obtained from an algorithm which uses superimposed currents,that is, the change of currents following the instant of fault.Superimposed currents are indicated with a dash mark ( ' ).

The sequence diagram for superimposed currents for an A-G fault is shown in Figure4-33.

For an A phase to ground fault:

0.33If = I1' = I2' = I0' (equation 2.2)

From which

0.66If = I1' + I2'

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= Ip1'D1 + Ip2'D2

where:

D1 = I1' / Ip1' and D2 = I2' / Ip2'

and

D2 approximately = D1 (assuming that the power system source andline positive and negative sequenceimpedances are approximately equal)

therefore

0.66If = D1(Ip1' + Ip2') (equation 2.3)

also

Ip' = Ip1' + Ip2' + Ip0'

therefore

Ip1' + Ip2' = Ip' - Ip0' (equation 2.4)

from equations 2.3 and 2.4

0.66If = D1 (Ip' - Ip0')

Hence angle If = angle D1 + angle (Ip' - Ip0')

where:

D1 = A SCALAR factor - assuming that the power system is homogeneous

= (Zsp1 + Zl1 + Zsq1) / ((1-m)Zl1 + Zsq1)

The angle of D1 depends upon the fault position but for the purposes of thisalgorithm this angle is assumed to be zero.

Thus:

angle If = d = angle (Ip' - Ip0') (equation 2.5)

Equation 2.5 shows that the phase angle of the fault current d can be estimated fromthe superimposed phase and neutral currents measured at the relay terminals.

therefore for a ground fault:

If (cos(d) + jsin(d))

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= kD1(Ip'-Ip0')= kD1[(Ia(fault) - Ia(prefault))- 0.33(In(fault) - In(prefault))]

where:

k is a scalar factor and d is the required phase angle of If at the instant of time thatthe faulted vectors are calculated.

similarly for a phase to phase fault:

If (cos(d)+ jsin(d)) = kD1[(Ia(fault) - Ia(prefault)) - (Ib(fault) - Ib(prefault))]

Thus using the calculated pre-fault and faulted vectors the fault locator is able tocalculate the angle of the fault current vector d at the instant of time that the faulted

vectors are calculated.

4.5.3 Data acquisition

The microprocessor commences sampling at a rate of 40 samples per cycle as soonas initialisation is complete. Sampling is then performed continuously and thesamples stored within a 16 cycle cyclic buffer.

Two interrupts control the sampling system; timer interrupt 1 and interrupt 0.

The whole sampling system is triggered off by timer interrupt 1. This interrupts the

processor and also provides an output signal pulsing at the sample rate to the dataacquisition system. At the start of the interrupt, the 80C186 moves the data from thelast-acquisition temporary buffer into one of five 16 cycle cyclic sample buffers. Thisensures that ample fault data buffering is available under practical fault conditions.While this is happening, the data acquisition system hardware acquires the nexteight samples (3 voltage, 4 current and 1 unused) and converts them to digitalwords. At the end of each conversion the data acquisition system hardware assertsinterrupt 0 which puts the sample into the last-acquisition temporary buffer. Thus foreach sample period, there is one timer interrupt and eight sample interrupts. Thetimer interrupt also handles the management of the five cyclic sample buffers. Thesample buffer is changed 6 cycles after the relay has tripped so that the correct set of data is fed to the fault calculation routines.

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4.5.4 Cyclic buffer processing

The cyclic sample buffer to be processed contains 16 cycles of data, 10 cycles of pre-trigger and 6 cycles of post-trigger. Fault calculation commences shortly after

this trigger point when a signal is received from the relays microcontroller.

The instant at which a fault calculation is triggered depends upon the STARTSENABLED or STARTS DISABLED setting on the relays settings menu.

If STARTS are ENABLED the trigger point corresponds to the relays start and a faultlocation will be provided whether or not the event results in a trip.

If STARTS are DISABLED the trigger point corresponds to the relays trip and faultlocations are provided for all relay trips.

The fault locator has five cyclic sample buffers for acquired data. At any moment intime one buffer must be in use for acquiring new data thus the fault locator can storeraw data for up to four faults. If more than four faults occur within a 20 secondperiod the fault locator may ignore faults until a fault data buffer is free.

The fault position and the breaker open position are first identified within the dataset, so that the fault duration can be determined. Then the fault type is identifiedusing a phase selection algorithm - see below - which uses superimposed currents.(i.e. The change in current caused by the fault.)

The instant of fault is determined by searching the data applicable to the current inthe faulted phase. The routine looks for a significant increase in current over onecycle. A 'significant increase' is 12.5% or more of the sample value but not less thana minimum threshold of 20 digital steps.

If no instant of fault can be found this implies that STARTS are disabled and the relayoperating time was greater than 10 cycles. In this case the fault locator assumes prefault current to be zero and the fault position to be three quarters of a cycle prior tothe relay trip point. Under these conditions the fault locator output will report "n/a"for pre fault values.

The breaker open position is determined by first finding at least 10 samples of zerocurrent (i.e. less than the minimum threshold ) at the end of a data set and thensearching backwards in time to find the point where two successive current samplesexceed the minimum threshold. This point is the breaker open position. In the eventof the breaker open position not being found within the data set the fault locatorreports 'n/a' for the fault duration.

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Faulty phase selection

Superimposed phase to phase currents are first examined to determine if the faulttype is a single phase to ground fault or a multiphase fault.

The maximum superimposed phase to phase current, Ippmax, is found and eachsuperimposed phase current is compared with it to identify if it is >25% or <25% of it, then the fault can be identified from the following chart (where superimposedcurrents are labelled with a ∆) :

Fault type ∆Ia-b ∆Ib-c ∆Ic-a

a-gnd > 25% < 25% > 25%

b-gnd > 25% > 25% < 25%

c-gnd < 25% > 25% > 25%

Multiphase > 25% > 25% > 25%

If this test identifies a multiphase fault the superimposed phase currents areexamined to identify a phase to phase fault.

The maximum superimposed phase current (Ipmax) is found and each superimposedphase current is compared with Ipmax to identify the fault type from the following

chart :-

Fault type ∆Ia ∆Ib ∆Ic

a-b > 25% > 25% < 25%

b-c < 25% > 25% > 25%

c-a > 25% < 25% > 25%

a-b-c > 25% > 25% > 25%

Identification of a phase to phase to ground fault is not required by the Optimhofault locator as these are treated as phase to phase faults.

If the fault type is identified as a-b-c then this situation is treated as being equivalentto 3 separate phase - phase faults occurring simultaneously and ideally the result of the fault calculation in each case would be the same. However, for lines which arenot fully transposed each calculation produces a slightly different result. Because of this all 3 fault locations are calculated and the smallest is used as the result.

4.5.5 Fourier filtering

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The real and imaginary components of each of the input signals is evaluated fromdata windows around the fault position selected as shown in figure 4-34. Each datawindow is 46 samples long. The pre fault data window ends 0.5 cycles prior to thefault position and the post fault data window ends 1.5 cycles after the fault position.(see Figure 4-34.)

The real component (or cosine term) of an input signal is obtained by multiplying aset of 40 samples by a cosine wave of fourier coefficients. These fourier coefficientsare calculated from the formula:

cosine_constant [ n ] = (2 / 40) cos(2 * π * n / 40)

Where n is the sample number in the series between 0 and 39.

These constants are calculated by the microprocessor on initialisation.

The imaginary component (or sine term) of an input signal is obtained by firstcalculating the real component of a wave 27 degrees prior to the required wave andalso calculating the real component of a wave 27 degrees after the required wave(see Figure 4-35). These two cosine terms are then used to calculate the requiredsine term using the following technique:

cos(ωt - φ) - cos(ωt + φ)

= cos(ωt)cos(φ) + sin(ωt)sin(φ) - cos(ωt)cos(φ) + sin(ωt)sin(φ)

= 2sin(ωt)sin(φ)

= 0.90798sin(ωt)

therefore:

in(ωt) = 1.1013(cos(ωt - φ) - cos(ωt + φ))

This method of obtaining the imaginary component gives maximum rejection of anyexponential component of the input wave-form.

4.5.6 Distance to fault calculation

Vector correction

All of the input voltage and current vectors are phase adjusted to compensate forsampling skew and any phase shifts present in the relay input circuitry. This isachieved by individually adjusting the sine and cosine terms of the input vectors toform a new vector of the same amplitude but adjusted by the required angle.

i.e.

cos(ωt+θ) = cos(ωt)cos(θ) - sin(ωt)sin(θ)

and

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sin(ωt+θ) = sin(ωt)cos(θ) + cos(ωt)sin(θ)

Where θ is the angle of phase adjustment.

Neutral currents

Having calculated the corrected real and imaginary components of the input voltageand current vectors the microprocessor then calculates the pre-fault and faultedneutral current vectors.

i.e.

in_cos_term = ia_cos_term + ib_cos_term + ic_cos_term.

and

in_sin_term = ia_sin_term + ib_sin_term + ic_sin_term.

Replica impedance

The fault location calculation needs vectors derived from the line voltage (Vp) andfrom the relay's "replica impedance" voltage (IpZr) under fault conditions. (See Figure4-36)

The replica impedance is derived from the relay settings and is effectively set to thesame value as the total line impedance.

i.e.

Zr = 5 * KZPh * KZF / THETA Ph + 5 * KZN * KZF / THETA N

where:

KZPh, THETA Ph, KZN and THETA N are the distance relay base settings and KZF isthe fault locator reach setting.

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This "replica impedance" is modified using the mutual compensation factor when themutual compensation feature is used.

i.e.

Zr = 5 * KZPh * KZF / THETA Ph + 5 * KZN * KZF / THETA N +5 * KZM * KZF / THETA Mwhere:

KZM and THETA M are the fault locator mutual compensation settings.

The fault location calculation

The fault location calculation works by:

a) First obtaining the vectors to satisfy equation 2.1 for the fault type

specified by the phase selector.

b) Then estimating the phase of the fault current If.

c) Finally solving equation 2.1 for the fault location m at the instant oftime where If = 0.

Obtaining the vectors

Different sets of vectors are chosen depending on the type of fault identified by thephase selection algorithm. The calculation using equation 2.1 is applied for either aphase to ground fault or a phase to phase fault.

thus for a A phase to ground fault:

IpZr=Ia(5*KZPh*KZF/THETA Ph)+In(5*KZN*KZF/THETA N) (equation 6.1)

and Vp=VA

and for a A phase to B phase fault:-

IpZr=Ia(5*KZPh*KZF/THETA Ph)-Ib(5*KZPh*KZF/THETA Ph) (equation 6.2)

and Vp = VA - VB

The calculation for a ground fault (Equation 6.1) is modified when mutualcompensation is used :-

IpZr =Ia(5*KZPh*KZF/THETA Ph)+In(5*KZN*KZF/THETA N)+Im(5*KZM*KZF/THETA M) (Modified equation 6.1)

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Solving the equation for the fault location

For systems with sources of generation connected to both line ends, it is assumedthat D1 is scalar, i.e. the system is homogeneous. It is obvious that the real

component of If becomes zero at a phase angle which lags by (90° - d) the referencetime after the instant of fault. At this later time, just as the sine wave of If passesthrough zero, the instantaneous values of the sine waves Vp and Ip can be used tosolve equation (2.1) for the fault location m. (The term IfRf being zero.)

The procedure is to phase lead the calculated vectors of Vp and IpZr by the angle(90° - d) and then divide the real component of Vp by the real component of IpZr.(See Figure 4-36.)

i.e.:

Phase advanced vector Vp

= Vp(cos(s) + jsin(s)) * (sin(d) + jcos(d))

= Vp[- sin(s-d) + jcos(s-d)]

Phase advanced vector IpZr

= IpZr(cos (e) + jsin (e)) * (sin (d) + jcos (d))

= IpZr[- sin(e-d) + jcos(e-d)]

therefore from equation 2.1

m = Vp ÷ (Ip * Zr) at If = 0

= Vpsin(s-d) / (IpZr * sin(e-d))

Thus the microprocessor evaluates m which is in effect the fault location as apercentage of the fault locator reach setting and then calculates the output faultlocation by multiplying this by the line length setting.

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4.5.7 Mutual compensation

As shown in Section 4.5.6 mutual compensation is achieved by a modification to the"replica impedance" used within the fault location calculation.

The major disadvantage of this technique is that faults on a line could cause a faultlocation from a relay "start" on a healthy parallel line to appear to be on the healthyline.

This effect is caused by a large mutual compensation signal from the faulted lineproviding misleading information to a fault locator on the healthy line.

The Optimho fault locator eliminates this possible problem by limiting the mutualcompensation component of modified equation 6.1 to 150% of the neutralcompensation component. In this way a large amount of mutual compensation

cannot be applied to a fault location on a healthy line.

A second problem on parallel feeders occurs when one circuit is out of service and isearthed at both ends. In this case an earth fault on the in service system can inducecurrent in the loop of the earthed line causing a misleading mutual compensationsignal to the fault locator.

It is therefore recommended that the mutual compensation is deselected when aparallel line is taken out of service.

4.5.8 Metering

The metering calculations are continuously performed using the same fouriertechnique used by the fault locator. The results of these calculations are continuouslyupdated and can be viewed using the relay user interface.

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Ep

Vp

Ip

Zsp

mZr

If

Rf

Eq

Iq(1-m)Zr

Zsq

Figure 4-32 Two machine equivalent circuit

for radial systems.

represent the load

Zsq1, Zsq2 and Zsq0

superimposed value

Dash (') indicates

Ip0 '

Zsp3

Vf '

mZL0

Ip2 '

Ip1 '

Zsp2

Zsp1

mZL2

mZL1

Line end 'p'

Superimposed currents flowwhen the switch is closed

at the instant of fault.

(1-m)ZL0

I0 '

Zsq0 0.33 If

(1-m)ZL2

I2 '

(1-m)ZL1

I1 '

Zsq2

Zsq1

Line end 'q'

3Rf

Figure 4-33 Superimposed symmetrical component sequence diagram for A - N fault

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Post fault data windowPre fault data window

Figure 4-34 Optimho fault locator data selection

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Sample rate - 40 samples

per cycle

Single cycle data window - angle x-27 degrees

Single cycle data window - angle x degrees

Single cycle data window - angle x+27 degrees

Figure 4-35 Optimho fault locator fourier data windows

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f = 0

Vp

pZr I

I

pZr Vp I

Figure 4-36 Optimho fault locator selection of fault current zero

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Section 5. SCHEME FUNCTIONS

5.1 Level detector pole dead logic

Figure 5-1 shows a logic equivalent of the software implementation of the pole deadlogic.

The level detector pole dead logic is used to inhibit the relay comparators duringpole dead conditions and is also utilised for other features, such as VTS, PSB, SOTF,weak infeed, bandpass filter switching, etc. With saturated CTs the current leveldetectors may chatter and cause transient pole dead signals. To prevent possibleslow-down of the relay under these conditions the pole dead signals are delayed by22.5ms.

When a transmission line is de-energised following a trip it is possible for the

comparators, although inhibited, to remain in an operated state. To over come this areset pulse is sent to all distance comparators when the All Poles Dead condition isdetected.

When the Relay Blocked optical isolator is used with miniature circuit breakers (MCB)(see Section 5.2) the function is to block and inhibit (via pole dead signals) allcomparators. When the MCB is reclosed there is a possible race between thecomparators tripping due to current and no restraining voltage and the restrainingvoltage establishing and stabilising the comparators. This possible mal-trip isprevented by the delay in drop off of the Block Relay signal.

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Figure 5-1 Pole dead logic

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5.2 Voltage transformer supervision (VTS)

5.2.1 Purpose

The voltage transformer supervision (VTS) feature is used to detect failure of the ac

voltage supply. Such failure can occur by faults in the primary voltage transformers,in the secondary wiring, in the fuses or within the distance relay itself. The VTS givesvisual and electrical alarms and can be selected, via the menu, to block the distancerelay comparators, in order to prevent any possible maltrip. The VTS feature can beused when miniature circuit breakers (MCB) are used to protect the ac supply, inplace of the voltage transformer fuses, by wiring the RELAY BLOCK optical isolator toan auxiliary contact on the MCB.

5.2.2 Principle of operation

The VTS operates by detecting the zero sequence voltage (V0) that arises when the ac

voltage supply is faulty. It is inhibited by zero sequence current because ground faultson the transmission line also produce zero sequence voltage.

5.2.3 Outputs

A visual indication of VTS operation is given by the message V~FAIL on the liquidcrystal display (LCD) and the ALARM light emitting diode (LED) on the front of therelay. Electrical indication is given via a VTS contact.

The VTS feature can be selected via the menu to indicate only or to indicate andblock the comparators. The latter option is used to prevent maltrips.

If the VTS feature operates and blocks tripping the LCD also contains the message'RELAY BLOCKED', the green RELAY AVAILABLE LED is extinguished and the RELAYINOPERATIVE ALARM (RIA) contact closed.

When the Block Relay optical isolator is energised the message on the LCD is RELAYBLOCKED, the ALARM LED will be on and the RELAY AVAILABLE LED extinguished.

The following description assumes the VTS feature is set to block tripping unlessotherwise stated.

5.2.4 Implemetation

The level detectors used to detect zero sequence voltage and current are located onthe level detector board ZJ0136. The VTS feature is implemented in software on theprocessor board ZJ0138. Figure 5-2 shows the logic equivalent circuit diagram

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Figure 5-2 Voltage transformer supervision logic

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5.2.5 Level detector settings

The zero sequence voltage level detector (LDV0) must be set such that it does notoperate for the maximum expected level of zero sequence voltage in a healthy

system (V0 = 10% Vn, where Vn is the rated phase-neutral voltage) but does operatefor an open circuit or a short circuit in the voltage supply (V0 = 33% Vn). A zerosequence voltage setting of 15% Vn has been used.

The zero sequence current detector (LDLSN) used is the low set neutral which is alsoused by the distance relay. This level detector is biased to prevent operation due tounbalance in load current. As this is the same level detector used by the distancerelay no loss of ground fault sensitivity is incurred. A description of the level detectorsis given in Section 4.3

5.2.6 Speed of operation

The VTS feature is required to respond to the loss of voltage supply faster then therelay comparators can operate, in order to prevent maltrips. This requires the zerosequence voltage detector to be faster than the comparators.

5.2.7 Seal-In of block and resetting

If the VTS feature does operate it blocks the relay comparators immediately and thusprevents a maltrip. If however a subsequent ground fault was to occur on the system,the resulting zero sequence current would reset the VTS and allow a trip for a faultnot necessarily in the zone of protection. To overcome this the block is sealed in aftera 5.5 second delay. The delay is provided so that the VTS feature can toleratetemporary faults i.e. momentary shorts, without permanently blocking the relay. Afault lasting for 5.5 seconds will be permanent and will seal in both the alarms andthe block on the comparators. The visual and electrical alarms are only given afterthe 5.5 second.

The VTS feature can be reset by pressing the READ key to accept the alarm and thenpressing the RESET key or by energising the RESET INDICATION optical isolator. TheVTS feature will not reset if the fault persists in the ac supply. In the case of the BlockRelay optical isolator being used the alarms are self resetting when the opticalisolator is de-energised.

A selection on the menu allows the VTS feature to self reset' when the healthy voltsare restored to the relay. This condition is detected when the three over voltage leveldetectors all operate and the zero sequence level detector has reset.

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5.2.8 Operation for indication only

When the VTS is required to give indication and alarms only, a failure of the voltagesupply may cause the relay to give an immediate trip. When the circuit breakeropened and de-energised the transmission line the zero sequence voltage detector

(LDV0) would reset before the 5.5 second seal-in time and thus not give theappropriate indications. Under these conditions the indication and alarms areaccelerated and given after 20 milliseconds. This delay is to prevent a transient pulsefrom the zero sequence detection circuits causing a false alarm. Such pulses ( typicalup to 2-3 milliseconds ) are the result of transmission line faults causing raceconditions between the zero sequence voltage and current detectors.

5.2.9 Operation with line side voltage transformers

When all three poles of a circuit breaker are open there may be sufficient inducedvoltage from an adjacent line to cause the zero sequence voltage detector to

operate. This condition could exist for longer than 5.5 seconds and thus seal-in theblock. To prevent this an All Pole Dead signal derived from internal voltage andcurrent level detectors, or from the BREAKER OPEN optical isolator, is used to blockthe 5.5 second timer and thus prevent the seal-in.

If the pole scatter on opening a circuit breaker is sufficiently long transient operationof the zero sequence voltage level detector may occur. To prevent this bringing upthe accelerated indication a latch is provided that only allows indications to beaccelerated if the zero sequence voltage detector operated before the comparators.

5.2.10 Operation with busbar voltage transformers

When busbar voltage transformers are used there is no loss of voltage when thecircuit breaker is open. However there may be a transient depression of the voltagewhen the circuit breaker is closed, caused by line charging current, magnetisinginrush etc. To overcome this problem the BREAKER OPEN optical isolator (via the anyPole Dead signal) is used to inhibit the instantaneous output of the VTS.

5.2.11 Operation with single pole tripping

The unbalance in the voltage supply when a single pole of a circuit breaker is openis likely to cause the zero sequence voltage detector to operate. If this happens thecomparators would be blocked and any subsequent fault on the other phases wouldnot be cleared. To overcome this the Any Pole Dead signal is used to inhibit theinstantaneous block. The 5.5 second seal-in is not inhibited as the single pole isunlikely to be open for that length of time. A 240 millisecond delay in drop off isprovided because line charging transients and capacitor voltage transformertransients may cause the zero sequence voltage detector to remain operated for ashort time after the breaker is closed.

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A side effect is that if a single phase of the voltage supply fails at a time when theload current is below level detector setting a pole dead will result. This will inhibit theinstantaneous block though the block will occur and be sealed in after 5.5 seconds.

This is not a practical problem since the comparators cannot operate when the

current is below level detector setting and so no maloperation can occur.

5.2.12 Operation during line energisation with a voltage supply fault present(line VTs)

If the transmission line is energised with one or two voltage transformer fuses missingthe subsequent action depends on the load current flowing in the transmission lineand whether the switch on to fault feature (SOTF) is enabled or not. If SOTF isenabled and the current is high enough to operate one or more current leveldetectors within the first 250 milliseconds of the line energising a SOTF trip willresult. If SOTF is not enabled a distance trip may occur. However if no current

detector operates the VTS will block the relay and give alarms after 5.5 seconds.

If the transmission line is energised with all three fuses missing again the actiondepends on whether SOTF is enabled. If SOTF is enabled the VTS will remaininhibited and SOTF will remain enabled until the load current increases above leveldetector setting at which time a SOTF trip will occur. With SOTF disabled the VTS willagain be inhibited and the distance relay may trip.

5.2.13 Operation with weak infeed schemes

For a weak infeed fault condition, the VTS can also operate, hence the instantaneousoutput can not be used to block the week infeed logic. However for genuine voltagesupply failure the sealed-in block may be used to inhibit the weak infeed.

5.2.14 Operation with MCB

The VTS feature will not operate correctly when MCBs are used to protect the acsupply. A fault on one phase will produce zero sequence voltage which will initiallyblock the comparators. However when the MCB trips the zero sequence voltagedetector will reset and remove the VTS block. By wiring the Block Relay opticalisolator such that it is energised when the MCB trips, the comparators will remainblocked as described in the section 5.3. When the optical isolator is energised therelay is totally inhibited from tripping, this includes the SOTF feature as well asnormal distance trips.

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5.2.15 Operation with DEF

When the optional Directional Earth Fault feature (DEF) is fitted the low set zerosequence level detector (LDLSI0) is used in association with the low set neutral level

detector (LDLSN) to inhibit the VTS. This additional zero sequence current detector isrequired because its sensitivity may be higher than the biased neutral detector andcan therefore prevent the VTS feature blocking the DEF for low current ground faults.

When a DEF aided tripping scheme is selected a second zero sequence detector(LDHSI0) is also included to cover certain system operating conditions were itssensitivity can be higher than the low set neutral level detector (LDLSN).

The DEF elements are stable at the instant of a voltage supply failure but to preventthe DEF maloperating on a subsequent fault the sealed-in block is used to inhibit theDEF.

5.3 Comparator level detector checks

Figure 5-3 shows a logic equivalent of the software implementation of the leveldetector gating logic.

As described in Section 4.3, phase current level detectors are used to preventspurious operation of the comparator during line de-energisation and when thecurrent levels are very low (i.e. provides a sensitivity to the comparators).

The high set level detector gating is used in the POR 2 based schemes and theBLOCKING scheme.

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High Set

Low Set

LDLSB

Comparator

Comparator

Comparator

LDLSC

CpBCZn

CpABZn

CpCZn

Comparator CpBZn

Comparator CpAZn

Comparator CpABZ6

LDLSA

LDLSN

&&

&

&

&

&

&

&

&

&

&

zone - 1,2 or 3n refers to

1

1

1

1

1

LDCpABZn

(Zn P/F)

(ZnN)

LDCpBCZn

(ZnC)

(ZnB)

LDCpCZn

(ZnA)

LDCpBZn

LDCpAZn

LDCpABZ6

&

LDHSC

LDHSB

Z2B

Z2C

&

& 1

1

&

Z2A

LDHSA

Block Relay

VTS Block

Comparators

Comparator

LDHSN

CpCAZn

0

t &

&

35ms

&

n=2n=1

LDHSZ2

1

1

10V

Z3Comp

Z1Comp

Z2Comp

n=3

Z1Z2Z3ANY

(Zn G/F)

LDCpCAZn

Zn Comp

Figure 5-3 Low set & high set level detectors gating of comparators

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5.4 Switch on to fault logic (SOTF)

Figure 5-4 shows a logic equivalent of the software implementation of the SOTFlogic. The SOTF logic in Optimho is an option which may be enabled or disabled viathe menu.

The SOTF feature is enabled a short time after all three poles of the transmission lineare de-energised, as determined by the "pole dead" logic (Figure 5-1). This time canbe either 200ms or 110s as set via the menu. The normal setting is 200ms, since thisallows the SOTF feature to be available as soon as possible but is long enough toprevent inadvertent operation of the SOTF feature during transient dips in the acvoltage supply. With this short time setting, the SOTF feature will be enabled duringauto-reclose dead time, so that upon reclosure a SOTF trip is possible. This is usuallyadvantageous for most distance schemes, since persistent faults in the remote end of a protected line section can be cleared instantaneously after reclosure of the localbreaker, rather than after the Zone 2 time delay.

When busbar VTs are used, "pole dead" signals will not be produced, but a normallyclosed circuit breaker auxiliary contact can be used via an optical isolator input(Breaker Open), to inform the relay that the circuit breaker is open. For single poletripping applications, the circuit breaker auxiliary contacts of each breaker poleshould be wired in series and connected to the relay, so that the relay is made awarethat all three poles of the breaker are open.

When it is desired that a SOTF trip indication is not given after auto-reclosure, orwhen two shot auto-reclose is used, then the 110s SOTF enable timer option shouldbe used. This will ensure that the SOTF feature is not enabled during theauto-reclose dead time. If a SOTF trip was allowed to occur on auto-reclosure, thedistance relay would also give a BAR signal to the auto-reclose relay and any secondauto-reclose shot would be prevented.

Once the SOTF feature has been enabled, it remains enabled for 250ms after theline has been re-energised, or until a SOTF trip has been cleared. This period is longenough for the synchronous polarising to be established if the line is healthy.However, if a fault is present, 250ms is ample time for the fault to be detected. Themenu allows for a choice of fault detectors.

The three options available are:


b) Tripping via the operation of any current level detector provided thatits corresponding voltage level detector has not picked up within20ms.

c) Tripping via the operation of any distance comparator or anycurrent level detector provided that its corresponding voltage leveldetector has not picked up within 20ms.

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With the relay set to give a SOTF trip for any distance comparator operation, thenany fault existing on the protected line, including a close-up three phase bolted faultwould be cleared. For the latter fault, where line voltage transformers are used, therewould be no voltage memory to allow Zone 1 or Zone 2 distance comparator

operation, but Zone 3 will operate if set forward looking as it has an offset to coverthe busbars. When the Zone 3 is set reverse looking, as a directional mho, the SOTFshould be set to give a trip via comparators or level detectors as the Zone 3comparators would not operate for a close-up three phase fault on the protectedline. For relay type LFZP114 any comparator or level detectors should also beselected since the relay does not have Zone 3 elements.

In some situations, it may be possible for the magnetising inrush current of bankedtransformers at the end of a line, or particularly of teed-off transformers, to causetransient operation of the Zone 3 comparators on line energisation, resulting in anincorrect SOTF trip. In such a situation, the SOTF tripping via level detectors should

be used.

While the SOTF feature is enabled the basic scheme trips and the carrier aidedscheme trips are disabled. When a fault is detected during the SOTF enable time, theSOTF logic outputs do not reset until the fault is cleared.

If the optional DEF is fitted and the time delayed trip enabled any trip resulting fromthis unit during SOTF enable time will result in a SOTF trip.

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Figure 5-4 SOTF Logic

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5.5 Power swing blocking (PSB)

This feature is not available on LFZP114 relays

The Power Swing Blocking (PSB) feature can be selected by means of the relay menuto any of the following conditions:

a) PSB feature disabled.

b) PSB feature set to indication only.

c) PSB feature set to indication plus blocking of any one or moreelected Zones.

The PSB feature utilises two sets of phase-phase connected comparators with concen-tric characteristics. The outer characteristic (Zone 6), is an offset mho/lenticularcharacteristic produced by a separate A-B comparator with independent forwardreach, reverse reach and aspect ratio settings. The inner characteristic selected viathe menu is either the Zone 3 or Zone 2 phase comparators.

Zone 6 may be set concentric with the Zone 3 characteristic, as shown in Figure 5-5,when Zone 3 is set as an offset mho/lenticular. When Zone 3 is set reverse lookingas a directional mho, Zone 6 may be set concentric with the Zone 2 mhocharacteristic, as shown in Figure 5-6. The zone used for the inner characteristic maybe selected via the user interface menu.

The PSB feature is implemented as software in the main microcontroller, theequivalent hardware logic diagram is shown in Figure 5-7.

Figure 5-5 shows an example of how a power swing can pass through thecharacteristics of the relay. The impedance of the power swing is detected initially byZone 6 (LDCPABZ6) and, in the absence of any other comparator operating, a timer

TZ6 is started. When the timer expires a bistable is set. When the power swingimpedance then enters the selected Zone 3 or Zone 2 phase fault characteristic, theoutput bistable is set, producing the signal PSB Alarm, which is used to selectivelyinhibit Zone 1 and/or Zone 1X and/or Zone 1Y and/or Zone 2 and/or Zone 3 asrequired.

Inhibiting the Zone 2/3 comparator has no effect on the inhibit signal produced bythe logic, due to the action of the output bistable.

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The power swing inhibit signal PSB Alarm is only removed when the power swingimpedance passes outside the Zone 6 characteristic. This arrangement ensures thatthe PSB cannot produce a blocking signal for fault conditions which appear insideZone 6 alone, or inside any Z1/Z2/Z3 comparator before the TZ6 timer expires.

The Power Swing Blocking is inhibited during the following conditions:

1) When the A or B poles of the circuit breaker are open. This ensures thatthe PSB feature does not block tripping if the measurement of the PSBfeature is affected by the A or B phases of the transmission line beingde-energised. This inhibition is brought about by the action of the low setcurrent level detector LDLSA and LDLSB (see Section 5.3).To extend thisperiod of non operation to the first 240ms after the line is re-energised,the Any Pole Dead signal is used. The pole dead A and pole dead B

signals also inhibit the Zone 6 A-B comparator.

2) When a signal is received from the auto-reclose unit, via the Single PoleOpen optical isolator, signifying that the distance relay has tripped, but thecircuit breaker has not yet reclosed, that is, dead time is in progress. Thisinhibition of the PSB feature ensures that if a power swing develops duringthe dead time of a single phase auto-reclose cycle, the distance relay cangive an immediate three phase trip.

3) When the low set neutral current level detector LDLSN operates. This leveldetector remains unoperated during balanced power swing conditions, butcan operate to prevent incorrect PSB operation under the followingconditions:

a) If a ground fault occurs during a power swing.

b) If a heavy ground fault occurs such that the impedanceseen by the A-B comparators lies between theboundaries of Zone 6 and Zone 3/2.

c) If a power swing develops during the dead time of asingle phase auto-reclose cycle.

4) When the DEF option is fitted operation of the negative sequence currentlevel detector will inhibit the PSB feature. This allows the distance relay tooperate for phase faults which develop during a power swing. The settingof this level detector is increased to 100% during detected power swings, toprevent operation due to spill currents.

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5) Under conditions of loss of a voltage supply, provided that the voltagetransformer supervision feature has been set to indicate and block therelay.

It is important to note that when PSB is enabled and the DEF is disabled,it is essential to set the 3Io (low set) current level detector, which isganged to the setting of the I2 current level detector (see Section 4.4.4)required to override the PSB unit under fault conditions.

Operation of the PSB feature is indicated on the LCD and an output contact isprovided to give a remote alarm of a power swing.

To assist commissioning the PSB feature, the signal TZ6 Timed out is available via amonitor option (see Section 3.14.3). A PSB test feature is available via the menuwhich removes the negative sequence current level detector check and the Any Pole

Dead inhibit check. This is to overcome problems simulating power swings with sometest sets .

Note: When a Zone is blocked during a power swing the blocking isperformed at the input to the scheme logic, ie. The scheme logiceffectively does not register operation of the blocked zone. As aconsequence, all functions derived from the blocked zones, eg.Signal send, start contact etc. Will also be inhibited during the swingcondition.

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X

PSB Alarm turns off Inhibit signal

Zone 1

POWER SWINGIMPEDANCE

R

Inhibit signalPSB Alarm turns on

Zone 6

Zone 2

Zone 3

Figure 5-5 Characteristic using zone 3

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POWER SWINGIMPEDANCE

Inhibit signalPSB Alarm turns on

Zone 3

Zone 1

Inhibit signal

PSB Alarm turns off

Zone 2Zone 6

X

R

Figure 5-6 PSB characteristic using Zone 2

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PwrSwg to BLOCK Z1 (menu)

0

t

&Block Z1 PSB

&

Z2 P/F

(menu)

PwrSwg BLOCKED (menu)

Single Pole Open opto

t

0

LDCpABZ6

Z2 Comp

TIMED Z6-Z3

Z3 P/F

Z1 Comp

Any Pole

Dead

240ms

&

1

1

&

&

1 &

&

&

(menu)

PSB TEST

LDLSI2



PwrSwg to BLOCK Z1Y (menu)

PwrSwg to BLOCK Z1X (menu)

t

0

t

0

4us

4us

&

SQ

R

&&T39

TZ6

SQ

R

Sensitivity

LDLSI2

Control

TZ6 Timed Out

SQ

R

Reset comparators

&

&

&

&

PSB Alarm

Block Z3 PSB

Block Z2 PSB

Block Z1Y PSB

Block Z1X PSB

Figure 5-7 Power swing blocking logic

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5.6 Standard schemes in optimho distance

Several schemes are available as standard in Optimho. The schemes are listed in

Table 5-1 and a description of each given in the following sections. All the schemescan be selected to be single or three pole tripping, or alternatively three pole onlytripping, via the menu.

The basic scheme (BASIC) consists of up to 3 independent zones of protection. SOTFand Loss of Load accelerated tripping feature are included as options.

The other schemes consist of Zone 1 extension and a number of carrier aidedschemes all of which incorporate the basic scheme. The scheme and other minoroptions (i.e. timers) are selected via the menu.

Table 5-1 The standard schemes

BASIC Zone 1, Zone 1XT, Zone 1YT, Zone 2T & Zone 3T.

Z1 EXTENSION Zone 1 extension.

PUR Permissive Underreach.

POR 1 Permissive Overreach using TP & TD for current

reversal guard.

POR 2 Permissive Overreach using reverse Zone 3 forcurrent reversal guard and including Weak InfeedEcho.

POR 2 WI TRIP Permissive Overreach using reverse Zone 3 forcurrent reversal guard and including Weak Infeed

Trip.

PUR UNBLOCK Unblocking Permissive Underreach.

POR 1 UNBLOCK Unblocking Permissive Overreach using TP & TDfor current reversal guard.

POR 2 UNBLOCK Unblocking Permissive Overreach using reverse Zone 3for current reversal guard and including Weak InfeedEcho.

POR 2 WI TRIP Unblocking Permissive Overreach using reverse Zone 3UNBLOCK for current reversal guard and including Weak Infeed

Trip.

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BLOCKING Blocking.

BLOCKING 2 Blocking.

Note: LFZP114 does not have the POR 2 based schemes or the BLOCKINGschemes as they require Zone 3 elements to operate.

5.7 Basic scheme and loss of load accelerated tripping

5.7.1 Basic scheme

The BASIC scheme is shown in a logic equivalent form in Figure 5-8. The schemeconsists of up to three independent zones of protection designated Zone 1, Zone 2

and Zone 3 with Zone 2 and Zone 3 time delayed. (LFZP114 does not have Zone 3).Additional time delayed zones Zone 1X and Zone 1Y are available by reach steppingZone 1. SOTF logic is described in Section 5.4.

Zone 1

The six Zone 1 comparator signals after being gated with the appropriate leveldetectors (see Figure 5-3), are used for Zone 1 tripping. Zone 1 tripping can beblocked via the menu if desired. It is also blocked if SOTF is enabled and active(SOTF En) or in the event of a power swing detected and set to block Zone 1 (BlockZ1 PSB).

Zone 2 time delayed

The six Zone 2 comparator signals after being gated with the appropriate leveldetectors (see Figure 5-3), are used to control the Zone 2 timer (TZ2) and henceZone 2 time delayed tripping (Z2T). Zone 2 time delayed tripping can be blocked viathe menu if desired or alternatively all time delayed ground faults can be blockedagain via the menu. If the latter option is selected the Zone 2 ground faultcomparators are not used to initiate the timer. Zone 2 tripping is also blocked if SOTF is enabled and active or in the event of a power swing detected and set toblock Zone 2 (Block Z2 PSB).

Zone 3 time delayed

The six Zone 3 comparator signals after being gated with the appropriate level

detectors (see Figure 5-3), are used to control the Zone 3 timer (TZ3) and henceZone 3 time delayed tripping (Z3T). Zone 3 time delayed tripping can be blocked viathe menu if desired or alternatively all time delayed ground fault trips can beblocked via the menu. If the latter option is selected the Zone 3 ground fault

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comparators are not used to initiate the timer. Zone 3 tripping is also blocked if SOTF is enabled and active or in the event of a power swing detected and set toblock Zone 3 (Block Z3 PSB).

Zone 1X and Zone 1Y reach stepped

Zone 1 reach can be changed under software control to either Zone 1X or Zone 1Yreach. The reach is controlled by Zone 2 and Zone 3 comparators initiating the Zone1X timer (TZ1X) and Zone 1Y timer (TZ1Y). After the timer has expired the reach ischanged to the appropriate zone. The six Zone 1 comparator signals, after leveldetector checking (LDZ1A etc.), are used for tripping. If the second timer expires thereach will change appropriately. The logic allows for the two reach stepped zonetimers to be set in any order, and the reach to any value, provided either Zone 2 orZone 3 reach is larger. If both timers are set the same Zone 1Y will result. Zone 1Xand/or Zone 1Y tripping can be blocked via the menu if desired or alternatively all

time delayed ground faults can be blocked via the menu. If the latter option isselected the ground fault comparators are not used to initiate the timers or to issuetrips. Both zones are also blocked if SOTF is enabled and active or in the event of apower swing detected and set to block the appropriate zone. The reach of Zone 1may be set to Zone 1X via the Zone 1 extension scheme (see Section 5.8) but shouldeither reach stepped timer run out the reach will be set according to the timer.

5.7.2 Loss of load accelerated trip feature

The loss of load accelerated trip feature is shown in logic equivalent form in Figure5-8B. This feature if selected is run in addition to the main scheme only if 3 pole onlytripping is also selected. It does not require a signalling channel or any extra input.

Any fault located within the reach of Zone 1 will result in the direct tripping of thelocal circuit breaker. For an end zone fault the remote breaker will operate (Zone 1)and the local relay can recognise this by detecting the loss of load current in thehealthy phases. This, coupled with operation of a Zone 2 comparator causes trippingof the local circuit breaker.

Load current is detected by either the low set current or the high set current leveldetectors as selected on the menu. Before an accelerated trip can occur load currentmust have been detected prior to the fault. The loss of load current opens a 40mswindow during which time a trip will occur if a Zone 2 comparator operates. Theaccelerated trip is delayed by 18ms to prevent initiation of a loss of load trip due tocircuit breaker pole discrepancy occurring for clearance of an external fault.

For circuits with load tapped off the protected line care must be taken in setting theload loss feature to ensure that the level detector setting is above the tapped loadcurrent.

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When selected the load loss feature operates together with the main scheme that isselected. In this way it provides high speed clearance for end zone faults when thebasic scheme is selected or alternatively in aided tripping schemes it provides highspeed back-up clearance for end zone faults if the channel fails.

During SOTF or when a trip as occurred the loss of load accelerated tripping isdisabled.

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Figure 5-8 Basic scheme logic

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Figure 5-8b Loss of load accelerated trip feature

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5.8 Zone 1 extension scheme

The Zone 1 extension scheme is shown in a logic equivalent form in Figure 5-9. Thisscheme incorporates the basic scheme described in Section 5.7. The scheme does

not require a signalling channel but it does require a signal from the auto-recloserelay.

The reach of Zone 1 comparators is normally set to Zone 1X reach and is reset to theZone 1 reach when the circuit breakers have tripped and are about to be reclosed byauto-reclose action. The signal to reset from the extended Zone 1 to the normalZone 1 is generated by the auto-reclose equipment, via the optical isolator inputReset Zone 1 Extension. In this scheme, trips issued are classed as Zone 1 and thenormal Zone 1 conditions apply (i.e. PSB etc.). Reach stepped Zone 1XT is normallyblocked when this scheme is used. Reach stepped Zone 1YT may be used with thisscheme and should TZ1Y time out the reach will change to Zone 1Y reach.

The scheme provides fast clearance of most faults. On the basis that most overheadline faults are transient in duration, the scheme will allow fast clearance of mostfaults along the protected section and also those just out of the section. Lack of discrimination does not matter as auto-reclosure of the protected section circuitbreaker(s) will take place. The operation of the auto-reclose relay is used to reset theextension facility so that if the fault is permanent, upon reclosure the faulted sectionof line will be cleared permanently by its own protection, as in the basic scheme.

5.9 Permissive underreach scheme (PUR)

The PUR scheme is shown in a logic equivalent form in Figure 5-12 and thecommunication receive logic is shown in Figure 5-10. This scheme incorporates thebasic scheme described in Section 5.7.

The underreaching directional Zone 1 elements are used to initiate local Zone 1tripping and to send a carrier signal (CTX) to the remote end of the feeder. Receiptof the carrier signal (via optical isolator input CRX) plus operation of theoverreaching Zone 2 elements gives an accelerated aided trip for faults occurring inthe end zones of the protected feeder. Once issued, the aided trip is only removedwhen the Zone 2 elements reset. This allows time for breaker failure protection to op-erate in the event of a local breaker failure for a fault near the remote end of theline. A 100ms delay on reset of the carrier received optical isolator (CRX) is neededto ensure that the relays at both ends of a single end fed faulted line of a parallelfeeder circuit have time to trip when the fault is close up at one end. Monitor pointlabelled Timer 1 is used during commissioning to check various timers.

If reach stepped Zone 1XT or Zone 1YT are used with this scheme the carrier is onlysent when the reach is set to Zone 1. When SOTF is enabled and active (SOTF En)the PUR scheme is not run. The Channel out of Service optical isolator (COS)converts single pole trips to three pole and can be used to block auto-reclose (seeSection 5.18). The use of this optical isolator is optional in this scheme.

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Reset Z1 Extension opto

1Z1Xs

Figure 5-9 Zone 1 extension scheme

CRX opto

1

1CRX1

CRX2

Figure 5-10 Communication receive logic standard schemes

0

t

&CRX opto

LGS opto

&

&

&

t

0

200ms

0

t

&

150ms

1TDW

CRX2

PSD

1CRX1

Figure 5-11 Communication receive logic unblocking schemes

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Figure 5-12 PUR scheme

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5.10 Permissive overreach scheme (POR 1)

The POR 1 scheme is shown in a logic equivalent form in Figure 5-13 and thecommunication receive logic is shown in Figure 5-10. This scheme incorporates thebasic scheme see Section 5.7. For relays with the optional DEF fitted, DEF aided

tripping can be enabled or disabled via the menu. The DEF uses the samesignalling channel as the distance. A duplex (two frequency) channel is essential forthis scheme.

The overreaching directional Zone 2 elements and/or the DEF forward lookingelement are used to send a carrier signal (CTX) to the remote end of the feeder.Receipt of the carrier signal (via optical isolator input CRX) plus operation of theZone 2 elements and/or DEF forward looking element permit tripping and in thisway, instantaneous tripping will only occur for internal faults. When single or threepole tripping is selected the DEF aided trip (three pole) is delayed for 50ms to givethe distance Zone 2 ground fault elements time is issue a single pole trip if

appropriate, and to block the DEF forward looking element (see Section 4.4). Thisdelay is not required when three pole only tripping is selected. Once issued, thedistance aided trip is only removed when the Zone 2 elements reset and the DEFaided trip is only removed when the DEF forward looking element reset. This allowstime for breaker failure protection to operate in the event of a local breaker failurefor a fault near the remote end of the line. The carrier signal (CTX) is maintainedfor 100ms following a Zone 1 or aided trip to ensure correct scheme operation forvarious faults and system configurations.

When SOTF is enabled and active (SOTF En) the POR 1 scheme is not run. TheChannel out of Service optical isolator (COS) converts single pole trips to three pole

and can be used to block auto-reclose (see Section 5.18). The use of this opticalisolator is optional in this scheme.

There is a requirement with the overreaching scheme for a current reversal guardfeature (see Section 5.15.1) to prevent inadvertent tripping of the circuit breakerassociated with the healthy line of a faulted parallel feeder circuit. Such a featureusing timers TP and TD for the distance elements and the DEF reverse lookingelement and timer TDG forms part of the scheme (see Section 5.15.5). Should thisfeature not be required it is easily disabled by setting TP = 98ms, TD = 0ms and

TDG = 0ms. Monitor points labelled Timer 1 and Timer 2 are used duringcommissioning to check various timers.

A feature is provided which enables fast tripping to be maintained along the wholelength of the protected line, ever when one terminal is open. This is the "ECHO"feature and it is initiated 250ms after the Breaker Open optical isolator has beenenergised. The 250ms time delay is provided to prevent superfluous open terminalecho due to the delay in drop off of the signal send following a trip. However, therewill be no time delay introduced in echoing the signal when the breaker is alreadyopen.

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1

1S

QR

1

CRX1

3 POLE ONLY (menu)

Basic Scheme Trip

SOTF En

DEF Delay Trip

Any Trip

CRX2

DEF_F

COS opto

PSD

1 1

1

&

0

t&

50ms

&

Channel Not In Service

SQ

RDEF Aided Trip

1 t

0

1

Z2N

Z2C

Z2B

Z2A

&

&

100ms

&

&

&

&

&

&

0

t

DEF Aided Trip

Dist Aided Trip

Z1 Trip

Breaker

Open opto

250ms

Z2 Comp

DEF_R

DEF AIDED En

DEF_F

(menu)

TD

t

0

t

t

TDG

TP

R

SQ

R

SQ

R

SQ

R

SQ

1

Aided Trip C

Aided Trip N

Aided Trip A

Aided Trip B

Dist Aided Trip

0

t

&

&

&

100ms

1 CTX

Timer 2

Timer 1

Figure 5-13 POR 1 scheme

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5.11 Permissive overreach scheme (POR 2)

The POR 2 scheme is shown in a logic equivalent form in Figure 5-14 and thecommunication receive logic is shown in Figure 5-10. This scheme incorporates the

basic scheme see Section 5.7. For relays with the optional DEF fitted, DEF aidedtripping can be enabled or disabled via the menu. The DEF uses the samesignalling channel as the distance. A duplex (two frequency) channel is essential forthis scheme. A requirement of this scheme is that the Zone 3 elements are setreverse looking (directional).

The overreaching directional Zone 2 elements and/or the DEF forward lookingelement gated with additional high set level detectors (see later) are used to send acarrier signal (CRX) to the remote end of the feeder. Receipt of the carrier signal(via optical isolator input CRX) plus operation of the Zone 2 elements and/or DEFforward looking element permit tripping and in this way, instantaneous tripping will

only occur for internal faults. When single or three pole tripping is selected the DEFaided trip (three pole) is delayed for 50ms to give the distance Zone 2 ground faultelements time to issue a single pole trip if appropriate, and to block the DEFforward looking element (see Section 4.4). The delay is not required when threepole only tripping is selected. Once issued, the distance aided trip is only removedwhen the Zone 2 elements reset and the DEF aided trip is only removed when theDEF forward looking element reset. This allows time for breaker failure protectionto operate in the event of a local breaker failure for a fault near the remote end of the line. The carrier signal (CTX) is maintained for 100ms following a Zone 1 oraided trip to ensure correct scheme operation for various faults and systemconfigurations.

When SOTF is enabled and active (SOTF En) the POR 2 scheme is not run. TheChannel out of Service optical isolator (COS) converts single pole trips to three poleand can be used to block auto-reclose (see Section 5.18). The use of this opticalisolator is optional in this scheme.

There is a requirement with the overreaching scheme for a current reversal guardfeature (see Section 5.15.1) to prevent inadvertent tripping of the circuit breakerassociated with the healthy line of a faulted parallel feeder circuit. Such a featureusing reverse looking Zone 3 elements, reverse looking DEF element and timers TDand TDG forms part of the scheme (see Sections 5.15.2 & 5.15.5). Monitor pointslabelled Timer 1 and Timer 2 are used during commissioning to check varioustimers. If the Zone 3 comparators are faulty there is a chance that the scheme canmal trip for faults on parallel lines. For this reason if faulty Zone 3 comparators aredetected the scheme reverts to BASIC.

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A feature is provided which enables fast tripping to be maintained along the wholelength of the protected line, even when one terminal is open. This is the "ECHO"feature and it is initiated 250ms after the Breaker Open optical isolator has beenenergised. The 250ms time delay is provided to prevent superfluous open terminal

echo due to the delay in drop off of the signal send following a trip. However, therewill be no time delay introduced in echoing the signal when the breaker is alreadyopen.

A further feature of this scheme is the Weak infeed echo. When one end of the lineis connected to a weak infeed terminal, the distance or DEF measuring elements atthe weak infeed end would not be able to operate for a forward fault.Consequently the relay at the strong infeed end terminal would not be able tooperate instantaneously for end zone faults, in the absence of carrier signal fromthe weak infeed end terminal. However, with certain additional logic in this schemeit is possible to achieve rapid tripping for end zone faults at the weak infeed end.

A requirement of the scheme is that the Zone 3 measuring elements are set reverselooking to cover the reach of the Zone 2 elements of the relay at the other end of the feeder.

The weak infeed condition is detected by the receipt of a carrier signal and thefailure of operation of Zone 3 and DEF reverse looking measuring elements. For anexternal fault, behind the weak infeed terminal, when the fault infeed is from thestrong infeed terminal source, the reverse looking Zone 3 would operate and blockthe operation of the weak infeed circuit. However, for an internal fault, the distanceor DEF measuring elements at the weak infeed terminal would not operate, thusenabling the weak infeed circuit.

When a carrier signal is received by the relay at the weak infeed end, a 10ms timeris started, provided that:

a) There has been no operation of any distance or DEFmeasuring units.

b) The breaker is closed.c) VTS alarm has not blocked the DEF/WI (see Section 5.2).d) A single pole is not open (Single Pole Open optical isolator).e) The relay is not blocked via Block Relay optical isolator.

After the 10ms time delay, a carrier signal (CTX) is sent for up to 100ms allowingthe relay at the strong infeed end to trip.

If the distance relays operate normally at both ends, the signal receive signal willstill be available even after the relay reset subsequent to fault clearance, due to thedelay in the reset of the carrier signal. This condition can operate the weak infeedcircuit causing weak infeed Signal Send (CTX), unless further action is taken.

To prevent this, a latch circuit is provided to inhibit the weak infeed feature, if any

of the Zone 1, Zone 2 distance elements or DEF forward looking element operateand trip the breaker. Before the carrier signal is received from the other end, thecomparators may reset after a fault clearance, and hence a time delay on drop off

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of 100ms is provided in the inhibit circuit. The latch resets only after the carriersignal resets.

When high source impedance's are present, there is the possibility of inadvertentoperation of the weak infeed circuit for external faults due to the reverse looking

Zone 3 or DEF elements failing to operate to generate the required inhibit signal. To safeguard against this problem high set current level detectors of the samephase as any Zone 2 element or DEF forward looking element must have alsooperated before the carrier signal is sent to the other end.

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&

&

&

Note Timer TDG is set equal to Timer TD

Z3 NOT Z2DEF_R

Z2 Comp

LDHSI0 &

&

t

0

t

0

1

&TD

TDG

Z2N

Z2C

DEF AIDED En

Z2B

Z2A

DEF_F

(menu)

CRX1

&

Basic Scheme Trip

3 POLE ONLY (menu)

DEF Delay Trip

Any Trip

Z3 Watchdog

CRX2

SOTF En

COS opto

PSD

1R

SQ

1

1

1&

1

1

&

1

1

TDG =TD

CTX

Dist Aided

Trip

R

SQ

R

SQ

R

SQ

R

SQ

DEF_F

&

&

&

TIMER 2

TIMER 1

&

50ms

0

t

&

1R

SQ

Aided Trip N

Aided Trip C

Aided Trip B

Aided Trip A


DEF Aided Trip

1 t

0

100ms

250ms

1

0

t

Z2 Comp

Z3 Watchdog


VTS Block WI/DEF

DEF Aided Trip

Dist Aided Trip

Z1 Trip

Block Relay

Z3 Comp

LDHSZ2

Breaker Open

Z1 Comp

opto

&t

0S

QR

100ms

&100ms

&

0

t

1 &

1

10ms

0

t

&

Figure 5-14 POR 2 scheme

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5.12 Permissive overreach scheme with weak infeed tripping(POR 2 WI TRIP)

The POR 2 WI TRIP scheme is shown in a logic equivalent form in Figure 5-15 and

the communication receive logic is shown in Figure 5-10. This scheme incorporatesthe basic scheme described in Section 5.7. For relays with the optional DEF fitted,DEF aided tripping can be enabled or disabled via the menu. The DEF uses thesame signalling channel as the distance. A duplex (two frequency) channel isessential for this scheme. A requirement of this scheme is that the Zone 3 elementsare set reverse looking (directional).

The overreaching directional Zone 2 elements and/or the DEF forward lookingelement gated with additional high set level detectors (see later) are used to send acarrier signal (CRX) to the remote end of the feeder. Receipt of the carrier signal(via optical isolator input CRX) plus operation of the Zone 2 elements and/or DEF

forward looking element permit tripping and in this way, instantaneous tripping willonly occur for internal faults. When single or three pole tripping is selected the DEFaided trip (three pole) is delayed for 50ms to give the distance Zone 2 ground faultelements time to issue a single pole trip if appropriate, and to block the DEFforward looking element (see Section 4.4). The delay is not required when threepole only tripping is selected.

Once issued, the distance aided trip is only removed when the Zone 2 elementsreset and the DEF aided trip is only removed when the DEF forward lookingelement reset. This allows time for breaker failure protection to operate in the eventof a local breaker failure for a fault near the remote end of the line. The carrier

signal (CTX) is maintained for 100ms following a Zone 1 or aided trip to ensurecorrect scheme operation for various faults and system configurations.

When SOTF is enabled and active (SOTF En) the POR 2 scheme is not run. TheChannel out of Service optical isolator (COS) converts single pole trips to three poleand can be used to block auto-reclose (see Section 5.18). The use of this opticalisolator is optional in this scheme.

There is a requirement with the overreaching scheme for a current reversal guardfeature (see Section 5.15.1) to prevent inadvertent tripping of the circuit breakerassociated with the healthy line of a faulted parallel feeder circuit. Such a featureusing reverse looking Zone 3 elements, reverse looking DEF element and timers TDand TDG forms part of the scheme (see Section 5.15.2 & 5.15.5). Monitor pointslabelled Timer 1 and Timer 2 are used during commissioning to check varioustimers. If the Zone 3 comparators are faulty there is a chance that the scheme canmal trip for faults on parallel lines. For this reason if faulty Zone 3 comparators aredetected the scheme reverts to BASIC.

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&

&

TIMER 2

TIMER 1

Note Timer TDG is set equal to Timer TD

0

t

Z2B

Z3 NOT Z2

DEF_R

Z2 Comp

LDHSI0

Z2N

Z2C

&

&&

3 POLE ONLY (menu)

Basic Scheme Trip

Z2A

DEF_F

DEF AIDED En

(menu)

CRX1

DEF Delay Trip

Any Trip

Z3 Watchdog

CRX2

SOTF En

R

SQ

&

1

1

t

0

t

01

&TD

TDG

1

1

1

&

&

1

1=

1

WI C Ind

WI B Ind

WI Ind

WI N Ind

WI A Ind

CTX

&R

S

Q

R

SQ

R

SQ

TDG =TD

&

&

R

SQ

1

DEF_F

COS opto

&

0

t

&50ms

PSD

R

SQ

1

1

1

1

Dist Aided

Trip

Aided Trip B

Aided Trip C

Aided Trip N

1


Aided Trip A

DEF Aided Trip

&

250ms

1

1

0

t

Z3 Watchdog


VTS Block WI/DEF

DEF Aided Trip

Dist Aided Trip

Block Relay

Z3 Comp

LDOVC

LDOVB

LDOVA

Z1 Trip

Breaker Open

Z1 Comp

Z2 Comp

LDHSZ2

opto

&

t

0

100ms

60ms

&t

0

100ms

&

SQ

R

0

t &

&

&

&

R

S

Q&

&

&R

SQ

R

SQ

100ms

&

0

t

1 &

4us

1

0

t

&

10ms

Figure 5-15 POR 2 weak infeed tripping scheme

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A feature is provided which enables fast tripping to be maintained along the wholelength of the protected line, even when one terminal is open. This is the "ECHO"feature and it is initiated 250ms after the Breaker Open optical isolator has beenenergised. The 250ms time delay is provided to prevent superfluous open terminalecho

due to the delay in drop off of the signal send following a trip. However, there willbe no time delay introduced in echoing the signal when the breaker is alreadyopen.

A further feature of this scheme is the Weak Infeed Echo and Tripping. When oneend of the line is connected to a weak infeed terminal, the distance or DEFmeasuring elements at the weak infeed end would not be able to operate for aforward fault. Consequently the relay at the strong infeed end terminal would notbe able to operate instantaneously for end zone faults, in the absence of carriersignal from the weak infeed end terminal, and the weak infeed end would fail totrip during these conditions. However, with certain additional scheme logic, it is

possible to achieve rapid tripping of both ends for any internal faults.

A requirement of the scheme is that the Zone 3 measuring elements are set reverselooking to cover the reach of the Zone 2 elements.

The weak infeed condition is detected by the receipt of a carrier signal and thefailure of operation of Zone 3 and DEF reverse looking measuring elements. For anexternal fault, behind the weak infeed terminal, when the fault infeed is from thestrong infeed terminal source, the reverse looking Zone 3 would operate and blockthe operation of the weak infeed circuit. However, for an internal fault, the distanceor DEF measuring elements at the weak infeed terminal would not operate, thusenabling the weak infeed circuit.

When a carrier signal is received by the relay at the weak infeed end, a 10ms timeris started, provided that:

a) There has been no operation of any distance or DEFmeasuring units.

b) The breaker is closed.c) VTS alarm has not blocked the DEF/WI (see Section 5.2).d) A single pole is not open (Single Pole Open optical isolator).e) The relay is not blocked via Block Relay optical isolator.

At the same time a 60ms timer is started provided one or more voltage leveldetectors have reset. After the 10ms time delay, a carrier signal (CTX) is sentallowing the relay at the strong infeed end to trip. The 60ms delay before issuing aweak infeed aided trip is to provide stability during current reversals in a parallelline.

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If the distance relays operate normally at both ends, the signal receive signal willstill be available even after the relay reset subsequent to fault clearance, due to thedelay in the reset of the carrier signal. This condition can operate the weak infeedcircuit causing weak infeed trip and Signal Send (CTX), unless further action is

taken.

To prevent this, a latch circuit is provided to inhibit the weak infeed feature, if anyof the Zone 1, Zone 2 distance elements or DEF forward looking element operateand trip the breaker. Before the carrier signal is received from the other end, thecomparators may reset after a fault clearance, and hence a time delay on drop off of 100ms is provided in the inhibit circuit. The latch resets only after the carriersignal resets.

When high source impedance's are present, there is the possibility of inadvertentoperation of the weak infeed circuit for external faults due to the reverse looking

Zone 3 or DEF elements failing to operate to generate the required inhibit signal. To safeguard against this problem high set current level detectors of the samephase as any Zone 2 element or DEF forward looking element must have alsooperated before the carrier signal is sent to the other end.

5.13 Unblocking permissive trip schemes

The permissive tripping schemes (PUR, POR 1, POR 2 and POR 2 WI TRIP) usedwith power line carrier may be required to transmit the trip signal via a fault on thepower line. The signal will therefore be attenuated or shorted out altogether by thefault. This problem can be over come by using frequency shift communication

channel with the permissive schemes operating in the unblocking mode.

The frequency shift communication equipment transmits a guard (or block)frequency continuously in the stand-by condition. The transmitter is keyed to trip (orunblocking) frequency whenever the distance relay CTX output is given.

The permissive tripping schemes are converted to unblocking mode of operation byadding the communication receive logic shown in Figure 5-11. This logic requires atrip signal receive optical isolator input (CRX) and a loss of guard signal opticalisolator input (LGS). These signals are sent from the communications equipment.

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If during fault conditions the trip signal is not shorted out the communicationequipment will issue LGS and CRX signals. The communication receive logic in thiscase behaves as in the standard schemes. However if the trip signal is shorted outthe communications equipment will issue LGS only. Under these conditions the

unblocking schemes can issue distance aided trips for a short duration up to150ms. A delay TDW is necessary to prevent over tripping during transient loss of guard signal.

All four permissive schemes have their unblocking counterparts namely, PURUNBLOCK, POR 1 UNBLOCK, POR 2 UNBLOCK and POR 2 WI TRIP UNBLOCK.

5.14 Blocking schemes

Optimho contains 2 blocking schemes labelled BLOCKING and BLOCKING 2.

5.14.1 Blocking Scheme

The BLOCKING scheme is shown in a logic equivalent form in Figure 5-16. Thescheme incorporates the basic scheme described in Section 5.7. For relays with theoptional DEF fitted, DEF aided tripping can be enabled or disabled via the menu.

The DEF uses the same signalling channel as the distance.

The directional Zone 2 and/or the DEF forward looking elements, gated withadditional high set level detectors (see later) are required to trip the circuit breakersprovided a blocking signal optical isolator input (CRX) has not been received fromthe remote end of the feeder, indicating that the fault is beyond the remote

busbars. The reverse looking Zone 3 and/or DEF reverse looking elements arerequired to send the blocking signal (CTX) for all external faults. However, since theZone 3 comparators may have a forward offset, a blocking signal could be sent forsome internal faults. The directional forward looking Zone 2 elements are thusused to cancel the blocking signal for these cases.

When single or three pole tripping is selected the DEF aided trip (three pole) isdelayed for 20ms to give the distance Zone 2 ground fault elements time to issue asingle pole trip if appropriate, and to block the DEF forward looking element (seeSection 4.4). The delay is not required when three pole only tripping is selected.Once issued, the distance aided trip is only removed when the Zone 2 elementsreset and the DEF aided trip is only removed when the DEF forward lookingelement reset. This allows time for breaker failure protection to operate in the eventof a local breaker failure for a fault near the remote end of the line.

When SOTF is enabled and active (SOTF En) the BLOCKING scheme is preventedfrom issuing aided trips but the carrier send logic is run. The Channel out of Serviceoptical isolator (COS) converts the BLOCKING scheme to BASIC and also convertsany Zone 1 single pole trips to three pole and can be used to block auto-reclose(see Section 5.18). This optical isolator is required for the correct operation of thescheme.

In practice a time delay on pick up for the tripping signal TP is required for faultsdetected by the Zone 2 elements. This is to allow time for a blocking signal to besent from the remote end, should it prove necessary, and to be received at the localend. A similar timer TPG is provided for the DEF forward element.

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A delay on drop off for the signal received (CRX) is also provided in the blockingscheme (TD and TDG), to safeguard against inadvertent tripping out of the healthysection of a faulted double circuit line, during a possible reversing current situation(see Section 5.15.3). Monitor points labelled Timer 1 and Timer 2 are used during

commissioning to check various timers.

When very high source impedance's are present, there is the possibility of inadvertent tripping occurring for external faults due to the overreaching elementsfailing to operate to generate the required blocking signal. To safeguard againstthis problem the Zone 2 and/or DEF forward looking elements are gated with theappropriate high set current level detectors (LDHS) before an accelerated aided tripcan be initiated. (see Figure 5-3)

5.14.2 Blocking 2 scheme

The BLOCKING 2 scheme is shown in a logic equivalent form in Figure 5-16B. Thescheme incorporates the basic scheme described in Section 5.7. For relays with theoptional DEF fitted, DEF aided tripping can be enabled or disabled via the menu.

The DEF uses the same signalling channel as the distance. The scheme is designedfor use with signalling equipment that requires a normally open signal start contactand a normally open signal stop contact but it will work with just signal start contactif required.

The directional Zone 2 and/or the DEF forward looking elements, gated withadditional high set level detectors (see later) are required to trip the circuit breakersprovided a blocking signal optical isolator input (CRX) has not been received fromthe remote end of the feeder, indicating that the fault is beyond the remotebusbars. The reverse looking Zone 3 and/or the Low Set Zero Sequence currentlevel detector (LDLSI0) are required to send the blocking signal (SIGNAL SEND) forall external faults. However, since the level detector sees faults in either direction,the blocking signal is removed by operation of the SIGNAL STOP contact controlledby the directional forward looking Zone 2 elements and/or the forward lookingDEF comparator.

When single or three pole tripping is selected the DEF aided trip (three pole) isdelayed for 40ms to give the distance Zone 2 ground fault elements time to issue asingle pole trip if appropriate, and to block the DEF forward looking element (seeSection 4.4). The delay is not required when three pole only tripping is selected.Once issued, the distance aided trip is only removed when the Zone 2 elementsreset and the DEF aided trip is only removed when the DEF forward lookingelement reset. This allows time for breaker failure protection to operate in the eventof a local breaker failure for a fault near the remote end of the line.

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When SOTF is enabled and active (SOTF En) the BLOCKING 2 scheme isprevented from issuing aided trips but the carrier send logic is run. The Channelout of Service optical isolator (COS) converts the BLOCKING 2 scheme to BASICand also converts any Zone 1 single pole trips to three pole and can be used to

block auto-reclose (see Section 5.18). This optical isolator is required for the correctoperation of the scheme.

In practice a time delay on pick up for the tripping signal TP is required for faultsdetected by the Zone 2 elements. This is to allow time for a blocking signal to besent from the remote end, should it prove necessary, and to be received at the localend. A similar timer TPG is provided for the DEF forward element.

A delay on drop off of the SIGNAL START contact is also provided in the blocking 2scheme (TD and TDG) to maintain the blocking signal, to safeguard againstinadvertent tripping out of the healthy section of a faulted double circuit line, during

a possible reversing current situation (see Section 5.15.3). Monitor points labelled Timer 1 and Timer 2 are used during commissioning to check various timers.

To prevent false operation of the scheme due to short interruption of the blockingsignal a 2ms/5ms timer is included in the signal receive logic.

During marginal external faults with low fault currents there is the possibility of thereverse looking elements failing to operate and therefore not sending the blocksignal, whilst the forward overreaching elements at the other end of the lineoperate and trip. To safeguard against this problem the Zone 2 and/or DEFforward looking elements are gated with the appropriate high set current leveldetectors (LDHS) before an accelerated aided trip can be initiated thus ensuring theexternal fault will be seen at both ends of the line. (see Figure 5-3)

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1

0

t

1

1

Z3 NOT Z2DEF_F

&

CTX

t

0

Z2N

Z2C

Z2B

Z2A

LDHSZ2

&

1

0

t

TD

TP &

&

&

DEF Delay Trip

Any Trip

CRX opto

Basic Scheme

Trip

SOTF En

COS opto

1

3 POLE ONLY (menu)

DEF AIDED En

DEF_R

ILDHS 0

Z2

(menu)

&&

t

0

1

R

SQ

TDG

&

&TPG


1

&R

SQ

R

SQ

R

SQ

&

&

R

SQ

&

Aided Trip N

Aided Trip C

Aided Trip B

Aided Trip A

Dist Aided

Trip

& 10

t

20ms

SQ

R

Timer 2

Timer 1

DEF Aided Trip

1

Figure 5-16 Blocking scheme

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1

LDHSI0 0

t

t0

&

t

0

R

SQ

1

&

&

SIGNAL START

3 POLE ONLY (menu)

Trip

1DEF Delay Trip

Basic Scheme

Any Trip

COS opto

SOTF En

&

(menu)

DEF_F

Dist Aided Trip

DEF Aided Trip

Z1 Trip

DEF AIDED En

DEF En (menu)

Z2

DEF_R

LDLSI0

&

&

1

t

0

&

100ms

1

1

40ms

&

0

t1

TPG

TD

TDG

&

&

DEF Aided Trip

S

QR

Test Point

&

TIMER 1

TIMER 2

SIGNAL STOP

(CTX)

SIGNAL START

Z3 NOT Z2

Z2B

Z2N

Z2C

2ms

Z2A

LDHSZ2

CRX opto

0

t

1

&TP

5mst

t

&

R

S

Q

R

S

Q

R

SQ

R

SQ

&

&

&

Aided Trip N

Aided Trip C

Aided Trip B


1

&

Trip

Aided Trip A

Dist Aided

Figure 5-16b Blocking 2 scheme

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5.15 Current reversal logic

In double circuit lines, the fault current distribution changes when circuit breakersopen sequentially to clear the fault. With one terminal line open, the change incurrent distribution can cause the directional looking distance comparators to see

the fault in the opposite direction to the direction in which the fault was initiallydetected. This can cause the Permissive Overreach, the Blocking and the DEFschemes to trip the healthy line due to the contact race between one set of directional comparators resetting and the other set operating.

A typical system configuration that could result in current reversals is shown inFigure 5-17 for a fault on line L1 close to circuit breaker B with all the circuitbreakers closed, which after circuit breaker B has opened, causes the direction of current flow in line L2 to be reversed.

5.15.1 Current reversal POR 1 scheme

Forward looking Zone 3 (Figure 5-18)

The current reversal guard incorporated in the scheme logic is initiated when ahealthy line relay receives a permissive trip signal, but does not have a Zone 2comparator operated. A delay on pick up TP in the current reversal guard timer isnecessary in order to allow time for the Zone 2 comparators to operate, if they aregoing to do so for an internal fault.

Recommended TP setting = 30ms - minimum signalling channel operating time

ms.

Once the current reversal guard timer has operated, the healthy line relay Dtransfer tripping is inhibited. The reset of the guard timer is initiated by either theloss of the permissive trip signal or by the operation of the Zone 2 comparators. Atime delay TD for the reset of the current reversal guard timer is required in casethe Zone 2 comparator at end D operate before the permissive trip signal from therelay at end C has reset, which could cause the relays on the healthy line tomaloperate.


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The current reversal sequence diagram shows how the relays in the healthy line areprevented from maloperation due to the sequential opening of the circuit breakersin the faulted line and the instance in the cycle at which it takes place. After currentreversal, the Zone 2 comparators of the relay at D will initiate the transmission of

the permissive trip signal from substation D to substation C and the relay at C willbe similarly prevented from maloperation. The relays at both D and C substationsbeing enabled once again when the faulted line is isolated and the current reversalguard timer setting TD has expired.

5.15.2 Current reversal POR 2 schemes

Reversed looking Zone 3 Figure 5-19)

The current reversal guard incorporated in the scheme logic is initiated when thereversed looking Zone 3 comparators operate on a healthy line. No time delay TP

is necessary with this scheme as the Zone 3 comparators will operate well beforethe arrival of the permissive trip signal initiated by the Zone 2 comparators at theopposite end of the line.

Once the reversed looking Zone 3 comparators have operated, the relay D transfertripping and weak infeed tripping is inhibited. The reset of the current reversalguard timer is initiated when the reversed looking Zone 3 resets. A time delay TD isrequired in case the Zone 2 comparators at end D operate before the permissivetrip signal from the relay at end C has reset, which could cause the relays at D tomaloperate.

When the reverse looking Zone 3 comparators at end D reset the weak infeedtripping timer is enabled, due to the delay in the reset of carrier receive. The weakinfeed is only inhibited after end A trips and the voltage level detectors at end Doperate. To prevent the weak infeed trip under these conditions a 60ms delaybefore issuing a weak infeed trip is provided.


The current reversal sequence diagram shows how the relays in the healthy line areprevented from maloperation due to the sequential opening of the circuit breakersin the faulted line and the instance in the cycle at which it takes place. After currentreversal, the reversed looking Zone 3 comparators at substation C will operate toinhibit the relays at substation C before the permissive trip signal is received fromsubstation D. The relays at D and C substations being enabled once again, whenthe faulted line is isolated and the current reversal guard timer setting TD hasexpired.

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5.15.3 Current reversal blocking scheme

(Figure 5-20)

The current reversal guard incorporated in the scheme logic is initiated when the

blocking signal transmission started by the reversed looking Zone 3 comparators isreceived on a healthy line to inhibit the aided trip. A time delay TP is needed withthe Zone 2 comparators in order to allow for the blocking signal transmission to bereceived in case the reversed looking Zone 3 comparators had operated for anexternal fault.

Recommended TP setting = maximum signalling channel operating time ms +16ms.

When the current reverses and the reversed looking Zone 3 comparators reset, theblocking signal transmission is stopped and the timer TD is started. After time TD,

the scheme resets and the relay aided trip is enabled once again.

Recommended TD setting = 20ms - minimum signalling channel reset time ms.

The current reversal sequence diagram shows how the relays in the healthy line areprevented from maloperation due to the sequential opening of the circuit breakersin the faulted line and the instance in the cycle at which it takes place. After currentreversal, the reversed looking Zone 3 comparators at substation D reset, but thoseat substation C operate to send the blocking signal to substation D and inhibit theaided trip. After the faulty line is isolated, the reversed looking Zone 3 comparatorswill reset and the scheme aided trip restored when the timer setting TD has expired.

5.15.4 Current reversal blocking 2 Scheme (Figure 5-20B)

The current reversal guard incorporated in the scheme logic is initiated when theblocking signal transmission, started by the reversed looking Zone 3 comparators,is received to inhibit the aided trip. A time delay TP is needed with the Zone 2comparators in order to allow time for the blocking signal transmission to bereceived in case the reversed looking Zone 3 comparators had operated for anexternal fault.

Recommended TP setting = maximum signalling channel operating time ms +14ms.

When the current reverses and the reversed looking Zone 3 comparators reset, theblocking signal transmission is maintained by the timer TD.

Recommended TD setting = maximum signalling channel operating time ms+14ms.

Note: If a simplex channel is used

TD setting= maximum signalling channel operating time ms - minimum signalling channel reset time ms + 14ms.

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The current reversal sequence diagram shows how the relays in the healthy line areprevented from maloperation due to the sequential opening of the circuit breakersin the faulted line and the instance in the cycle at which it takes place. After currentreversal, the reversed looking Zone 3 comparators at substation D reset but theblock is maintained for time TD, in order to allow the relays at substation C to send

the blocking signal to substation D and inhibit the aided trip. After the faulty line isisolated, the reversed looking Zone 3 comparators at subsation C and the forwardlooking comparators at subsation D will reset.

5.15.5 Current reversal DEF POR 1, POR 2 schemes

(Figure 5-21)

The current reversal guard incorporated in this DEF Permissive Overreach schemelogic is similar to the distance scheme with reversed looking Zone 3 comparatorsPOR 2, except that the operation of the scheme is controlled by the reversed

looking directional earth fault comparator instead of the distance reversed lookingZone 3 comparators. It uses a separate current reversal guard timer TDG, but itshares a common signalling channel.Recommended TDG setting = maximum signalling channel reset time ms + 35ms.

Note: In the POR 2 schemes TDG is automatically set to the same value as TDand does not appear on the menu.

5.15.6 Current reversal DEF blocking scheme

(Figure 5-22)

The current reversal guard incorporated in this DEF Blocking scheme logic is similarto the distance blocking scheme, except that the operation of the scheme iscontrolled by the reversed looking directional earth fault comparator instead of thedistance reversed looking Zone 3 comparators. It uses a separate current reversalguard timer TPG to allow time for the blocking signal to be received in the event of an external fault, and a second timer TDG to maintain the aided trip inhibition untilthe forward looking directional comparator at the opposite end has reset.

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Recommended TPG setting = maximum signalling channel operating time ms+26ms.

Recommended TPG setting = 20ms - minimum signalling channel reset time ms.

5.15.7 Current reversal DEF blocking 2 scheme

(Figure 5-22B)

The current reversal guard incorporated in this DEF Blocking 2 scheme logic issimilar to the distance blocking scheme, except that the operation of the scheme iscontrolled by both the low set current zero sequence level detector (LDLSI0) and thereverse looking directional element (DEF_R) instead of the distance Zone 3comparators. It uses a separate current reversal guard timer TPG to allow time for

the blocking signal to be received in the event of an external fault, and a secondtimer TDG to maintain the blocking signal until the forward looking directionalcomparator (DEF_F) at the opposite end has reset.

Recommended TPG setting = maximum signalling channel operating time ms+4ms.

Recommended TDG setting = maximum signalling channel operate time ms+14ms.

Note: If a simplex channel is used:

TDG setting = maximum signalling channel operating time ms - minimum signalling channel reset time ms + 14ms.

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L1A

Source

B

Weak

Fault

AFTER CURRENT REVERSAL

NOTE HOW AFTER CIRCUIT BREAKER B ON LINE L1 OPENSTHE DIRECTION OF CURRENT FLOW IN LINE L2 IS REVERSED

BEFORE CURRENT REVERSAL

Strong

Source

C

A

Strong

Source

C

Fault

L2

L1

D

B

L2

D

Source

Weak

Figure 5-17 Current reversal in double circuit lines

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Current reversal system configuration

Current reversal sequence diagram

A

C

B

D

Fault

CTXReset

A

C

Fault

B

D

C Z2C CTX Z2C Reset

Inception

CION

AT

FaultReversalCurrent

Relay DDisabled

Time

Current reversal logic

CB Operating time

D

BR

Ay

LO

EL

Z1B

CRX

Z2 &

TP Z2D

TP

TD

&

&

EnabledRelay D

Reset

TD

CTX

Aided trip

Figure 5-18 Current reversal POR 1 scheme

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Current reversal configuration

Current reversal sequence

A

C

B

D

Fault

A

C

Fault

B

D

Z2CC CTX ResetZ2C Reset

Inception

CAT

ON

I

Fault

DisabledRelay D

Reversal

Current

Time


CB Operating time

D

BRE

LA

Y

LO

Z3RD

Z1B

Z2

Z3R

CRX

&

CTX

Z3RD

Reset

0

TD

&

&

Enabled

Relay D

Reset

TD

CTX

Aided trip

Figure 5-19 Current reversal POR 2 & POR 2WI trip schemes

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A

C

B

D

Fault

Reset

A

C

Fault

B

D

Z2CCTP Z2C Reset

Inception

CAT

ON

I


DisabledRelay C

Time


CB Operating logic

TP

0

Z3R

D

BRELA Y

LO

Z3RD

Z1B

Z2

CRX

COS

CTXCTX

Z3RDReset

0

TD &

&

TD

EnabledRelay C

Reset

CTX

Aided trip

Figure 5-20 Current reversal blocking scheme

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A

C

B

D

Fault

A

C

Fault

B

D

L CTX

Inception

C

OC

T

ON

I

A

Fault

Z2C

ReversalCurrent

Z2C Reset

DisabledRelay C

TP

Time


CB Operating time

0

TD

TP0

&

D

B

Y

RELA

Z3R

Z1B

Z3RD

Z2

CRX

COS

ResetReset

Z3RD TD

&

&

CTX

EnabledRelay C

Reset

Start CTX

Stop CTX

Aided trip

Figure 5-20b Current reversal blocking 2 scheme

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A

C

B

D

Fault

A

C

Fault

B

D

CDEF FC

CTXResetDEF FC

Inception

CION

AT

DisabledRelay D


Time

Reset


CB Operating time

D

BR

A Y

LO

E

LDEF RD

Z1B

DEF F

DEF R

CRX

&

CTX

ResetDEF RD

TDG

0

&

&

EnabledRelay D

ResetTDG

CTX

Aided trip

Figure 5-21 Current reversal DEF POR 1, POR 2& POR 2 WI trip schemes

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A

C

B

D

Fault

Reset

A

C

Fault

B

D

CDEF FC TPG DEF FC

Inception

CION

AT


DisabledRelay C

Time

Reset


CB Operating time

D

BR

A Y

LO

E

LDEF RD

Z1B

DEF R

DEF F

COS

CRX

TPG

0

CTXCTX

Reset

TDG

0&

&

TDG

EnabledRelay C

Reset

CTX

Aided trip

Figure 5-22 Current reversal DEF blocking scheme

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Current reversal sysytem configuration


A

C

B

D

Fault

DisabledRelay D

A

C

Fault

B

D

D Y

Inception

C

N

O

T

OI

CA

L

Fault

DEF FC

LDLSI0D

Disabled

CurrentReversal

Relay C

CTX

TPG

Time

CTX

Reset

DEF FC

DEF RC

ResetReset


CB Operating time

&

BRELA

LDLDI0

DEF R

LDLSI0D

DEF RD

Z1B

0

TDG

DEF F

COS

CRX

TPG

0

1

TPG

DEF RD

DEF FD

TDG

&

&

Relay CEnabled

ResetCTX

Start CTX

Stop CTX

Aided trip

Figure 5-22b Current reversal DEF bocking 2 scheme

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5.16 Bandpass filter, memory and comparator count control logic

Figure 5-23 shows a logic equivalent of the software implementation of thisfunction.

The voltage bandpass filters are switched in 30ms after any voltage level detectorhas reset, any distance comparator has operated or the zero sequence current leveldetector has operated. The filters remove dc offsets in the voltage signal (seeSection 6.7). At the instance of switching in the voltage bandpass filters, a step inthe voltage waveform may arise and to ensure that this causes no confusion to thecomparators a momentary inhibit pulse is sent to all the comparators.

The current bandpass filters, which attenuate the higher frequencies caused bytravelling waves, are switched in 10ms later. The times were chosen to optimise therelay performance under the different system conditions.

When the current bandpass filters are switched in the distance and DEFcomparators are switched to operate on count 4. This action prevents stabilityproblems when the line is de-energised. Count 4 is also selected while SOTF isenabled and during any time delayed reach stepping. This action ensures that anydiscontinuities, in the voltage signals caused by the change in reach, will not causea mal trip.

The synchronous memory is instructed to run out on detecting any possible faultcondition (see Section 4.2.2).

5.17 Trip latching logic


This logic controls the output trip contacts Trip A, Trip B, Trip C, 3 Pole Trip andAny Trip. When single or three pole tripping is selected via the menu single poletrips are allowed for single ground faults detected as Zone 1 or Aided includingweek infeed. All other faults including phase to phase, time delayed, SOTF andDEF are converted to three pole trips. All trips are latched in for a minimum of 60ms and maintained until the appropriate current level detectors reset. Whenthree pole tripping only is selected via the menu all trips are converted to three poletrips and are maintained until the last level detector resets. This action ensures thatthe trip signals remain until the circuit breaker opens. With evolving faults singlepole trips can change to three pole but not vice versa. Weak infeed trips reset whenthe Breaker Open optical isolator is energised.

To prevent comparator chatter on the boundary of operation amplitude hysteresis isused (see Section 6.7.2). When a trip is issued a signal is sent to the input modulewhich decreases the gain of the voltage signals by 5%, thereby increasing the relayreach (see Section 6.7).

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Figure 5-23 Bandpass filter, memory & count 4 control

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Figure 5-24 Trip latching logic

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5.18 Block auto-reclose logic


Any Zone 3 time delayed trip or SOTF trip will cause Optimho to close the BLOCK AUTO-RECLOSE contact (BAR). A number of other conditions which can be selectedvia the menu can also cause BAR. These include Zone 1X time delay, Zone 1Y timedelay, Zone 2 time delay, DEF Aided, DEF Delay, Channel out of Service, 2 or 3Phfault in Zone 1 or Aided and 3Ph fault Zone 1 or Aided.

5.19 External fault locator start logic


These contacts are provided for data logging functions, such as phase selection,starting of external fault locators, fault recorders etc. Two or more contacts close fora fault condition, e.g.

A - G fault closes Start A and Start NA - B fault closes Start A and Start BA - B - G fault closes Start A, Start B and Start NA - B - C fault closes Start A, Start B and Start C

If a fault is detected by Zone 1 comparators, the phase information of Zone 1 takes

preference over phase information from Zone 2. Similarly Zone 2 takes preferenceover Zone 3. This action ensures that the closest forward fault condition detectedduring any simultaneous fault situation is used for phase selection purposes. Thesmaller distance relay zones also offer the best phase discrimination.

The phase information during SOTF trips is derived from either the comparators orthe level detectors depending on which is selected, via the menu, for SOTF tripping.

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&

&

BAR on Z1X(T) TRIP (menu)

BAR on Z1Y(T) TRIP (menu)

Z1X(T)

1

& 12/3 Phase fault

BAR on Z1+AT 3Ph/F (menu)

3 Phase fault

Z3T

SOTF Trip

&

1

BAR on Z1+AT 2&3Ph/F (menu)

BAR on DEF AIDED TRIP (menu)

BAR on DEF DELAY TRIP (menu)

DEF Delay Trip

BAR on CHANNEL OUT (menu)

COS BAR (Initiated upon Trip)

BAR on Z2(T) TRIP (menu)

DEF Aided Trip

Z1YT

Z2T

1

&

&

1

&

&

t

0

100ms

BAR

Figure 5-25 Block autoreclose logic

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&

&

&

Z3C

Z2C

LDOVB

Z2B

Z1BZ1B'

LDLSBWI B Ind

Z3B

LDLSALDOVA

WI A Ind

Z1AZ1A'

Z1 Comp

Z3A

Z2A

Z2 Comp

1&

1

&

&

1

&

&

1

1

&

1

&

&

1&

&

1Start B

1Start A

SOTF Trip

(menu)

SOTF COMPARATOR (menu)

SOTF En

SOTF CNV

LDLSN

LDLSI0

&

&

1

&

Z1N'

Any Z1Z2Z3

DEF_F/RWI N Ind

Z2N

Z1N

LDOVC

Z3N

Z1CZ1C'

LDLSC

WI C Ind

1

&

&

1

&

&

&

&1

Start N

Start C

Figure 5-26 External fault locator start logic

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Section 6. MODULE AND BOARD DESCRIPTIONS

6.1 Self monitoring

6.1.1 Introduction

Optimho relays have continuous self-monitoring. If a failure is detected an alarm isissued by extinguishing the "Relay Available" LED and closing the "Relay InoperativeAlarm" contact.

Diagnostic information is automatically displayed if the failure is such that it doesnot disable the main microcontroller or the Liquid Crystal Display (LCD).

Monitoring of the analogue circuits includes :

a) The dc supply and all internal dc supply rails.b) The ac supplies and internal analogue current and voltage

circuits.

Monitoring of the digital circuits includes :

a) Digital bus integrity.b) Checking of RAM and EEPROM used by the main

microcontroller.c) Watch-dog circuit outputs for each microcontroller.

Figure 6-1 shows a schematic of the monitoring arrangement.

6.1.2 Analogue circuits

The internal voltage rails +5V, +12V, -12V and +12V (relays) are constantlymonitored. In the event of any of the voltages dropping below specified tolerancelimits, or failure of the external dc supply, then the "Relay Inoperative Alarm"contact will be closed and the "Relay Available" LED extinguished. Also, should the+5V rail fail, the main microcontroller will be held reset.

Voltage Transformer Supervision logic (see Section 5.2) can be set to block the

operation of the relay in the event of the failure of a VT fuse. All models have anoptically coupled isolator to monitor the auxiliary contact of a miniature circuitbreaker for applications were the VT supplies are protected by a Miniature CircuitBreaker (MCB) instead of fuses.

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Current Transformer supervision logic (see Figure 6-2), is used to examine thestatus of the current input circuits. The logic is based on the premise that for healthyline conditions, when the three phase currents are well balanced, the biased low-setneutral level detector (see Section 4.3) will not be operated.

If the biased neutral low-set level detector operates, for a period of five secondscontinuously, without the operation of one of the following :

a) Any Pole Dead.b) Any zone comparator.c) The Vo level detector.d) Any DEF comparator (if DEF fitted).e) Single Pole Open opto-isolator.

then the relay will respond by closing the "Relay Inoperative Alarm" contact and

extinguishing the "Relay Available" LED. The main microcontroller writes themessage:

'ERROR# I~FAIL '' '

to the default diagnostic page on the LCD.

Figure 6-2 also shows the logic used to monitor the status of the High-set andLow-set current level detectors. If any High-set level detector operates for acontinuous period of five seconds, without operation of the corresponding Low-setlevel detector, the relay will close the "Relay Inoperative Alarm" contact andextinguish the "Relay Available" LED.

6.1.3 Digital bus intergrity

In bus structured equipment the integrity of the address and data buses is of paramount importance. In the Optimho relay the integrity of the address and databus lines is checked, on a cyclic basis, each loop of the main microcontrollersoftware. Furthermore, to ensure that any trip commands perceived to be fromZone comparator circuits are legitimate (i.e. are not the result of a false READ dueto an address or data bus failure), a full check of the address and data buses isperformed by the main microcontroller before any trip command to the outputrelays is issued.

The bus check feature incorporates both hardware and software in itsimplementation. The hardware arrangement is shown in Figure 6-3. This hardwareis located on the front panel PCB.

The bus check ensures that no address or data line is tied to a logic high or low, orshorted to any other line, and that there is no break in the connections between themain microcontroller and the bus check hardware.

The digital bus structure consists of eight address lines, eight data lines, a READline and a WRITE line. During normal operation the software cycles through

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checking one line from the address bus and data bus each loop of the mainmicrocontroller program.

The check consists of reading an address (1,2,4,8,16,32,64, or 128), which will

individually put an address line to a logic 1. The individual reads of theseaddresses is immediately followed by a READ of address 255, which results in theprevious address being output as data from the address latch in the bus checkinghardware. This results in the corresponding data lines being individually set to alogic 1. By cycling through the addresses listed above, and following each with aREAD to address 255, then each line on the address bus and data bus will beindividually set to a logic one.

The complete cycle is as listed below :

Operation Address bus lines Data bus lines

READ (1) 00000001 XXXXXREAD (255) 11111111 00000001READ (2) 00000010 XXXXXREAD (255) 11111111 00000010READ (4) 00000100 XXXXXREAD (255) 11111111 00000100READ (8) 00001000 XXXXXREAD (255) 11111111 00001000READ (16) 00010000 XXXXXREAD (255) 11111111 00010000READ (32) 00100000 XXXXXREAD (255) 11111111 00100000READ (64) 01000000 XXXXXREAD (255) 11111111 01000000READ (128) 10000000 XXXXXREAD (255) 11111111 10000000WRITE (255) 11111111 XXXXXREAD (255) 11111111 11111111

Note: X = do not care

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If the WRITE line is stuck at logic 0 (on):

During the READ of addresses < 255 the latch becomes 'transparent', i.e. theinternal data lines of the latch simply reflect the status of the address lines. At theend of the READ cycle the address is latched on the trailing edge of the READ

pulse. The address bus will subsequently return to 255 (due to action of passivepull-up resistors on the bus lines), this will make the latch become 'transparent'again (due to WRITE line being stuck at logic 0), resulting in the latched addressbeing erased and replaced with 255. When the READ of address 255 occurs thiswill result in 255 being output - wrong answer, and so the fault will be detected.

If the WRITE line is stuck at a logic 1 (off) :

The WRITE to 255 test will fail (since the WRITE line cannot pulse low) and so thefault will be detected.

If the READ line is stuck at logic 0 (on) :

During the READ of addresses < 255 the latch will become 'transparent'. At the endof the READ cycle the latch will remain 'transparent' (due to READ line being stuckat logic 0), until the address decoder logic detects the address 255 (the quiescentstate of the address bus). At this time, due to propagation delays in the addressdecoding logic, the address 255 will be held by the latch. When the bus checksoftware performs a READ of address 255 in the cyclic sequence it will always getthe same answer on the data bus - 255, which is only valid for one of the steps inthe cycle.

The fault on the READ line will therefore be detected.If the READ line is stuck at logic 1 (off) - The sequence will fail at all READ tests.

Should a failure of the address or data bus lines be detected then the mainmicrocontroller responds, after 60mS, by extinguishing the "Relay Available" LED onthe front panel, closing the "Relay Inoperative Alarm" contact, and opening all otherrelay contacts. The main microcontroller will then solely perform continuous buschecking. Should the bus structure recover from the fault condition, the mainmicrocontroller will respond by running the power up initialisation routine to restoreall settings, before resuming normal operation.

A temporary fault on the bus lines may have been caused by the failure of anaddress decoder or data input / output latch. Such a failure can also be detectedby the onboard watch-dog feature. (See later)

6.1.4 Memory checks - RAM and EEPROM

The main microcontroller uses both internal and external RAM (Random AccessMemory) for processing data. Directly after power up, both internal and external

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RAM are tested and cleared. If any locations cannot be written to or read fromcorrectly, then an error condition exists.

The main microcontroller board uses EEPROM (Electrically EraseableProgrammable Read Only Memory) to provide non-volatile storage of relay settings

and fault records. Whenever data is written to the EEPROM a checksum value forthe data is computed and also stored. The data is then read back from theEEPROM and a further checksum calculated. Provided this checksum matches theone stored with the data originally, then the data is intact. If the checksums do notmatch then an error condition exists.

Should an error condition be detected in either the RAM or EEPROM, then a defaultdiagnostics page is written to the LCD, indicating an error on the mainmicrocontroller board in slot 11. An alarm is also issued by extinguishing the "RelayAvailable" LED, and closing the "Relay Inoperative Alarm" contact. Monitor option24 (see Section 3.14.4) may be used to determine whether the error is in internal

RAM, external RAM, or the EEPROM.

6.1.5 Watch-dog monitoring

Optimho relays use several 80C51 microcontrollers in the hardwareimplementation. These microcontrollers perform the various functions required, e.g.level detectors, sequence comparators, voltage memory feature, frequencytracking, combinatorial logic, etc. These various functions are performed by an80C51 microcontroller that has been "masked" with the software required for allthe features.

On dc energisation, each microcontroller "identifies" its required function byenergising a control line and reading the resultant information from one of its inputports. The microcontroller then releases the control line and, based on theinformation returned to the input port, runs the required software. According to thesoftware function required, the microcontroller assigns one of the output pins as its"watch-dog" output. The output pin used for this purpose is unique for eachsoftware application.

Each loop of the software the microcontroller toggles the status of the watch-dogpin. This produces a square wave output, the frequency of which is determined bythe loop time of the software that is being run (typically 100us - 200us). The outputfrom the watch-dog pin is used to trigger a re-triggerable monostablemultivibrator, the output of which will be at a logic low (0) provided that themicrocontroller keeps re-triggering the monostable input.

Should the microcontroller fail to output the watch-dog signal the monostablecircuit will respond by taking its output signal to a logic high (1). The CR circuit onthe output of the monostable will transfer the logic high as a pulse to the reset pin

of the microcontroller, thus re-starting it.

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If the microcontroller fails to re-start correctly the output from the monostable willstay high. Figure 6-5 shows a schematic representation of the watch-dog feature.

The monostable output is also connected to the output data latch.

Each time the main microcontroller loops through its software program it reads the

data from all the processing boards output data latches. The status of the data bitsrepresenting watch-dog outputs are examined and should any watch-dog bit behigh (1) then the data from that latch will be declared void for that loop of themain microcontroller program.

Before issuing a trip signal, the main microcontroller again reads the status of thewatch-dog signals. If any have operated since the last read of the watch-dogs thenthe main microcontroller does not issue the trip signal and re-starts its programloop.

Should any watch-dog circuit operate then the main microcontroller writes a

message to the default diagnostic page on the LCD, indicating which board slot theerror has been detected. An alarm is also issued by extinguishing the "RelayAvailable" LED and closing the "Relay Inoperative Alarm" contact.

A further advantage of the watch-dog feature is that it is also capable of detectingother board failures. The "quiescent" state of the digital data bus is for all lines tobe at a logic high (1). When the main microcontroller reads the output data fromthe latch, the watch-dog "bit" will be low provided that:

a) The circuit being monitored by the watch-dog is healthy.b) The onboard address decoding circuitry is functioning

correctly.c) The output data latch is functioning correctly.

In the LFZP 111 model, equipped with both Quadrilateral and Mho ground faultcharacteristics, remedial action is taken if a watch-dog operation on theQuadrilateral comparator board occurs and the Quadrilateral characteristic hadbeen selected via the menu. If the Zone 3 quadrilateral ground fault watch-dogoperates, then the alternative Zone 3 lenticular ground fault elements are used. If the Zone 1 / Zone 2 quadrilateral watch-dog operates, then the alternative Zone 1/ Zone 2 shaped mho ground fault elements are used. Since most system faults areground faults, this capability considerably increases the overall availability of therelay. The error associated with the Quadrilateral board will be alarmed in theusual manner.

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In Models of Optimho equipped with Zone 3 elements, if the scheme selected isany POR 2 scheme, and a fault is detected on the Zone 3 comparator board, therewill be a danger of the relay mal tripping for a fault on a parallel line (refer toSection 5.11 and Section 5.12). To prevent this occurring, the scheme will revert

back to the Basic scheme for this condition.

If the clock signal for the polarising phase shift circuits (located on the Zone 1 /Zone 2 shaped mho comparator board) fails, the clock circuit watch-dog willoperate. Should this occur, the Zone 1 and Zone 2 data is ignored. Also, if theZone 3 elements are set reverse only, then the data from the Zone 3 reverseshaped mho elements is also ignored.

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Figure 6-1 Self monitoring

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Single pole open opto

Any pole dead

Any Z1, Z2, Z3

LDVO

5sRelayFail

0

&

Current level detector anomalies

LDLSC

LDHSN

LDLSN &

Current transformer supervision

LDLSA

LDHSB

LDLSB

LDHSC

LDHSA

DEF_F/R

LDLSN

&

1&

&

Figure 6-2 Monitoring of anomalous conditions

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Figure 6-3 Digital bus check hardware

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Example WR line stuck at logic 0 (on)

D3

D5

D6

D7

D4

D2

D0

RD

WR

high impedance output

pulled up

0

D7

D6

Ad1

0Ad7

Ad3

Ad5

Ad6

Ad4

Ad2

0

0

0

0

0

1Ad0

COMPAREFAILS

D1

1

1

1

1

1

1

1

1

latch Adr

LE

D4

D5

D1

D2

D3

D0

OE

Ad4

Ad6

Ad7

Ad5

Ad3

Ad1

Ad2

Ad0

take in Adr

Adr to

Data bus

output

take in Adr

Figure 6-4 Digital bus check cycle

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Figure 6-5 Watchdog monitoring

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6.2 Main microcontroller software

6.2.1 Introduction

The scheme logic software for Optimho is contained in a 64k * 8 bit CMOS

EPROM and is run in a CMOS 80C51 masked microcontroller. Details of thehardware are given in Section 6.4.

Each relay version in the Optimho range requires different software. This softwarehas been broken down into smaller modules each doing a specific function. In thisway many of the modules are common to all the relays in the range. Wheredifferences do occur (i.e. input/output routines) specific modules have been written.

The appropriate modules are then linked together to form the overall software foreach relay type.

The software structure is shown in Figure 6-6. Much of the software is described,

with the aid of logic equivalent circuit diagrams, in other sections of this manualand a cross reference is given in Figure 6-6.

6.2.2 Initialisation

On power up or after a reset the main microcontroller performs the followingfunctions:

a) A full bus check as described in Section 6.1.3.

b) Flashes the ALARM and TRIP LED's.

c) Checks the internal and external RAM as described in Section6.1.4.

d) Resets all the other micro controllers in the relay.

e) Reads the settings from E2PROM.

f) Translates the settings and initialises the relay internal circuitsincluding the DEF and fault locator when fitted.

g) Initialises the LCD.

h) Sends the menu and software variable timer settings to theslave timer microcontroller.

i) Preloads internal registers ready for the main loop.

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6.2.3 Main loop

After the initialisation the software enters the main program loop as shown inFigure 6-6. This loop consists of a number of modules which are run in sequence.

The loop takes approximately 2 to 3ms to run.

The user interface and serial communication modules handle the display,keyboard, printer and RS232 serial communication functions. The remainingmodules handle the distance and DEF relay functions.

The internal registers used for storing data are cleared and the data is read fromall the latches on the boards. This data is sorted and stored in the microcontroller'sinternal registers.

The other software modules process this data storing the results in internal registers.

Finally the appropriate data is outputted to the various boards in the relay.

6.2.4 Timers

Extensive use is made of software timers. These are run in a separatemicrocontroller under the control of the main microcontroller.

Three types of timers are required. The simplest are fixed length timers whoselength is defined in the timer microcontroller (Table 6-1).

The second type are variable length timers whose length is defined by theinitialisation software (Table 6-2).

The third type are variable length timers whose length is defined by the menusettings (Table 6-3). The actual timer lengths are passed to the timermicrocontroller as part of the initialisation.

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INITIALISATION

LEVEL

PSB LOGIC

DEF LOGIC

SOTF LOGIC

DETECTOR

Section

Section

Section

Section

OUTPUT INTERNAL

DATA

OUTPUT CONTACT

5.5

5.6

4.4

5.3

MONITOR

TEST OPTIONS

INFORMATION

CONDITIONS

INDICATION

ANOMALOUS

BAR LOGIC

REGISTERS

BUS CHECK

POLE DEAD LOGIC

VTS LOGIC

INPUT ALL DATA

Section

Section

Section

TOGGLE WATCHDOG

COMMUNICATIONS

SERIAL

CLEAR

INTERFACE

CLEAR OPTO

REGISTERS

USER

Section

Section

NO

FAULT LOCATOR

FILTER SWITCHING

TRIP LATCHING

SELECTED SCHEME

5.2

5.1

6.1

MEMORY COUNT

EXTERNAL

STARTS

LOGIC

COMBINING LOGIC

3.13 YES

3.1-3.12

BASIC SCHEME

BASIC SCHEME

Section 6.1

Section

Section 3.14

8.6

Section 5.19

Section 5.20

Section 5.17

Section 5.18

Section 5.9-5.15

Section 5.8

Figure 6-6 Main software loop

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Table 6-1 Timers with fixed lengths

Timer ref. Timer name Setting ms

T2 Pole Dead A Ph DO 22.5

T3 Pole Dead B Ph DO 22.5 T4 Pole Dead C Ph DO 22.5 T5 VTS Accelerated

Indication PU20

T6 SOFT Current noVolts Pick Up

20

T7 LDLSI2 Drop Off 20 T9 Z1 Ph Comparator

Block35

T10 Z2 Ph Comparator

Block

35

T11 Weak Infeed PU 60 T13 Trip Drop Off 60 T14 Loss of Guard

Drop Off 200

T15 Signal Received DO 100 T16 Block Auto-reclose

Drop Off 100

T17 Weak Infeed anyComparator DO

100

T18 POR/Weak InfeedCarrier Echo

100

T20 DEF Reset 22.5 T21 SOTF Dead Time 200 T22 Any Pole Dead DO 240 T23 All Poles Dead DO 250 T25 ALARM LED flash 750 T26 VTS Pick Up 5500 T28 SOTF Dead Time 110 000 T29 Home Key Delay 900 000 T30 Weak Infeed PU 10 T33 POR Carrier Delay 100 T34 Permissive scheme

Disable150

T45 Real time clock Timer

1000

Table 6-2 Timers whose length are fixed in the software

Timer ref. Timer name Setting ms

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T8 Bandpass filter(volts)

30

T12 POR CircuitBreaker Open PU

250

T19 DistancePreference

50or 20

T24 Relay blockedopto drop off

20

T27 Reset key repeat 2000 T32 Bandpass filter

(current)40

T44 Anomalousconditions

5000

Table 6-3 Timers whose length are set via the menu

Timer ref. Timer name Minimumms

Maximumms

Stepms

T1 TDW 0 98 2 T35 TZ2 100 9980 20

T36 TZ1X 100 9980 20 T37 TZ1Y 100 9980 20 T38 TZ3 100 9980 20 T39 TZ6 20 90 5 T40 TD 0 98 2 T41 TP 0 98 2 T42 TDG 0 98 2 T43 TPG 0 98 2

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6.2.5 Input routine

The input routine reads the status of all the comparators, level detectors, opticalisolators and the DEF if fitted. It checks the validity of the data by testing thewatchdog bit, as described in Section 6.1.5 and stores the data in internal RAM for

use later in the loop.

The following is a list of all the input signals and the action taken on testing thevarious check bits. In all cases if the watchdog bit (WD D7) is a 1 data from thatparticular latch is ignored.

Distance comparators

If the quadrilateral (QUAD) characteristic is selected ground fault data from theQuad latches is used instead of the ground fault data from the mho/lenticularlatches.

BOARD ADDRESSZJ0130 62HZJ0130 63HZJ0131 44HZJ0132 51HZJ0132 52H

ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

62H WD WD

MEM

CpCAZ1 CpBCZ1 CpABZ1 CpCZ1 CpBZ1 CpAZ1

63H WD WD CLK CpCAZ2 CpBCZ2 CpABZ2 CpCZ2 CpBZ2 CpAZ2

44H WD CpABZ6 CpCAZ3 CpBCZ3 CpABZ3 CpCZ3 CpBZ3 CpAZ3

51H WD CpCZ2 CpBZ2 CpAZ2 CpCZ1 CpBZ1 CpAZ1

52H WD CpCZ3R CpBZ3R CpAZ3R CpCZ3F CpBZ3F

CpAZ3F

If WD MEM = 1 data is acceptedIf WD CLK = 1 Zone 1 & Zone 2 data is ignored.

If WD CLK = 1 and Zone 3 set reverse Zone 3 data is ignored.If WD CLK = 1 and Zone 3 set offset Zone 3 data accepted from ZJ0131If Quad selected and Zone 3 quad WD fails for 24 loops Zone 3 Lent G/F data isused.If Quad selected and Zone 1/2 quad WD fails for 24 loops Zone 1 & Zone 2 MhoG/F data is used.

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Level detectors

BOARD ADDRESSZJ0136 1BHZJ0136 1CH


1BH WD LDHSI0 LDLSI2 LDV0 LDLSI0 LDOVC LDOVB LDOVA

1CH LDHSN LDLSN LDHSB LDHSB LDHSA LDLSC LDLSB LDLSA

If WD = 1 data from both latches is ignored.

Optical isolators

BOARD ADDRESSZJ0133 12H


12H WD ResetInd

RelayBlocked

CRX COS BreakerOpen

SinglePole

Open

ResetZ1Ext/LGS

DEF (if fitted)

BOARD ADDRESSZJ0139 09H


09H WD CpDEFR CpDEF Not DEF T BU

Not DEFStart

MAGINRUSH

6.2.6 Output routine

As the loop is run the various control signals such as pole dead A, bandpass filterswitching etc. are built up in internal registers. At the end of each loop the outputroutine sends this data to the appropriate latches on the boards in order to controlthe relay circuits.

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Distance comparators

BOARD ADDRESS REGISTERZJ0130 64H O_P_COMPAZJ0131 45H O_P_COMPC

ZJ0132 53H O_P_COMPB


64H Vmemrun

Count 3 Reset M PDA PDB PDC Reset C Count 4

45H Z3 a/b Z3 a/b Count 3 PDA PDB PDC Reset C Count 4

53H Count 3 Reverse PDA PDB PDC Reset C Count 4

AC input

BOARD ADDRESS REGISTERZJ0134 03H O_P_AC1ZJ0135 07H O_P_AC2


03H FilterVolt

AMPhyst

FilterCurrent

THETA Ph

07H FilterVolt

AMPHyst

THETA N

Level detectors

BOARD ADDRESSZJ0136 1DH


1DH Reset

DEF (if fitted)

BOARD ADDRESS REGISTERZJ0139 0AH O_P_DEF


0AH FilterCurrent

Count 3 ResetAll

Inhibit Reset C Count 4

Output relays

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BOARD ADDRESS REGISTERZJ0140 05H OUTPUT1ZJ0140 04H OUTPUT2ZJ0140 06H OUTPUT3


05H 53-55 49-51 45-47 41-43 37-39 29-35 29-33 29-31

04H 54-56 50-52 46-48 42-44 38-40 30-36 30-34 30-32

06H 81-83 77-79 73-75 69-71 65-67 57-63 57-61 57-59

(e.g. 50-52 refers to the contact connected across the external connector terminalnumbers 50 and 52)

The data in OUTPUT1, OUTPUT2 and OUTPUT3 is dependent on the contact

configuration selected via the menu. See Section 8.0 for output configurations.

6.3 Power supply unit GJ0236

6.3.1 IntroductionSee Fig. 6-7

The single PCB (ZJ0143) power supply unit is contained within a solid enclosurewhich is mounted on the back of the Optimho. It can be detached from the mainrelay case by removing four retaining nuts and withdrawing the push-on power

leads from the terminal block.

Three versions of the power supply are available, for nominal input voltage ratings48/54, 110/125, 220/250 volts dc. These versions have operating ranges 37.5 to64.8, 87.5 to 150, 175 to 300 volts d.c. respectively, each version producesregulated output voltage rails with maximum load current capabilities of +12V @1A, +12V @ 0.5A, +5V @ 0.5A, and -12V @ 0.5A. Any output can beshort-circuited for a brief time with no resultant power supply damage.

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6.3.2 Operation

As can be seen by reference to Fig.6-7, the dc supply from the secure stationbattery is used as a power source for the production of the isolated smooth and

regulated internal supply rails. The dc is firstly passed through a filtering sectionwhich attenuates electrical noise and voltage spikes and ensures that the Optimhois immune to interference generated by other equipment connected to the stationbattery. It also prevents the power supply from transmitting interference to thissame equipment.

The filtered voltage is sensed by the voltage detector and when this exceeds aminimum value the internal voltage rail of the power supply electronics isenergised. This eliminates the danger of power supply maloperation for inputvoltages less than the minimum operating voltages given above.

The "feed forward" principle is used in the pulse width modulator section to producea 40kHz square wave with a mark to space ratio (duty factor) which varies inverselywith the filtered supply voltage. This ensures that the power supply output voltagesremain relatively constant despite differing or changing input supply voltages. Theswitching transistor is driven "on" and "off" by the pulse width modulator to energisethe primary of the transformer with current from the filtered voltage supply. Thetransformer electrically isolates the station supply from the relay electronics (2kV for1 minute) and transforms the primary voltage to a level suitable for the outputs.Screens are incorporated on the transformer to render the relay insensitive tocommon mode interference between the station battery supply and the relaycase/ground.

A pulsed voltage waveform is produced at each of the transformer secondarieswhich are smoothed by L - C low pass filters to produce near constant dc voltages.It is then necessary to regulate these voltages since small variations in them occurdue to ripple, input voltage variation and load regulation. This is accomplished bythe use of solid state regulator devices which also feature overcurrent and thermaloverload protection.

If some part of the power supply fails such that a large current is drawnfrom the station battery then a fusible resistor, connected in series withthe station battery voltage supply, operates and disconnects the batteryvoltage. Before resetting this device the fault resulting in its operationmust be investigated.

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Figure 6-7 Power supply GJ236

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6.4 Main microcontroller board ZJ0138

6.4.1 Versions

There are two versions of the main microcontroller board :

ZJ0138 001 for 50Hz relays,ZJ0138 002 for 60Hz relays.

6.4.2 Introduction

This board contains the main 80C51 microcontroller integrated circuit (sometimesreferred to as main processor) which together with peripheral components forms acomputer based system which controls operation of the relay. The main elements of this system are :

a) Main 80C51 microcontroller.b) 64K EPROM (Contains relay software program code).c) 32K RAM (Used to store information generated by program

execution).d) EEPROM (Non-volatile memory used to store relay settings and fault

records).e) Address Latch (Used to latch lower address code during read or write

instructions to external EPROM or external RAM).f) Address and Data busses

Additional elements include :

g) Address decoding logic.h) Slave 80C51 microcontroller.i) Identifier circuit.

j) DC rail monitoring circuit.k) Watchdog circuits.l) Transceiver and Latch circuits (Used to control the flow of information

external to the Main Microcontroller board).m) RS232 buffers (Used for serial communications).n) Buffer circuits (Used to buffer external Read (RD), Write (WR) and LCD

control lines).o) Logic circuits (Used for RELAY FAIL and CONTACT CLEAR

signals).p) Buffer/squaring circuit (Used for synchronising calendar clock to

system frequency).

Each of the above elements are explained in the text following.

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6.4.3 Operation - computer system

What follows is just a brief summary of some fundamental aspects of a busorientated computer system, a detailed explanation would run for volumes. A blockdiagram illustration of the Main Microcontroller board circuit is shown in Figure 6-8.

Bus architecture and timing

To address up to 64K of external program memory a 16 bit wide address bus isrequired. For data transmission an 8 bit wide data bus is used. In order to reduce thetotal number of bus lines required the Intel 80C51 microcontroller time multiplexesthe 8 lower address lines (A0 to A7) for joint use as data bus lines (D0 to D7). Whenthe main microcontroller executes a program instruction from external EPROM orreads data from external RAM it first asserts the 16 bit wide address of the location inEPROM or RAM where the instruction or data is stored, it then removes the assertedaddress code from the lower address/data bus lines to allow the EPROM or RAM

device to assert an instruction or data. The instruction or data is then read by themain microcontroller.

An address latching circuit is used to latch and maintain the lower address codeapplied to the external EPROM or RAM devices whilst these devices are outputtinginformation on the data bus. Timing control of signals used to execute instructions orread and write data is derived from an external crystal, this ensures that the controlsignals generated by the main microcontroller occur in the correct sequence and areestablished for a sufficient period of time.

The 80C51 main microcontroller uses three control lines, namely RD (read), WR(write) and PSEN (program store enable). To address external RAM the RD and WRlines are used. To address external EPROM (program memory) the PSEN line is usedas a read strobe (only read instructions are required for EPROM).

Figures 6-9 illustrate control signal timing required for a read (RD) and write (WR)from external RAM, and a read from external EPROM. The waveforms are describedin Section 6.4.13 Accessing External Memory.

Tri-state condition

The ability to tri-state the outputs of devices connected to the data bus isfundamental for operation of a bus configured system. When the output of a deviceis in a tri-state condition it appears as a high impedance (effectively open circuit) toany other device driving the data bus. The driving device is thus free to force the buslines either high or low. No conflict or contention occurs since only one device isallowed to drive the bus lines at any particular instant in time.

6.4.4 Main microcontroller

The main microcontroller is referred to as a microcontroller rather than amicroprocessor because the device is actually a self contained micro computer

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system fabricated as a single integrated circuit. The device contains; a CPU (Centralprocessing Unit) comprising an Arithmetic and Logic Unit (ALU), 128 bytes of RAMand 4K bytes of masked ROM, 4 Bi-directional 8 bit Ports (P0 to P3), two 16 bittimer/counters and a UART (Universal Asynchronous Receive and Transmit) for serialcommunication.

The CPU is responsible for executing software instructions and also provides apowerful boolean processor which is used extensively to implement the relay schemelogic. The device is configured to run software code residing in both internal maskedROM and external EPROM. The internal ROM is referred to as masked because thiscode is pre-programmed during manufacture and cannot be changed.

6.4.5 Slave microcontroller - timers

In order to implement software timers and the real time calendar clock a separateSLAVE microcontroller is used. Information is transferred between the SLAVE and the

MAIN micro controllers via the external 32k RAM. Since only one microcontroller isallowed to access the external address and data busses at any one time, the othermicrocontroller is forced to run code residing within its internal ROM. Externalinterrupts are used to ensure that only one microcontroller has control of the externalbusses at any one time. An external logic circuit is used to switch the ALE (AddressLatch Enable) control signals from each microcontroller.

6.4.6 Identifier circuit

The 4k of masked program code within each 80C51 microcontroller comprisesseveral distinct programs. The function implemented by a particular microcontroller(i.e. main microcontroller, comparator, level detector etc.) is dependant on theprogram code selected. In order for the 80C51 to know which function is requiredan external identify circuit is used. The identifier circuit utilises a transistor which isconfigured to ground a port pin of the 80C51. The particular port pin groundeduniquely identifies the program code required. This principle is used for all 80C51devices with the exception of the SLAVE microcontroller, this device is identified by aunique code issued by the main microcontroller. Refer to Section 6.1.5 for a detailedexplanation.

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6.4.7 Transceiver and latch circuits - external bus control

Communication with devices on other boards, external to the main microcontrollerboard, occupies only a small amount of the overall program loop. The majority of instructions in the program loop affect only components located on the main

microcontroller board. Since bus communications are mainly confined to the mainmicrocontroller board the address and data busses external to this board aretri-stated when no external communication is required. This arrangementconsiderably reduces any possible cross talk from the digital to the analogue bus. Abidirectional transceiver circuit is used to control the flow of data on the external databus and a latch circuit is used to control the external address bus. These devices arecontrolled by an address decoding circuit which monitors upper address lines A11 toA15. The external busses are only activated when a read instruction from an addressF8xxH or a write instruction from an address F0xxH is made (xx is a unique addressallocated to an external device).

Figure 6-10 shows the logic circuit used to control the transceiver and latch circuits.In order to avoid bus contention between the 32K RAM and external devices, whenexternal communication is in progress, the 32k RAM chip select (CS) input iscontrolled from address line A15. As a consequence of decoding the top addresslines and also utilising the 4k of internal masked code, the EPROM code memorymaps from 1000H to EFFFH.

6.4.8 External control lines - RD, WR, RS and R/W

The read (RD), write (WR), LCD select (RS) and LCD read/write (R/W) signals arebuffered from external boards by a tri-state buffer circuit. In line with the generalphilosophy of maintaining external bus lines as quiet as possible, to minimise anypossible cross talk from external digital bus signals to external analogue bus signals,the above control lines are only applied to external boards when they are required.

The tri-state buffer is controlled by an address decoding circuit which monitors upperaddress lines A12 to A15. The four control signals are only activated, as appropriate,when a read instruction from an address F8xxH or a write instruction from anaddress F0xxH is made (xx is a unique address allocated to an external device).Figure 6-10 shows the logic circuit used to control the tri-state buffer.

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6.4.9 EEPROM - non-volatile memory

This area of memory is non-volatile, that is, it maintains the information stored withinit even if the dc supply is removed.

All settings and fault records are stored in an 8k parallel EEPROM. Control signalWR and RD timing is similar to that used for external RAM. Address lines A15 andA14 are decoded and used to chip enable the device, effectively mapping EEPROMdata storage to the 32k to 40k region. An inbuilt software protection algorithmensures that inadvertent data writes cannot occur during dc power on/off or whenthe relay is subjected to external electrical noise.

6.4.10 Serial communication

80C51 UART

All serial communications are handled by a UART (Universal Asynchronous Receiveand Transmit) device within the main microcontroller. This device enables full duplexcommunication (transmit and receive simultaneously) at several baud rates withvarious protocols, refer to Section 3.13. The UART is controlled from software storedin EPROM.

RS232

Two separate RS232 buffer/converter circuits are provided, one for the front (LOCAL)serial port and one for the rear (MODEM) serial port. The function of these circuits isto convert TTL logic signals used by the main microcontroller to corresponding signallevels required for serial communications and visa versa. A TTL logic 1 output istransformed to a voltage level in the range +5V to +15V. A TTL logic 1 input istransformed from a voltage in the range +3V to +15V. A TTL logic 0 output istransformed to a voltage in the range -5V to -15V. A TTL logic 0 input is transformedfrom a voltage in the range -3V to -15V.

Each RS232 device is enabled from data bus line D5 ( 1 for LOCAL, 0 for MODEM)via a latch circuit connected to the internal data bus. The latch circuit is in turncontrolled by an output signal from the main microcontroller and the external write(WR) signal. Data is read and written serially to the RS232 devices using the TX(Transmit) and RX (Receive) port connections from the main microcontroller. Modemcontrol lines RTS (output) and DTR (output) are derived from data lines D3 and D4respectively, and applied to the modem RS232 buffer via a latch circuit. The latchcircuit is controlled by an output signal from the main microcontroller and theexternal write (WR) signal. Modem control lines CTS (input) and DSR (input) areconnected from the RS232 modem buffer to appropriate port pins on the mainmicrocontroller.

6.4.11 Monitor circuits

DC rail monitor

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Circuits are provided to monitor the 5V, 12V and -12V dc rail voltages. If the 5V dcrail drops by more than 10% a reset is applied to the main microcontroller. The resetis only removed when the 5V rail is within 10% of nominal 5V. Similarly, a reset isapplied if either the +12V or -12V dc rails are lost. In addition to resetting the mainmicrocontroller the CONTACT CLEAR and RELAY FAIL signals are pulled low when a

reset is issued. The CONTACT CLEAR signal is applied to all output auxiliary relayboards (ZJ0140) to prevent operation of any output auxiliary relay. The RelayInoperative Alarm contact closes and the Relay Available LED is extinguish when theRELAY FAIL signal goes low.

Watchdog monitor

Both the main and slave micro controllers are monitored by separate watchdogcircuits. The function of a watchdog circuit is to initiate a reset in the unlikely event of a software upset. The operating principle of the watchdog circuit relies on thesoftware code executing a periodic toggling of an output port connected to an

external monostable circuit. The periodic signal is used to hold off the output fromthe monostable circuit which is ac coupled to the reset pin of the mainmicrocontroller. Should a software upset occur, the periodic signal will be lost andconsequently a reset will be issued. The slave microcontroller reset pin is controlledfrom the main microcontroller.

6.4.12 Clock reference circuit

When the menu option to reference the CALENDAR CLOCK to the system voltagefrequency is selected the SLAVE microcontroller uses an input derived from theanalogue VB signal to reference the clock. The 'V MEM IN' sine wave signal issquared up to a uni-polar (+5V, -0.5V) signal using an open loop operationalamplifier and zener diode circuit. The SLAVE microcontroller counts edge changesfrom the squaring circuit, 100 (50Hz version) or 120 (60Hz version) changesconstituting a 1 second period. The Level Detector Overvoltage B signal (LDOVB) ismonitored by the SLAVE microcontroller. Should the system voltage fall to less than70% of nominal the LD0VB signal is pulled high. In this event the CALENDARCLOCK is automatically referenced to the relay crystal until the system voltage risesto above 70% of nominal.

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6.4.13 Accessing external memory -- bus cycle timing

Program memory read sequence (Figure 6-9a)

Each Program Memory bus cycle consists of six oscillator periods. These are referred

to as T1, T2, T3, T4, T5 and T6 on Figure 6-9a. The address is emitted from themicrocontroller during T3. Data transfer occurs on the bus during T5, T6 and thefollowing bus cycle's T1. The read cycle begins during T2, with the assertion of address latch enable signal ALE '1'. The falling edge of ALE '2' is used to latch theaddress information, which is present on the bus at this time '3'. At T5, the address isremoved from the Port 0 bus and the microcontroller's bus drivers go to the highimpedance state '4'. The program memory read signal PSEN '5' is also assertedduring T5. PSEN causes the addressed device to enable its bus drivers to thenow-released bus. At some later time, valid instruction data will become available onthe bus '6'. When the 80C51 subsequently returns PSEN to the high level '7', theaddressed device will then float its bus drivers, relinquishing the bus again '8'.

Data memory read sequence (Figure 6-9b)

Each External Data Memory bus cycle consists of twelve oscillator periods. These areshown as T1 through T12 on Figure 6-9b. The twelve period External Data Memorycycle allows the 80C51 to use peripherals that are relatively slower than its programmemories. Data transfer occurs on the bus during T7 through T12. T5 and T6 is theperiod during which the direction of the bus is changed for the read operation. Theread cycle begins during T2, with the assertion of address latch enable signal ALE '1'.

The falling edge of ALE '2' is used to latch the address information, which is presenton the bus at this time '3'. At T5, the address is removed from Port 0 bus and themicrocontroller's bus drivers go to the high-impedance state '4'. The data memoryread control signal RD '5', is asserted during T7. RD causes the addressed device toenable its bus drivers to the now-released bus. At some later time, valid data willbecome available on the bus '6'. When the 80C51 subsequently returns RD to thehigh level '7', the addressed device will then float its bus drivers, relinquishing the busagain '8'.

Data memory write sequence (Figure 6-9c)

The write cycle, like the read cycle, begins with the assertion of ALE '1' and theemission of an address '2'. In T6, the microcontroller emits the data to be written intothe addressed data memory location '3'. This data remains valid on the bus until theend of the following bus cycle's T2 '4'. The write signal WR goes low at T6 '5' andremains active through T12 '6'.

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Figure 6-8 Main microcontroller ZJ0138

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ADDRESS A15 - A8

ADDRESS A15 - A8

Program Memory Read Cycle Timing (a)

Data Memory Read Cycle Timing (b)

PSEN

ALE

OSC

1

T1 T2

5

T5

2

T3 T4

7

T6 T7 T10T8 T9 T11 T12 T2T1

PORT 2

PORT 0 FLOATINST IN

WR

PSEN

ALE 1

2

3

A7 - A0

2

5

PORT 2

PORT 0

RD

PSEN

FLOATINST IN

ALE

PORT 0

PORT 2

RD, WR

FLOAT

1

FLOAT

3

3 4

A7 - A0

6

5

ADDRESS A15 - A8

6

FLOAT

2

A7 - A0

3 4

3

INST IN FLOAT

8

4

DATA OUT

6

OR FLOAT

ADDRESS

DATA IN

8

FLOAT

7

ADDRESS A15 - A8

A7 - A0 FLOAT FLOATINST IN

ADDRESS

OR FLOAT

Data Memory Write Cycle Timing (c)

Figure 6-9 Program memory read cycle timing

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ANDA14A15

TRI-STATE CONTROLFOR RD, WR, RS & R/W

TRI-STATE CONTROL

FOR ADDRESS BUS

DIRECTIONAL CONTROL

FOR DATA BUS

TRI-STATE CONTROL

FOR DATA BUS

TRANSCEIVER

TRANCEIVER

BUFFER

RD

A13

A12

A11

ANDOR

OR

LATCH

Figure 6-10 Address decoding circuit for external bus control

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6.5 Front module GJ0240 (Board ZJ0137 / ZJ0166)

The Front Module GJ0240 consists of a hinged front panel assembly which housesthe front panel board ZJ0137 or ZJ0166. Figure 3-1 shows the horizontal aspectfront panel layout arrangement. Figure 6-11 is a block diagram illustration of the

front panel circuit.

6.5.1 Versions

There are two versions of the front panel module, these are :-

GJ0240 001 (Board ZJ0137 001) for horizontal aspect,GJ0240 002 (Board ZJ0166 001) for vertical aspect.

6.5.2 Mechanical

The front panel board is mounted on the hinged front panel assembly. Connectionsare made to the main microcontroller board (ZJ0138) via a 64 way plug/socketconnector. Connections are made to the opto-isolator board (ZJ0133) and outputrelay boards (ZJ0140) via a 64 way ribbon cable connector mounted on the side of the front board. A special hinge alignment mechanism ensures that the front panelboard connector locates accurately with the main microcontroller board connectorwhen the front panel is closed. A spring loaded support arm is provided to hold thefront panel open when withdrawing or inserting circuit boards.

6.5.3 Liquid crystal display

A 2 line by 16 character dot matrix liquid crystal module is used. This display moduleconsists of a liquid crystal panel with CMOS drive/control, character generator ROMand display data RAM circuitry.

LCD operation

Three control lines, namely RS, R/W and E are used to control the writing andreading of information to and from the LCD. Information written to the LCD modulemay be either control instructions or data for display. Before any information iswritten to the LCD module the data line D7 (BUSY line) is tested and information isonly written provided the LCD is ready to action it. The BUSY line is routed through abuffer circuit and connected to external data bus line D7. Note, the address anddata buses external to the main microcontroller board are referred to as externaladdress and external data bus. These buses are only activated when the mainmicrocontroller reads or writes to devices external to the main microcontroller board(ZJ0138). Display data or control commands are written to the LCD module via alatch circuit connected to the external data bus.

The latch and buffer circuits are controlled by separate outputs from an address

decoding circuit connected to the external address bus. Unique addresses areallocated for the control of the buffer and latch circuits. The BUSY line is read onexternal data bus line D7 whenever the main microcontroller executes a read (RD)instruction from the LCD buffer address (3AH). Display data or control instructions

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applied to the external data bus, are written to the LCD latch circuit whenever a write(WR) instruction to the LCD latch address (39H) is executed by the mainmicrocontroller.

6.5.4 Keypad operation

The keypad consists of four cursor (arrow) keys mounted in a cruciform pattern, aRESET key, a SET key and a ACCEPT/READ key. One side of each key is connectedto 0V, the other side is connected to a data line. When a key is pressed theconnected data line is grounded. When a key is not pressed, the connected data lineis pulled high (5V) via a pull up resistor. The table below shows data line keyconnections and the corresponding code present on the data bus when each key ispressed in turn.

KEY DATA BUS LINECONNECTED DATA BUS CODEWHEN KEYPRESSED

PARALLEL PORTPIN CONNECTED

UP D0 FEH 17RIGHT D1 FDH 16DOWN D2 FBH 15LEFT D3 F7H 14SET D4 EFH 13

ACCEPT/READ D5 DFH 12RESET D6 BFH 10

No Key FFH

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A latch circuit is used to buffer the external data bus from the keypad keys. The latchcircuit is controlled by the output of an address decoding circuit connected to theexternal address bus. A unique address (38H) is allocated for the control of the latchcircuit. The main microcontroller reads the keypad status by executing a read (RD)

instruction from address 38H. Software code run by the main microcontroller is usedto de-bounce a key by only actioning it if its status has remained constant for morethan about 20ms. The keypad connected data lines are also connected to thePARALLEL port pins, as indicated in the table above, this allows key presses to bemimicked by grounding the appropriate PARALLEL port pin using external testequipment connected to the PARALLEL port. Note, pins 22 to 25 on the PARALLELport are connected to 0V.

6.5.5 Address/data bus checking circuit

The electrical integrity of the address bus, data bus, READ (RD) line and WRITE (WR)line, is continually monitored by the main microcontroller using circuitry located onthe front panel board. The bus check circuitry consists of an address decoding circuitwhich controls a latch circuit connected between the address and data buses. A fullexplanation of the circuit operation and method used to implement bus checking isgiven in Section 6.1.3.

6.5.6 Parallel port

Output signals - printer strobe

The Printer Strobe signal is used in conjunction with the Printer Busy signal toimplement handshaking between the relay and a connected parallel printer. Printdata sent to the PARALLEL port is only acknowledged and read by a parallel printerwhen the Printer Strobe signal is low. The Printer Strobe signal is controlled by thedata line output D3 of a latch circuit connected to the external data bus. The latchcircuit is controlled by the output from an address decoding circuit connected to theexternal address bus. A unique address (3BH) is allocated to control the latch circuit.

Output signals - DC

For monitoring purposes the 5V, 12V, -12V and 12V(Relay) dc rail voltages arebrought out to PARALLEL port pins 18, 19, 20 and 21 respectively via 10 kohmresistors.

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Output signals - for parallel printer and monitor options

Eight npn transistor circuits are used to provided 8 TTL compatible outputs. Theseoutputs are suitable for direct connection to a parallel printer or can be used byexternal test equipment to monitor the logical status of various internal signals, refer

to Monitor Option Section 3.14.4. The TTL compatible outputs are controlled by thedata line outputs D0 to D7 of a latch circuit connected to the external data bus. Thelatch circuit is controlled by the output from an address decoding circuit connected tothe external address bus. A unique address (3CH) is allocated to control the latchcircuit. The logic inversion introduced by the transistor circuits is reversed bycomplementing (inverting) data before writing it to the output latch.

Input signals - keypad mimic

Key presses can be mimicked by grounding appropriate pins on the PARALLEL port,see KEYPAD OPERATION section above.

Input signals - printer busy

The Printer Busy signal is used in conjunction with the Printer Strobe signal toimplement handshaking between the relay and a connected parallel printer. Printdata is only sent to the PARALLEL port when the printer pulls its Printer Busy line lowto indicate that it is ready to receive data. The Printer Busy line, connected to dataline D7, utilises the keypad latch circuit. The main microcontroller reads the PrinterBusy line by addressing the latch using the same method as used for reading thekeypad status, as described in KEYPAD OPERATION above.

Isolation

This port is intended for local connection only and as such has only limited protectionagainst high voltage interference. Precautions should be taken to isolate externalconnections made to this port if excessive noise voltages are possible.

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Summary Table of PARALLEL Port Pin Connections

PARALLELPORT PIN

PRINTERCONNECTIONS

FUNCTION NAME

1 STB (Pin 1) Printer strobe (Output)2 D0 (Pin 2) Data line D0 (Output)3 D1 (Pin 3) Data line D1 (Output)4 D2 (Pin 4) Data line D2 (Output)5 D3 (Pin 5) Data line D3 (Output)6 D4 (Pin 6) Data line D4 (Output)7 D5 (Pin 7) Data line D5 (Output)8 D6 (Pin 8) Data line D6 (Output)9 D7 (Pin 9) Data line D7 (Output)10 Do not connect Data line D6 RESET key (Input)

11 BUSY (Pin 11) Data line D7 Printer Busy (Input)12 Do not connect Data line D5 READ key (Input)13 Do not connect Data line D4 SET key (Input)14 Do not connect Data line D3 LEFT key (Input)15 Do not connect Data line D2 DOWN key (Input)16 Do not connect Data line D1 RIGHT key (Input)17 Do not connect Data line D0 UP key (Input)18 Do not connect 5v Monitor (Output)19 Do not connect 12v Monitor (Output)20 Do not connect -12v Monitor (Output)21 Do not connect 12v(Relay) Monitor (Output)22 0v (Pin 22) 0v23 0v (Pin 23) 0v (Note: All are commoned,24 0v (Pin 24) 0v only 1 connection25 0v (Pin 25) 0v necessary)


6.5.7 Indication LED's

Three indication light emitting diodes (LED) designated TRIP (red), ALARM (yellow)

and RELAY AVAILABLE (green) are provided. The TRIP and ALARM LED's arecontrolled by the data line outputs D0 (for TRIP LED) and D2 (for ALARM LED) of alatch circuit connected to the external data bus. The latch circuit is controlled by theoutput from an address decoding circuit connected to the external address bus. A

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unique address (3BH) is allocated to control the latch circuit. In order to turn ON the TRIP LED a data byte having bit D0 set is written to the data bus at address 3BH. Toturn OFF the TRIP LED a data byte having bit D0 cleared is written to the data bus ataddress 3BH. The ALARM LED is similarly controlled using data bit D2. The RELAYAVAILABLE LED is operated from the normally open contact of the Relay Inoperative

Alarm auxiliary relay mounted on output relay board ZJ0140 002. Under normalworking conditions the RIA auxiliary relay is picked up and the RELAY AVAILABLE LEDis turned on.

6.5.8 Serial Port

Relevant connections made to the 25 way D type front mounted (LOCAL) SERIAL portare routed directly to the main microcontroller board (ZJ0138) via the 64 wayfront/main microcontroller plug/socket.

Note, this port is intended for local connection only and as such has only limited

protection against high voltage interference. Precautions should be taken to isolateexternal connections made to this port if excessive noise voltages are possible, referto Section 3.13.

Summary Table - SERIAL port pin connections for front (local) socket

SERIALPORT PIN

FUNCTION NAME

1 0V (Ground)2 TXD (Transmit)

3 RXD (Receive)4 Not connected5 Reserved, do not connect6 Not connected7 0V (Signal ground)

8 to 24 Not connected25 Reserved, do not connect

Refer to Figure 3-7 for appropriate connections.

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Figure 6-11 Front Panel ZJ137 / ZJ166

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6.6 Optical isolator board ZJ0133

6.6.1 Introduction

The board contains seven optical isolators as shown in block diagram form in Figure

6-12. These allow the scheme logic to access information from external equipmentand take appropriate action, as described in Section 5.0.

The main microcontroller reads the status of the optical isolators via the address anddata bus.

6.6.2 Voltage rating

There are two different voltage ratings (Vx2) as shown in the table.

V x 2 Operative Range Maximum Withstand48/54V 37.5 to 60V 64.8V

110/125V 87.5 to 137.5V 150V

For Vx2 = 220/250V the 110/125V option is used with an external resistor boxGJ0229 002.


The PCB plugs directly into the rear Midos terminal block and communicates with themain microcontroller through the ribbon cable at the front of the relay. The rearconnection and function of each optical isolator are shown in the following table.

CASE TERMINAL NAME+ve -ve58 60 Reset Zone 1 Extension / Loss of Guard62 64 Single Pole Open66 68 Breaker Open70 72 Channel Out of Service

74 76 CRX78 80 Relay Blocked82 84 Reset Indications

The optical isolators have a defined minimum operating voltage of greater than 10V. Transient operation is prevented by filtering the output of each optical isolator. Transient suppressers are fitted across the inputs to prevent damage to the opticalisolators. A screen, connected to the case, diverts interference to the case, thuspreventing coupling into the secondary circuits.

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Figure 6-12 ZJ0133 Optical Isolator Board

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6.7 Input Module GJ0233

6.7.1 Introduction

The input module provides the electrical isolation between the relay and substation

equipment for the ac voltage and current inputs. The module contains three voltagetransformers, five current transactors and 2 printed circuit boards (ZJ0134 &ZJ0135) which contain calibration and filter circuits. The transformers are mountedon a metal plate with their primaries wired to a Midos terminal block. Thesecondaries are wired to a small backplane on the rear of the module. Thebackplane has edge connectors for two PCBs and a connector to couple it to themain backplane.

The module connects to the rear terminal block for external connections and to themain backplane for internal connections.

Block diagrams of the 2 PCBs are shown in Figures 6-13 and 6-14.

The main microcontroller controls setting etc. via the digital address and data bus. The analogue signals are transferred to the measuring boards located in the centralsection of the case via the analogue bus. The voltage and current circuits will bedescribed separately.

6.7.2 Voltage input circuits

The input module isolates and filters the ac inputs from the transmission line voltage

transformers. The module has three phase-neutral connected isolating transformersinsulated to 5kV peak. These have interwinding screens to attenuate common-modehigh frequency interference.

Figure 6-15 shows a simplified block diagram of one phase of the voltage circuit.

The output from each transformer is passed to the backplane and on to the PCBwhere it passes through an overvoltage surge protection circuit which limitsovervoltages due to lightning strikes, cross country faults and other high voltagetransients to within limits which are safe for the electronic circuitry contained withinthe relay.

The signals are calibrated and filtered by low pass filters with cut-off frequencies of 300Hz. The purpose of the filters is to remove unwanted high frequency signals suchas line reflections following the incidence of a fault or interference induced onsubstation wiring by switching operations. Each output is then passed to a bandpassfilter. The filters are of second order with centre frequencies equal to the nominalsupply frequency and Q values of 0.5. This type of filter is very effective ineliminating unwanted exponential and high frequency components of the inputvoltage.

Under normal conditions the distance measuring elements use the voltage signalproduced by the low pass filter. However, the measuring elements are automaticallyswitched to the filtered output of the bandpass circuits after a predetermined interval

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of time from the incidence of a fault. This ensures that, if the comparator operatingtime has been extended by abnormally severe exponential or high frequencycomponents of the voltage signal, the comparators have the opportunity of remeasuring on a relatively uncontaminated voltage signal.

This arrangement prevents any possibility of excessively long comparator operatingtimes which might otherwise occur under certain extreme conditions, such as:

a) Severe CVT transient errors with high SIR and high faultposition.

b) Severe travelling wave distortion on a long line at highfault position.

c) Large mismatch between source and line time constants withhigh SIR and high fault position. An example is shown inFigure 6-16.

The voltage level detectors, distance comparators and the zero sequence currentlevel detector are used as fault detectors for the purpose of controlling the transferfrom normal to bandpass filtered voltage signals (see Section 5.16). Solid stateswitches are used under the control of the main microcontroller.

The reset time of the voltage level detectors is 0 to 5.5ms depending onpoint-on-wave of fault incidence, and a further delay of 30ms is introduced by asoftware timer. Resetting of any voltage level detector causes all three phases of voltage signal to be transferred to the bandpass filter outputs. The time delay of 30to 35.5ms between fault inception and signal transfer is sufficient to allow fasttripping to occur, if electrical conditions permit, before the intervention of the filters.If fast tripping does not occur, the delay is long enough for the transient errors of thebandpass filters caused by the collapsing voltage to have decayed away beforesignal transfer to the bandpass outputs. At the instance of switching in the voltagebandpass filters, a step in the voltage waveform may arise and to ensure that thiscauses no confusion to the comparators a momentary inhibit pulse is sent to all thecomparators.

The voltage supply is switched back to normal when:

a) The fault is removed by a remote breaker so that the voltage isrestored to normal and the voltage level detectors pick up again.

b) The fault is cleared by de-energising the line such that one ormore pole dead conditions exist.

This control logic is performed by software in the main microcontroller described inSection 5.16.

When the relay trips the circuit breaker the relay reach is increased by 5%. This isachieved by reducing the gain of the voltage buffer amplifiers, which reduce theoutputs VA, VB and VC, by 5%. This hysteresis under control of the mainmicrocontroller defines the reset ratio of the relay and prevents chatter of relay

output contacts for faults on the boundary of operation.

The B phase output from the bandpass filter (VMEM IN) is used to generate thesynchronous memory facility on the Zone 1/2 comparator board (ZJ0130).

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The overall transfer functions for the voltage input signals at the nominal powersystem frequencies are:

Vout/Vin = 0.066299 /-10° (50 Hz models)Vout/Vin = 0.065874 /-12° (60 Hz models)

6.7.3 Current input circuits

The input module isolates and filters the ac current transformers. The standard relayrequires the use of only four current transactors, the fifth is fitted for use by either theDEF and/or fault locator features when fitted.

Figure 6-17 shows a simplified block diagram of one phase of the current circuit.

All the current transactor primaries are electrically isolated, to a level of 5kV peakfrom their corresponding secondaries and the relay case. In addition each device is

fitted with a screen which helps to couple any common mode electrical noise presenton the relay current input terminals to ground.

The output from each transactor, at approximately 0.3*I/In V /-90°, is wired to thebackplane and then to the PCBs. Any noise is further reduced by the capacitorslabelled C, which couple the noise to ground. These capacitors also attenuate highfrequency transverse noise present on the transactor secondaries. Zener diodes,labelled D on the diagram, limit the transactor output voltages, following heavysurges of current flowing in the transmission line, to a level which is safe for theelectronic circuits in the module.

The output signals from the three phase current transactors are attenuated by DACs,under the control of the main microcontroller, to produce the relay base setting KZPh(same for phases A,B and C). Similarly the output from the neutral transactor isattenuated by a DAC, again under the control of the main microcontroller, toproduce the relay base setting KZN.

Each of the attenuated signals is passed through a calibrated low pass filter whichhas a cut-off frequency of 300Hz. Each output is then passed to a second orderbandpass filter with centre frequency equal to the nominal supply frequency and Qvalue of 0.5. The output from the low pass filter is normally used but 10ms after thevoltage bandpass filters are switched in the current bandpass filters are also switchedin.

The filters reduce the harmonic and travelling wave distortion in the current signals. The resulting signals, LDIA, LDIB and LDIC are used by the level detectors. Thesesignals are also phase shifted by programmable all pass filters which gives thenecessary phase shift to form the replica impedance signals IAZPH, IBZPH, ICZPHand -INZN. The phase shifts produced are determined by the setting THETA Ph &

THETA N.

The respective output signals are:

IAZPH = (I * 0.3348)/(In * KZPh) V /(THETA Ph - 10)° (50 Hz)IAZPH = (I * 0.3325)/(In * KZPh) V /(THETA Ph - 12)° (60 Hz)

-INZN = (I * 0.3348)/(In * KZN) V /-(THETA N - 10)° (50 Hz)

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-INZN = (I * 0.3325)/(In * KZN) V /-(THETA N - 12)° (60 Hz)

Note: Phases B and C output signals are derived similarly.

6.7.4 Optional current circuits

Relay type LFZP111, which has quadrilateral characteristics, and relays with theoptional DEF or Fault Locator, require additional circuits. Signals which are 90° inadvance of the primary current, i.e. equivalent to a characteristic angle of 90°, arerequired. The output signal from each transactor is passed through a calibrated lowpass filter to produce signals labelled -IAX, -IBX, -ICX and INX.

The respective output signals are:-

-IAX = (I * 0.2678)/In V /(-90 - 10)° (50 Hz models)-IAX = (I * 0.2660)/In V /(-90 - 12)° (60 Hz models)

INX = (I * 0.2678)/In V /(90 - 10)° (50 Hz models)INX = (I * 0.2660)/In V /(90 - 12)° (60 Hz models)


For relays with DEF and/or Fault Locator a fifth transactor is fitted in the module. Theoutput of this transactor is fed through a circuit similar to the INX circuit to produce asignal labelled IPX.

In relay type LFZP111 the quadrilateral characteristic requires signals in phase with

the primary current. The -IAX, -IBX and -ICX signals are passed through a bandpassfilter which is similar to those previously described. The signals are then phaseretarded to bring them back in phase with the input currents i.e. signals -IAR, -IBRand -ICR. These signals are then summed to provide INR.

The respective output signals are:-

-IAR = (I * 0.3273)/In V /(-180 - 13)° (50 Hz models)-IAR = (I * 0.3250)/In V /(-180 - 15)° (60 Hz models)

INR = (IAR + IBR + ICR)


6.7.5 Input module calibration

The calibration of the boards in the input module is related to thespecific current and voltage transformers in that module. Therefore,under no circumstances should the boards be replaced with boards fromanother module without the module being recalibrated.

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KZN magDAC to set

DAC to setKZPH mag

I5

I4

I3

4 Ohm

Setting

4 OhmSetting

Low Pass

Low Pass

Filter

Filter

Setting

4 Ohm

Filter

Low Pass

Filter

Low Pass

Low PassFilter

logic

RD / WR

decoding

Address &

DAC to set

KZPH mag

KZPH mag

DAC to set

I2

Latch

I1

RD WRAd0 - Ad7

D0 - D7

4 Ohm

Setting

4 Ohm

Setting

Low Pass

Low Pass

Filter

Filter

Low Pass

Filter

Low Pass

Filter

THETA PHAngle Set

Switched

Bandpass

Filter

Switched

Bandpass

Filter

IPX

INX

-IN

LDIC

-ICX

ICZPH

THETA PH

Angle Set

THETA PH

Angle SetFilter

Switched

Bandpass

Filter

Latch

Switched

Bandpass

IBZPH

LDIB

-IBX

LDIA

-IAX

IAZPH

Figure 6-13 Input Board 1 ZJ134

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E3 Low Pass Amplitude

-ICX

-IBX

-IAX

Filter

Bandpass

Filter

Filter

Bandpass

Filter

Bandpass

Hysteresis

93 DEG LAG

93 DEG LAG

93 DEG LAG

Bandpass

Filter

logic

RD / WRdecoding

Address &

E2

E1

Low Pass

Filter

Low PassFilter

-IN

RD WR

Ad0 - Ad7

D0 - D7

Amplitude

Hysteresis

Hysteresis

Amplitude

Bandpass

Switched

Filter

Switched

Bandpass

Filter

Switched

VC

INR

-ICR

-IBR

-IAR

Latch

Angle SetTHETA N

VB

VA

-INZN

Figure 6-14 Input Board 2 ZJ135

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Figure 6-15 Voltage Input Circuits

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WAVEFORMS REPRESENT FAULT IN ZONE 1 CLOSE TO BOUNDARY

ZERO CROSSINGS RESTORED

COMPARATOR CAN OPERATE

TO ALL COMPARATORS

BANDPASS FILTER SWITCHED IN

NO ZERO CROSSINGS

COMPARATOR CANNOT OPERATE

30-35.5ms

INHIBIT PULSE

OF OPERATION WITH A LARGE OFFSET IN VOLTAGE

V-IZ

V-IZ

SENT

Figure 6-16 Action of switched bandpass filter

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Figure 6-17 Current input circuits

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6.8 Level detector board ZJ0136

6.8.1 Introduction

Optimho requires various voltage and current level detectors for its operation. These

level detectors are located on this PCB, a block diagram is shown in Figure 6-18. Twelve level detectors are required in the standard relay with an additional three if the DEF option is fitted.

The main microcontroller communicates with the PCB via the address and data bus.It reads the status of the level detectors, controls the settings for the DEF leveldetectors when fitted and sends resets when required.


The principle of operation of a level detector is described in Section 4.3. The

hardware consists of an analogue comparison circuit where the input signal iscompared with positive and negative reference levels producing a logic signal and a80C51 masked programmed microprocessor running an algorithm. The referencelevels were chosen so that the pick up level is 70% of Vn or 2.932V, the requiredlevel for the voltage level detectors. Other lower pick up levels are obtained byamplifying the input signal.

As part of the continuous monitoring the negative reference is monitored and analarm given if it is not within the required tolerance. Both the 80C51s havewatchdog circuitry to monitor the software. A local reset is given should a failureoccur and an alarm is also given.

To prevent chatter each level detector has approximately 15% hysteresis. This isachieved by reducing the reference on individual level detectors when they operate.

The table below lists each level detector with its corresponding T1 and T2 timersettings and its pick up level in terms of percent of rating and voltage level on thePCB.

Table 6-4 Level Detectors

IC6 NAME T1 (cycles) T2 (cycles) PICK UP% OF RATING

PICK UPVOLTS

D0 LDOVA 0.275 0.275 70% 2.932VD1 LDOVB 0.275 0.275 70% 2.932VD2 LDOVC 0.275 0.275 70% 2.932VD3 LDLSIO * 0.275 0.275 5% 13.39mVD4 LDVO 0.15 1.1 45% 1.8945VD5 LDLSI2 * 0.275 0.275 3.5% 9.37mVD6 LDHSI0 * 0.275 0.275 5% 13.39mV

* only if DEF option fitted.

Table 6-4 level detectors (cont.)

IC7 NAME T1 (cycles) T2 (cycles) PICK UP% OF RATING

PICK UPVOLTS

D0 LDLSA 0.275 0.275 5% 16.74mV

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D1 LDLSB 0.275 0.275 5% 16.74mVD2 LDLSC 0.275 0.275 5% 16.74mVD3 LDHSA 0.275 0.275 7.5% 25.11mVD4 LDHSB 0.275 0.275 7.5% 25.11mVD5 LDHSC 0.275 0.275 7.5% 25.11mVD6 LDLSN 0.15 1.1 5% 16.74mV

D7 LDHSN 0.15 1.1 16% 51.36mV

6.8.3 Voltage level detectors

The voltage level detectors LDOVA, LDOVB, LDOVC and the zero sequence voltagelevel detector LDV0 all have a fixed pick up level as given in the table.

6.8.4 Phase current level detectors

The three low set LDLSA, LDLSB and LDLSC and the three high set LDHSA, LDHSBand LDHSC phase current level detectors have pick up levels which are dependenton the KZPh settings. The values given in the table refer to a KZPh setting of 1. Theactual setting are as follows:

Low set = 0.05 * In / KZPh AHigh set = 0.075 * In / KZPh A

6.8.5 Neutral current level detectors

The low set neutral LDLSN and the high set neutral LDHSN are slightly different tothe other level detectors in that the reference level is not fixed. This is described inSection 4.3.4. The reference is formed by the largest instantaneous value of the threeprecision rectified phase to phase currents. The signal, smoothed by a resistorcapacitor network and limited by a zener diode is buffered and split into two signalsfor the high set and low set level detectors. In each case the negative reference isobtained by inverting the positive.

The base pick up level is dependent on the KZPh setting in the same way as thephase current level detectors. This is achieved by summing the three phase currentsto give the neutral current. This gives the pick up levels as given in the table at

KZPh = 1.0.

6.8.6 DEF level detectors (If DEF fitted)

The three level detectors required by the DEF feature LDLSI0, LDHSI0 and LDLSI2have adjustable pick up levels. The actual pick up level is determined by settings onthe menu and implemented by DACs controlled via the main microcontroller. Thepick up levels in the table refer to maximum setting on the DACs i.e. maximumsensitivity.

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-ve reference

level monitor

+ & - voltage

Reference level

logic

RD / WR

decoding

Address &

To set

Level

Pickup

Levels

Detector

DAC's33I0

3I2B

Circuit

Latch

VA

VB

VC

RD WR

Ad0 - Ad7

D0 - D7

RELAY FAIL

Amplitude

Comparators

shifting

circuits

& level

+ve

-ve

G

Reset

Control

Circuits

1

LDOVC

in 80C51

DETECTORS

Watchdog

Monitor &

WD

LEVEL

LDLSI0

LDV0

LDLSI2

LDHSI0

R

LDOVA

LDOVB

Level

1

Detector

output

Latch

D7

D0

Variable Reference

Ph-Ph currents &

Full Wave Rectifying

G

G

Level formed by

Peak smoothing

Comparators

shifting

circuits

Amplitude

& level

G

G

G

G

G

G

LDIB

LDIC

LDIA

Comparators

shifting

circuits

Amplitude

& level

in 80C51

LDLSB

DETECTORS

LEVEL

LDHSN

LDLSC

LDHSA

LDHSB

LDHSC

LDLSN

D7

Level

Detector

output

Latch

WD

LDLSA

R

reset

Latch

D0

Reset

Figure 6-18 Level detectors ZJ136

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6.9 Zone 1 / Zone 2 mho comparator board (ZJ0130)

6.9.1 Introduction

See Figure (6-19), Figure (6-20)

This board provides the reach settings, polarising signals and comparators for Zone1, Zone 1X, Zone 1Y and Zone 2 shaped mho phase and ground fault protection.

The board is power system frequency dependent and 50 or 60Hz versions areavailable.

6.9.2 Operation

Zone reach settings

The voltage vectors from the analogue bus (see Section 6.7) are attenuated by the12 bit Digital to Analogue converters, and buffered to provide the required zonereach multiplication. These attenuated sine wave voltage signals are then mixed withthe IZ base setting vectors from the analogue bus, squared up and level shifted togenerate the V-IZ vectors. These form the À input to the main comparatorprocessor. The sine wave IZ vectors are also squared up to be used in the directionalline inhibits and memory sensitivity.

The V-IZ vectors for Zone 1/1X/1Y and Zone 2 Quadrilateral forward reactancereach are also supplied, via the backplane bus, to the Quadrilateral ground faultcomparator board (ZJ0132). The quadrilateral Zone 1 guard zone requires a

forward setting which is ten times that of the Zone 1 ground fault setting (see Section4.2.6). This is obtained by further attenuating the Zone 1 voltages, after the Zone1/1X/1Y attenuation, by a factor of ten, mixing these with the appropriate IZ signalsand squaring to produce the (V-IZ)GZ1 square waves.

For underground cable protection the phase and ground reaches are halved. This isaccomplished by altering the mix ratio of the voltage vector with the IZ base settingvector, to effectively double the voltage vector and hence halve the reach.

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Polarising circuits

The polarising signals required for the shaped mho characteristics (see Section 4.2)form the `B input to the main comparator. They consist of mixing the three

phase-neutral voltages and the memory signals, squaring and digitally phaseshifting. The voltage memory signals VMEM A, VMEM B, VMEM C are producedwithin the inhibit/voltage memory processor using VMEM IN [VB (bandpassed)] asthe phase-neutral reference vector for the voltage memory. This permanentlybandpassed filtered voltage is used to prevent high frequency interference signalscorrupting the voltage memory. When the memory is not available it is replaced witha small percentage of -IZ signal. This provides a restraining influence in thepolarising for close up three phase faults after the memory has expired. This preventsoperation of Zone 1 and Zone 2 main comparator for close up 3 phase reversefaults.

The polarising signals are also used in forming the directional line inhibits for Zone 1and Zone 2 and are provided for the reverse Zone 3 shaped mho, and thequadrilateral directional line.

Comparators

The main comparator treats the input square waves A` and `B as logic variableswhich can each have a high or low logic state at any time (see Section 4.1). Basicallyif signal À lags `B and no directional or external pole dead inhibits are presentthe comparator will issue a trip (high logic ) to the appropriate output data latch.

The main comparators for Zone 1 and Zone 2 are implemented in 80C51 microcontrollers. One 80C51 is used for Zone 1/1X/1Y phase-neutral and phase-phasefaults and one for Zone 2 phase-neutral and phase-phase faults. Each maincomparator has directional inhibit inputs which when active force it to restrain. Theinhibit comparator is implemented in a 80C51 microcontroller (clocked at 12MHz),and provides the directional inhibits operating on Zone 1 and Zone 2. The maincomparator clocks are 10MHz for 50Hz power system frequency and 12MHz for60Hz. This clock is divided down by a factor of 800 and used for digital phaseshifting in the polarising circuits to provide the required phase shifts appropriate tothe nominal system frequency.

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External controls

External controls from the main microcontroller board are written to the input data

latch, these include:

1. memory run-out control.2. power-up resets.3. comparator resets to be OR-ed with watch-dog resets.4. main comparator trip count control.

Monitoring

All comparators and polarising clock are monitored by watch-dog circuits. In the

event of failure an alarm will be read from the appropriate output data latch by themain microcontroller board. The technique used will only allow a trip from the outputdata latch if it is followed by a successful bus check (see Section 6.1). A watch-dogfailure may indicate a failure of the micro controllers, clock circuitry, addressdecoding logic or output latch.

Data transfer

Digital inputs to and from the board are controlled by address decoding and datalatches. When the appropriate address is placed on the address bus and the readRD or write WR signal is activated then the information will be written into therequired data latch or read from the required data latch.

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Figure 6-19 Zone 1 / Zone 2 shaped mho ZJ0130

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Vpol A Z1

B

AIAZph + INZn

Inh A

Z1 CA Directional Inh

Z1 BC Directional Inh

Z1 AB Directional Inh

1

Z1 C Directional Inh

Z1 B Directional Inh

Z1 A Directional Inh

IBZph + INZn

Vpol C Z1

Inh B

Vpol B Z1

B

A

1

Vmem-run Control

Vmem-in

CK C

D

Q

Synchronous Polarising

ICAZph

Vpol CA Z1

Vpol BC Z1

IBCZph

B

A

B

A

ICZph + INZn

Vpol AB Z1

IABZph

Inh C

B

A

B

A

1

1

1

1

Vmem B

Vmem C

Vmem A

Watchdog

Figure 6-20 Directional Inhibits and Voltage Memory Processor ZJ0130

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6.10 Zone 3 / Zone 6 Offset Lenticular Comparator Board (ZJ0131)

6.10.1 Introduction

See Figure 6-21 See Figure 6-22

(Not used on LFZP114)

This board provides the forward and reverse reach settings, polarising signals andlenticular aspect ratio control for the offset mho/lenticular characteristic (see Fig.4-17). For the selectable reverse shaped mho the cross polarising vectors are obtainedfrom the Zone 1 / Zone 2 board, ZJ0130, via the backplane bus. The board ispower system frequency dependent and 50 or 60Hz versions are available.

6.10.2 Operation

Zone reach settings

The forward Zone 3 reach is obtained by attenuating the voltage vectors with the 12bit DACs (digital to analogue conversion) and buffering to provide the required zonereach multiplication. These attenuated sinewave voltage signals are then mixed withthe IZ base setting vectors from the analogue bus, squared up and level shifted togenerate the (V-IZ) vectors.

The reverse Zone 3 reach is similarly obtained, the fractional settings being obtainedby an amplifier on the voltage signals. The (V+IZ) vectors are obtained by mixing thevoltage signals with the IZ vectors, squaring and level shifting. The (V+IZ) and (V-IZ)signals form the À inputs to the main comparator processor and inhibit processorrespectively.

For underground cable protection the phase and ground reaches are halved. This isaccomplished by altering the mix ratio of the voltage vector with the IZ base settingvector, to effectively double the voltage vector and hence halve the reach.

The Power Swing Blocking zone (Zone 6) operates only on the A-B phase-phaseelement. The forward and reverse reaches are set in a similar manner to the Zone 3,but using the AB phase-phase voltage and IZ quantities to obtain the Zone 6 (V-IZ)AB and (V+IZ)AB vectors. Zone 6 has the same range of forward and reversereach settings as Zone 3.

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Polarising circuits

The polarising signals required to produce the offset lenticular are described asfollows. The (V-IZ) and (V+IZ) vectors are phase shifted by the appropriate angles

using digital shift registers. Digital multiplexers are then used to select theappropriate signals for the a/b aspect ratio selected. The resulting vectors (V-IZ)/-øo

and (V+IZ)/-øo form the `B inputs to the main comparator and inhibit comparator.

The partially cross polarised vectors to produce the reverse Zone 3 shaped mho areobtained from the Zone 1 / Zone 2 board ZJ0130, and when selected form the `Bìnput to the main comparator.

Comparators

The main comparator treats the input square waves A` and `B as logic variableswhich can each have a high or low logic state at any time, (see section 4.1). Basicallyif À lags `B and no inhibits are present the comparator will issue a trip (logichigh) to the appropriate output data latch.

The inhibit for the reverse shaped mho is the external pole dead signal.

The lenticular characteristic is produced by the intersection of two circles generatedby the main and inhibit comparators. The inhibit characteristic together with the poledead inputs now form the inhibit signal to the main comparator.

The main comparators for Zone 3 phase-phase and phase-ground, and Zone 6phase-phase faults are implemented in a 80C51 microcontroller. The inhibitcomparator is implemented in a 80C51 microcontroller. The main comparator clockis 10MHz for a 50Hz power system frequency and 12MHz for 60Hz, the clock for thedigital phase shift registers is divided down from this to give the required phase shiftsappropriate to the nominal frequency. The inhibit comparator clock is 12MHz.

External controls

External controls from the main processor board are written to the input data latch,these include;

1. main and inhibit comparator resets to be OR-edwith on board watch-dog resets.

2. power-up resets.3. Zone 3 / Zone 6 aspect ratio control.4. main comparator trip count control.

Monitoring

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All comparators and aspect shift registers are monitored by watch-dog circuits sothat in the event of failure an alarm will be read from the appropriate output datalatch by the main processor board. The technique used will only allow a trip from theoutput data latch if it is followed by a successful bus check (see Section 6.1). Awatch-dog failure may indicate a failure of the microcontrollers, clock circuitry,

address decoding logic or output latch.

Data transfer

Digital inputs to and outputs from the board are controlled by address decodinglogic and data latches. When the appropriate address is placed on the address busand the read RD or write WR signal is activated then the information will be writteninto the required data latch, or read from the required data latch.

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Figure 6-21 Zone 3/ Zone 6 Offset Mho / Lenticular Selectable Zone 3 Reverse Shaped

Mho ZJ0131

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a/b Code bit Z6

a/b Code bit Z6

a/b Code bit Z3

a/b Code bit Z3

(V-IZ)A Z3

(V+IZ`)A Z3

Inh AZ3 A Inh

B

A

1&

CK

(V+IZ`)CA Z3

(V+IZ`)BC Z3

(V-IZ)CA Z3

B

B

A

CQ

D

&

&

(V-IZ)BC Z3

(V+IZ`)AB Z3

(V+IZ`)AB Z6

(V-IZ)AB Z3

A

B

B

A

(V-IZ)C Z3

Inh C

(V-IZ)AB Z6

(V+IZ`)C Z3

Inh B(V+IZ`)B Z3

(V-IZ)B Z3

A

B

A

B

A

&

&

&

&

Watchdog

Z3 CA Inh

1

Z3 BC Inh

1

Z3 AB Inh

1

Z6 AB Inh

1

Z3 C Inh

1

Z3 B Inh

1

=1

=1

Figure 6-22 Inhibit comparator controller ZJ0131

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6.11 Zone 1 / Zone 2 / Zone 3 Quadrilateral Comparator Board (ZJ0132)

6.11.1 Introduction

See Figure 6-23, Figure 6-24 and Figure 6-25

(LFZP111 only) This board sets the resistive reach for Zone 1, Zone 2 and Zone 3 and combines withvectors inputted from the Zone 1 / Zone 2 (ZJ0130) and Zone 3 (ZJ0131) boards,which set the forward and reverse "reactance" line reach, to provide the overallquadrilateral characteristic for Zone 1, Zone 2, Zone 3 offset, and Zone 3 reverse(see Figure4-18 and 4-21). The board is power system frequency dependent and 50or 60Hz versions are available.

6.11.2 Operation

Producing the quadrilateral characteristics

Zone 1 characteristic

The main comparator of Zone 1 produces the top or "reactance" line of thequadrilateral from:

À input = ( V-IZ ) ground fault vectors inputted from theZJ0130 board,

`B input = INR where INR = (IAR+IBR+ICR) / -3°

The polarising vector INR is obtained by summing the three calibrated -IAR, -IBR,-ICR signals provided from the input module (see Section 6.7). The top line moveswith active power-flow to avoid the overreach or underreach problems associatedwith phase-current-polarised reactance characteristics.

The other three sides of the Zone 1 quadrilateral are formed by two inhibitcomparators arranged to inhibit the main comparator. The main comparator canonly count up when the two inhibit comparators agree that the impedance is withinthe operating zone. The signals used are as follows:

"Directional" line

À` = Vpol

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`B` = IZRight-hand "resistance" line

À` = IZ`B` = V-IR

Left-hand "resistance" line

À` = V+IR`B` = IZ

Throughout, V is the faulty phase voltage, the voltage vectors from the analogue busare attenuated by the 12 bit Digital to Analogue converters, and buffered to providethe required Right-hand and Left-hand resistive reach.

Vpol is the ground fault cross polarising vector inputted from the ZJ0130 board and

IZ is the residually compensated vector (IPHZPH+INZn) provided from the inputmodule (see Section 6.7).

The IR signal for the resistance lines is derived from the phase current only, theabsence of residual compensation permitting good phase selection forsingle-pole-tripping purposes.

Zone 1 Guard Zone

The three Zone 1 ground fault comparators each have a corresponding "guard" zone(see Section 4.2.6), whose characteristic shape comprises the same side anddirectional lines as Zone 1, the signals used are as follows:-

À = Z1 guard zone (V-IZ)`B` = IZ∠-10°

The top line of the "guard" zone has ten times the reach of Zone 1. The Zone 1Guard zone (V-IZ) vectors are set and inputted from the ZJ0130 board, also due tothe different polarisation (IPhR+INR), under two-phase-to-ground fault conditions thereactance lines of the Zone 1 and corresponding "guard" zone tilt with respect toeach other. This action is used to prevent operation of the ground fault comparatorsfor two-phase-to-ground faults(see Section 4.2.6).

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Zone 2 Characteristic

The main comparator of Zone 2 produces the top or "reactance" line of thequadrilateral from the following vectors:-

À input = ( V-IZ ) ground fault vectors inputted from the ZJ0130board

`B input = IPhR+INR

To avoid having to provide guard zones for Zone 2 and 3, the polarising signal(IPhR+INR) for these two zones provides a compromise between single phase andtwo-phase to ground fault requirements.

The other three sides of the Zone 2 quadrilateral are formed in a similar manner toZone 1.

Zone 3 Characteristic

Zone 3 Forward and reverse offset

The forward and reverse offset quadrilateral characteristics of Zone 3 are producedin a similar way to that of Zones 1 and Zone 2. The main comparator producing theforward top or "reactance" line from:-

À input = ( V-IZ )`B input = IPhR+INR

and the reverse offset "reactance" line from:-

À` input = IPhR+INR`B input = ( V+IZ )

The other three sides of the Zone 3 forward and reverse offset are formed in asimilar manner to Zone 1 acting as the inhibit to the main comparator.

Zone 3 Reverse

The quadrilateral Zone 3 reverse is selected from the menu and will then onlymonitor the Zone 3 reverse quad, output from the main comparator.

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Comparators

The main comparators treat the input square waves A` and `B as logic variableswhich can each have a high or low logic state at any time (see Section 4.1). Basicallyif signal À lags `B and no sideline/directional inhibit is present then the

comparator will issue a trip ( high logic ) to the appropriate output data latch.

The main comparators for Zone 1, Zone 2 and Zone 3 are implemented in 80C51micro controllers which have inhibit inputs that are composite signals from thedirectional and sideline vectors, which when active force it to restrain. The inhibitcomparators are also implemented in 80C51 micro controllers. The maincomparator clocks are 10MHz for 50Hz power system frequency and 12MHz for60Hz. The inhibit comparator clock is 12MHz.

External Controls

External controls from the main processor board are written to the input data latch,these include:

1. main and inhibit comparator resets to be OR-ed with onboard watchdog resets

2. power-up resets3. pole dead inhibit4. comparator trip count control.

Monitoring

The main and inhibit comparators are monitored by watchdog circuits. In the eventof failure an alarm will be read from the appropriate output data latch by the mainprocessor board. The technique used will only allow a trip from the output data latchif it is followed by a successful bus check. A watch-dog failure may indicate a failureof the micro controllers, clock circuitry, address decoding logic or output latch.

Data transfer

Digital inputs to and outputs from the board are controlled by address decodinglogic and data latches. When the appropriate address is placed on the address busand the read RD or write WR signal is activated then the required information will bewritten into, or read from, the required data latch.

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Figure 6-23 Zone 1 / Zone 2 / Zone 3 quadrilateral ZJ0132

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B

AVpol A

&

&

&

Directional A

&

11

1

B

A

CK

ICR+INR

(V-IZ) C GZ1

(V-IZ) A GZ1

(V-IZ) B GZ1

IBR+INR

IAR+INRB

A

B

A

C

DQ

1=

Side C (fwd)

Side C (rev)

Side B (fwd)

Side B (rev)

Fwd / Rev

Side A (fwd)

Side A (rev)

ICZph+INZn

Vpol C

IAZph+INZn

IBZph+INZn

Vpol B

B

A

B

A

&

&

&

&

1

1

&

1

Watchdog

Z1C Quad Inh

Z1B Quad Inh

Z1A Quad Inh

Z2C Inh

Z2B Inh

Z2A Inh

Directional C

Directional B

Figure 6-24 Directional inhibit and Z1 guard zone logic ZJ0132

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B

A

B

A

IAZph+INZn

(V-IR)A

(V+IR)A

Inh A

1

1

1

1

1

1

11

Side A (fwd)

Side A (rev)

B

A 1

C

DQCK

Directional C

(V-IR)C

1B

A

(V+IR)C

ICZph+INZn

Directional B

Inh C

B

A

(V+IR)B

(V-IR)B

IBZph+INZn

Directional A

Inh B

B

A

1

1

Watchdog

Side C (fwd)

Side C (rev)

Side B (fwd)

Side B (rev)

Figure 6-25 Sidelines & pole dead inhibits forward & reverse inhibits ZJ0132

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6.12 Directional overcurrent ground fault protection board ZJ0139

6.12.1 Introduction

The Directional Earth Fault (DEF) feature, (optional on LFZP111, 112 and 114) isused to cover high resistance ground faults. See Section 4.4 for a description. Theboard contains circuits to produce the signals for the four types of polarisingrequired, the comparators for forward and reverse looking directional elements, anovercurrent unit and a mag-inrush circuit. A block diagram of the board is shown inFigure 6-26.

The main microcontroller communicates with the PCB via the address and data bus.It reads the status of the comparators, controls the settings for the DEF, the switchedfilters etc. and sends resets when required.

6.12.2 Comparators

The principle of operation of the comparator is described in Section 4.1. Thedirectional elements employ two sequence comparators, one forward looking, theother reverse looking, both contained in an 80C51 microcontroller. The A and Binput signals are swapped over for the reverse looking element. The directionalelement inhibit is controlled by the main microcontroller. The comparator has awatch dog circuit to monitor it as described in Section 6.1.5.

6.12.3 Comparator input signals

There are four types of polarising, selected via the menu, allowing a choice of zerosequence voltage, zero sequence current, dual zero sequence current and voltageand negative sequence voltage.

Table 6-5 DEF Forward looking comparator input signals

POLARISING A INPUT B INPUT

ZERO SEQUENCEVOLTAGE

3VO /-THETA G° 3IO /-90°

ZERO SEQUENCECURRENT

IP 3IO /-90°

ZERO SEQ. VOLTAGE &CURRENT

3VO /-THETA G° + kIP 3IO /-90°

NEGATIVE SEQUENCEVOLTAGE

3V2B / -THETA G° 3I2B /-90°

The appropriate signals are connected to the comparator via analogue solid stateswitches controlled by the main microcontroller.

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The zero sequence voltage (3V0) is derived internally by summing the three phase -neutral voltages VA, VB and VC. The resulting signal is phase lagged by the DEFcharacteristic angle THETA G and converted to a square wave (3VO /-THETA G) toproduce one input to the comparator.

The signal 3I0 / -90° is derived from INX. This signal is filtered by a second orderbandpass filter with centre frequencies equal to the nominal supply frequency and Qvalues of 0.5. This filter reduces the harmonic and travelling wave distortion in thecurrent signals. The unfiltered signal is normally used being switched to the filteredsignal under the control of the main microcontroller (see Section 5.16). The signal,3I0, is converted to a square wave suitable for the comparator input.

The signal IPX derived from a current transactor is filtered by a second orderbandpass filter with centre frequencies equal to the nominal supply frequency and Qvalues of 0.5. This filter reduces the harmonic and travelling wave distortion in thecurrent signals. The signal is then phase lagged 90° and converted to a square wave

to produce an appropriate signal (IP) for the comparator.

Zero sequence voltage and current polarising is obtained by mixing the signals 3VO/-THETA G and IP. The ratio is chosen such that the resultant signal level caused byrated 3V0 is the same as that caused by rated IP. The factor k in Table 6-5 = 16.

Negative sequence polarising requires negative sequence voltage for the polarisingquantity and negative sequence current for the operate quantity.

The negative sequence voltage signal is produced from signals VA, VB and VCaccording to the following formula:

3V2B = -(VAB + VCA /60°)

The resulting signal is phase lagged by the DEF characteristic angle THETA G andconverted to a square wave (3V2B /-THETA G) to produce one input to thecomparator.

The negative sequence current signal is produced from signals -IAX, -IBX and -ICXaccording to the following formula:

3I2B = -(IAB + ICA /60°)

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The resulting signal is filtered by a second order bandpass filter with centrefrequencies equal to the nominal supply frequency and Q values of 0.5. This filterreduce the harmonic and travelling wave distortion in the current signals. Theunfiltered signal is normally used being switched to the filtered signal under the

control of the main microcontroller (see Section 5.16). The signal, 3I2B, is convertedto a square wave suitable for the comparator input.

Negative sequence voltage and currents are derived using filters to mix and phaseshift the input signals. Most filters are prone to unacceptable errors as the frequencydrifts away from the nominal thus limiting the sensitivity. These errors are causedbecause the filter produces a fixed time shift (CR time constant) rather than a fixedphase shift, in this case +60°, as the input frequency varies. These errors areovercome by a filter which has 8 selectable centre frequencies and which isautomatically adjusted to the appropriate one thus maintaining errors below therequired sensitivity level. See Figure 4-31. The adjustment is made by an 80C51

microcontroller measuring the system frequency and controlling the filter. Themicrocontroller has a watch-dog circuit to monitor it as described in Section 6.1.5.

6.12.4 Directional overcurrent backup protection

The overcurrent backup protection consists of a 6805 microcontroller, similar to thatused in the MCGG range of overcurrent relays, a multiplying digital to analogueconverter (DAC), a rectifying circuit and some control latches.

The permanently bandpass filtered INX signal is attenuated via a DAC, rectified andfed to a 6805 microcontroller which runs the overcurrent algorithm. The choice of definite time, inverse IEC or American curves, selected via the menu, are passed tothe 6805 by the main microcontroller. The DAC setting, again controlled via themain microcontroller is used to directionalise the over current unit and to control thesensitivity. The INX signal is inhibited (via maximum attenuation) until the software inthe main microcontroller, using the DEF forward looking element identifies the faultas forward and changes the attenuation to give the appropriate setting. Details of the controlling software are given in Section 4.4.

6.12.5 Magnetising inrush current detector

A magnetising current inrush detector is used to prevent maloperation whenenergising multiple in-zone transformers. The circuit uses the principle of detectingzeros in the current lasting for a quarter cycle or more. See Section 4.4.7 for details.

Two detectors are used, one working on signal IAB the other on IAC. Each signal isrectified and compared with a signal representative of 1/3 of its peak. The resulting2 signals are analysed via an algorithm running in the 80C51. The 80C51 also doesthe frequency tracking. The algorithm detects the gaps in the mag-inrush currentwaveform and passes the information to the main microcontroller.

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Figure 6-26 DEF ZJ0139

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6.13 Fault locator module GJ0277

6.13.1 Introduction

The Optimho distance relay fault locator is optional on relay types LFZP111, 112,

113 (but see section 4.5.1) and 114. The fault locator module consists of a printedcircuit board ZJ0165 and an attached electromagnetic screen. The board plugs intothe bus system of the relay. Data is exchanged between the main microcontroller inthe relay and the locator, and the locator also measures line voltages and currentsdigitally. The outputs to the main microcontroller include accurate fault locationmeasurements.

The fault locator board for the Optimho Distance Relay makes use of the 80C18616 bit microprocessor. The following features are incorporated on the board:-

a. 80C186 Processor

b. 8k or 32k 16 bit Non Volatile Memoryc. 32k,64k or 128k 16 bit Read Only Memoryd. 32k or 128k 16 bit Random Access Memorye. 8 Channel 12 Bit Data Acquisition Systemf. Watch-dog Timerg. 8 bit Parallel Communication to Protectionh. Mode Link Connectionsi. Test Serial I/O Port

j. Test 8 Bit Parallel Output Port

Refer to figure 6-27 which is a block diagram of the complete system.

6.13.2 80C186 Processor

The 80C186 processor is a 16 bit device constructed in CMOS. A high level of integration is incorporated in the IC so many functions are resident on-chip,reducing the chip count for such a versatile processing unit. Many of the on-chipfunctions including the timers, interrupts and memory management unit have beenused to produce a minimal hardware board which requires minimal system software.

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6.13.3 Memory

The memory is arranged in three blocks; static, read only and non-volatile. Since the80C186 has programmable memory select outputs, three of these are used solely todecode the addresses. The start address and size of these three blocks are set by

writing to memory locations in the 80C186 control block.

The following memory sizes are used on the fault locator:

Memory Type Size

Static RAM 32k wordsErasable

Programmable ROM 32 k wordsElectrically

Erasable PROM 8 k words

6.13.4 Data and address line buffering

The address lines must be latched because the 80C186 bus is multiplexed. Threeoctal D-Type flip flops are used with a common latching signal, ALE, provided by the80C186.

The data lines are buffered with bi-directional tri-state transceivers, controlled directlyby the microprocessor.

6.13.5 Eight channel 12 bit data acquisition system

This section describes the input filters, acquisition components and control circuit of the data acquisition system.

General discussion

A single sample/hold circuit and analogue to digital converter is fed with inputsignals from a multiplexer. Up to eight channels need to be sampled and convertedat a rate of 40 samples per cycle. This corresponds to a conversion rate of 19.2kHz

for a 60Hz device or 16kHz for a 50Hz device. The multiplexer, sample/hold andADC must convert at this rate. The system has been designed to sample at rates upto 25kHz which is about 52 samples per cycle at 60Hz and 62 samples per cycle at50Hz. If less than 8 channels are sampled, the conversion rate can be higher.

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In order to free the 80C186 processor from as much control of the sampling systemas possible, a circuit which handles the sampling of several channels automaticallyhas been designed. The system is started by a single pulse from a timer pin on the80C186. Successive channels are fed through the multiplexer, sampled and

converted. The 80C186 is interrupted after each conversion and reads the value. Thetimer pins on the 80C186 can be configured to pulse at a defined frequencyindefinitely, also interrupting the processor to inform it of the beginning of a sampleset.

Input filters

The input filters are two stage single pole types with a voltage 3db point at 320Hz.An operational amplifier is used as a buffer between the two stages.

Multiplexer

An 8 channel multiplexer is provided and this device has a low channel resistance. The output of this is fed into the high input impedance of the sample/hold circuit.

Thus each of the inputs are passed in turn to the A/D converter via the sample/holdcircuit for conversion to a digital level.

Sample/hold

The sample/hold circuit is a precision device which holds the instantaneous inputlevel for the duration of time which the following A/D converter requires to performits function.

Analogue to digital converter

The A/D converter which converts an input analogue signal to 12 bits of digital datain less than 25µs. The device is configured to output data to a 16 bit bus. Tri-statebuffers are used between the converter and the 80C186 data bus. The top bit of theADC output is inverted and fed to each of the top four bits of the 80C186 bus. Thisconverts the output into a 16 bit signed integer which is presented onto the data buswhen the device is read as a peripheral.

Control circuit

The control circuit sends signals to the multiplexer, sample/hold, A/D converter and80C186, making the software processing overhead on the 80C186 minimal. Thesystem's major component is a decade counter. Successive pins on the counterbecome active as it is clocked, and some of these pins control the sequence andtiming of the data acquisition components. Once every pin has pulsed, one channelhas been selected, sampled and converted. This counter is clocked from the outputof a programmable divider which is factory set to suit the system clock frequency.

6.13.6 Watch-dog timer and reset circuit

Power up reset

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The reset circuit ensures that the reset pin on the 80C186 is held low for a period of approximately 11ms after power is applied.

This ensures that the microprocessor does not attempt to execute its program until

the power supply rails on the board are fully established.

Watch-dog

The watch-dog circuit is formed by a dual monostable circuit. Once the firstmonostable is triggered by accessing it as a peripheral its output goes high for84ms. The output will continue to stay high if the monostable is re-triggered before84ms has expired. If, however, the monostable is not re-triggered, the output will golow, causing the second monostable to trigger. The second monostable pulses thereset pin low for 7ms. The relay fail line is pulled low when the watch-dog times out.

This line triggers the "Relay Inoperative Alarm".

6.13.7 Eight bit parallel communication to protection

Three 8 bit memory locations are provided between the 80C51 relay mainmicrocontroller and the fault locator 80C186 microprocessor. These areuni-directional buffers and form data,response and command bytes.

When the 80C51 writes to the command location, the 80C186 is interrupted so thatthe fault locator board can be made to respond quickly to power system faults.

6.13.8 Mode link connections

Three links control the mode of the board and are normally factory set. The linkscontrol frequency setting, relay rated current and test mode as follows:-

Pins Bit No Link On (Bit = 0) No Link (Bit = 1)

1,4 0 60 Hz 50 Hz

2,5 1 1A relay 5A relay

3,6 2 Test Mode Locator Mode

Note: The test mode is only used as a factory test feature and requires

specialised equipment.

6.13.9 Test serial I/O port

The test serial I/O port uses an 82C51 serial I/O controller. Also a D type flip flopand a TTL to RS232 level converter are used. This port is only used during factory testprocedures and no communication features are provided.

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Serial fault locator output information is available however from the relay serialoutput ports at the front and rear of the relay. These ports use the relays mainmicrocontroller to communicate with the fault locator.

6.13.10 Test eight bit parallel output port

An 8 bit output latch is provided on the board and this is used for factory testpurposes. The output pins of the latch are brought out onto a 10 way single in lineheader.

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Figure 6-27 Fault Locator ZJ0165

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6.14 Output relay board ZJ0140

Relay versions LFZP 11x have a total of 24 separate output contacts. All contactsare normally open except for the Relay Inoperative Alarm (RIA) contact which is

normally closed.

6.14.1 Mechanical arrangement

Three printed circuit boards (PCBs), each with eight auxiliary relays plus theirassociated drive circuits, are used to provide a total of 24 auxiliary relay circuits.Parts 001, 002 and 003 of a common PCB type ZJ0140 are used, these arelocated in slot position numbers 3, 4 and 2 respectively.

In order to minimise the effects of external electrical interference the three outputPCBs are mounted within a screened area of the relay case, separate from the relay

measuring circuits, as shown in Figure 2-1.

A special connector, mounted on the output PCB, enables the PCB to plug directlyinto the terminal block/s mounted at the back of the relay case. This arrangementprovides a compact design and eliminates hand wired connections with aconsequent improvement in reliability.

A standard 64 way ribbon cable connector mounted on the adjacent (input) side of the output PCB facilitates connection to the relay circuitry via a 64 way ribbon cableconnected to the front panel board.

6.14.2 Circuit operation description

Versions ZJ0140 001 & ZJ0140 003

Refer to Figure 6-28 for block diagram illustration of the above output PCBs.

When addressed by the main microcontroller, each auxiliary output relay, RL1 toRL8, is controlled by a data line D0 to D7 respectively, ie., data line D0 controlsRL1 and data line D7 controls RL8. Each output PCB has an address decoder circuitwhich monitors the external address bus and issues an output whenever it sees aunique eight bit address code.

Each output PCB has a unique address code allocated to it. Instructions issued fromthe main microcontroller to turn auxiliary relays ON or OFF are latched by alatching circuit which is controlled by the output from the address decoder and thewrite (WR) line from the main microcontroller. For example, in order to only turnON auxiliary relay RL2 on output board ZJ0140 003 the main microcontrollersends out (writes) the address code for this board (06) on the external address busand also writes 00000010 (binary) to the external data bus. To turn OFF allauxiliary relays on this board the data 00000000 is written to the same externaladdress (06).

Each auxiliary output relay is driven from a simple two stage npn/pnp transistorswitching circuit. The drive circuits for all auxiliary relays are identical. For all except

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the RIA circuit (version 002 only), a capacitor discharge assist is used on each drivecircuit to speed up the pick up time of the auxiliary relay. Since the nominal ratingof the auxiliary relay is approximately half (5V) the Vcc (12V) voltage applied to thedriving circuit, the auxiliary relay is initially energised, via the charged capacitor, atapproximately twice its nominal rating when the pnp transistor turns on. The

discharge from the capacitor provides additional amp turns which speeds up pickup of the auxiliary relay. A resistor in series with the pnp transistor drops about 7V,leaving 5V across the auxiliary relay.

Version ZJ0140 002

Refer to Figure 6-29 for block diagram illustration of the above output PCB.

This version is basically identical to versions 001 and 003 with some additionalcircuitry to control the Relay Inoperative Alarm (RIA) RL1.

Operation of RL2 to RL7 is as described above for versions 001 and 003.

No capacitor assist is required for the RIA auxiliary relay since very fast operatingspeed is not required, a 12V rated auxiliary relay is therefore used.

The Relay Inoperative Alarm contact is normally closed when the auxiliary relay isde-energised.

Under normal working conditions, when the relay is available for protectionoperation, the RIA auxiliary relay is energised and its output contact is open. TheRIA auxiliary relay also has a separate normally open contact which is connected tooperate the Relay Available LED on the front panel board.

Contact clear

This signal line is controlled by the main microcontroller. Its function is to preventoperation of any output auxiliary relay (except Relay Inoperative Alarm on version002) if certain error conditions are detected. Refer to Sections 6.1 and 6.2 for adescription of diagnostics and action taken. When pulled low, this control lineclears the latching circuit outputs and thereby turns OFF all (except RIA) auxiliaryrelays.

During dc power up, a capacitor/resistor circuit holds the latching circuit clear linelow. This resets the outputs from the latching circuit and thus prevents operation of

any output auxiliary relay whilst power up initialisation is in progress.

Relay fail and time delay circuit (Version 002 only)

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The Relay Inoperative Alarm circuit on version 002 is controlled by the D0 outputfrom the latching circuit and also the RELAY FAIL line. This line, which is normallyheld high when the relay is available for protection operation, is pulled low forvarious conditions as described in Section 6.1.

A time delay circuit delays de-energisation of the Relay Inoperative Alarm auxiliaryrelay by approximately 0.5s when the RELAY FAIL line is pulled low.

In the event of any transiently initiated watchdog reset signals issued locally to anyboard other than the main microcontroller board, the RELAY FAIL line is pulled low.If a local board reset is accomplished successfully within a 0.5s interval the RELAYFAIL line is taken high again and the reset event is not annunciated by closure of the Relay Inoperative Alarm contact.

Any persistent fault condition will be detected by the main microcontroller which willde-energise the RIA circuit by setting the D0 data output of the latch circuit, this will

cause the RIA contact to close and will extinguish the Relay Available LED.

6.14.3 Noise suppression

To minimise the effects of external electrical interference and interferencegenerated when switching inductive loads, special consideration has been given toscreening and PCB layout. The layout of the PCB ground plane, earthing, powerrails and auxiliary relays are particularly important.

Ground plane and earthing

A 0V ground plane, extending below the 8 auxiliary relays, and connected to the0V side of the auxiliary relay coil (OV(1), see Figures 6-28 & 6-29) is connected tocase earth via the extreme top and bottom terminals of the special PCB mountedterminal strip.

Each output auxiliary relay has two contacts but only one contact is used (except theRIA auxiliary relay which uses its other contact to operate the internal RelayAvailable LED). The unused contact from each auxiliary relay is connected to the0V(1) ground plane. All other remaining circuitry utilises 0V, which is connected tothe relay back plane via the 64 way ribbon cable. For a general description of grounding arrangements refer to Section 2.0.

Power rails

A separate 12V (Relay) power rail is provided to supply the output auxiliary relaysonly. Any noise induced onto this rail is shunted directly back to the relay powersupply unit.

Position of auxiliary relays

The output auxiliary relays are positioned as far away from the control and drivecircuits as is possible, this arrangement reduces the affects of radiated interference

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generated when switching inductive loads and attenuates interference produce byhigh frequency disturbances applied to auxiliary contacts.

6.14.4 Contact connections to terminal block

Auxiliary relay contacts are connected as shown in Figures 6-28 and 6-29. Noticethat one side of the contacts of RL1, RL2 and RL3 are commoned. Figure 6-30shows contact connections made from output boards to external terminal blocks.

The assignment of specific names and functions to each contact is dependant onthe contact configuration number menu option selected. Output contactconfigurations are detailed in Section 8.0.

6.14.5 Operating time and power dissipation

The average pick up time for a capacitor assisted auxiliary relay is 4ms. The average pick up time for the RIA auxiliary relay is 10ms. The average drop off time for a capacitor assisted auxiliary is 5ms.Power dissipation per output auxiliary relay when picked up (energised) = 240mW.

6.14.6 Output option

A commission option menu test facility is available to allow operation of all outputcontacts, refer to Section 3.5.5.


The status of all output contacts can be viewed using the monitor option test facilityin the commission tests section of the menu, refer to Section 3.5.4.

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Figure 6-28 Output relay board for ZJ0140 001 & ZJ0140 003

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Figure 6-29 Output relay board ZJ0140 002

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ZJ 0140 001ZJ 0140 002

RL1

33

31

RL1

SLOT 2

ZJ 0140 003

34

32

RL1

59

61

55

SLOT 4

RL8

RL7

53

51

49

47

SLOT 3

56

54

52

50

48

RL8

RL7

RL8

RL7

RL6

RL5

RL4

45

43

39

41

RL3

RL2

29

37

35

46

44

42

40

RL6

RL5

RL4

RL6

RL5

RL4

38

36

30

RL3

RL2

RL3

RL2

83

81

79

77

75

73

71

67

69

57

65

63

Figure 6-30 Output contact connections to terminal blocks

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Section 7. TECHNICAL DATA

7.1 Input ratings

AC voltage Vn: 100 to 120V rms phase-phase.

AC current In: 1A or 5A rms per phase.

Frequency fn: 50Hz or 60Hz.

Operative frequency 47 to 51Hz or 56.4 to 61.2Hz.range:

DC supply Vx1: For power supply, available in 3 versions.

V x 1 Operative Range Maximum Withstand

48/54V 37.5 to 60V 64.8V110/125V 87.5 to 137.5V 150V220/250V 175 to 275V 300V

There is negligible change of accuracy with change of voltage within the operativerange.

DC supply Vx2: For optical isolators, available in the same options as Vx1. For220/250V option the 110/125V version is used with anexternal resister box GJ0229 002.

7.2 Maximum overload ratings

AC voltage: 1.5Vn continuous withstand.2.5Vn withstand for 10s.

AC current: 2.4In continuous withstand.100In withstand for 1s (In = 1A).80In withstand for 1s (In = 5A).

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7.3 Burdens

AC voltage circuits: 0.1VA per phase at Vn.

AC current circuits: 0.08VA per phase (In = 1A).0.5VA per phase (In = 5A).

DC supply 1: 18W under healthy live line conditions at Vx1.28W maximum.

DC supply 2: 10mA per energised optically coupled isolator at Vx2.

7.4 Distance elements

7.4.1 Settings

Impedance:

Range of positive sequence settings referred to line VT and CT secondaries:

Zone 1, Zone 1X, Zone 1Y, Zone 2 and Zone 3 reach:

In = 1A range is 0.2 to 250 ohms (All versions except LFZP113)0.1 to 125 ohms (LFZP113)


Zone 3 reverse:



Reach setting method is by digitally controlled analogue attenuators. Attenuationfactors KZPh and KZN operate on current signals and are common to all zones.

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Attenuation factors KZ1, KZ1X, KZ1Y, KZ2, KZ3 and KZ3' operate on voltagesignals and are specific to Zone 1, Zone 1X, Zone 1Y, Zone 2, Zone 3 and Zone 3reverse respectively. The positive sequence reach for Zone 1 is given by:-

Zone 1 = KZ1.KZPh.5/In (All versions except LFZP113) = KZ1.KZPh.5/2.In (LFZP113)

Either KZPh or KZ1 is set to unity. To obtain the formula for other zones employed,replace KZ1 by the appropriate attenuation factor for the zone.Extra settings for ground fault distance:

Residual compensation factor:KZN

KZPh

ZLO ZL1

3ZL1

= −

Where ZL0 and ZL1 are the vector values of zero and positive sequence impedanceof the protected line.

Quadrilateral resistive reach settings: Right-hand reach = KR.5/InLeft-hand reach = KR.6/ In

Zone 3 lenticular aspect ratio:

The aspect ratio a/b of the lenticular elements is 1.0, 0.67 or 0.41 where b is thesum of the forward and reverse reach setting and a is the maximum width of theimpedance characteristic measured perpendicular to the characteristic angle.

Setting ranges:

SETTING MINIMUM MAXIMUM STEP

KZPh 0.04 1.0 0.001KZN 0.0 1.360 0.001KZ1 1.00 49.98 0.02KZ1X 1.00 49.98 0.02

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KZ1Y 1.00 49.98 0.02KZ2 1.00 49.98 0.02KZ3 1.00 49.98 0.02KZ3' 0.2 49.9 0.1KR 1 30 1

Z3 Lenticular a/b 1.00, 0.67, 0.41

Characteristic angle: THETA Ph = arg ZL1 to nearest availablesetting

Residual compensation THETA N = arg (ZL0 - ZL1) to nearestangle: available setting

Note: LFZP113 is not designed to be used with a ground fault

loop setting (2ZL1 + ZL0)/3 with an argument less than 30°°°°.

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Setting ranges:


THETA Ph 50° 85° 5° * THETA N 50° 85° 5° * THETA Ph 45° 80° 5° **

THETA N -45°, -35°, -25°, to 80° in steps of 5° **

* LFZP Versions 111, 112 & 114.** LFZP 113

7.4.2 Accuracy of distance elements

Reach: ±5% at 2In and 20°C.

Characteristic angle: ±2°.

Resetting ratio: 105%.

7.4.3 Current sensitivity

Determined by the low set current level detectors. The sensitivity varies inversely withthe base setting (KZPh) and is given by:

0.05 * In / KZPhA.

7.4.4 Timers

Timer ranges:


TZ1X 100ms 9980ms 20ms TZY1 100ms 9980ms 20ms

TZ2 100ms 9980ms 20ms TZ3 100ms 9980ms 20ms TP 0ms 98ms 2ms TD 0ms 98ms 2ms

TDW 0ms 98ms 2ms TPG 0ms 98ms 2ms TDG 0ms 98ms 2ms

Timer accuracy: ±1% of setting and ±3ms

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7.4.5 Polarising

Proportion and type of cross polarising for Zones 1 and 2 for partially cross

polarised mho and for Zones 1 and 2 directional lines.

Phase to Ground fault: )Phase to Phase to Ground fault: ) 16% square wave from healthyPhase to Phase fault: ) phases

3 Phase fault: 16% square wave from synchronous memory

Synchronous memory is effective for 16 cycles after fault incidence and is available12.5 cycles after energising the line.

7.4.6 Operate and reset times

Operate times: Typical relay operating times for Zone 1 are shown in Figures7-1 to 7-8 50Hz and Figures 7-9 to 7-16 60Hz.

Mho characteristic 50Hz minimum: 14mstypical: 18ms


Quad characteristic 50Hz minimum: 16mstypical: 23ms


Reset times: The trip contacts are sealed in for 60ms following the initialcontact closure. Thereafter, the maximum reset time is 35ms.

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G/F Mho Characteristic 50Hz SIR 1

Fault Position (% of setting)

O p e

r a t i n g T i m e ( m s )

0

5

10

15

20

25

30

0 10 20 30 40 50 60 70 80 90

min

max

Figure 7-1 Zone 1 typical operating times

G/F Quad Characteristic 50Hz SIR 1


O p e r a t i n g

T i m e ( m s )

0

5

1015

20

25

30

0 10 20 30 40 50 60 70 80 90

min

max


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P/F Mho Characteristic 50Hz SIR 1


O p e


05

101520253035

0 10 20 30 40 50 60 70 80 90

min

max


3P/F Mho Characteristic 50Hz SIR 1


O p e r a t i n g

T i m e ( m s )

0

5

1015

20

25

30

0 10 20 30 40 50 60 70 80 90

min

max


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O p e r a t i n g T i m e ( m s )

0

10

20

30

40

5060

0 10 20 30 40 50 60 70 80 90

min

max




O p e r a

t i n g T i m e ( m s )

0

20

40

60

80

100

0 10 20 30 40 50 60 70 80 90

min

max


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O p e r a t i n g T i m e ( m

s )

0

10

20

30

40

50

60

0 10 20 30 40 50 60 70 80 90

min

max




O p e


0

5

10

15

20

25

30

0 10 20 30 40 50 60 70 80 90

min

max


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0

5

10

15

20

25

30

0 10 20 30 40 50 60 70 80 90

min

max

Figure7-9Zone 1 typical operating times



O p e r a t i

n g T i m e ( m s )

0

510

15

20

25

30

0 10 20 30 40 50 60 70 80 90

minmax


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0

5

10

15

20

25

30

0 10 20 30 40 50 60 70 80 90

min

max




O p e r a t i n g

T i m e ( m s )

0

5

1015

20

25

30

0 10 20 30 40 50 60 70 80 90

min

max


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0

10

20

30

40

50

60

0 10 20 30 40 50 60 70 80 90

min

max





0

1020

30

40

50

60

0 10 20 30 40 50 60 70 80 90

min

max

Figure 7-14 Zone 1 Typical Operating Times

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0

5

10

15

20

25

30

0 10 20 30 40 50 60 70 80 90

min

max




O p e r a t i n g

T i m e ( m s )

0

10

20

30

40

50

0 10 20 30 40 50 60 70 80 90

min

max


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7.5 Switch on to fault (SOTF)

SOTF can be disabled, or enabled in 200ms or 110s after all poles of the line havebeen de-energised. Once the SOTF feature has been enabled, it remains enabledfor 250ms after the line has been re-energised, or until a SOTF trip has been

cleared. The menu allows for a choice of fault detectors. The three optionsavailable are:


b) Tripping via the operation of any current level detectorprovided that its corresponding voltage level detectorhas not picked up within 20ms.

c) Tripping via the operation of any distance comparatoror any current level detector provided that its

corresponding voltage level detector has not picked upwithin 20ms.

Voltage level detector setting: 44.5V (70% Vn)

Current level detector setting: 0.05 * In / KZPh

The operating time for close up 3 Phase faults and close up Phase to Ground faultswere measured for each of the modes of SOTF operation and for Line VTs and BusBar VTs.

SOTF times (50Hz relays)

Fault Type

SourceImpedance

Any comparator By Level detectors

SOTF operate times ( ms )

Ω

angle 88°Line VTs Bus Bar VTs Line VTs Bus Bar VTs

min max min max min max min max3P/F 108 29 35 16 24 32 37 25 32

36 29 34 15 23 31 36 22 323 29 35 14 22 30 35 24 32

G/F 108 29 37 16 27 32 39 27 43mho 36 28 37 13 25 31 39 27 33

3 30 37 15 27 31 38 25 34G/F 108 30 37 18 29 32 39 27 43quad 36 30 38 14 26 31 39 27 33

3 29 37 15 23 31 38 25 34

Zone 1 set to 5Ω angle 75°, Zone 3 set to 25Ω angle 75°100% Ground fault compensated, Source angle 88° Lag

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7.6 Voltage transformer supervision (VTS)

The VTS operates when zero sequence voltage is detected without the presence of zero sequence current. The VTS does not limit the current sensitivity of the distance

measuring elements.

Setting of V0 detector: 15%

7.7 Power swing blocking (PSB)

Power swing detected by transit time of impedance between Zone 6, which can bean offset mho or a lenticular characteristic, and either Zone 3 or Zone 2 asselected.

Setting ranges:


KZ6 1.00 49.98 0.02KZ6' 0.2 49.9 0.1 TZ6 20ms 90ms 5ms

Z6 Lenticular a/b 1.00, 0.67 & 0.41

The PSB feature may be enabled or disabled, and can be set to surround eitherZone 3 or Zone 2. The later option is used if Zone 3 is set reverse looking. Whenenabled the PSB feature can be set to give alarms only or to block individuallyselected zones. Blocking disabled if a ground fault occurs or (if DEF fitted) a phasefault occurs during a power swing.

7.8 Block auto-reclose

Auto-reclose is blocked after SOTF trips and Zone 3 time delayed trips.

Auto-reclose may be enabled or blocked on:

Zone 1 or aided trip caused by 2 or 3 phase faultZone 1 or aided trip caused by 3 phase faultZone 1X time delayed tripZone 1Y time delayed tripZone 2 time delayed tripChannel out of serviceDEF aided tripDEF time delay trip

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Class X current transformers are required to meet the following specification:

VK = IF * (1 + X/R) * (RB + RCT + RL)

Where:

IF = The maximum secondary fault current at the relayZone 1reach point.

X/R = The primary system ratio.

RB = The relay burden.

RCT = The CT secondary winding resistance.

RL = The resistance of the cable connecting the relayto the CTs, (lead and return for ground faults,lead only for phase faults).

The calculation is done for ground faults and phase faults and the highest kneepoint voltage calculation is used.

Burdens:

The resistance of the relay current transactors measured at twice rated current aregiven below. They do not include the DEF polarising CT.

Fault type In = 1A In = 5A

3P/F 0.073 to 0.079Ω 0.012 to 0.02ΩG/F 0.146 to 0.152Ω 0.024 to 0.04Ω

7.10 Directional earth fault (DEF)

DEF may be enabled or disabled.

Directional measuring one forward looking, one reverse looking.elements:

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Setting ranges:


Lowset 3Io 0.05In 0.8In 0.05In

THETA G 10° 80° 10°Highset 3Io 0.05In 0.8In 0.05InDEF MUTL*t 0.025 1.000 0.025

DEF Base setting Is 0.05In 1.2In 0.05In

Polarising: Zero sequence volt.Zero sequence current.Zero sequence volts and current.Negative sequence volts.

Sensitivity: Depends on polarising selected.

Polarising quantity: 1V Residual Voltage or1.5% Polarising Current as appropriate.

Operating quantity: 3I0 & 3I2 (if appropriate) set via menu.

Overcurrent curves: See Figures 7-17 & 7-18

IEC: CURVE 1 (Standard Inverse)CURVE 2 (Very Inverse)CURVE 3 (Extremely Inverse)CURVE 4 (Longtime Stand-By Earth Fault)

American: CURVE 5 (US Moderate Inverse)CURVE 6 (US Standard Inverse)CURVE 7 (US Very Inverse)CURVE 8 (US Extremely inverse)

Definite time: 2 SECOND4 SECOND8 SECOND

Accuracy at fn, 20°C, Time mult=1:

Current: +10% to 0%Operating time: definite time ±3% over 2Is to 31Is.

curves 1, 2, 4, 5, 6, 7 & 8 ±5% over 2Is to 31Is.curve 3 ±7.5% over 2Is to 20Is.

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Current (Multiples of Is)

Operating

10

5

50

100

curve 4

0.11 5

0.5

1

5010 100

curve 1

curve 3

curve 2

time (s)

Figure 7-17 IEC characteristics (time multiplier = 1)

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Operating

10

5

50

100

0.11 5

0.5

1

5010 100

curve 5

curve 8

curve 6

curve 7

time (s)

Figure 7-18 American characteristics (time mulitplier = 1)

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7.11 Fault location and instrumentation

Range of fault locator positive sequence settings referred to line VT and CTsecondaries:



The positive sequence reach for the fault locator is given by:

Zone F = KZF.KZPh.5/In (for overhead line models)Zone F = KZF.KZPh.5/2In (cable models)

KZPh and residual compensation are common to distance measuring elements.

KZM and THETA M are provided for mutual compensating the fault locator if required.

Setting ranges:


KZFKZM

THETA M

1.000.050°

40.001.36085°

0.010.001

5°Line units miles or km or 100%

Line Length 0 to 99.99 in steps of 0.01 plus100 to 999.9 in steps of 0.1

CT Ratio 1 : 1 and 10 : 1 to 5000 : 1 in steps of 10 : 1VT Ratio 1 : 1 and 10 : 1 to 9990 : 1 in steps of 10 : 1

Accuracy: ±2% at 2In, fn, 20°C for faults within the protected section ofline the Fault Locator option is available for the 113 relay,primarily for metering purposes, as its accuracy on power systemscontaining cable sections can not be guaranteed.

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7.12 Output contacts

Ratings:Make and carry 0.2s 7500VA subject to a maxima of 30A

300V, ac or dc.

Carry continuously 5A ac or dc.Break ac: 1250VA

dc: 50W resistive25W L/R = 0.04ssubject to a maxima of 5A and 300V

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Figure 7-19 Arrangement & outline panel mounting horizontal

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Figure 7-20 Arrangement & outline rack mounting

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Figure 7-21 Arrangement & outline panel mounting vertical

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7.13 Dimensions

Weight: 15kgOverall size: see Figures 7-19, 7-20 & 7-21

7.14 Serial communications.

Active port: LOCAL (front) or MODEM (rear).

Baud rate: Separate setting for each port.300, 600, 1200, 2400 & 4800.

Protocol: Separate setting for each port.

Protocols available are :

No OF DATA BITS PARITY No OF STOP BITS8 NONE 18 EVEN 18 ODD 18 NONE 27 EVEN 17 ODD 17 EVEN 27 ODD 27 NONE 2

Modem control lines: Selectable in use or not in use.CTS, DTR, RTS and DSR

7.15 Atmospheric environment

TemperatureIEC 255-6:1988 Operative -25°C to +55°C.

Storage and transport -25°C to +70°C.

IEC 68-2-1:1990 Cold

IEC 68-2-2:1974 Dry heat

HumidityIEC 68-2-3:1969 56 days at 93% RH and 40°CBS2011 part 2.1 Ca

Enclosure protectionIEC 529: 1989 IP50 (dust protected)BS 5490

7.16 Mechanical environment

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VibrationIEC 255-21-1:1988 Response Class 1BS 142: 1982 section 2.2Category S2

7.17 Durability

Loaded contact 10,000 operations minimumUnloaded contact 100,000 operation minimum

7.18 High voltage withstand

Insulation resistance

IEC 255-5:1977 >100MΩ when measured at 500V dc.

High voltage impulse

IEC 255-5:1977 Three positive and three negativeBS 142:1982 section 1.3 impulses of 5kV peak, 1.2/50µs, 0.5J

between all terminals and terminals andcase earth.

7.19 Electrical environment

High frequency disturbanceIEC 255-22-1:1988 Class III 2.5kV peak between independent circuitsBS 142:1982 section 1.4 and case.ANSI C37.90.1:1989 1.0kV peak across terminals of the same circuit.

Fast transient disturbanceIEC 255-22-4:1992 Class IV 4.0kV, 2.5kHz applied directly to auxiliaryIEC 801-4: 1988 Level 3 supply.ANSI C37.90.2:1987 2.0kV, 5kHz applied directly to all inputs.

Electrostatic dischargeIEC 255-22-2: 1989 Class III 8.0kV, discharge in air with cover in place

Electromagnetic interferenceIEC 255-22-3 Class III 25MHz-1GHz 10V/m

Draft ANSI C37.90.2

Radio frequency interferenceEMC Compliances Compliance to the European Commission88/336/EEC Directive on EMC is claimed via theEN50081-2:1994 Technical Construction File rout.EN50082-2:1995 Generic Standards were used to establish

conformity.

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Section 8. OPTIMHO DISTANCE RELAY EXTERNAL CONNECTIONS

See Figures 8-1 and 8-2 for typical external connection diagrams.

The input terminal connections are listed below.

8.1 Power supply (Vx1):

13 +DC14 -DC

8.2 Ac voltage:

15 Va16 Vb17 Vc18 Vn

8.3 Ac current:

19-20 Ia21-22 Ib23-24 Ic

25-26 In27-28 Ip or Im. This input can be used for zero sequence polarising the DEF or

for mutual compensating the fault locator.

8.4 Optical isolators:

+ve -ve FUNCTION58 60 Reset Zone 1 Extension / Loss of Guard62 64 Single Pole Open66 68 Breaker Open

70 72 Channel Out of Service74 76 CRX78 80 Relay Blocked82 84 Reset Indications

For Vx2 = 220/250V external box GJ0229 002 is required.

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8.4.1 Breaker open

Circuit breaker contacts connected in series to indicate all poles open. Required

with busbar VTs or if the Weak infeed or echo feature of POR schemes arerequired.

8.4.2 Relay blocked

Closed contact from miniature circuit breaker required when no VT fuses are used.

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ROTATION

PHASE

A

DIRECTION OF POWERFLOW FOR OPERATION

CT SHORTING LINKS MAKE BEFORE b)

P2

C

1) CT CONNECTIONS AS SHOWNARE TYPICAL ONLY

OR c) DISCONNECT

b)

NOTES

a)2)

c)

S1S2

P2

P1

B23

24

26

25

In

Ic

20

22

21

Ib

Ia

P1

18

Vn

19

Vc17

Vb

16

Va

15

C - 14

C - 15

C - 16

C - 13

C - 10

C - 12

C - 11

C - 9

48

50

56

54

52

46

44

30

42

32

34

36

38

40

C - 8

C - 6

C - 7

C - 5

C - 4

C - 3

C - 2

C - 1

41

53

55

43

51

49

47

45

33

35

39

37

31

29

82

RESET INDICATIONS

CASE EARTH

Vx1 14

84

13

SINGLE POLE OPEN

DEF CURRENT POLARISATION

CHANNEL OUT OFSERVICEVx2

S2 S1

RELAY BLOCKED

CRX

BREAKER OPEN

78

80

74

76

66

68

70

72

RESET ZONE 1

LOSS OF GUARD

EXTENSION /

64

58

60

62

27

28

Ip

4

OPTIMHO

+12V

10

20DTR

-12V

5

6

7

9

RTS

CTS

0V

DSR

C - 23

C - 24

C - 21

C - 22

C - 17

C - 18

C - 19

C - 20

3RXD

TXD

1

2GND

83

81

79

77

67

75

69

73

71

57

61

63

65

59

SECONDARIES

VT

REAR SERIAL

COMMUNICATION PORT

Figure 8-1 Typical external connection diagram

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DIRECTION OF POWER

FLOW FOR OPERATION

CT SHORTING LINKS MAKE BEFORE b)

DIRECTION OF POWER

FLOW FOR OPERATION

P1

PARALLEL

P2

ROTATION

PHASE

C B

S1S2

LINE

1) CT CONNECTIONS AS SHOWNARE TYPICAL ONLY

OR c) DISCONNECT

b)

A

NOTES

a)2)

c)

S1S2

P2

23

24

26

25

In

Ic

20

22

21

Ib

Ia

P1

18

Vn

19

Vc

17

Vb

16

Va

15

C - 14

C - 15

C - 16

C - 13

C - 10

C - 12

C - 11

C - 9

48

50

56

54

52

46

44

30

42

32

34

36

38

40

C - 8

C - 6

C - 7

C - 5

C - 4

C - 3

C - 2

C - 1

41

53

55

43

51

49

47

45

33

35

39

37

31

29

82

RESET INDICATIONS

CASE EARTH

Vx1 14

84

13

SINGLE POLE OPEN

CHANNEL OUT OFSERVICE

PROTECTION

Vx2

RELAY BLOCKED

CRX

BREAKER OPEN

7880

74

76

66

68

70

72

COMPENSATION INPUTMUTUAL ZERO SEQUENCE

RESET ZONE 1

LOSS OF GUARD

EXTENSION /

64

58

60

62

27

28

Im

4

OPTIMHO

+12V

10

20DTR

-12V

5

6

7

9

RTS

CTS

0V

DSR

C - 23

C - 24

C - 21

C - 22

C - 17

C - 18

C - 19

C - 20

3RXD

TXD

1

2GND

83

81

79

77

67

75

69

73

71

57

61

63

65

59

REAR SERIAL

COMMUNICATION PORT

VT

SECONDARIES

Figure 8-2 Typical external connection diagram with mutual zero sequence input

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8.4.3 Single pole open

Open contact from auto-reclose relay required with single phase tripping and any

of the following:

a) DEF option selected.b) PSB option selected and busbar VTs.c) POR 2 scheme selected. (Weak infeed).

The optical isolator must be energised during single pole dead times.

8.4.4 Unblocking schemes

For the unblocking schemes CRX is used for the unblock frequency (trip frequency)and Reset Zone 1 Extension for the block frequency (guard frequency).

8.5 Serial Communications Port

(Figure 3-7)

PIN NO FUNCTION1 GND2 TXD

3 RXD4 RTS5 CTS6 DSR7 0V9 +12V10 -12V20 DTR

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8.6 Output connections

The output relay connections are dependent on the relay version and are listed on

the next pages together with a list of abbreviations used.

The following conditions will cause the relay inoperative alarm contact RIA toclose:-

a) Loss of dc supply.b) Operation of voltage transformer supervision if this feature is set to

block tripping.c) Failure detected by relay monitoring system.d) Operation of Relay Blocked optical isolator.e) Test mode selected.

f) Block contacts option selected.

When 3 phase tripping is selected TRIP A, TRIP B, TRIP C and ANY TRIP respond as TRIP 3PH.

8.6.1 Output relays for LFZP111 without DEF

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The relevant external connection diagram is: 10 LFZP 111 05

The software number without fault locator is: 18 LFZP 146

The software number with fault locator is: 18 LFZP 145

CONTACT CONTACT CONFIGURATION No.REFERENCE

TERMINAL No 01 02 03 04 05C-1 29-31 RIA RIA RIA RIA RIAC-2 29-33 VTS SOTF VTS VTS VTSC-3 29-35 DIST TRIP Z1 Ph TRIP 3PH ANY TRIP DIST TRIPC-4 37-39 TRIP A Z2 INST ph TRIP 3PH TRIP A TRIP A

C-5 41-43 TRIP B BAR Z1 TRIP B TRIP BC-6 45-47 TRIP C TRIP A Z2 ( T ) TRIP C TRIP CC-7 49-51 SIGNAL SEND TRIP B SIGNAL SEND TRIP A SIGNAL SENDC-8 53-55 SOTF TRIP C SOTF TRIP B SIGNAL STOPC-9 30-32 TIME DELAY Z3 ( T ) Z3 ( T ) Z1 TIME DELAYC-10 30-34 ANY TRIP Z1Y ( T )+Z2 ( T ) ANY TRIP Z2 (T) ANY TRIPC-11 30-36 AIDED TRIP Z1X ( T ) AIDED TRIP Z3 (T) AIDED TRIPC-12 38-40 TRIP A START A TRIP PH TRIP C TRIP 3PHC-13 42-44 TRIP B START B TRIP G ANY TRIP TRIP 3PHC-14 46-48 TRIP C START C SIGNAL STOP Z2 INST STARTC-15 50-52 BAR START G BAR BAR BARC-16 54-56 START Z3.NOT Z2 START BAR BAR

C-17 57-59 TRIP A Z1 A-G TRIP A START A TRIP PHC-18 57-61 TRIP B Z1 B-G TRIP B START B TRIP GC-19 57-63 TRIP C Z1 C-G TRIP C START C Z1 G TRIPC-20 65-67 TRIP A Z2 INST A-G TRIP A START N TRIP AC-21 69-71 TRIP B Z2 INST B-G TRIP B SIGNAL SEND TRIP BC-22 73-75 TRIP C Z2 INST C-G TRIP C AIDED TRIP TRIP CC-23 77-79 ANY TRIP PSB ANY TRIP SOTF TIME DELAYC-24 81-83 PSB VTS PSB PSB TIME DELAY

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8.6.2 Output relays for LFZP111 with DEF




CONTACT CONTACT CONFIGURATION No.REFERENCE/

TERMINAL No 01 02 03 04 05C-1 9-31 RIA RIA RIA RIA RIAC-2 9-33 VTS SOTF VTS VTS VTS

C-3 9-35 DIST TRIP Z1 Ph TRIP 3PH DIST TRIP DIST TRIPC-4 7-39 TRIP A DEF FWD TRIP 3PH TRIP A TRIP AC-5 1-43 TRIP B BAR Z1 TRIP B TRIP BC-6 5-47 TRIP C TRIP A Z2 ( T ) TRIP C TRIPCC-7 9-51 SIGNAL SEND TRIP B SIGNAL SEND TRIP A SIGNAL SENDC-8 3-55 SOTF TRIP C SOTF TRIP B SIGNAL STOPC-9 0-32 TIME DELAY Z3 ( T ) Z3 ( T ) Z1 TIME DELAYC-10 0-34 DEF TRIP Z1Y ( T )+Z2 ( T ) DEF TRIP Z2 ( T ) DEF TRIPC-11 0-36 AIDED TRIP Z1X ( T ) AIDED TRIP Z3 ( T ) AIDED TRIPC-12 8-40 TRIP A DEF FWD TRIP PH TRIP C TRIP 3PHC-13 2-44 TRIP B DEF ( T ) TRIP G DEF TRIP TRIP 3PHC-14 6-48 TRIP C Z2 INST ph SIGNAL STOP Z2 INST/DEF F START

C-15 0-52 BAR DEF REV BAR BAR BARC-16 4-56 START Z3.NOT Z2 START BAR BARC-17 7-59 TRIP A Z1 A-G TRIP A START A TRIP PHC-18 7-61 TRIP B Z1 B-G TRIP B START B TRIP GC-19 7-63 TRIP C Z1 C-G TRIP C START C Z1 G TRIPC-20 5-67 TRIP A Z2 INST A-G TRIP A START N TRIP AC-21 9-71 TRIP B Z2 INST B-G TRIP B SIGNAL SEND TRIP BC-22 3-75 TRIP C Z2 INST C-G TRIP C AIDED TRIP TRIP CC-23 7-79 ANY TRIP PSB ANY TRIP SOTF TIME DELAYC-24 1-83 PSB VTS PSB PSB TIME DELAY

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8.6.3 Output relays for LFZP112 wihtout DEF





TERMINAL No 01 02 03 04C-1 29-31 RIA RIA RIA RIAC-2 29-33 VTS SOTF VTS VTSC-3 29-35 DIST TRIP Z1 Ph TRIP 3PH ANY TRIPC-4 37-39 TRIP A Z2 INST ph TRIP 3PH TRIP A

C-5 41-43 TRIP B BAR Z1 TRIP BC-6 45-47 TRIP C TRIP A Z2 ( T ) TRIP CC-7 49-51 SIGNAL SEND TRIP B SIGNAL SEND TRIP AC-8 53-55 SOTF TRIP C SOTF TRIP BC-9 30-32 TIME DELAY Z3 ( T ) Z3 ( T ) Z1C-10 30-34 Z1Y ( T )+Z2 ( T ) Z2 ( T )C-11 30-36 AIDED TRIP Z1X ( T ) AIDED TRIP Z3 ( T )C-12 38-40 TRIP A START A TRIP PH TRIP CC-13 42-44 TRIP B START B TRIP G ANY TRIPC-14 46-48 TRIP C START C SIGNAL STOP Z2 INSTC-15 50-52 BAR START G BAR BARC-16 54-56 START Z3.NOT Z2 START BAR

C-17 57-59 TRIP A Z1 A-G TRIP A START AC-18 57-61 TRIP B Z1 B-G TRIP B START BC-19 57-63 TRIP C Z1 C-G TRIP C START CC-20 65-67 TRIP A Z2 INST A-G TRIP A START NC-21 69-71 TRIP B Z2 INST B-G TRIP B SIGNAL SENDC-22 73-75 TRIP C Z2 INST C-G TRIP C AIDED TRIPC-23 77-79 ANY TRIP PSB ANY TRIP SOTFC-24 81-83 PSB VTS PSB PSB

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TERMINAL No 01 02 03 04C-1 29-31 RIA RIA RIA RIAC-2 29-33 VTS SOTF VTS VTSC-3 29-35 DIST TRIP Z1 Ph TRIP 3PH DIST TRIP

C-4 37-39 TRIP A DEF FWD TRIP 3PH TRIP AC-5 41-43 TRIP B BAR Z1 TRIP BC-6 45-47 TRIP C TRIP A Z2 ( T ) TRIP CC-7 49-51 SIGNAL SEND TRIP B SIGNAL SEND TRIP AC-8 53-55 SOTF TRIP C SOTF TRIP BC-9 30-32 TIME DELAY Z3 ( T ) Z3 ( T ) Z1C-10 30-34 DEF TRIP Z1Y ( T )+Z2 ( T ) DEF TRIP Z2 ( T )C-11 30-36 AIDED TRIP Z1X ( T ) AIDED TRIP Z3 ( T )C-12 38-40 TRIP A DEF FWD TRIP PH TRIP CC-13 42-44 TRIP B DEF ( T ) TRIP G DEF TRIPC-14 46-48 TRIP C Z2 INST ph SIGNAL STOP Z2 INST/DEF FC-15 50-52 BAR DEF REV BAR BAR

C-16 54-56 START Z3.NOT Z2 START BARC-17 57-59 TRIP A Z1 A-G TRIP A START AC-18 57-61 TRIP B Z1 B-G TRIP B START BC-19 57-63 TRIP C Z1 C-G TRIP C START CC-20 65-67 TRIP A Z2 INST A-G TRIP A START NC-21 69-71 TRIP B Z2 INST B-G TRIP B SIGNAL SENDC-22 73-75 TRIP C Z2 INST C-G TRIP C AIDED TRIPC-23 77-79 ANY TRIP PSB ANY TRIP SOTFC-24 81-83 PSB VTS PSB PSB

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8.6.5 Output relays for LFZP113


The software number is: 18 LFZP 174


TERMINAL No 01 02 03C-1 29-31 RIA RIA RIAC-2 29-33 VTS SOTF VTSC-3 29-35 DIST TRIP Z1 Ph TRIP 3PHC-4 37-39 TRIP A Z2 INST ph TRIP 3PHC-5 41-43 TRIP B BAR Z1

C-6 45-47 TRIP C TRIP A Z2 ( T )C-7 49-51 SIGNAL SEND TRIP B SIGNAL SENDC-8 53-55 SOTF TRIP C SOTFC-9 30-32 TIME DELAY Z3 ( T ) Z3 ( T )C-10 30-34 Z1Y ( T )+Z2 ( T )C-11 30-36 AIDED TRIP Z1X ( T ) AIDED TRIPC-12 38-40 TRIP A START A TRIP PHC-13 42-44 TRIP B START B TRIP GC-14 46-48 TRIP C START C SIGNAL STOPC-15 50-52 BAR START G BARC-16 54-56 START Z3.NOT Z2 STARTC-17 57-59 TRIP A Z1 A-G TRIP A

C-18 57-61 TRIP B Z1 B-G TRIP BC-19 57-63 TRIP C Z1 C-G TRIP CC-20 65-67 TRIP A Z2 INST A-G TRIP AC-21 69-71 TRIP B Z2 INST B-G TRIP BC-22 73-75 TRIP C Z2 INST C-G TRIP CC-23 77-79 ANY TRIP PSB ANY TRIPC-24 81-83 PSB VTS PSB

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8.6.6 Output relays for LFZP114 without DEF





TERMINAL No 01 02 03 04C-1 29-31 RIA RIA RIA RIAC-2 29-33 VTS SOTF VTS VTSC-3 29-35 DIST TRIP Z1 Ph TRIP 3PH DIST TRIPC-4 37-39 TRIP A Z2 INST ph TRIP 3PH TRIP AC-5 41-43 TRIP B BAR Z1 TRIP BC-6 45-47 TRIP C TRIP A Z2 ( T ) TRIP CC-7 49-51 SIGNAL SEND TRIP B SIGNAL SEND SIGNAL SENDC-8 53-55 SOTF TRIP C SOTF SOTFC-9 30-32 TIME DELAY Z2 ( T ) Z1X ( T ) TIME DELAYC-10 30-34 ANY TRIP Z1Y ( T ) ANY TRIP ANY TRIPC-11 30-36 AIDED TRIP Z1X ( T ) AIDED TRIP AIDED TRIPC-12 38-40 TRIP A START A TRIP PH TRIP AC-13 42-44 TRIP B START B TRIP G TRIP B

C-14 46-48 TRIP C START C Z1Y ( T ) LDHS PHASESC-15 50-52 BAR START G BAR BARC-16 54-56 START Z2 INST START STARTC-17 57-59 TRIP A Z1 A-G TRIP A TRIP AC-18 57-61 TRIP B Z1 B-G TRIP B TRIP BC-19 57-63 TRIP C Z1 C-G TRIP C TRIP CC-20 65-67 TRIP A Z2 INST A-G TRIP A TRIP AC-21 69-71 TRIP B Z2 INST B-G TRIP B TRIP BC-22 73-75 TRIP C Z2 INST C-G TRIP C TRIP CC-23 77-79 ANY TRIP ANY TRIP ANY TRIP ANY TRIPC-24 81-83 VTS TRIP BAR

Continued on next page.

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Continued from previous page.


TERMINAL No 05 06C-1 29-31 RIA RIAC-2 29-33 VTS VTSC-3 29-35 DIST TRIP ANY TRIPC-4 37-39 TRIP A TRIP AC-5 41-43 TRIP B TRIP BC-6 45-47 TRIP C TRIP CC-7 49-51 SIGNAL SEND TRIP AC-8 53-55 SIGNAL STOP TRIP BC-9 30-32 TIME DELAY Z1

C-10 30-34 ANY TRIP Z2 ( T )C-11 30-36 AIDED TRIP Z3 ( T )C-12 38-40 TRIP 3PH TRIP CC-13 42-44 TRIP 3PH ANY TRIPC-14 46-48 START Z2 INSTC-15 50-52 BAR BARC-16 54-56 BAR BARC-17 57-59 TRIP PH START AC-18 57-61 TRIP G START BC-19 57-63 Z1 G TRIP START CC-20 65-67 TRIP A START NC-21 69-71 TRIP B SIGNAL SENDC-22 73-75 TRIP C AIDED TRIPC-23 77-79 TIME DELAY SOTFC-24 81-83 TIME DELAY PSB

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TERMINAL No 01 02 03 04C-1 29-31 RIA RIA RIA RIAC-2 29-33 VTS SOTF VTS VTSC-3 29-35 DIST TRIP Z1 Ph TRIP 3PH DIST TRIP

C-4 37-39 TRIP A DEF FWD TRIP 3PH TRIP AC-5 41-43 TRIP B BAR Z1 TRIP BC-6 45-47 TRIP C TRIP A Z2 ( T ) TRIP BC-7 49-51 SIGNAL SEND TRIP B SIGNAL SEND SIGNAL SENDC-8 53-55 SOTF TRIP C SOTF SOTFC-9 30-32 TIME DELAY Z2 ( T ) Z1X ( T ) TIME DELAYC-10 30-34 DEF TRIP Z1Y ( T ) DEF TRIP DEF TRIPC-11 30-36 AIDED TRIP Z1X ( T ) AIDED TRIP AIDED TRIPC-12 38-40 TRIP A DEF FWD TRIP PH TRIP AC-13 42-44 TRIP B DEF ( T ) TRIP G TRIP BC-14 46-48 TRIP C Z2 INST ph Z1Y ( T ) LDHS PHASESC-15 50-52 BAR START BAR BAR

C-16 54-56 START Z2 INST START STARTC-17 57-59 TRIP A Z1 A-G TRIP A TRIP AC-18 57-61 TRIP B Z1 B-G TRIP B TRIP BC-19 57-63 TRIP C Z1 C-G TRIP C TRIP CC-20 65-67 TRIP A Z2 INST A-G TRIP A TRIP AC-21 69-71 TRIP B Z2 INST B-G TRIP B TRIP BC-22 73-75 TRIP C Z2 INST C-G TRIP C TRIP CC-23 77-79 ANY TRIP ANY TRIP ANY TRIP ANY TRIPC-24 81-83 VTS TRIP BAR

Continued on next page.

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Continued from previous page.


TERMINAL No 05 06C-1 29-31 RIA RIAC-2 29-33 VTS VTSC-3 29-35 DIST TRIP DIST TRIPC-4 37-39 TRIP A TRIP AC-5 41-43 TRIP B TRIP BC-6 45-47 TRIP C TRIP CC-7 49-51 SIGNAL SEND TRIP AC-8 53-55 SIGNAL STOP TRIP BC-9 30-32 TIME DELAY Z1

C-10 30-34 DEF TRIP Z2 ( T )C-11 30-36 AIDED TRIP Z3 ( T )C-12 38-40 TRIP 3PH TRIP CC-13 42-44 TRIP 3PH DEF TRIPC-14 46-48 START Z2 INST/DEF FC-15 50-52 BAR BARC-16 54-56 BAR BARC-17 57-59 TRIP PH START AC-18 57-61 TRIP G START BC-19 57-63 Z1 G TRIP START CC-20 65-67 TRIP A START NC-21 69-71 TRIP B SIGNAL SENDC-22 73-75 TRIP C AIDED TRIPC-23 77-79 TIME DELAY SOTFC-24 81-83 TIME DELAY PSB

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8.6.8 Reserved

This contact arrangement is common to all versions and is used during the GEC

ALSTHOM T&D production testing of all relays.

CONTACT

CONTACTCONFIGURATION

RESERVED

REFERENCE/ TERMINAL NoC-1 29-31 RIAC-2 29-33 VTSC-3 29-35 BARC-4 37-39 ANY TRIP

C-5 41-43 START AC-6 45-47 START BC-7 49-51 START CC-8 53-55 START GC-9 30-32 SOTFC-10 30-34 AIDED TRIPC-11 30-36 Z1C-12 38-40 Z2 ( T )C-13 42-44 Z3 ( T )C-14 46-48 SIGNAL SENDC-15 50-52 PSBC-16 54-56 DEF TRIPC-17 57-59C-18 57-61C-19 57-63C-20 65-67C-21 69-71C-22 73-75 TRIP AC-23 77-79 TRIP BC-24 81-83 TRIP C

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8.6.9 Abbreviations used in contact names

Trips

TRIP A Trip pole A of circuit breaker TRIP B Trip pole B of circuit breaker TRIP C Trip pole C of circuit breaker TRIP 3PH Trip all 3 poles of circuit breaker

Trip alarms

Z1 Zone 1 tripZ1X(T) Zone 1X time delay trip

Z1Y(T) Zone 1Y time delay tripZ2(T) Zone 2 time delay tripZ3(T) Zone 3 time delay tripSOTF Switch on to fault tripDIST TRIP Distance tripDIST AIDED Distance aided tripDEF AIDED DEF aided tripDEF (T) DEF time delayed trip

TIME DELAY Any time delayed tripDEF TRIP Any DEF tripANY TRIP Any tripAIDED TRIP Any aided trip

TRIP PH Trip for a phase fault TRIP G Trip for ground fault

Miscellaneous aarms

RIA Relay inoperative alarm (normally closed)VTS Voltage transformer supervision operatedPSB Power swing in progress

Starts

START DEF forward or reverse or any Z1, Z2, Z3 elementSTART A Any fault involving A phase detected by distanceSTART B Any fault involving B phase detected by distanceSTART C Any fault involving C phase detected by distanceSTART G Any fault involving ground detected by distance or DEF

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Instantaneous operation of elements for external scheme logic

Z2 INST Any Z2 element operatedZ2 INST A-G Zone 2 A-G element operated

Z2 INST B-G Zone 2 B-G element operatedZ2 INST C-G Zone 2 C-G element operatedZ2 INST ph Any Zone 2 phase - phase element operatedZ1 INST ph Any Zone 1 phase - phase element operatedZ1 A-G Zone 1 A-G element operatedZ1 B-G Zone 1 B-G element operatedZ1 C-G Zone 1 C-G element operatedZ3.NOT Z2 Any Zone 3 element without any Zone 2 elementDEF FWD DEF forward comparator operatedDEF REV DEF reverse comparator operated

Miscellaneous

BAR Block auto-recloseSIGNAL SEND Initiate signal sendSIGNAL STOP Stops signal send (Z2 INST or DEF FWD)LDHS PHASES LDHSA or LDHSB or LDHSC

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Service Manaul R-5911BLFZP 11x Chapter 2

Appendix APage 1 of 26

OPTIMHO menu tree

for relay versions: LFZP 111 (DEF and FAULT LOCATOR are optional)LFZP 112 (DEF and FAULT LOCATOR are optional)LFZP 113 (FAULT LOCATOR IS OPTIONAL. See Section 4.5.1)LFZP 114 (DEF and FAULT LOCATOR are optional)

Default level

The top of the menu tree is designated the default level. when the operator interface is not in usethe liquid crystal display will always show an appropriate default page. the normal default orroot page will be as selected in the section of the menu.


This will be either a blank page or a group identification string of up to 32 characters which hasbeen entered by the user (see Section 3.10) or the setting group number selected. Under certainconditions, as indicated below, the root page may be replaced by one of the following defaultpages which are listed in a hierarchical order, item a) having the highest precedence :

a) 'SERIAL COMMS ' If serial communications is logged on. Note, serial'LOGGED ON ' communications can only log on when either a root page or

one of the default pages a) to h) below are displayed.

b) 'Push SET to ' Only if setting changes have been made.

'update changes ''OR ''Push SET to ' Only if setting group no. has been changed.'update group '

c) 'Z1 ' Fault or event information.'AN V~FAIL '

d) 'PwrSwg TEST ' If the power swing test commission option has been selected.'ENABLED '

e) 'CONTACTS ' If either the 'contacts blocked' or the contacts blocked'BLOCKED ' except any trip' commission options have been selected.

f) 'ERROR# SLOT No 1 ' Diagnostic information, if any faults have been detected'5 6 7 8 9 10 11 '

g) 'ERROR# I~FAIL ' Diagnostic information, if an anomalous condition has beendetected

h) 'Please set ''CALENDAR CLOCK ' If a power up reset has occurred.

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MENU TREE

ROOT ORDEFAULTDISPLAY

OPTIONSACTIVE SETTINGS

OPTIONSPRINT

PRINT SETTINGSPRINT FAULT RECORDS

OPTIONSFAULT RECORDS

VIEW RECORDSCLEAR RECORDS

OPTIONSMETERING

OPTIONSIDENTIFIERS

SET GROUP IDENTIFIER

SOFTWARE VERSIONDEFAULT DISPLAY

OPTIONSCALENDAR CLOCK

READ TIME & DATESET TIME & DATECLOCK REFERENCE

OPTIONSCOMMISSION TESTS

CONTACT CONTROLON LOAD DIR TESTPwrSwg TESTMONITOR OPTIONOUTPUT OPTION

OPTIONSCOMMUNICATIONS

SERIAL CONTROL

OPTIONSSETTINGS

CONTACT CONFIGURATION

SCHEMEDISTANCE

BLOCK AUTORECLOSEVT SUPERVISIONSTART INDICATIONDEFFAULT LOCATOR

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!

OPTIONS ACTIVE SETTINGS ACTIVE SETTINGSACTIVE SETTINGS ! GROUP = 1 ! GROUP = 1 "

GROUP 8 SETTING GROUPSSETTING TRAP ARE AVAILABLE

If no change made #

If change made #

!

Push SET to !

update group

SET settings group !

updated

#

RESET

# settings group !

change ignored

OPTIONS PRINT push ! to print 'printing in' 'printer not'

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PRINT ! push ! to print ! all settings ! 'progress' or 'ready'

$ $ push ! to printfault records

Note1) 'OPTION '

'PRINT '

display is stepped to from the root or default display when the ! key is pressedprovided the default display is not :-


For this display the menu steps to:-'OPTIONS ''CALENDAR CLOCK '

2) If serial comms. is logged on printing is directed to the ACTIVE serial port.If serial comms. is not logged on printing is directed to the PARALLEL port.

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OPTIONS

FAULTRECORDS !

FAULT RECORDSpush ! to view !

push ! to viewLAST FAULT ! See Fig 3-2 &3-3 for

$ $ $ typical fault records

push ! to viewLAST FAULT -1 !

$ (If fault record is empty,

push ! to viewLAST FAULT -2 ! ' No record ',

↑ $

push ! to view is displayed.)

LAST FAULT -3 !

FAULT RECORDS ! push SET to SET all fault

clear records clear records records cleared

Note, if ACCESS LEVEL (COMMUNICATIONS section) is set to LIMITED, the display:- 'FAULT RECORDS' 'clear records 'is not visible

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OPTIONS Va= 63.50 KVMETERING ! 0.0 degrees (Only if FAULT LOCATOR fitted)

$

$ Vb= 63.50 KV -120.0 degrees

$ Vc= 63.50 KV120.0 degrees Note, metered values are updated every 2 seconds.

$ Ia= 2.00 KA- 20.0 degrees

$ Ib= 2.00 KA-140.0 degrees

$ Ic= 2.00 KA100.0 degrees

$ REAL POWER= 358.0 MW

REACTIVE POWER= 130.3 MVAR

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OPTIONS IDENTIFIERS GROUP IDENTIFIER (32 character string entered

IDENTIFIERS !!!! GROUP ! push ! to set ! via relay keypad)

$

IDENTIFIERS SOFTWARE VERSION DISTANCESOFTWARE VERSION ! DISTANCE ! 18 LFZP xxx x

$ $

(Only if FAULT SOFTWARE VERSION FAULT LOCATORLOCATOR fitted) FAULT LOCATOR ! 18 LFZP xxx x

IDENTIFIERS DEFAULT DISPLAY DEFAULT DISPLAYDEFAULT DISPLAY ! Blank display ! Blank display "

DEFAULT DISPLAYGROUP ID "

Note: DEFAULT DISPLAYGroup 1 GROUP ACTIVE GROUP "

IDENTIFIER is used asthe logon password forthe serial communications

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OPTIONS CALENDAR CLOCK CALENDAR CLOCK !!!! READ TIME & DATE ! 1980 JAN 01

$ $ 00:00:00

CALENDAR CLOCK SET TIME & DATE SET TIME & DATESET TIME & DATE ! SET YEAR 1980 ! SET YEAR 1980 "

$ $

SET TIME & DATE SET TIME & DATESET MONTH JAN ! SET MONTH JAN "

$

SET TIME & DATE SET TIME & DATESET DAY 01 ! SET DAY 01 "

$

(Time is set when SET TIME & DATE SET TIME & DATE #is pressed) SET HOUR 00 ! SET HOUR 00 "

$

SET TIME & DATE SET TIME & DATESET MINUTE 00 ! SET MINUTE 00 "

$

SET TIME & DATE SET TIME & DATESET SECOND 00 ! SET SECOND 00 "

CALENDAR CLOCK CLOCK REFERENCE CLOCK REFERENCECLOCK REFERENCE ! RELAY CRYSTAL ! RELAY CRYSTAL "

CLOCK REFERENCESYSTEM VOLTAGE "

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OPTIONS ! COMMISSION TESTS ! ALL CONTACTS ! ALL CONTACTSCOMMISSION TESTS CONTACT CONTROL ENABLED ENABLED "

$ $

ALL CONTACTSBLOCKED "

CONTACTS BLOCKEDEXCEPT ANY TRIP "

COMMISSION TESTS ON LOAD DIR TEST 'Fault seen as' *1ON LOAD DIR TEST ! push SET to test SET 'FORWARD '

$ or 'Fault NOT seen' 'as FORWARD'

or'Test aborted '

'check I &/or V'

(Except version 114) COMMISSION TEST PwgSwg TEST PwgSwg TEST *2PwrSwg TEST ! DISABLED ! DISABLED"

$

PwgSwg TESTENABLED"

COMMISSION TEST MONITOR 23456789 MONITOR 23456789 *3MONITOR OPTIONS ! OPT 25 ******** ! OPT 25 " ********

$

COMMISSION TEST *4OUTPUT OPTION push SET to test push SET to test

! OUTPUT OPT #27 ! OUTPUT OPT #27 "

or ' Contacts blocked'(If contact block has

been selected) *5

*1 Note, this test is only active whilst the SET key is held pressed. The RELAY AVAILABLE LED is turned off and the RIAcontact closes when the page :- 'ON LOAD DIR TEST''push SET to test' is displayed and the SET key is pressed. TheRELAY AVAILABLE LED is turned on and the RIA contact opens when the SET key is released.

*2 Note, when Power Swing test is enabled, monitor option number 8 should be selected in order to view relay response

*3 Note, * = 0 or 1. Monitor options are detailed in section 3.14

*4 Note,a) this test is only active whilst the SET key is held pressed. The RELAY AVAILABLE LED is turned off and the RIA contact

closes when the page :- 'push SET to test' , 'OUTPUT OPT #xx' is displayed. The RELAY AVAILABLE LED is turned onand the RIA contact opens when the user steps back to the page:-'COMMISSION TEST' 'OUTPUT OPTION' b) The 15 minute timeout feature is not applicable when the page :-.'push SET to test' 'OUTPUT OPT #xx' is displayed

c) Output options are detailed in section 3.14

*5 Note, If ACCESS LEVEL (COMMUNICATIONS section) is set to limited the pages:-'COMMISSION TEST' 'ON LOADDIR TEST' & 'COMMISSION TEST' 'OUTPUT OPTION' are not visible

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OPTIONSCOMMUN-

ICATIONS!

COMMUNICATIONS

ACCESS LEVEL !

ACCESS LEVEL

FULL !

ACCESS LEVEL

FULL"

Note, when ACCESS LEVEL is set to

LIMITED, only time/ date and ACCESS LEVEL can be

$ $ changed. -see note 6 on page 12

ACCESS LEVEL and notes at bottom of page 10

LIMITED"

COMMUNICATIONSSERIAL CONTROL SERIAL CONTROL ACTIVE PORT ACTIVE PORT

! ACTIVE PORT ! MODEM ! MODEM "

$

ACTIVE PORTLOCAL"

( BAUD Settings

are :-

SERIAL CONTROLMODEM BAUD RATE

MODEM BAUD RATE MODEM BAUD RATE

4800 ! 4800"

2400

1200

$

60 0

300 )

SERIAL CONTROLMODEM PROTOCOL

MODEM PROTOCOLDATA PARITY STOP

DATA PARITY STOP8 NONE 1 DATA PARITY STOP

8 NONE 1"

$

DATA PARITY STOP8 EVEN 1 "

DATA PARITY STOP 8 ODD 1 "

DATA PARITY STOP8 NONE 2 "


DATA PARITY STOP7 ODD 1 "


DATA PARITY STOP7 ODD 2 "


Note,1) To gain access to the menu via the serial comms the user must first type in the Group 1 GROUP IDENTIFIER, see IDENTIFIER

section, followed by carriage return. Provided the ID matches that stored in the relay a prompt GECAM: will appear. The userthen types LOGON followed by carriage return, at which point he will be logged onto the menu provided the LCD display is at aroot or default display. The message 'Operator interface in use' will be written to the VDU if the menu is not at the root or defaultlevel.

2) When the GECAM: prompt is displayed on the remote VDU, the relay LCD changes to :-'Serial comms.' 'Logged on'

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COMMUNICATIONS continued:-

SERIAL CONTROL CONTROL LINESCONTROL LINES ! IN USE "

$

CONTROL LINESNOT IN USE "

SERIAL CONTROLLOCAL BAUD RATE !

LOCAL BAUD RATE4800 !

LOCAL BAUD RATE4800 !

$

SERIAL CONTROLLOCAL PROTOCOL !

LOCAL PROTOCOL DATA PARITY STOP!

DATA PARITY STOP 8NONE 1!



3) Serial comms. is logged off whenever Q on the remote keyboard or DATA PARITY STOPRESET on the relay keypad is pressed 8 ODD 1 "

4) When the MODEM serial comms. is logged on, the option to select DATA PARITY STOPLOCAL port is not available, this prevents lockout of the modem 8 NONE 2 "

control.DATA PARITY STOP

5) A timeout feature will automatically log off serial comms. if no key is 7 EVEN 1 "

pressed within a 15 minute interval. The LCD will return to anappropriate root or default display. DATA PARITY STOP

7 ODD 1 "

6) When serial comms. is logged on to the MODEM port and theACCESS LEVEL is set to LIMITED, no settings (except time/date) can DATA PARITY STOPbe changed. When serial comms. is logged on to the LOCAL port and 7 EVEN 2 "

the ACCESS LEVEL is set to LIMITED, no settings (except time/dateand ACCESS LEVEL) can be changed. DATA PARITY STOP

7 ODD 2 "

7) A 60s timeout on X-OFF will automatically select X-ON if X-OFFis active for more than 60s. DATA PARITY STOP

7 NONE 28) Any change made to any setting in this branch of the menu tree iscopied to all the other setting groups when settings are updated.

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OPTIONSSETTINGS !

SETTINGSCONTACT CONTACT CONFIG- CONTACT CONFIG- CONFIG! RESERVED! RESERVED"

$

CONTACT CONFIG-1) RESERVED contact configuration is URATION No. 01"

for GECAM test use onlyCONTACT CONFIG-

2) For all versions a minimum of 3 or 4 URATION No. 02"

contact configurations are alwaysavailable, additional configurations may beavailable for specific relay versions

CONTACT CONFIG-URATION No. 03"

CONTACT CONFIG-URATION No. 04"

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SCHEME SETTINGS continued:-

SETTINGSSCHEME SCHEME SCHEME SELECTION SCHEME SELECTION

$ ! SELECTION ! BASIC ! BASIC "

$ $

(Only if POR1, POR1 UNBLOCK,SCHEMESELECTION

BLOCKING or BLOCKING 2 selected) TP = 98ms !

TP = 98ms "

SCHEME SELECTIONZ1 EXTENSION"

(Only if POR1,POR1 UNBLOCK,POR2,POR2 UNBLOCK,POR2 WI

$ SCHEMESELECTION

TRIP,POR2 WI TRIP UNBLOCK,BLOCKING or BLOCKING 2 selected)

TD = 98ms !

TD = 98ms "

SCHEME SELECTIONPUR "

(Only if PUR UNBLOCK, POR1UNBLOCK, POR2 UNBLOCK or $ SCHEMESELECTIONPOR2 WI TRIP UNBLOCK selected) TDW= 98ms!

TDW= 98ms "

SCHEME SELECTIONPUR UNBLOCK "

SCHEME SELECTION( timer range = 0 to 98ms in 2ms steps) POR 1"

SCHEME SELECTION(Except 114 POR 1 UNBLOCK "version)

SCHEME SELECTIONPOR 2"

SCHEME SELECTION

POR 2 WI TRIP"

SCHEME SELECTIONPOR 2 UNBLOCK "

SCHEME POR 2W1 TRIP UNBLOCK "

SCHEME SELECTIONBLOCKING"

SCHEME SELECTIONBLOCKING 2"

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SCHEME SETTINGS continued:-

(Versions 111,112 SCHEME SELECTION DEF ELEMENTS DEF ELEMENTS

& 114 only with DEF ELEMENTS ! ALL ENABLED! ALL ENABLED"

DEF fitted)$ DEF ELEMENTS

ALL BLOCKED"

(Only if DEFELEMENTS

DEF ELEMENTSDEF AIDED TRIP!

DEF AIDED TRIPENABLED!

DEF AIDED TRIPENABLED "

ALLENABLED) $

Note, DEF AIDED TRIP is set to DEF AIDED TRIPBLOCKED if BASIC,Z1 EXTENSION, BLOCKED "

or PUR UNBLOCk schemes areselected

(Highset 3Io (Only if DEF AIDED TRIP ------------- DEF AIDED TRIP DEF HIGHSETrange=0.05 ENABLED and SCHEME TYPE HIGHSET ! 3Io = 0.8In"

to 0.8In in any POR or any BLOCKING)0.05In steps) $

Only if DEF AIDED TRIP -------------- DEF AIDED TRIP DEF AIDED TRIP(Scheme timer ENABLED and SCHEME TYPE is TPG = 98ms ! TPG = 98ms "

range = 0 to any BLOCKING)98ms in 2ms $

steps) (Only if DEF AIDED TRIP ------------- DEF AIDED TRIP DEF AIDED TRIP ENABLED and SCHEME TYPE is TDG = 98ms ! TDG = 98ms "

POR1, POR1 UNBLOCK, BLOCKING orBLOCKING 2 )

SCHEME LOSS OF LOAD LOSS OF LOADLOSS OF LOAD ! FEATURE ENABLED! FEATURE ENABLED "

$

LOSS OF LOADFEATURE BLOCKED "

(O nly if ENABLED)- LL ENABLED BY LL ENABLED BYLS I LEVEL DET ! LS I LEVEL DET "

LL ENABLED BYHS I LEVEL DET "

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SCHEME SETTINGS continued : -SETTINGS DISTANCE TYPE OF TRIP TYPE OF TRIPDISTANCE! TYPE OF TRIP ! 1 OR 3 POLE ! 1 OR 3 POLE"

$ $

TYPE OF TRIP3 POLE ONLY"

DISTANCE ZONE 1 TRIPPING ZONE 1 TRIPPINGZONE 1 TRIPPING ! ENABLED ! ENABLED"

$

ZONE 1 TRIPPINGBLOCKED"

DISTANCE TIME DELAY TRIP TIME DELAY TRIP TIME DELAY TRIP! Z1X(T) ENABLED! Z1X(T) ENABLED

$ $

TIME DELAY TRIPZ1X(T) BLOCKED"

(TZ1X range = (Only if Z1X(T) --------- TIME DELAY TRIP TIME DELAY TRIP100ms to 9980ms in 20ms steps) ENABLED) TZ1X = 9.98s ! TZ1X = 9.98s"

$

TIME DELAY TRIP TIME DELAY TRIPZ1Y(T) ENABLED ! Z1Y(T) ENABLED"

$

TIME DELAY TRIPZ1Y(T) BLOCKED "

(TZ1Y range = (Only if Z1Y(T) -------- TIME DELAY TRIP TIME DELAY TRIP100ms to 9980ms in 20ms steps) ENABLED) TZ1Y=9.98s ! TZ1Y=9.98s"

$

TIME DELAY TRIP TIME DELAY TRIPZ2(T) ENABLED ! Z2(T) ENABLED"

$

TIME DELAY TRIPZ2(T) BLOCKED"

(TZ2 range = (Only if Z2(T) ----------- TIME DELAY TRIP TIME DELAY TRIP100ms to 9980ms in 20ms steps) ENABLED) TZ2=9.98s ! TZ2=9.98s"

$

TIME DELAY TRIP TIME DELAY TRIPZ3(T) ENABLED ! Z3(T) ENABLED"

$

TIME DELAY TRIP

Z3(T) BLOCKED"

(TZ3 range = 100ms to 9980ms in (O nly if Z3(T) -----------

TIME DELAY TRIP TZ3= 9.98s !

TIME DELAY TRIP TZ3= 9.98s"

20ms steps) ENABLED) $

TIME DELAY TRIPALL G ENABLED !

TIME DELAY TRIPALL G ENABLED"

TIME DELAY TRIPALL G BLOCKED"

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(KZPh range = 0.04 to 1.00 in steps of 0.001)

DISTANCEBASE SETTING!

BASE SETTINGKZPh = 1.000 !

BASE SETTINGKZPh = 1.000"

(THETA Ph range = 50° to 80° in 5° $ $

steps, versions 111, 112 & 114 only)(THETA Ph range = 45° to 80° in 5°steps, version 113 only)

BASE SETTING THETA Ph = 85°

! BASE SETTING THETA Ph = 85°"

$

BASE SETTINGKZN= 1.360 !

BASE SETTINGKZN= 1.360"

(KZN range = 0 to 1.360 in steps of $

0.001)BASE SETTING

THETA N = 85° !

BASE SETTING THETA N = 85°"

(THETA N range = 50° to 85° in 5°steps, versions 111, 112 & 114 only)(THETA N range = -45°,-35°, -25° to 80° in 5° steps, version 113 only)

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DISTANCE SETTINGS DISTANCE DIST G CHAR'STIC DIST G CHAR'STIC

continued:- DIST G CHAR'STIC ! MHO ! MHO "(Version 111only)

$ $

DIST G CHAR'STICQUADRILATERAL"

KR range = 1 to 30 in DIST G CHAR'STIC DIST G CHAR'STIC(steps of 1) KR = 30 ! KR = 30"

(Only if QUADRILATERAL)

(KZ1 range = 1.00 to49.98 in steps of 0.02)

DISTANCEZ1 & Z2 SETTING !

Z1 & Z2 SETTINGKZ1 = 49.98 !

Z1 & Z2 SETTINGKZ1 = 49.98"

$ $

(KZ1X range = 1.00 to49.98 in steps of 0.02)

Z1 & Z2 SETTINGKZ1X = 49.98 !

Z1 & Z2 SETTINGKZ1X = 49.98"

$(KZ1Y range = 1.00 to49.98 in steps of 0.02)

Z1 & Z2 SETTINGKZ1Y = 49.98 !

Z1 & Z2 SETTINGKZ1Y = 49.98"

$


Z1 & Z2 SETTINGKZ2 = 49.98 !

Z1 & Z2 SETTING KZ2 = 49.98"

DISTANCE ZONE 3SETTING !

ZONE 3 SETTINGOFFSET!

ZONE 3 SETTINGOFFSET"

$

ZONE 3 SETTING REVERSELOOKING"

(KZ3'range = 0.2 to 49.9in steps of 0.1)

ZONE 3 SETTINGKZ3'= 49.9 !

ZONE 3 SETTINGKZ3'= 49.9"

(Only for $


O FFSET) ZONE 3 SETTINGKZ3= 49.98 !

ZONE 3 SETTINGKZ3= 49.98"

$

(LENT a/b range =1.00,0.67, 0.41)

ZONE 3 SETTINGLENT a/b = 1.00 !

ZONE 3 SETTINGLENT a/b = 1.00"

DISTANCESWCH ON TO FAULT !

SWCH ON TO FAULTENABLED !

SWCH ON TO FAULTENABLED"

$ $

SWCH ON TO FAULT

BLOCKED"

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DISTANCESETTINGS (O nly if ENABLED) SWCH ON TO FAULT SWCH ON TO FAULT

continued:- ENABLED IN 110s! ENABLED IN 110s"

SWCH ON TO FAULT$ ENABLED IN 0.2s"

SWCH ON TO FAULT SWCH ON TO FAULTBY COMPARATORS! BY COMPARATORS"

SWCH ON TO FAULTBY LEVEL DETECT"

SWCH ON TO FAULTBY LD OR COMP"

(Versions 111,112 &113 only) DISTANCEPwrSwg DETECTOR!PwrSwg DETECTORENABLED!

PwrSwg DETECTORENABLED"

$

PwrSwg DETECTORBLOCKED"

(O nly if ENABLED) PwrSwg DETECTOR PwrSwg DETECTOR TIMING Z6-->Z2! TIMING Z6-->Z2"

$

PwrSwg DETECTOR TIMING Z6-->Z3"

PwrSwg DETECTOR PwrSwg DETECTOR

To ALLOW Z1! To ALLOW Z1"$

PwrSwg DETECTOR To BLOCK Z1"

PwrSwg DETECTOR PwrSwg DETECTOR

To ALLOW Z1X! To ALLOW Z1X"

$

PwrSwg DETECTOR To BLOCK Z1X"

PwrSwg DETECTOR PwrSwg DETECTOR To ALLOW Z1Y ! To ALLOW Z1Y"

$PwrSwg DETECTOR

To BLOCK Z1Y"

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DISTANCE

SETTINGS continued

PwrSwg DETECTOR PwrSwg DETECTOR TO ALLOW Z2! TO ALLOW Z2"

$ PwrSwg DETECTOR TO BLOCK Z2"

PwrSwg DETECTOR PwrSwg DETECTOR TO ALLOW Z3! TO ALLOW Z3"

$

PwrSwg DETECTOR TO BLOCK Z3"

PwrSwg DETECTOR PwrSwg DETECTOR(TZ6 range = 20ms TZ6 = 90ms! TZ6 = 90ms"

to 90ms in steps 0f $

5ms) PwrSwg DETECTOR PwrSwg DETECTOR

KZ6 = 49.98! KZ6 = 49.98"

(KZ6 range = 1.00to

$

49.98 in steps of PwrSwg DETECTOR PwrSwg DETECTOR0.02) KZ6' = 49.9! KZ6' = 49.9"

$

(KZ6' range = 0.2 to PwrSwg DETECTOR PwrSwg DETECTOR 49.9 in steps of 0.1) LENT a/b = 1.00! LENT a/b = 1.00"

(LENT a/b = 1.00, 0.67, 0.41)

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SETTINGS BLOCKA/R ON BLOCK A/R ONBLOCK AUTORECLSE! Z1+AT 2&3Ph/F! Z1+AT 2&3Ph/F"

$ $

ALLOW A/R ONZ1+AT 2&3Ph/F"

BLOCK A/R ONZ1+AT 3Ph/F"

BLOCK A/R ON!

Z1X(T) TRIPBLOCK A/R ONZ1X(T) TRIP"

$

ALLOW A/R ONZ1X(T) TRIP"

BLOCK A/R ON!

Z1Y(T) TRIP

BLOCK A/R ON

Z1Y(T) TRIP"$

ALLOW A/R ONZ1Y(T) TRIP"

BLOCK A/R ONZ2(T) TRIP !

BLOCK A/R ONZ2(T) TRIP"

$

ALLOW A/R ONZ2(T) TRIP"

BLOCK A/R ONCHANNEL OUT !

BLOCK A/R ONCHANNEL OUT"

$

ALLOW A/R ON

CHANNEL OUT"

(Only for versions 111,112 & 114 with DEF)

BLOCK A/R ONDEF DELAY TRIP !

BLOCK A/R ONDEF DELAY TRIP"

$

ALLOW A/R ONDEF DELAY TRIP"

(Only for versions 111,112 & 114 with DEF)

BLOCK A/R ONDEF AIDED TRIP !

BLOCK A/R ONDEF AIDED TRIP"

ALLOW A/R ONDEF AIDED TRIP"

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SETTINGSVT SUPERVISION

VT SUPERVISION TO ALLOW TRIP!

VT SUPERVISION TO ALLOW TRIP"

$ $

VT SUPERVISION TO BLOCK TRIP"

VT SUPERVISIONSELF RESETTING!

SELF RESETTINGENABLED!

SELF RESETTINGENABLED"

SELF RESETTINGDISABLED"

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SETTINGSSTART INDICATION!!!!

START INDICATIONENABLED!

START INDICATIONENABLED"

$

START INDICATIONBLOCKED"

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(Only for versions111, 112 & 114 SETTINGSDEF !

DEFLOW SET !DEF LOW SET3 Io = 0.8 In !

DEF LOW SET3 Io = 0.8 In "

with DEF) $ $

DEFELEMENTS !

DEF ELEMENTSALL ENABLED !

DEF ELEMENTSALL ENABLED "

(3Io range = 0.05 to 0.8Inin 0.05 In steps)

$

DEF ELEMENTSALL BLOCKED "

(Only if ALL DEF ELEMENTS DEF DELAY TRIP DEF DELAY TRIPENABLED) DELAY TRIP ! ENABLED ! ENABLED "

$ $

DEF DELAY TRIP

BLOCKED "

(Only if

ENABLED)

DEF DELAY TRIP CURVE 1 !

DEF DELAY TRIPCURVE 1 "








DEF DELAY TRIPDEFINITE t = 2s "



8/9/2019 LFZP11x_R5911D




DEF SETTINGS continued:-DEF DELAY TRIP DEF DELAY TRIPMULT *t =1.000 ! MULT *t =1.000 "

$

DEF DELAY TRIP(*t range = 0.025 to 1.000 BASE SETTING !

in steps of 0.025)

DEF BASE SETTING DEF BASE SETTING(Is range = 0.05In to 1.20In Is = 1.20 In ! Is = 1.20 In "

in steps of 0.05

DEF ELEMENTS DEF POLARISING DEF POLARISINGPOLARISING ! NEGATIVE SEQ V ! NEGATIVE SEQ V"

$ DEF POLARISINGZERO SEQ I"

DEF POLARISINGZERO SEQ V "

DEF POLARISINGZERO SEQ V & I "

(THETA G range = 10° to80° in 10° steps)

DEF ELEMENTSANGLE !

DEF ANGLE THETA G = 80°!

DEF ANGLE THETA G = 80°"

$

DEF ELEMENTS DEF MAG INRUSH DEF MAG INRUSHMAG INRUSH ! STABILISER ON ! STABILISER ON"

DEF MAG INRUSHSTABILISER OFF"

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(Only for versions with fault locator fitted)

SETTINGS !!!!

FAULT LOCATORFAULT LOCATORREACH !

REACHKZF = 40.00 !

REACHKZF = 40.00"

$

(KZF range = 1 to 40 in0.01 steps.)

FAULT LOCATORLINE UNITS !

LINE UNITS= km !

LINE UNITS= km"

$

LINE UNITS= miles"

(LINE LENGTH -0 to 99.99 km or miles in steps of 0.01100 to 999.9 km or miles in steps of 0.1)

LINE UNITS= 100%"

(Only if km selected) FAULT LOCATORLINE LENGTH !

LINE LENGTH999.9 km !

LINE LENGTH999.9 km "

$

(Only if miles selected) FAULT LOCATORLINE LENGTH !

LINE LENGTH999.9 miles !

LINE LENGTH999.9 miles"

$

(Only if 100% selected) FAULT LOCATORLINE LENGTH= 100%

$

(CT ratio - 1:1 or 10:1 to 5000:1 in 10:1 steps)(VT ratio - 1:1 or 10:1 to 9990:1 in 10:1 steps)

FAULT LOCATORCT RATIO =5000:1 !

FAULT LOCATORCT RATIO =5000:1"

$

FAULT LOCATORVT RATIO =9990:1 !

FAULT LOCATORVT RATIO = 9990:1"

$

FAULT LOCATOR MUTUALCOMP !

MUTUAL COMPENABLED !

MUTUAL COMPENABLED"

$ MUTUAL COMPDISABLED "

(Only if MUTUAL MUTUAL COMP MUTUAL COMP( KZM range =0 to 1.360 in COMP ENABLED) KZM =1.360 ! KZM =1.360"

steps of 0.001)$

(THETA M range = 50° MUTUAL COMP MUTUAL COMPto 85° in 5° steps) THETA M = 85° ! THETA M = 85°

"

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SETTING TRAP

If no change made #

If change made #

Note, any changes made to TIME/DATE will not be ignored if RESET keyis pressed at the setting trap.

!

'Push SET to ' SET 'all changes ' !

'update group' 'updated'

#

RESET

'all changes ' !

'ignored' #

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Service Manaul R-5911DLFZP 11x Chapter 2

GlossaryPage 1 of 6

Glossary of terms

a/b Code bit Aspect ratio selection digital code

A/D Analogue to digital converter

ALE Address latch enable

BAR Block auto-reclose

B.P.Filter Band pass filter

COS BAR Channel Out-Of-Service block auto reclose

CK Clock

COS Channel Out-Of-Service

CpAZ1 Zone 1 A-N comparator

CRX Carrier receive

CTS Clear to send

CTX Carrier transmit

CVT Capacitor voltage transformer

DCE Data communication equipment

DEF Directional earth fault

DEF BU Directional earth fault back-up

DEF SOTF Directional earth fault switch-on-to-fault

DEF T BU Directional earth fault time delayed back-up

DSR Data set ready

DTE Data terminal equipment

DTR Data terminal ready

E Operation start signal for data read/write

E2PROM Electrically erasable and programmable read

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GlossaryPage 2 of 6

EEPROM only memory (e squared prom)

EPROM Electrically programmable read only memory

G/F Ground faults

IAR Resistive replica impedance (A phase)

IAZph Replica impedance voltage (A phase)

LCD Liquid crystal display

LDCpAZ1 Comparator gated with level detectors

(A phase, Zone1)

LDHSA Level detector high set (A phase)

LDHSI0 Level detector high set (I0)

LDLSA Level detector low set (A phase)

LDLSI0 Level detector low set (I0)

LDLSI2 Level detector low set (I2)

LDOVA Level detector over-voltage (A phase)

LDV0 Level detector zero sequence voltage

LED Light emitting diode

LGS Loss of guard signal

ModemModulator / demodulator

Mux Multiplexer

Osc Oscillator

PDA Pole dead A phase

P/F Phase faults

PORT 0 Main processor address/data port

PORT 2 Main processor address port

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GlossaryPage 3 of 6

PSB Power swing blocking

PSD Permissive scheme disable

PSEN * Program store enable

RAM Random access memory

RD * Read

RIA Relay inoperative alarm

RL29-31 Contact connected to case terminals 29-31

RS Signal to select register

RS232 An internationally recognised serialcommunications standard for the interfacebetween data terminal equipment (DTE) and datacommunication equipment (DCE)

RTS Request to send

R/W Signal to select read or write

RXD Received data

SOTF CNV Switch-on-to-fault current-no-volts

SOTF EN Switch-on-to-fault enable

SOTF TRIP Switch-on-to-fault trip

Timer 1 Scheme dependant commissioning test point

Timer 2 Scheme dependant commissioning test point

TXD Transmitted data

VA Voltage ac (A phase)

Vmem A Voltage memory (A phase)

Vpol A Polarising voltage (A phase)

VTS Voltage transformer supervision

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GlossaryPage 4 of 6

WI Weak infeed

WR * Write

Z1A Zone 1 (A phase)

Z1XS Scheme request Zone 1 extension

Z1XT Zone 1X time delayed Trip

Z1YT Zone 1Y time delayed Trip


Z2T Zone 2 time delayed Trip


Z3T Zone 3 time delayed Trip

* = Signals active low

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GlossaryPage 5 of 6

Figure G-1 Logic Symbols

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GlossaryPage 6 of 6

Figure G-2 Logic Symbols

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CHAPTER 3

INSTALLATION AND HANDLING

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LFZP 11x SERIES R-5911

SERVICE MANUAL CHAPTER 3

CONTENTS Page 1

1. RECEIVING........................................................................................................................... 2

2. HANDLING........................................................................................................................... 2

3. STORAGE ............................................................................................................................. 2

4. INSTALLATION................................................................................................................... 2

4.1 Rack mounting.................................................................................................................. 2

4.2 Panel mounting................................................................................................................. 3

4.3 Earthing ............................................................................................................................ 3

5. HANDLING PRECAUTIONS, STATIC ELECTRICITY DANGERS................................ 3

6. NOTES ON WIRING ............................................................................................................ 4

7. INPUT MODULE CALIBRATION...................................................................................... 4

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Page 2

INSTALLATION

Section 1. RECEIVING

Remove the relay from the container in which it is received and inspect for obvious

damage. If damage has been sustained in transit, a claim should be made immediately

to the transport company concerned and a report sent to the nearest GEC Alsthom

Protection and Control office or agent.

Section 2. HANDLING

The relay in its case is extremely robust and no special precautions are necessary.

However, to prevent the ingress of dirt, it is strongly advised that modules, or PCBs are

not removed from the case. If the front plate is opened, care should be taken when it is

reclosed, to fully locate the 64 way connector between the processor PCB (slot #11)

and the front plate PCB, before the front plate screw is tightened. This can be achieved

by pressing firmly on the frontplate directly infront of the connector.

Section 3. STORAGE

If not required for immediate use, return the relay to its original wrapper and carton and

store in a clean dry place. The silica gel unit supplied with the relays delivered outside

the United Kingdom should be heated at 60°-70°C for one hour before being replaced.

Section 4. INSTALLATION

Relays should be installed in a location free from excessive vibration. The relay cases

can be supplied for either rack or panel mounting.

4.1 Rack mounting

Relays for rack mounting are supplied in cases designed for housing in standard 19 inch

(483 mm) racks.

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Page 3

4.2 Panel mounting

Relays can be supplied for either flush or semi-projecting panel mounting. Panels

should be vertical to within 5°. Dimension, fixing details and cut-out sizes for the cases

are shown in the relevant case outline drawing.

Flush mounted relays are inserted from the front into the panel cut-out and secured by

means of nuts and bolts through holes in the upper and lower flanges in the relay and

corresponding holes in the panel.

Semi-projecting mounted relays are fitted with an extending collar and are otherwise

secured using the same means as those described for the flush mounted relays.

When installation is complete the relays must be set up and commissioned as described

in the relevant instructions.

4.3 Earthing

The relay case earthing terminal on the rear of the relay case must be connected to earth

(ground).

Section 5. HANDLING PRECAUTIONS, STATIC ELECTRICITY DANGERS

The modules/boards in Optimho contain circuitry which consists of devices that have

been manufactured by the CMOS process (Complementary Metal Oxide Silicon).

CMOS devices are susceptible to damage due to static discharge and for this reason it is

essential that the correct handling procedure is followed:-

The following procedure is recommended when handling all modules:-

1. Before removing modules from the Optimho case, the operator should firstlyground himself to the relay case, in order to remove any static charge

difference between the operator and the Optimho.

2. Modules should only be handled by holding the module frontplate, or board

edges, the board assemblies must not be "grasped".

3. Modules must not be passed from one person to another unless both persons

are grounded.

4. Do not place modules in polystyrene trays.

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Page 4

Section 6. Notes on wiring

In the event of a power supply failure access is required to the back pack. This would

be assisted if the wiring loom does not run across the back pack.

Section 7. Input module calibration

The calibration of the boards in the input module is related to the specific current and

voltage transformers in that module. Therefore, under no circumstances should the

boards be replaced with boards from another module without the module beingrecalibrated.

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CHAPTER 4

COMMISSIONING

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Service Manual R5911DLFZP11x Chapter 4

ContentsPage 1 of 3

Page

1. GENERAL NOTES 1

2. TEST EQUIPMENT REQUIRED 13. PRELIMINARY INSTRUCTIONS 23.1 Wiring 23.2 Rating details 23.3 CT shorting contacts 23.4 Insulationtest 64. SECONDARY INJECTION TESTS (MAIN) 64.1 Isolation 64.2 Initial Checks 74.3 Settings 74.4 Test plugs 8

4.5 Level detector checks 84.5.1 Voltage level detectors 84.5.2 Fixed current level detectors 94.5.3 Biased high set and low set residual current level detectors 104.6 Reach and fault location checks 114.6.1 Fault locator 124.6.2 Ground faults zone 1 134.6.3 Phase faults zone 1 144.6.4 Zone 1X reach (If applicable) 144.6.5 Zone 1Y reach (If applicable) 144.6.6 Zone 2 reach checks 15

4.6.7 Zone 3 reach checks (Not fitted on LFZP 114) 154.6.8 Resistive reach check (If quadrilateral characteristic is applicable)164.7 Operation times 164.7.1 Zone 1 operation times 164.7.2 Zone 1X operation time (If applicable) 174.7.3 Zone 1Y operation (if applicable) 174.7.4 Zone 2 operation time 174.7.5 Zone 3 operation time 174.8 Power swing blocking checks 184.8.1 Zone 6 reach check 194.8.2 TZ6 time 19

4.8.3 Simulated power swing with blocking checks 204.9 Voltage transformer supervision 204.9.1 Operation on zero sequence volts 204.9.2 Timing check 204.9.3 Instantaneous indication 204.9.4 Blocking check 214.10 Switch on to fault 214.11 Memory feature (Synchronous polarising) 214.12 Loss of load accelerated trip feature 254.13 Fault location using mutual compensation 26

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ContentsPage 2 of 3

Page

5 SECONDARY INJECTION TESTS (SCHEME) 295.1 Zone 1 extension 29

5.2 Permissive under-reach 305.2.1 Aided trip check 305.2.2 Signal send checks 305.2.3 TDW timer (Unblocking scheme only) 305.2.4 Channel out of service 305.3 Permissive overreach 315.3.1 Aided trip check 315.3.2 Signal send checks 315.3.3 TP and TD timer checks 315.3.4 TDW timer (unblocking schemes only) 335.3.5 Echo feature (POR 1 or POR 2) 34

5.3.6 Weak infeed echo (POR 2) 345.3.7 Weak infeed trip (POR 2) if selected 355.3.8 Channel out of service 355.4 Blocking scheme (see section 5.5 for blocking 2 scheme) 355.4.1 Measurement of TP 365.4.2 Measurement of TD

365.4.3 Signal send check 375.4.4 Channel out of service check 375..5 Blocking 2 scheme 375.5.1 Measurement of TP and distance aided trip test 38

5.5.2 Measurement of TD and signal start check 395.5.3 Channel out of service check 395.6 Signalling channel check 396 DIRECTIONAL EARTH FAULT (DEF) IF FITTED 406.1 Current level detectors 406.2 Mag inrush detector 416.3 Back up time delay 416.3.1 Current sensitivity 416.3.2 Operation time 426.4 DEF aided tripping 446.4.1 POR 1 or POR 2 1 unblock 44

6.4.2 POR 2 (any version) 476.4.3 Blocking 476.4.4 Blocking 2 476.4.5 Aided trip check 486.4.6 Channel out of service check 487 LIVE SYSTEM CHECKS 497.1 Signalling channel check 497.2 Trip test 497.3 Final setting checks 507.4 On load checks 51

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ContentsPage 3 of 3

Page

7.4.1 Voltage transformer checks 51

7.4.2 CT/VT phasing check 517.4.3 Directional check 53

COMMISSIONING TEST RESULT SHEETS 57

Figure 1 Recommended MMLG test block connections for optimho 11Xrelays

Figure 1a Normal test plug connections for secondary injectionFigure 2 Test plug connection for on load test CT/VT phasing

Figure 3 VTS instataneous indicationFigure 4 Memory feature (Synchronous polarising)Figure 5 Test plug connections for secondary injection test of mutual

compensation setting on the fault locatorFigure 6 Connections to prove polarity of panel wiring for mutual

compensation on the fault locatorFigure 7 Def simulated mag inrush currentFigure 8a Lec characteristicsFigure 8b American CharacteristicsFigure 9 Determination of the load angle from load informationFigure 10 Vector diagram on load directional check

Figure 11 Test plug connections for on load test current reversal

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Page 1 of 70

Section 1. GENERAL NOTES

The commissioning engineer should be supplied with all the required settings forthe relay.

The type of test set used for commissioning should ideally be capable of producingthree phase dynamic faults, ie. capable of switching from a prefault conditionsimulating normal load conditions, to that of a fault condition. It is possible to testthe relay with non-dynamic test equipment, though some care must be exercised inthe interpreting of the test results, as a non-dynamic test set may give rise to largerthan expected errors. It is possible to test some functions of the relay with non-dynamic test equipment.

Although not essential, the use of a computer running the Opticom software mayaid with commissioning the relay.

The tolerances quoted throughout this chapter make no allowance forinstrumentation errors.

Section 2. TEST EQUIPMENT REQUIRED

a) 1 three phase dynamic test set

b) 1 interval timer capable of being triggered by a contact or a 5V signaland able to measure dwell times.

c) 2 Multimeters (20,000 Ω/V on dc ranges)

d) 1 high impedance digital voltmeter

e) 1 variable auto transformer capable of supplying

f) 1 variable resistor 0-200Ω rated current

g) 3 double pole switches

h) 1 variable resistor 10kΩ

i) 1 Optimho monitor point box

j) 1 dc. power supply (if panel supply unavailable)

k) 2 MMLB01 test plugs (if MMLG test blocks are used)

l) 1 phase rotation meter

m) 1 phase angle meter

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Page 2 of 70

n) 1 electronic insulation tester (if panel wiring is to be checked)

o) 2 diodes rated 10A at 600V (only required if the magnetising inrush

detector test is required to be done when the DEF is fitted)

Section 3. PRELIMINARY INSTRUCTIONS

Test result sheets are provided in Appendix B

3.1 Wiring

Check that the external wiring is correct to the relevant external connectiondiagram and/or scheme diagram. If test blocks type MMLG are provided, theconnections should be checked to the scheme diagram particularly that the supply

connections are to the live side of the test block (coloured orange and allocatedwith odd numbered terminals 1, 3, 5, 7 etc.). See Figure 1 for recommendedconnections.

3.2 Rating details

Check that the ratings for frequency, current, ac volts, auxiliary dc supplies Vx(1)and Vx(2) are correct. These will appear on the nameplate on the front of therelay.

Note: Auxiliary dc supply Vx(1) and opto isolator supply Vx(2) may bedifferent. If Vx(2) supply is 220/250V an external box GJ0229002 containing 7 resistors will be required.

3.3 CT shorting contacts

Observing electro static discharge precautions (i.e. wear an earthed wrist strap ortouch earth and only handle the module by the front plate and board edges) andensuring that all dc supplies are isolated from the relay, open the relay front panel.

Remove the input module (on the right hand side using the handle provided) andcheck that the contact block within the case is fitted with CT shorting contacts. Thefollowing pairs of terminals will be provided with shorting facilities 19 and 20, 21and 22, 23 and 24, 25 and 26, 27 and 28. If the MMLB test blocks are fitted therelay is easily isolated from its supply CT’s using Figure 2 Test Plug 1 connection.

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Page 3 of 70

1 2

43

65

87

109

1211

1413

1615

1817

2019

2221

2423

2625

2827

MMLG 01

TEST BLOCK 1

IA

BI

CI

VA

BV

CV

19

20

21

22

23

24

13

14

49

51

25

26

27

28

18

17

16

15

79

77

78

74

70

66

62

58

TEST BLOCK 2

MMLG 01

27 28

25 26

23 24

21 22

19 20

17 18

15 16

13 14

11 12

9 10

7 8

5 6

3 4

21

DIRECTION OF POWER FLOW

FOR OPERATION

P2

S2

P1

S1

IN

P2 S2

P1 S1

DEFCURRENT

POLARISATION

84

80

76

72

68

64

60

SIGNAL

SEND

O

P

T

I

M

H

O

ANY TRIP

DC SUPPLY+

-

RESET ZONE 1 EXTENSION / LOSS OF GUARD

BREAKER OPEN

CHANNEL OUT OF SERVICE

CARRIER RECEIVE

RELAY BLOCKED

* SINGLE POLE OPEN

* INHIBITS PSB,DEF

NOTE:

IF DEF CURRENT POLARISATION

IS NOT REQUIRED THE SAME

INPUT TERMINALS CAN BE USED

TO PROVIDE MUTUAL COMPENSATION

FOR THE FAULT LOCATOR

NV

Figure 1 Recommended MMLG test block connections for Optimho 11X relays

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Page 4 of 70

INSERTED

THE TEST PLUG IS

MUST BE MADE BEFORE

THESE CONNECTIONS

I

12

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

MMLB 01

TEST PLUG 2

TEST PLUG 1

MMLB 01

2728

2526

2324

2122

1920

1718

1516

1314

1112

910

78

56

34

2 1A

BI

CI

IN

polIDEF ORFAULT LOCATOR

MUTUAL COMPENSATION

A

B

C

N

V

V

V

V

THESE CONNECTIONS

MUST BE MADE AFTER

THE TEST PLUG ISINSERTED

VX1CHECK VOLTS

BEFORE LINKING

Figure 1a Normal test plug connections for secondary injection

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Page 5 of 70

INSERTED

THE TEST PLUG IS

MUST BE MADE BEFORE

THESE CONNECTIONS

12

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

MMLB 01TEST PLUG 2

TEST PLUG 1

MMLB 01

2728

2526

2324

2122

1920

1718

1516

13141112

910

78

56

34

2 1

-+

CURRENT COIL

PHASE ANGLE METER

PHASE ANGLE METER

VOLTAGE COIL

+-

Figure 2 Test plug connection for on load test CT / VT phasing

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Page 6 of 70

Pass current through each pair of contacts to ensure a circuit is indicated or checkthat a low resistance is measured.

The equipment label is on the back of the front panel and gives PCB/Module

identification numbers. These numbers are needed if replacements are everrequired. The external connection diagram number is also given (10 LFZP11 0 )

SAFETY ADVICEDO NOT OPEN CIRCUIT THE SECONDARY CIRCUIT OF A CURRENTTRANSFORMER SINCE THE HIGH VOLTAGE PRODUCED MAY BE LETHALAND COULD DAMAGE INSULATION.

When type MMLG test block facilities are installed it is essential that the sockets inthe type MMLB01 test plug which correspond to the current transformer secondarywindings are LINKED BEFORE THE TEST PLUG IS INSERTED INTO THE TEST

BLOCK . Similarly, an MMLB02 single finger test plug must be terminated with anammeter BEFORE IT IS INSERTED to monitor CT secondary currents.

3.4 Insulation test

This test may be done by the main plant contractor at an earlier date. Anelectronic or brushless insulation tester should be used having a dc output notexceeding 1000V.

Deliberate circuit earthing links removed for these tests must subsequently bereplaced. The relay and associated wiring may be tested between :

a) All electrical isolated circuits

b) All circuits and earth

Accessible terminals of the same circuit should first be strapped together.

SECTION 4. SECONDARY INJECTION TESTS (MAIN)

4.1 Isolation

All the relay contacts can be prevented from operating while the rest of the relayfunctions normally and gives indications also signals for operation times may betaken from the monitor point box. It is, however, necessary to check the operationof contacts during commissioning so alternative trip isolation must be obtained asnecessary.

It is possible to inhibit all contacts, except ANY TRIP if only secondary injection testsare being performed rather than full commissioning. See Chapter 2 Appendix Afor the menu tree plan.

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Page 7 of 70

4.2 Initial checks

If the dc supplies are available on the panel they should be checked for correctpolarity and voltage before linking through to the relay. If the panel supply isunavailable, a suitable supply should be connected to the relay side of the test

block.

On power up it will be observed that the red and yellow LED's (trip and alarmrespectively) will flash on and then off once, followed by the green LED (relayavailable) lighting and remaining on. The power up process takes about 700ms.

Check the Relay Inoperative Alarm contact (RIA) is open.

Note 1: On power up the LCD will display the prompt "Please Set CALENDARCLOCK". It is not necessary to conform to this prompt, however, toprevent confusion it should now be set.

It should be noted that if the dc auxiliary supply Vx(1) is removed the CALENDARCLOCK will have to be reset.

Note 2: If after power up the relay inoperative alarm contact closes and there isan error on the LCD, investigation is required. If the watchdogsystem has found a problem an appropriate error message will beseen on the LCD.

4.3 Settings

When commissioning an Optimho for the first time the engineer should allow anhour to get familiar with the menu.

All settings on the optimho are by means of a built in keypad, and the settingsshould now be entered. It is recommended that the final service settings are usedduring commissioning. The software version number should be checked (in menuunder identifiers), reference should then be made Chapter 2 ‘output connections’for standard models, or Chapter 5 for special models, for the contactconfiguration tables. The chosen contact configuration should then be checkedagainst the wiring diagram.

Note: The menu returns to the default display' or `press set to updatechanges' if left in another part of the menu for 15 minutes or longer.

The relay can store eight independent groups of settings identified as group 1 to 8.Ensure that group 1 is selected for the first or only new set of settings to beentered. The user can select the default display to be either a blank display, thegroup identification code or the active group number selected.

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Page 8 of 70

The user has to decide what commissioning is necessary for any additional settinggroups that will be used. If only different zone reaches are involved then the usermay select to test the appropriate settings. Alternatively having proved that correctsettings can be selected by the menu then for additional groups of settings it may

only be necessary to obtain a record or printout of the selections. Alternatively acomplete repetition of the commissioning procedure for each additional groupused may be required by some users.

4.4 Test plugs

If GEC ALSTHOM T&D P&C MMLG 01 Test Blocks are installed, it isrecommended that they are wired as shown in Figure 1 and the test plug typeMMLB 01 wired for normal secondary injection as shown in Figure 1a.

4.5 Level detector checks

4.5.1 Voltage level detectors

Each phase to ground input voltage is monitored and the pick up of the leveldetector is fixed at 44.5V (± 10%).

Select monitor option 06. (The protection logic is fully functional when in monitoroptions).

Apply volts in turn to each voltage input and determine the pick up and drop off of each level detector.

Pick up is indicated by a `1' appearing on the LCD in the appropriate column asshown below.

LCD POSITION/SOCKET NO

MONTIOR 2 3 4 5 6 7 8 9

OPT 06 A B C

Drop off should be within 20% of pick up.

The 25 way Optimho monitor point box may also be used. This should be pluggedinto the `Parallel' socket on the front of the relay. The numbered sockets of the boxcorrespond exactly to the numbers indicated on the LCD. A voltage of 5V willappear on the appropriate socket, No 22 being OV. A high impedance digitalvoltmeter must be used.

The monitor point box has the added advantage that the data is on the box all thetime once a monitor option has been selected even if the relay is in another part of the menu.

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Page 9 of 70

4.5.2 Fixed current level detectors

i) Low set

Each phase current is monitored, and the pickup of the level detector is dependenton the setting of KZPh, the most sensitive value being 5% of In.

The pick up is given by:

5 x 1 x In Amps ± 10%100 KZPh

If the supply contains significant harmonics results outside this tolerance may beobtained.

Select monitor option 06

Inject current in turn into each pair of phase termination's and determine the pickup and drop off of each level detector. The drop off should be within 20% of pickup.

LCD POSITIONS/SOCKET NO

MONTIOR 2 3 4 5 6 7 8 9

OPT 06 A B C

Note: The biased neutral level detector will operate at the same value. If thebiased neutral low - set level detector operates, for a period of fiveseconds continuously, without the operation of one of the following :

a) Any pole dead

b) Any zone comparator

c) The Vo level detector

d) Single pole open opto - isolator

then the relay will respond by closing the "Relay Inoperative Alarm" contact andextinguishing the "Relay Available" LED. The main micro controller writes themessage:

,,ERROR# I∼FAIL

,,

to the fault diagnostic page on the LCD

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Page 10 of 70

The relay calculates the neutral current from the vector addition of phase currents. Thus the message may be created during commissioning but will automaticallyreset and can be ignored in these circumstances.

When an 'error' message is given closure of the inoperative alarm contact onlymeans investigation is necessary NOT that the relay has been taken out of service.

ii) High Set

current setting is given by:

7.5 x 1 x In Amps ± 10%100 KZPh


Inject current as above and determine the pick up and drop off. Drop off to bewithin 20% of pick up.

LCD Position/Socket No

MONTIOR 2 3 4 5 6 7 8 9

OPT 07 A B C

4.5.3 Biased high set and low set residual current level detectors

The biasing only comes into action when a minimum phase difference current isexceeded. The residual signal is derived by summing the vectors of the voltages inthe relay which are proportional to the phase currents.

The operation level when biasing varies directly with the highest phase differencecurrent until a limit is reached. The minimum operate level varies inversely withKZPh. In commissioning it is only necessary to check this fixed level.

i) Low set

The minimum operate current is given by:



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Page 11 of 70

Inject current in turn into each pair of phase termination's and determine the pickup and drop off of each level detector. The drop off should be within 20% of pickup.

LCD POSITIONS/SOCKET NO

MONTIOR 2 3 4 5 6 7 8 9

OPT 06 N

ii) High set

The minimum operate current is given by:



Inject current as above and determine the pick up and drop off. Drop off to bewithin 20% of pick up.


MONTIOR 2 3 4 5 6 7 8 9

OPT 07 N

4.6 Reach and fault location checks

Connections and preliminaries

The relay should now be connected to equipment able to supply phase to neutralvolts and current in the correct phase relation for a particular type of fault on theselected relay characteristic angle. The facility for altering the loop impedance(phase + ground fault compensation or phase-phase) presented to the relay is

essential, this may be a continuous adjustment or steps of around 1% in thevoltage or current.

Connect the test equipment to the relay via the test block(s) taking care not to opencircuit any CT secondary. If MMLG type test blocks are used, the live side of the testplug must be provided with shorting links before it is inserted into the test block.

VT Supervision should be set "TO ALLOW TRIP", giving indication only.

It may prove useful if "START INDICATION" is "ENABLED" which will speed up the

process of determining the reaches.

4.6.1 Fault locator

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If the fault locator is fitted checks can be done on its location readings whilechecking Zone 1 reaches. The location reading is based on the secondary ohmsetting being unaffected by whatever CT and VT ratios are selected in the faultlocator part of the menu its only reach setting KZF sets the line length in ohms.Locations can be selected to be given in percentages, miles or kilometres.

If Zone 1 is set to 80% of the line then KZF is set to 1.25 x KZ1.

If miles or kilometres have been set just multiply the line length by the abovepercentage to check the location given for the Zone 1 reach.

Pressing the ACCEPT/READ' key after a fault brings up the fault location, thealarm LED then ceases to flash and the indications could be reset, however,continued pressing of the ACCEPT/READ' key will display all the pre-fault andfault information. Time delayed trips will have no pre-fault information available if starts are not enabled.

Reverse faults will give a negative reading but locations given should be regardedas a guide only. SOTF trips will give a location and the fault information willindicate the faulted phase or phases.

Note: The fault locator has five cyclic buffers for acquired data. At any moment intime one buffer must be in use for acquiring new data thus the fault locator canstore raw data for up to four faults.If more than four faults occur within a 20 second period the fault locator mayignore faults until a fault data buffer is free. In this situation if data from a previousfault exists in the buffer it will be available with the new fault type and timeinformation which will always be correct.

Note: If mutual compensation is to be used on the fault locator see Section 4.13.

4.6.2 Ground faults zone 1

If the Zone 1 Extension or Blocking scheme is selected read 5.1 or 5.4 beforeproceeding.

Commence with connections for an A-N fault. The appropriate loop impedance isgiven by:

(KZPh + KZN) x KZ1 x 5 OHMS (See later if THETA Ph and THETA N In differ by more than 5°)

(See note 2 for LFZP113)

Apply an impedance slightly greater than above momentarily to the relay. If STARTINDICATION has been ENABLED and impedance is outside Zone 1, the LCD will

indicate START AN (for the enabled forward zones). DEF start will also be obtainedif fitted and enabled. If START INDICATION has been BLOCKED, the LCD willremain unchanged.

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Make small adjustments, say 1%, to the impedance and re-apply to the relay untilthe highest impedance which gives the indication Z1 AN occurs.

Note 1: If the Circuit Breaker Open optical isolator input is connected then all

faults can appear as SOTF. Appropriate action must be taken toprevent the optical isolator input from being energised. This is easilydone if the recommended test blocks are used.

Note 2: The loop impedance required for the LFZP113 version is half that givenby all the formulae in Section 4.6 as the nameplate formulae have adivide by 2 factor.

It will also be seen that the ALARM LED will flash continuously and the TRIP LED willlight. The trip may now be accepted by pressing the ACCEPT/READ key (twopresses will be necessary if the fault locator is fitted, the second press will only be

effective when the fault location calculation is finished, this may be 3 seconds forone fault and much longer for a series of faults) which will cause the ALARM LEDto stop flashing and become continuously illuminated. Pressing the RESET key willextinguish the ALARM and TRIP LED's and clear the fault information on the LCD.

However, any new event is automatically displayed and the previous 3 stored formenu recall.

The measured impedance should be within 10% of the calculated value assumingthe angle of the impedance presented is within 5° of THETA Ph and N as set onthe relay. If the angle difference is greater then KZN and KZPH must be addedvectorially before applying the appropriate zone multiplier.

Check the appropriate contacts operate, for single or three phase tripping asselected. In particular check the ANY TRIP contact and the Block Auto-reclose (BAR)contact.

Change the direction of the current and ensure that the relay does not operate(check with a close up fault briefly applied).

Repeat the above tests for the other two phases i.e. B-N and C-N.

4.6.3 Phase faults Zone 1

The appropriate loop impedance is now given by:

2 x KZPh x KZ1 x 5 OHMS In

Carry out the tests as for ground faults for A-B, B-C and C-A faults. Undercommissioning conditions the measured values should be within 10% of thecalculated values.

4.6.4 Zone 1X reach (If applicable)

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The ground fault loop impedance required is given by:

(KZPh + KZN) x KZ1X x 5 OHMS In

and for phase to phase faults the loop impedance required is given by:-

2 x KZPh x KZ1X x 5 OHMS In

The reach for each phase to ground and phase to phase element of the relayshould be checked and the operation of the appropriate contacts confirmed.

4.6.5 Zone 1Y reach (If applicable)

The ground fault loop impedance required is given by:

(KZPh + KZN) x KZ1Y x 5 OHMS In

and for phase to phase faults the loop impedance required is given by:

2 x KZPh x KZ1Y x 5 OHMS In

The reach for each phase to ground and phase to phase element of the relayshould be checked and the operation of the appropriate contacts confirmed.

4.6.6 Zone 2 reach checks

The ground fault loop impedance required is:

(KZPh + KZN) x KZ2 x 5 OHMS In

and for phase to phase faults the loop impedance required is given by:


The reach for each phase-ground and phase-phase element of the relay should bechecked and the operation of the appropriate contacts confirmed.

4.6.7 Zone 3 reach checks (not fitted on LFZP114)

Zone 3 has the facility for setting forward and reverse reaches of the line angle upto the same impedance. There are three possible shapes of characteristic availablethese being circular or lenticular for phase faults or ground faults plus

quadrilateral for ground faults.

The aspect ratio of the lenticular characteristic can be set to either 1.0, 0.67 or0.41.

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The quadrilateral resistive reach will be dealt with later.

The ground fault loop impedance for forward checks is:

(KZPh + KZN) x KZ3 x 5 OHMS Inand for reverse ground faults is :

(KZPh + KZN) x KZ3' x 5 OHMS In

The phase fault loop for forward checks is


and for reverse phase faults

2 x KZPh x KZ3' x 5 OHMS In

The reach checks should be performed for each element of the relay and theappropriate outgoing contacts checked.

4.6.8 Resistive reach check (If quadrilateral characteristic is applicable)

Checks are done using resistive faults, thus in the forward direction all zones willoperate at the same loop impedance.

The loop resistance for forward faults will be

RR = KR x 5 OHMS (This reach is common to all zones but In only Z1 will be indicated. See note below).

and for reverse resistive faults (applicable to Zone 3 only) will be

RR' = KR x 6 OHMS In

The checks should be done for all phase to ground faults and results should bewithin 15% of the selected settings.

Note: Indication locks to first zone giving trip and can only change when anew event occurs, therefore Zone 1 indication of operation will begiven on the LCD, for Zone 2, indication will be given by selectingmonitor option 12 and observing LCD positions 2, 3 and 4 for A, Band C ground faults respectively. For Zone 3, monitor option 13should be selected, LCD positions 2, 3 and 4 indicating A, B and Cground faults respectively.

4.7 Operation times

4.7.1 Zone 1 operation times

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Zone 1 operation times should be checked by applying a fault at 50%(approximately) of Zone 1 reach.

An interval timer should be started when the fault is applied and stopped by asuitable pair of contacts.

The following points should be noted:

a) To obtain 'correct' operating times, it is essential to use dynamic testsstarting with all phase to neutral voltages above the level detectorsetting. If this is not done, filters in the voltage and current circuits willalready be switched in and operation times will be slower up to20ms.

b) If the polarising quantities are not correctly provided by the test set, someslower times may be measured. This may be noticed when doing phase

to phase faults.

c) Times vary with the point-on-wave of fault application. It is thussuggested that 10 operations be done for each type of fault and themean value recorded.

d) Times vary with the type of characteristic, typical times being

(a) Shaped Mho 15-30ms(b) Quadrilateral 20-35ms

If the polarising quantities are not correct or if the voltage filters are in initiallytimes may increase by 10-20ms. Times on 60Hz relays are approximately 10%faster.

4.7.2 Zone 1X operation time (If applicable)

Apply a fault midway between Zone 1X and the next inward zone and check theoperation time. This need only be done for one type of fault. The time measuredwill be that of the software timer plus the comparator time plus the output contactoperation

The actual measured time should be within 60ms of the set time. Check for correctindication and contact operation.

Note: Z1X does not have to be smaller than Z1Y but they must both be setsmaller than the largest forward looking zone. Time stepped zoneoperation times include the operation times of two comparators.

4.7.3 Zone 1Y operation (if applicable)

Apply a fault midway between Zone 1Y and the next inward zone and check as in

4.7.2 Check for correct indications and contact operations.

4.7.4 Zone 2 operation time

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Apply a fault midway between Zone 2 and the next inward zone and check theoperation time as in 4.7.2 The measured time should be within 40ms of the settime. Check for correct indication and contact operation.

4.7.5 Zone 3 operation time

Apply a fault midway between Zone 3 and the next inward zone and check theoperation time as in 4.7.2

Check for correct indication and contact operation.

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4.8 Power swing blocking checks

If this feature is to be used it should now be enabled. Also enable the power swingtest within the commissioning menu. Remember the selection is not made until thesetting trap update is done

The feature works for comparators on A-B only and utilises Zone 6. the outerboundary, Zone 6, can be set around Zone 2 or Zone 3.

A power swing is detected when the transfer time of an impedance from Zone 6 tothe inner zone exceeds the setting of Zone 6 timer TZ6.

Note: If Zone 6 is set around Zone 2 and Zone 3 is reverse looking, it is notpossible to completely block Zone 3.

If set around Zone 3, and the Lenticular characteristic is selected, it is usual to have

the aspect ratios set the same.

The recommended settings for the Power Swing Blocking characteristic Zone 6forward and reverse reach can be obtained from the following expressions:

With Zone 3 set looking in the forward direction:

Z6 forward reach = 1.3 x Z3 forward reachZ6 reverse reach = 0.3 x Z3 forward reach + Z3 reverse reach

With Zone 3 set looking in the reverse direction:

Z6 forward reach = 1.3 x Z2 forward reachZ6 reverse reach = 0.3 x Z2 forward reach

With these impedance settings, the recommended timer setter TZ6 is 50ms.

4.8.1 Zone 6 reach check

The loop impedance required for checking the forward boundary is given by:

2 x KZPh x KZ6 x 5 OHMS I

nand for the reverse boundary:

2 x KZPh x KZ6' x 5 OHMS In

Select monitor option 08.

The above impedance's must be prepared as A-B faults. The boundary may bedetermined either by momentarily applying the fault' or by gradually decreasingthe impedance until the A-B comparators pick up as indicated.

LCD POSITION/SOCKET NO

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MONTIOR 2 3 4 5 6 7 8 9

OPT 08 1

The measured impedance should be within 10% of the calculated value.

4.8.2 TZ6 Time

Select monitor option 08 and insert the monitor box into the "parallel" socket onthe front of the relay. Arrange a timer capable of working off 5V levels to start onsocket 8 (going 0 to 5V) and stop on socket 9 (going 0 to 5V), 22 being common.(The timer should be set to `Break for Start' and `Break for Stop').

Apply an impedance midway between Zone 6 and Zone 2 or 3 as appropriate. The timer will start when comparator A-B picks up and will stop when TZ6 time hasexpired.

The time measured should be TZ6 ± 10%

4.8.3 Simulated power swing with blocking checks.

Return to the default display `Power Swing Test Enabled'.

It is now necessary to simulate a power swing for the A-B element of the relay.Apply an impedance just outside Zone 2 or 3 as appropriate and reduce it withoutswitching off (say 1% steps) until power swing indication is given, check that thePSB alarm contact also closes. Re-select monitor option 08 which makes availableinformation on all zones giving trip outputs after any set time delays:


MONTIOR 2 3 4 5 6 7 8 9

OPT 08 Z1 Z1XT Z1YT Z2T Z3T

With this it is easy to check which zones are being blocked by the PSB feature inthe menu selection. The power swing will be simulated by applying an A-B fault

just outside Zone 3 or Zone 2 as appropriate, moving the fault to just inside thezone and then moving it again to inside Zone 1.

Apply the fault used in 4.8.3 and again move in to just inside Zone 2 or Zone 3 asappropriate and then move the fault again to inside Zone 1 in less time than thelowest time delay setting.

Only the forward zones not blocked by the PSB feature will change form 0 to 1 onthe LCD display.

Note: It may help to provide a temporary increase to the time delays.

If a close up fault is applied from a volts only condition then all forward zones

enabled in the 'distance' part of the MENU will be seen as operating. Indicationsfor operation of the time stepped comparator zones are latched in this monitoroption.

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4.9 Voltage transformer supervision

Operation occurs when zero sequence voltage above a set level is detected withoutany zero sequence current being detected above a set level. If set `TO ALLOW

TRIP', instantaneous indication will be given if operation conditions are satisfied

and a comparator is operated, otherwise time delayed indication will be given. If set for blocking, blocking can take place instantaneously if a comparator operatesand the indication will be (RELAY BLOCKED V~ FAIL). The relays have the facilityfor self resetting of the VTS alarm contact and relay blocking. This feature can beenabled or disabled via the menu.

4.9.1 Operation on Zero sequence volts

The operation time is 5.5 seconds± 0.1 seconds. The zero sequence voltagesetting is 15% of 63.5V, thus the required voltage reduction on one phase is 45%of 63.5V (28.6V ± 20%).

Apply balanced 3 phase-neutral volts and reduce the voltage on one phase untilV~ FAIL indication is given. The reduction in one phase-neutral voltage requiredfor operation should be between 22.9 and 34.3 volts, (ie the measured voltageabout 29 to 40 volts).

4.9.2 Timing check

Timing is checked by using a double pole switch to remove one healthy voltageand start a timer which is stopped by the VTS alarm contact. The time obtainedshould be as stated above.

4.9.3 Instantaneous indication

To perform this check it is necessary to provide the relay with zero sequencevoltage but no zero sequence current, and a Zone 1 comparator operation.

This can be acheived by applying a prefault condition of two phases of nominalvoltage, and one phase where the voltage is below the VTS detector setting. Thecurrent inputs can either be zero, or a balanced condition. Then before the VTS 5.5second time delay has elapsed switch to a Zone 1 fault condition. Instantaneous V~ FAIL indication should be given.

For a test with three phase volts and a single phase

Note 1: If a pole dead is seen before and not during the fault VTS operationwill be delayed by 240ms.

Note 2: Any fault locator position information should be ignored during thesetests due to the abnormal connections.

4.9.4 Blocking check

If VTS is now set to BLOCK TRIP, check that the indication RELAY BLOCKED isobtained when the above conditions are satisfied and no trip is given. The `RELAY

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BLOCKED' indication can not be reset or other information viewed (other than dateand time of V~ FAIL) until normal volts are restored.

If self resetting has been selected in the menu the RELAY BLOCKED indication willautomatically reset when volts are restored leaving the V~ FAIL indication only.

If `blocking' is to be used only select it after all tests are finished.

4.10 Switch on to fault

The feature is enabled when all poles have been dead for either 200ms or 110sas selected by the menu.

When the poles dead signal goes off, the feature remains available for 250ms. To check, go from a poles dead condition to a fault condition and arrange a timerto start when the fault is applied and to stop when the SOTF Alarm contact closes.

Confirm SOTF indication is given. Note, no phase indication is given, however anyphase information from the last event is retained.

The time obtained should be less than 40ms.

(Times will be faster if comparator operation is selected for SOTF trips).

If SOTF is set to be enabled after 110 sec then this period of time must elapsebefore another shot is attempted.

If Busbar VTs are to be used, BREAKER OPEN opto isolator input should beenergised. Faults can then be applied in the normal way giving SOTF indicationand the times already indicated.

4.11 Memory feature (synchronous polarising)

This can only be done with a dynamic type of test equipment. The memory ismainly to deal with 3 phase close up faults but is made to run out when anyvoltage level detector resets or when any comparator operates. There is nominally16 cycles of memory polarising which is derived from B phase volts. We thus haveto satisfy the above conditions and make the relay behave as though it is seeing athree phase close-up fault.

For a test set with three phase volts and three phase current this can be achievedby applying a prefault condition, for at least 500ms, then switch to a faultcondition. The fault condition must have balanced three phase current above thehigh set level detector setting, and the voltage must collapse to zero on all threephases.

For a test set with three phase volts and single phase current, the test can be

carried out using a B-N fault condition. The A and C phase voltage inputs shouldbe removed, the connect the relay Va and Vc inputs to the B phase input, as shownin Figure 4. A prefault condition should be applied for at least 500ms, the switch

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to a B-N Zone 1 fault condition where the current is above the high set leveldetector setting, and the voltage collapses to zero.

For both cases the Memory Time can be measured by measuring the dwell time of the ‘distance Trip’ contact (the dwell time is measured by arranging the timer to

start when the contact closes, and stop when the contact opens).

It may be necessary to select a different contact configuration for this test toprovide the 'distance trip' contact.

All other trip contacts are kept operated until the fault current is removed.

On 50Hz the time measured should be 330 - 360msOn 60Hz the time measured should be 270 - 300ms

Note 1: When the voltage inputs are all in phase V~ FAIL is obtained.

Note 2: Dwell time is the time for which a contact remains closed.

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12

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TEST PLUG 1

THESE CONNECTIONS

MUST BE MADE BEFORE

THE TEST PLUG ISINSERTED

IN

IA

Figure 3 VTS instantaneous indication

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MUST BE MADE AFTER

THE TEST PLUG IS

INSERTED

Figure 4 Memory feature (synchronous polarising)

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4.12 Loss of load accelerated trip feature

This feature can be selected in conjunction with any 3 pole only tripping scheme. It

provides the facility for fast end zone tripping if there is:

i) No signalling channel.ii) Signalling channel out of service.iii) No auto-reclose enabling the use of Zone 1 extension scheme.

It can only be used in conjunction with 3 pole only tripping and provides Loss of Load tripping if Zone 2 and/or DEF forward comparators have operated and lossof load is detected in two phases. Load must have been present in all three phasesprior to detecting a load loss and no other form of tripping is in progress (i.e. Zone1 or aided). The presence and loss of load is detected via the low set or high set

current level detectors as selected on the menu.

A convenient way of testing this feature is to have the test set arranged for an A-Gfault just inside Zone 2 and to use a variac and resistor to supply current above theselected level detector setting in phases B and C via one pole of a two pole switch.

The current should go in one direction though B phase and the opposite waythough C phase so that the resultant is zero.

Supply the current to phases B and C and connect a timer to start when the 2 poleswitch is opened and to stop when the relay ANY TRIP contact closes. Apply theA-G fault from the test set and open the 2 pole switch before Zone 2 time delayhas expired (extend or disable the time if required). The relay will display (DIST +DEF) LL if DEF* is fitted and enabled or DISTANCE LL if the DEF is not fitted or isdisabled. The trip time will be 30 to 40ms. The trip times on a real system will beincreased by the time taken for the remote circuit breaker to open.

Another method is to apply a perfect condition of three phase nominal voltage,and three phase current above the low set level detector (or high set level detector).

Then to apply an A-N fault just within Zone 2, at the same time reducing thecurrent in B and C phases to zero. Indication of ‘DISTANCE LL’ or (DIST + DEF) LLshould be give, with the measured trip time between 30 to 40ms.

* The DEF part of the logic has been removed for versions later than "C" series of the LFZP.

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4.13 Fault location using mutual compensation

Connect the test set as shown in Figure 5 and apply a ground fault at the Zone 1reach point.

The location obtained will be given by:

Location with Mutual = KZPh + KZN * Location without MUTUAL KZPh + KZN + KZM

in %, Miles or Kilometres, provided THETA Ph, THETA N and THETA M are within10° of each other.

The mutual compensation can be enabled or disabled in the fault locator part of the menu. However when enabled the compensation can NOT effectively be

shorted on the compensation terminals.

It should also be noted that if Io polarising is selected in the menu for the DEFfeature then the mutual compensation is automatically disabled even when youmay think it has been enabled in the menu.

The two relays on the parallel line ends should be connected on the relay panel tothe test set as shown in Figure 6. If the panel wiring is correct the predictedlocation will be obtained, if incorrect a higher value will be obtained. As the samecurrent is going through both relays all the fault locator testing could be done inthis connection but it is not recommended as lead lengths involved could have anappreciable effect on the phase angle of the fault presented to the relays. Testingin this connection with the added lead resistance may effect the distance relaysperformance and is not recommended.

If mutual compensation is set to unrealistic high values compared with the neutralcompensation than location errors can be obtained.

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INSERTEDTHE TEST PLUG IS

MUST BE MADE BEFORE

THESE CONNECTIONS

I

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MMLB 01TEST PLUG 2

TEST PLUG 1

MMLB 01

2728

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2324

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34

2 1A

BI

CI

IN

A

B

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V

V

V

V

THESE CONNECTIONS

MUST BE MADE AFTER

THE TEST PLUG IS

INSERTED

VX1CHECK VOLTS

BEFORE LINKING

Figure 5 Test plug connections for secondary injection test of mutual compensation setting

on the fault locator

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TERMINALS

REAR

WIRING TO

SCHEME

PART OF

CB

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A NVOLTAGE

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TEST PLUG 1MMLB 01

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Figure 6 Connections to prove polarity of panel wiring for mutual compensation on the faultlocator

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Section 5. SECONDARY INJECTION TESTS(SCHEME)

Standard schemes in Optimho

Note: relay type LFZP114 does not have the POR 2 or blocking schemes:

BASIC:Z1 EXTENSION:PUR: Permissive Underreach.PUR UNBLOCK: Unblocking Permissive Underreach.POR 1: Permissive Overreach using Tp & Td for current

reversal guard.POR 1 UNBLOCK: Unblocking Permissive Overreach using Tp & Td

for current reversal guard.POR 2: Permissive Overreach using reverse Z3 for

current reversal guard and including WeakInfeed echo.

POR 2 WI TRIP: Permissive Overreach using reverse Z3 forcurrent reversal guard and including WeakInfeed Trip.

POR 2 UNBLOCK: Unblocking Permissive Overreach using reverseZ3 for current reversal guard and including Weak

Infeed Trip.POR 2 WI TRIP UNBLOCK: Unblocking Permissive Overreach using reverseZ3 for current reversal guard and including Weak

Infeed Trip.

BLOCKING:BLOCKING2:

The Loss of Load Accelerated Trip feature can be selected in conjunction with anyof the above schemes but it is only functional if 3 pole only tripping is selected.

5.1 Zone 1 extension

If this scheme is selected, Zone 1 reach is extended to that of Zone 1X.

The loop impedance's required will be as given in 4.6.4

Ensure the opto isolator input for RESET ZONE 1 EXTENSION is de-energised.

Check the reaches as in 4.6 for each fault condition. Indication given will be as forZone 1, ie Z1 on the LCD.

Energise RESET ZONE 1 EXTENSION opto-isolator input and recheck the reacheswhich will now by that of Z1.

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5.2 Permissive under-reach

5.2.1 Aided trip check

Energise opto-isolator input CRX and check that application of a Zone 2 fault givesan instantaneous aided trip. Make sure that a Zone 2 time delayed trip is obtainedwhen CRX opto-isolator input is de-energised.

Note: If the UNBLOCKING scheme is selected LOSS OF GUARD (LGS) opto-isolator input must also be energised from the same switch as CRX.

5.2.2 Signal send checks

With CRX de-energised (and LGS if UNBLOCKING) check that application of aZone 1 fault causes the SIGNAL SEND contact to operate and a Zone 2 fault does

not.

Note: If the reach stepped Zones 1X, 1Y are used, the SIGNAL SEND contactwill go off after Zone 1X or Zone 1Y time delay.

5.2.3 TDW timer (unblocking scheme only)

Ensure CRX opto-isolator is de-energised.

Apply a Zone 2 fault and measure the trip time from energising LGS opto isolatorinput.

The time measured will be TDW time + up to 9ms to allow for program loop timeand contact operation time.

Note: If Zone 2 time delay is short, it may prove helpful to temporarilylengthen it to facilitate this test to be performed. Remember to reset it tothe required setting.

The recommended setting for TDW is 10ms.

5.2.4 Channel out of service

If the CHANNEL OUT OF SERVICE opto isolator input is energised, only 3 poletrips will be allowed. If 1 or 3 pole tripping has been selected, this may be provedby applying a single phase to ground fault and monitoring the A, B and C tripcontacts which should all close simultaneously.

If it has been selected to BLOCK AUTORECLOSE when CHANNEL OUT OFSERVICE, the BAR contact should be checked to confirm that it operates when a tripoccurs. (Apply an A-G Zone 1 fault).

5.3 Permissive overreach

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If DEF aided tripping is to be used it should now be blocked until the later tests aredone alternatively Ph-Ph faults could be applied.

If POR 2 WI TRIP or POR 2 WI TRIP UNBLOCK are to be used, the WEAK INFEED TRIPPING feature should not be selected until that particular test is to be

performed.


Energise opto-isolator input CRX and check that application of a Zone 2 fault givesan instantaneous aided trip. Make sure that a Zone 2 time delayed trip is obtainedwhen CRX opto-isolator is de-energised.

Note: If an UNBLOCKING SCHEME is selected energise CRX and LOSS OFGUARD opto-isolator from the same switch.

5.3.2 Signal send checks

With CRX opto-isolator input de-energised (and LGS if UNBLOCKING), check thatapplication of a Zone 2 fault causes the signal send contact to operate.

5.3.3 TP and TD timer checks

1) Recommendations for timer settings in current reversals

POR 1, POR 1 Unblock

Distance

The current reversal guard is not required if there is no parallel line or the Zone 2reach is not set to more than 150% of the line length.

If current reversal guard is not required set TP = 98ms, TD = 0ms.

If required :

TP = 30ms - minimum signalling channel operating time TD = 35ms + maximum signalling channel reset time

DEF

If current reversal guard is not required set TDG = 0ms.If required (the DEF guard is always required if there is a parallel line).

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TDG = 35ms + maximum signalling channel reset time.(This can only be set in the menu when DEF aided tripping is enabled).

POR 2, POR 2 Unblock, POR 2 WI Trip, POR 2 WI Trip Unblock

The current reversal guards used at the DISTANCE and DEF have only one timesetting, they can however be initiated by reverse Zone 3 or the DEF reverse lookingcomparators. Zone 3 must be set to reverse looking only.

If the guard is not required set TD = 0ms (i.e. there is no parallel line or Zone 2does not reach more than 150% of the line length and DEF aided tripping is not inuse).

If required :

TD = 35ms + maximum signalling channel reset time.

In all settings the nearest available above should be selected if the exact settingcannot be obtained.

2) TP (POR 1 only)

The current reversal guard in the POR 1 scheme is initiated when a healthy circuitrelay receives a permissive trip signal, however, a time delay, TP, is required togive time for a Zone 2 comparator to pick up.

Note: That TP is not used in schemes which utilise the weak infeed feature andthe guard is initiated by Zone 3 set to be reverse looking.

Arrange a double pole switch to energise CRX opto isolator input and start a timer.Select Monitor Option 19 and use terminals 3 and 22 on the monitor point box tostop the timer. If using a timer, 22 must be connected to common and set to`break to stop'.

Energise CRX opto isolator and note the time displayed on the timer which will be TP setting + up to 7ms to allow for program loop time.

Note: If an UNBLOCKING SCHEME is selected, arrange a timer to start whenCRX and LGS opto isolators are energised. Note the time fromenergising to an output from terminals 3 and 22 using monitoroption 19.

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3) TD

When the current reversal guard is picked up, transfer tripping is inhibited until thepermissive trip signal is removed or the Zone 2 comparator operates in POR 1. InPOR 2 the guard is on when a reverse looking comparator is picked up. A delay

on reset (TD) is required in case the Zone 2 comparator picks up while thepermissive trip signal is in the process of resetting which would otherwise causehealthy circuit tripping.

If POR 1 is selected, proceed as follows:Select Monitor Option 19 and arrange a timer to start on terminal 9 (going 0 to5V) and stop on terminal 3 (going 5V to 0) of the Monitor Point box with terminal22 being common.

Timer should have Break for Start' and Make for Stop'.

Ensure CRX opto isolator is energised. Apply a Zone 2 fault and note the timewhich will be TD setting + up to 5ms to allow for program loop time.

If an Unblocking scheme is selected, energise CRX and LGS opto isolator and thenproceed as above.

If POR 2 is selected, proceed as follows:

Select Monitor Option 19 and arrange a timer to start on terminal 8 (going 5V to0) and stop on terminal 2 (going 5V to 0) of the monitor point box, 22 beingcommon.

Apply a reverse Zone 3 fault, reset the timer and then remove the fault

The time obtained will be TD setting + up to 5ms to allow for program loops.

Timer should have Make for Start' and Make for Stop'.

The time obtained will be TD setting + up to 5ms to allow for program loops.

5.3.4 TDW timer (unblocking schemes only)

Time delay TDW is necessary to prevent mal-tripping during transient loss of guard.

Ensure CRX opto-isolator input is de-energised.

Apply a Zone 2 fault and measure the trip time from energising LGS opto-isolatorinput.

TDW time will be its setting + up to 9ms to allow for program loop time andauxiliary relay operation time.

Note: If Zone 2 time delay is short it may prove helpful to temporarily lengthenthe delay to facilitate this test to be performed. The recommendedsetting for TDW is 10ms unless other information is available.

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5.3.5 Echo feature (POR 1 OR POR 2)

To make this functional, an opto isolator input has to be available to inform the

relay when the breaker is open. The feature causes signal send for 100ms onreceipt of carrier once the breaker has been open for 250ms.

If the feature is to be used, check it as follows:Connect a double pole switch so that one pole energises the BREAKER OPEN optoisolator input and the other pole starts a timer. The switch should be open initially.Stop the timer on the SIGNAL SEND contact.

Energise CRX opto isolator input then close the double pole switch. A time delay of 255-265ms should be obtained.

Re-arrange the timer to measure the dwell time of the SIGNAL SEND contact.Open the double pole switch and on re-closing it a time of 100-110ms should beobtained.

5.3.6 Weak infeed echo (POR 2)

The normal' echo feature is not enabled when the breaker at the weak infeed endis closed. Thus make sure that the BREAKER OPEN opto isolator input isde-energised.

If the weak infeed trip feature is to be used, this should not be selected yet toenable this test to be performed.

No ac volts should be supplied to the relay.

There is a 10ms delay on the echo once the CRX opto-isolator is energised. Tocheck this, use a double pole switch to energise CRX opto isolator and start atimer. Stop the timer on the SIGNAL SEND contact.

The time measured should be 15-20ms.

Measure the dwell time of the SIGNAL SEND contact when energising CRX optoisolator which should be 100-115ms.

Note: If the weak infeed feature is to be used, the relay at the other end of theline must also have POR 2 selected which will then only send carrierwhen Zone 2 + high set current level detector have picked up.

5.3.7 Weak infeed trip (POR 2) if selected

The logic contains a delay on tripping of 60ms.

Ensure the BREAKER OPEN opto isolator is de-energised and no ac volts areapplied to the relay. Use a double pole switch to energise CRX opto isolator inputand start timer. Stop the timer on the any trip contact.

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A time delay of 60ms + up to 10ms to allow for program loop time and auxiliaryrelay contact operation time, should be obtained.

Aided trip indication should be obtained and 3 phase trips given.

Note: (For Sections 5.3.6 and 5.3.7) If an Unblocking scheme is selected,LOSS OF GUARD opto isolator input must be energised with the sameswitch as CRX.

If 1 or 3 pole tripping has been selected, this may be confirmed by applying 3phase volts on to the relay and reducing one phase to neutral voltage. EnergiseCRX as above and observe that single pole tripping is achieved and the correctindication is given.

5.3.8 Channel out of service

This can be done as in Section 5.2.4

5.4 Blocking scheme (see Section 5.5 for blocking 2 scheme)

In this scheme, a block signal is sent when a particular Zone 3 comparatoroperates and the corresponding Zone 2 comparator does not. an aided trip occurswhen a Zone 2 comparator operates, the CHANNEL OUT OF SERVICE OPTOisolator is not energised and no block signal is received.

Reverse looking Zone 3 operation must be selected in the menu.

Certain time delays are necessary to prevent maloperation. These time delays haveto be set to take into account different signalling channel times, comparatoroperation times and logic processing times.

TP is the time set to delay tripping after Zone 2 comparator has operated to allowa possible blocking signal to be received from the relay at the other line end.

For current reversal conditions a small delay in drop off of the blocking signal isrequired to prevent unwanted trips while the Zone 2 comparator is resetting.

The recommended settings are:

Distance

TP = Maximum signalling channel operating time + 16ms TD = 20ms - minimum signalling channel reset time

DEF (if fitted)

These settings can only be put on when DEF aided tripping is enabled.

TPG = Maximum signalling channel operating time + 26ms

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TDG = 20ms - minimum signalling channel reset time

5.4.1 Measurement of TP

DEF aided tripping should be inhibited (if available) until later tests are done(alternatively Ph-Ph faults should be applied).

Select Monitor Option 19 and arrange a timer to start on terminals 9 (going 0 to5V) and 22 and to stop on the ANY TRIP contact.

Ensure CRX opto isolator and CHANNEL OUT OF SERVICE opto isolator arede-energised.

A timer should have `Break to Start' and `Make to Stop' selected. Apply a fault justoutside Z1.

The time obtained will be TP setting + up to 6ms for program loop timeDISTANCE AIDED indication will be given on the LCD.

The aided trip alarm contact should be checked if used.

5.4.2 Measurement of TD

Arrange a double pole switch to de-energise CRX opto isolator and start a timer.Select Monitor Option 19 and use terminals 3 and 22 to stop the timer (going 5Vto 0), a timer should be re-set to `Break To Start' and `Make To Stop'.

Ensure CHANNEL OUT OF SERVICE opto isolator is de-energised.CRX opto isolator should initially be energised.

De-energise CRX opto isolator and note TD time which will be TD setting + up to4ms to allow for program loop time.

Energise CRX opto isolator, apply a fault outside Zone 1 and check that a timedelay trip is obtained.

5.4.3 Signal send check

Check that application of a Zone 3 reverse fault causes the SIGNAL SEND contactto operate and a Zone 2 fault does not.

5.4.4 Channel out of service check

If the channel is out of service, the relay reverts to a basic scheme. This may bechecked by energising the CHANNEL OUT OF SERVICE opto isolator, applying afault outside Zone 1 and noting that a time delay trip will be obtained.

If it has been selected to BLOCK AUTORECLOSE when the channel is out of service, check that the BAR contact closes when a trip occurs for a Zone 1 singlephase to ground fault. Three phase tripping will also be obtained.

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In this scheme, a normally open contact is used to start sending carrier and a

normally open contact stops carrier send when it closes but it will work with justsignal start contact if required.

Zone 3 must be set reverse looking and this causes SIGNAL START, if the DEF isfitted and enabled the low set zero sequence current level detector also causesSIGNAL START.

The SIGNAL STOP is controlled by the Zone 2 comparator and also the DEFforward comparator if fitted and enabled. Aided tripping is obtained when eitherof these comparators operate and no block signal is received within a small delaytime. The START and STOP signals are also used internally to control aided

tripping.

Certain time delays are necessary to prevent maloperation. These time delays haveto be set to take into account different signalling channel times, comparatoroperation times and logic processing times.

TP is the time set to delay tripping after Zone 2 comparator has operated to allowa possible blocking signal to be received from the relay at the other line end.

For current reversal conditions a small delay in drop off of the blocking signal isrequired to prevent unwanted trips while the Zone 2 comparator is resetting.

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The recommended settings are:

Distance

TP = TD = Maximum signalling channel operating time + 14ms

If a simplex channel is used TD can be reduced by the minimum signallingchannel reset time

DEF (if fitted)

These settings can only be put on when DEF aided tripping is enabled.

TPG = Maximum signalling channel operating time + 4ms TDG = Maximum signalling channel operating time + 14ms

If a simplex channel is used TPG can be set to 0ms and TDG can be reduced bythe minimum signalling channel reset time

5.5.1 Measurement of TP and distance aided trip test

Apply a fault just inside Zone 2 with sufficient current to operate the high set leveldetectors. DEF aided tripping should be inhibited (if available) until later tests aredone (alternatively Ph-Ph faults should be applied).

Select Monitor Option 19, the pick-up of any Zone 2 comparator is detected by theoutput of the monitor box terminal 9 and the trip output by terminal 5. Monitorbox terminal 22 is the common zero volt rail.


A timer should have `Break to Start' and `Break to Stop' selected.

The time obtained will be TP setting + up to 3ms for program loop timeDISTANCE AIDED indication will be given on the LCD.

Check that the SIGNAL STOP contact closes and also the aided trip alarm contactshould be checked if used.

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5.5.2 Measurement of TD and signal start check

Select Monitor Option 19, the pick-up of any Zone 3 comparator is detected by theoutput of the monitor box terminal 8 and the output on terminal 3 going low will

indicate when TD has run out after Zone 3 is allowed to reset. Monitor boxterminal 22 is the common zero volt rail.

A timer should have `Make to Start' and `Make to Stop' selected.

Ensure CHANNEL OUT OF SERVICE opto isolator is de-energised.

Apply a reverse Zone 3 fault and measure the time obtained on removing thefault. This will give the set TD + up to 3ms.

Also check that the SIGNAL START contact closes while the fault is applied.


If the channel is out of service, the relay reverts to a basic scheme. This may bechecked by energising the CHANNEL OUT OF SERVICE opto isolator, applying afault outside Zone 1 and noting that a time delay trip will be obtained.

If it has been selected to BLOCK AUTORECLOSE when the channel is out of service, check that the BAR contact closes when a trip occurs for a Zone 1 singlephase to ground fault. Three phase tripping will also be obtained even if single/3pole tripping has been selected on the menu.

5.6 Signalling channel check

This test should be applied to any scheme using a signalling channel when thechannel in service is available and in service.

An engineer will be required at each end of the protected line and some form of verbal communication is necessary.

At end A, select OUTPUT OPTION 6 (SIGNAL SEND) and at end B selectMONITOR OPTION 5 and observe LCD position 6 (CRX opto isolator).

Push the SET button at end A. LCD position 6 at end B will display 1' to indicatecarrier has been received.

The procedure should then be reversed.

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Note 1: It has been assumed that CONTACT CONFIGURATION 1 is selected. Ifany other configuration is selected the appropriate drawings must bemade available.

Note 2: If the BLOCKING 2 scheme is selected refer to the appropriate externalconnection diagram.

Section 6. DIRECTIONAL EARTH FAULT (DEF) IF FITTED

Note: If current polarising is used, the transformer should be checked forcorrect polarity by primary injection. The directional checks belowshould then be carried out.

Directional checks

Apply rated current of the correct polarity to DEF polarising input and to theneutral CT. The phase difference between the two should be 0º and the DEFforward comparator should be picked up (LCD position 6 monitor option4).

The phase angle of the neutral current should be rotated so that it lags thepolarising current. The angle that the DEF reverse comparator picks up(LCD position 7 monitor option 4) should be -90º ±5º.

The angle of the neutral current should be rotated around to a leadingangle and the angle that the DEF reverse comparator picks up (LCDposition 7 monitor option 4) should be +90º ±5º.

6.1 Current level detectors

Low set

Set monitor Option 7.

The settings available are 0.05 to 0.8 In

Apply phase to neutral current and note the pick-up and drop-off of the leveldetectorby LCD position 2.

This may be achieved with a suitable variac and resistor.

High set

This is only seen on the menu when DEF aided tripping is enabled in the SCHEMEpart of the menu.

The settings available are 0.05 to 0.8 In

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Select Monitor Option 7

Apply current as for the low set and note the pick up and drop off current whichwill be indicated by LCD position 4.

The sensitivities are menu selectable, and given by 3Io = %In. The pick up valuesshould be within 10% of that set. Drop off to be within 20% of Pick up.

6.2 Mag inrush detector

The Mag inrush detector works by measuring a ‘Gap’ greater than 5ms in thecurrent waveform, the most convenient method of testing this is by applying half wave rectified current.

Some test sets can generate half wave rectified current, if this feature is not

available a half wave rectified current can be achieved by connecting two diodesof suitable rating as shown in Figure 7.


Inject 0.2In and check the mag inrush detector picks up as indicated by LCDPosition 2.

6.3 Back up time delay

6.3.1 Current sensitivity


Current sensitivity is given by Is = SETTING x In

The available range is 5 to 120% In

Inject current for each phase to ground fault and note the level required to obtaina `1' in LCD Position 3.

The DEF forward comparator must be picked-up, when a ground fault is applied,this is shown by LCD Position 6 in Monitor Option 4.

Tolerance = +10%-0%

6.3.2 Operation Time

Set the relay to the required curve setting. For curves 1 to 4 inject 10 x Is (or seeNote 3) and note the time for the DEF TRIP contact to operate which will be

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CURVE TIME (x MULT t) TOLERANCE UNDER COMMISSION-Secs ING CONDITIONS ± 10% FOR

CURRENTS GREATER THAN 2 IsDefinite 2 2

Definite 4 4Definite 8 8Curve 1 2.971Curve 2 1.500Curve 3 0.808Curve 4 13.333

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12

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

TEST PLUG 1

IB

IA

THESE CONNECTIONS

MUST BE MADE BEFORE

THE TEST PLUG IS

INSERTED

CI

NI

Fgure 7 DEFf simulated mag inrush current

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For curves 5 to 8 it may be necessary to check 2 points see Note 3.

Note 1: If zero sequence current polarising is selected, it will be necessary toroute the current via the polarising CT. This may be achieved by

connecting the neutral connection to relay terminal 27 and linking 26and 28.

Note 2 If single pole tripping has been selected (and is available i.e. COS notenergised) then if the fault is seen by Zone 1 DEF will be inhibited until a3 pole trip occurs via Z1X.Z1Y or Zone 2. Either take this into accountor energise COS opto-isolator.

Note 3: If the test equipment used is not capable of supplying 10 x Is or adifferent point on the curve is to be checked, refer to Figure 8 whichgives the DEF back up time delay curves.

Note 4: If a blocking scheme is selected, energise CRX opto isolator input.

6.4 DEF aided tripping

DEF Aided Tripping is available on all the Permissive Overreach schemes and inthe Blocking schemes. Schemes POR 1 and POR 1 UNBLOCK make use of timer

TDG. If these schemes are to be used, they may be checked as follows:

Note: POR 2 DEF uses the same reversal guard timer setting as the distance,there is only one menu setting for the drop off time delay for the guard,

it is TD.

6.4.1 POR 1 or POR 1 unblock

TDG


Apply a fault that will only pick up the reverse looking DEF comparator, this isshown by Monitor Point 6 going to 5V. The guard pick-up is shown by MonitorPoint 2 going to 5V. On removing the fault, time from M.P.6 falling to 0V to M.P.2falling to 0v.

(Monitor point 22 is the 0V common connection). The time obtained will be TDG+ up to 5ms processing time. A timer should be set for `Make to Start' and `Maketo Stop'.

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Operating

10

5

50

100

curve 4

0.11 5

0.5

1

5010 100

curve 1

curve 3

curve 2

time (s)

Figure 8a Iec characteristics

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Operating

10

5

50

100

0.11 5

0.5

1

5010 100

curve 5

curve 8

curve 6

curve 7

time (s)

Figure 8bAmerican characteristics

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6.4.2 POR 2 (any version)

The procedure is exactly the same as above but the time obtained will be TD + upto 5ms processing time.

6.4.3 Blocking

TPG

Select Monitor Option 19 and start a timer when M.P.7 goes to 5V on theapplication of a fault only seen by the DEF forward comparator, stop the timer withthe any trip contact. (Monitor point 22 is the 0V common terminal). A timer shouldhave `Break to Start' and `Make to Stop'.

If single or 3 pole tripping is selected:-

Measured Time = TPG + 20ms + up to 8ms (for contact operation and processing) Time delay to give distance singlepole tripping preference.

If 3 pole tripping is selected, the time measured will be as above less the 20ms.

TDG

Select Monitor Option 19. Connect MP2 to stop a timer which has a start given byde-energising the CRX input.

A timer should have `Break to Start' and `Make to Stop'. The time obtained will be TDG and up to 6ms processing time.

6.4.4 Blocking 2

TPG

Apply a ground fault that will only be seen by the DEF forward looking comparator(i.e. a high impedance or resistive fault outside the reach of the distance).

Select Monitor Option 19, the pick-up of the DEF forward comparator is detectedby the output of the monitor box terminal 7 and the trip output by terminal 4.Monitor box terminal 22 is the common zero volt rail.


A timer should have `Break to Start' and `Break to Stop' selected.

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The time obtained will be TPG setting + up to 3ms for program loop time (+40ms+ up to 3ms if single/three pole tripping is selected thus giving preference todistance single pole tripping). DEF AIDED indication will be given on the LCD.

Check that the SIGNAL STOP contact closes and also the aided trip alarm contact

should be checked if used.

TDG

Select a reverse ground fault outside the reach of the distance elements and selectMonitor Option 19. The pick-up of the DEF reverse comparator is detected by theoutput of the monitor box terminal 6 and the output on terminal 2 going low willindicate when TDG has run out after DEF is allowed to reset. Monitor box terminal22 is the common zero volt rail.

A timer should have `Make to Start' and `Make to Stop' selected.

Ensure CHANNEL OUT OF SERVICE opto isolator is de-energised.Apply the fault and measure the time obtained on removing the fault. This will givethe set TDG + up to 3ms.

Also check that the SIGNAL START contact closes while the fault is applied.


If a POR scheme is selected, energise CRX opto isolator input, if an unblockingPOR scheme is selected, energise LOSS OF GUARD opto isolator alone. If theBLOCKING scheme is selected ensure that all opto isolator inputs arede-energised.

Apply a forward fault outside the distance Zones and check that the instantaneousDEF AIDED TRIP is given. (There must be sufficient current to pick up the DEFCurrent Level Detectors).


Apply a forward fault with the CHANNEL OUT OF SERVICE opto isolatorenergised, and check that DEF aided tripping can not be obtained.

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Section 7. LIVE SYSTEM CHECKS

If current polarising is used the transformer polarity should be proved by primaryinjection.


If the scheme requires the use of a signalling channel and the check has not beendone recently then 5.5 should be repeated.

7.2 Trip test

Trip isolation should be obtained if breaker operation is not wanted.

Auto reclose should be blocked.

Breaker operation will of course only occur if previously closed.

Select the appropriate output option in the commissioning tests part of the MENU.When the SET button is pressed, the appropriate contact will operate as shown.

The relay inoperative alarm will also be closed.

The output test options are as follows:

NUMBER CONTACT OPERATED

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1 29-332 29-353 37-394 41-435 45-476 49-51

7 53-558 30-329 30-3410 30-3611 38-4012 42-4413 46-4814 50-5215 54-5616 57-5917 57-6118 57-63

19 65-6720 69-7121 73-7522 77-7923 81-8324 TRIP A & ANY TRIP25 TRIP B & ANY TRIP26 TRIP C & ANY TRIP27 TRIP A, B, C, 3PH & ANY TRIP

Note: Option 24, 25 & 26 only applicable if 1 or 3 pole tripping is selected.

7.3 Final setting checks

The check list (in Appendix 3) should now be referred to, and used in conjunctionwith the menu scrolling facility to check that all settings are correct. If the VTS is toblock tripping check this is set before commencing the scrolling.

As an alternative a print out of settings may be obtained using the print option inthe MENU and a suitable printer.

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7.4 On load checks

As there could be a risk of tripping, maintain trip isolation or block contactoperation in the menu if required.

For the following checks it has been assumed that 2 type MMLG test blocks havebeen fitted and are wired as recommended in Figure 1.

If alternative test facilities are provided, the panel wiring diagram will need to bereferred to and the procedure adapted to suit.

7.4.1 Voltage transformer checks

Insert an MMLB01 test plug into test block 2.

With the line energised, check the voltage input to the protection across each pairof phases and between each phase and neutral.

Check for correct phase rotation with a phase rotation meter.

7.4.2 CT/VT phasing check

To ensure that the corresponding voltage and current go to a given relay elementit is necessary to check the phase angle between them agrees with the known loadpower factor. If the information available is in terms of import/export MW andMVAR, Figure 9 gives guidance.

Connect A-N volts to a phase angle meter voltage input terminals, paying carefulattention to polarity.

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IA

-M.V.A.R. +M.V.A.R.

-M.W.

+M.W.

VA

- = IMPORT + = EXPORT

= TAN-1 M.V.A.R.

MW

DETERMINATION OF THE LOAD ANGLE FROM LOAD INFORMATION

AI

IAAI

Figure 9 Determination of the load angle from load information

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If the fault locator is fitted `metering' information should be checked foragreement. (If the current is below about 7.5% In no current value will be givenand zero will be indicated). Prewire another MMLB01 connecting A phase currentto the current connection of the phase angle meter and providing shorts for the

other current paths as shown in Figure 2.

Insert this plug into MMLG test block 1.

Check that the phase angle measured gives reasonable agreement with the knownload power factor.

This procedure must be repeated for another phase.

Remove both test plugs.

7.4.3 Directional check

The test must be carried out with the relay energised from the line voltagetransformers and current transformers with the load current above the minimumsensitivity of the low-set current level detectors (5% In) and preferably at a laggingpower factor in the tripping direction.

Select on load directional check.

When the Set key is held pressed it automatically sets the relay low set current level

detectors to their most sensitive settings, THETA Ph to the minimum value and Zone1 to a straight line directional characteristic. As shown in Figure 10.

All contacts will be disabled and the Relay Inoperative Alarm will close.

If the current vector Ia as determined in 7.4.2 is drawn on Figure 10, and it comesinside the Òperate' area, then it will be seen as a `Forward Fault' when the Setkey is pressed. If In appears to be on a boundary line voltage rotation may benecessary to give a definite confirmation.If using MMLB test plugs, the voltage plug must be fully inserted BEFORE anyrotation is performed.

Push the SET key to perform the test. One of the three following messages willappear which are self-explanatory.

a) Fault seen as forwardb) Fault not seen as forwardc) Test aborted check i & or v

A check must be performed with the fault in the opposite direction which isachieved by reversing the current input to the relay and the new appropriate

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message seen when the set key is pressed.If MMLG Test blocks are fitted, this maybe achieved by referring to Figure 11.At the end of these tests the calendar clockshould be correctly set. Any relay inhibits or special test facilities should beremoved and trip links put back.

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OPERATION

NO OPERATION

NO OPERATIONOPERATION

I

RCA

a

VB

CV

VA

PHmin

1

FROM FIG. 9

LET TAN -1M.V.A.R.

M.W.=

NOTE : ON LOAD CHECKS ONLY INVOLVE OPERATION OF PHASE - PHASE

COMPARATORS, FOR SIMPLICITY THIS DIAGRAM IS DRAWN ON A

SINGLE PHASE BASIS.

THEN MUST SHOW REASONABLE1

AGREEMENT WITH

Figure 10Vector diagram on load directional check

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12

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

MMLB 01

TEST PLUG 2

TEST PLUG 1

MMLB 01

2728

2526

2324

2122

1920

1718

1516

1314

1112

910

78

56

342 1

Figure 11Test plug connections for on load test current reversal

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COMMISSIONING TEST RESULT SHEETS

Static distance prot. type LFZP 11 Serial number:

Model:

Station: Date:

Circuit: Engineer:

Scheme type: Witness:

Active settings group no:

1. Preliminary Checks

a) Rating Details

b) CT Shorting Contacts

c) DC supply

d) Power up

e) Wiring

f) Relay Inoperative Alarm Contact

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2. Voltage level detectors (monitor option 06)

Level Relay Terminal Mon Opt 6 Pick Up Drop Off Drop off % Detector Injected LCD POS Volts Volts Pick up

PhA 15-18 2 PhB 16-18 3 PhC 17-18 4

3. Phase current level detectors

Low set

Level Relay Terminal Mon Opt 6 Pick Up Drop Off Drop off % Detector Injected LCD POS Current Current Pick up

PhA 19-20 6 PhB 21-22 7 PhC 23-24 8

High set

Level Relay Terminal Mon Opt 7 Pick Up Drop Off Drop off % Detector Injected LCD POS .Current .Current Pick up PhA 19-20 6 PhB 21-22 7 PhC 23-24 8

Biased low set

Relay Terminal Mon Opt 6 Pick Up Drop Off Drop off % Injected LCD POS .Current .Current Pick up 19-20 9 21-22 9 23-24 9

Biased high set

Relay Terminal Mon Opt 7 Pick Up Drop Off Drop off % Injected LCD POS .Current .Current Pick up 19-20 9 21-22 9 23-24 9

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4a. Reach tests using a computer based test set

RelayAngle

ReqdReach

Fault Type

RelayVolts

RelayAmps

EquivZΩ

Actual % %Error

θn /θph

Zr

__ ° __ °

Zone1

A-GB-GC-G

__ ° __ °

Zone1X

A-GB-GC-G

__ ° __ °

Zone1Y

A-GB-GC-G

__ ° __ °

Zone2

A-GB-GC-G

__ ° __ °

Zone3

A-GB-GC-G

__ ° __ °

Zone3 Rev

A-GB-GC-G

__ °

__ °

Quad

Res.

A-G

B-GC-G

__ °Zone1

A-BB-CC-A

__ °Zone1X

A-BB-CC-A

__ °Zone1Y

A-BB-CC-A

__ °Zone2

A-BB-CC-A

__ °Zone3

A-BB-CC-A

__ °Zone3 Rev

A-BB-CC-A

5. Fault location (if fitted)

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KZ1=

KZF=

LINE LENGTH =

KZM THETA M

MUTUAL ENABLED/DISABLED COMPENSATION

Location with Mutual = KZPh + KZN * Location without MUTUAL KZPh + KZN + KZM

PHASE LOCATION GIVEN FOR Z1 REACH LOCATION GIVEN FOR Z1 REACH% OR Km OR MILES

(NO MUTUAL)% OR Km OR MILES

(WITH MUTUAL)EXPECTED ACTUAL

A-G B-G C-G A-B

B-C C-A

6. OPERATION TIMES

PHASE Zone 1 Zone 1X Zone 1Y Zone 2 Zone 3(ms) (seconds) (seconds) (seconds) (seconds)

A-B

B-CC-AA-GB-GC-G

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7. Power swing blocking

a) Zone 6 boundary

Required forward loopimpedance =

Measured forward loopimpedance =

Required reverse loop impedance=

Measured reverse loop

impedance =

b) TZ6 Timer

Measured time = ms

c) Simulated power swing

d) Blocking and contact check

Block Zone 1

Block Zone 1X

Block Zone 1Y

Block Zone 2

Block Zone 3

PSB Alarm

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8. Voltage transformer tupervision

a) Operation on zero sequence volts

Voltage for

operation

V

Operation time seconds

Indication

b) Instantaneous operation

Indication

c) Self resetting ENABLED/DISABLED

Operation checked

9. Switch on to fault

SOTF Indication

Trip time ms

10. Memory feature (synchronous polarising)

Distance trip alarm contact dwell time ms

11. Loss of load accelerated trip feature

Loss of load accelerated trip feature ENABLED/DISABLED

Trip time msIndication

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12. Zone 1 extension

RESET Z1 EXTENSION energised,Z1 Reach =

RESET Z1 EXTENSION de-energised,Z1 Reach =

13. Permissive underreach

Aided trip check

Signal send check

TDW Timer (if applicable) ms

3 pole trip if COS

BAR contact

14. Permissive overreach

Aided trip check

Signal send check

TP Time ms

TD Time ms

TDW Timer (if applicable) ms

ECHO feature

Breaker open time ms

Signal Send dwell time(100-110ms)

ms

Weak infeed echo

Delay on echo (15-25ms) ms

Signal Send dwell time(100-110ms) ms

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Weak infeed trip

Delay on tripping (54-66ms) ms

Delay on drop off (100-124ms) ms

15. Blocking

TP Time ms

TD Time ms

Signal send check

Channel out of service check

BAR

16. Signalling channel check

17. DEF

Low set

Level Pick Up Drop Off Drop off %Detector Current Current Pick upA-GB-GC-G

High set

Level Pick Up Drop Off Drop off %Detector Current Current Pick upA-GB-GC-G

Current Polarising Test

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Mag Inrush Detector

Time delayed back up operation

Sensitivity

Phase Is Pick upInjected mAA-GB-GC-G

Operation time

Phase Current Curve Expected ActualInjected Injected Selected Time TimeA-GB-GC-G

DEF aided tripping

TD Time (if applicable) ms

TPG Time (if applicable) ms

TDG Timer (if applicable) ms

Aided trip check

18. Live system checks


18.2 Trip test

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18.3 Final setting check

21. On load checks

a) Voltage correct

b) Phase rotation correct

c) CT/VT phasing correct

d) Forward directional check

e) Reverse directional check

Engineer Witness

Date Date

SETTINGS CHECK SHEETS

STATIC DISTANCE PROT. TYPE LFZP11 SERIAL NUMBER

MODEL

STATION DATE

CIRCUIT ENGINEER

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ACTIVE SETTINGS GROUP NO.

IDENTIFIERS

DISTANCE 18 LFZPFAULT LOCATOR 18 LFZP

DEFAULT DISPLAY BLANK / GROUP IDENTIFIER / ACTIVE GROUP NO.

CLOCK REFERENCE CRYSTAL / SYSTEM VOLTAGE

CONTACT CONFIGURATION NO.

SCHEME ONLY THE APPROPRIATE QUANTITIES

TP ms FOR THE SCHEME SELECTED WILL

TD ms BE DISPLAYED

TDW ms

DEF ELEMENTS ENABLED/BLOCKED HIGH SET In

TPG ms

TDG ms

LOSS OF LOAD ENABLED/BLOCKED BY LOW SET/HIGH SETACCELERATED TRIP LEVEL DETECTORS

DISTANCE

TYPE OF TRIP1 OR 3 POLE/3 POLEZONE 1 TRIPENABLED/BLOCKED

TIME DELAY TRIPS

TZ1X ENABLED/BLOCKED TZ1X s TZ1Y ENABLED/BLOCKED TZ1Y s TZ2 ENABLED/BLOCKED TZ2 s TZ3 ENABLED/BLOCKED TZ3 sALL G ENABLED/BLOCKED

BASE SETTINGS

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KZPh

THETA Ph

KZN

THETA N

DIST G CHAR'STIC MHO/QUADRILATERAL KR

Z1 & Z2 SETTING

KZ1

KZ1X

KZ1Y

KZ2

Z3 SETTING OFFSET/REVERSE

KZ3'

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KZ3LENT a/b

SWCH ON TO FAULT ENABLE/BLOCK ENABLED IN 110s/0.2s

BY

PWRSWG DETECTOR ENABLE/BLOCK

TIMING Z6-Z3/Z6-Z2ZONE 1 ALLOW/BLOCK ZONE 1X ALLOW/BLOCK ZONE 1Y ALLOW/BLOCK ZONE 2 ALLOW/BLOCK ZONE 3 ALLOW/BLOCK

TZ6 ms

KZ6KZ6'LENT a/b

BLOCK AUTORECLOSE BLOCK/ALLOW ON Z1 + AT 2 & 2/3 Ph/F

BLOCK/ALLOW ON Z1X(T) TRIP

BLOCK/ALLOW ON Z1Y(T) TRIP

BLOCK/ALLOW ON Z2(T) TRIP

BLOCK/ALLOW ON CHANNEL OUT

BLOCK/ALLOW ON DEF DELAY TRIP

BLOCK/ALLOW ON DEF AIDED TRIP

VT SUPERVISION ALLOW/BLOCK TRIP SELF RESETTING (ENABLED/DISABLED)

START INDICATION ENABLED/BLOCKED

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DEF

LOW SET In

DEF ELEMENTS ENABLe/BLOCK DELAY TRIP ENABLe/BLOCK CURVEMULT *tBASE SETTING InPOLARISING THETA GMAG INRUSH ON/OFFSTABILISER

FAULT LOCATOR

KZF

LINE UNITS

LINE LENGTH

CT RATIO

VT RATIO

MUTUAL ENABLE/DISABLE KZMCOMPENSATION

THETA M

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SERVICE MANUAL R5911D Types LFZP

continued overleaf

REPAIR FORM

Please complete this form and return it to AREVA T&D with the equipment to be repaired.This form may also be used in the case of application queries.

AREVA T&DSt. Leonards WorksStaffordST17 4LX,England

For: After Sales Service Department

Customer Ref: _______________________ Model No: __________________

AREVA Contract Ref: _______________________ Serial No: __________________

Date: _______________________

1. What parameters were in use at the time the fault occurred?

AC volts _____________ Main VT/Test set

DC volts _____________ Battery/Power supply

AC current _____________ Main CT/Test set

Frequency _____________

2. Which type of test was being used? ____________________________________________

3. Were all the external components fitted where required? Yes/No(Delete as appropriate.)

4. List the relay settings being used

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

5. What did you expect to happen?

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

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6. What did happen?

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

7. When did the fault occur?

Instant Yes/No Intermittent Yes/No

Time delayed Yes/No (Delete as appropriate).

By how long? ___________

8. What indications if any did the relay show?

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

9. Was there any visual damage?

____________________________________________________________________________

________________________________________________________________________________________________________________________________________________________

10. Any other remarks which may be useful:

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

Documents

LFZP11x_R5911D