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2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 1
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION ––
Lesson-12: ARM
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 2
The ARM architecture processors The ARM architecture processors popular in Mobile phone systemspopular in Mobile phone systems
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 3
ARM Features ARM Features � ARM has 32-bit architecture but supports 16
bit or 8 bit data types also. � ARM is programmable as little endian or big
endian data alignment in memory. � ARM provides the advantage of using a
CISC in terms of functionality, along with the advantage of an RISC in terms of faster program implementation as well as reduced code lengths.
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 4
ARM7, ARM9 and ARM 11 microprocessorsARM7, ARM9 and ARM 11 microprocessors� ARM processor has an RISC core for
processing� Combination of RISC and CISC features─
ARM supports to a complex addressing modes based instruction set
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 5
InIn--built compilation unitbuilt compilation unit
� Compiles the CISC instructions into RISC formats, which are then implemented by the RISC core of the processor.
� Internally the implementation for many instructions is like in an RISC (without the micro-programmed unit)
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 6
JazelleJazelle technologytechnology
� Faster Java codes execution
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 7
ARM Thumb 16ARM Thumb 16--bit instructionsbit instructions� Thumb Set designed for 16-bit word lengths and
instructions, which internally executes by same 32-bit core.
� Instruction fetch of 2 bytes in Thumb mode in place of 4 bytes in ARM mode.
� Data alignment at steps of 2 bytes in Thumb mode in place of 4 bytes in ARM mode Memorysavings of up to 35%, over the equivalent 32-bit code, while retaining all the benefits of a 32-bit system (such as access to a full 32-bit address space).
� Enables 32-bit performance at the 8/16-bit system cost in terms of memory needs.
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 8
Thumb and 32Thumb and 32--bit ARM modesbit ARM modes� Switch from one mode to another � No overheads (in terms of time and
memory) in moving between Thumb and the normal ARM state of the codes. Two states are compatible on a normal basis.
� Gives code designer complete control over performance and code-size optimisation
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 9
ARM7 versionsARM7 versions� ARM7TDMI® (Integer Core) � ARM7TDMI-S™, (Synthesisable version of
ARM7TDMI) � ARM7EJ-S™ (Synthesisable core with DSP and
Jazelle technology) � ARM720T™ (cached processor macrocell , 8K
Cached Core with Memory Management Unit (MMU) supporting operating systems1 including Windows CE, Palm OS, Symbian OS and Linux)
� 130 MIPS using Dhrystone 2.1 benchmark in typical 0.13µm process
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 10
ARM9 versionsARM9 versions� ARM920T (Dual 16k caches with MMU support
multiple OSs. � ARM922T (Dual 8k caches for applications
support multiple OSs1. � ARM940T™ (Dual 4k caches for embedded
control applications running a RTOS) � 32-bit RISC processor core Super scaling 5-stage
integer pipeline. 8-entry write buffers to avoid blocking the processor on external memory writes
� Achieves 1.1 MIPS/MHz, 300 MIPS (Dhrystone 2.1) in a typical 0.13µm process
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 11
ARM11 versionsARM11 versions� Families with ARMv6 instruction set architecture
that includes the Thumb® extensions for code density, Jazelle™ technology for Java™ acceleration, ARM DSP extensions, and SIMD media processing extensions. MMU) supporting operating systems1 and palm OS
� 32-bit RISC processor core with 8-stage integer pipeline, static and dynamic branch prediction, and separate load-store and arithmetic pipelines to maximize instruction throughput
� Targets a performance range of Dhrystone MIPS 400 to 1200
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 12
Memory Architecture Memory Architecture • ARM7 has Princeton memory architecture.• ARM9 processor has Harvard architecture
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 13
Faster implementation and Reduced code Faster implementation and Reduced code lengths lengths
� Due to the instant availability of the register word to the execution-unit.
� Reduced code lengths─Most instructions use registers as operands.
� Few bits in the instruction specify a register as operand. 8, 16 or 32 bits specify a memory address as operand and the displacement bits in the instruction.
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 14
ARM registers ARM registers � R0 to R15. � R15 also function as program counter.� R14 function as link register. � R13 may be used as stack pointer� CPSR (current program status register)� SPSR (saved program status register).
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 15
ARM ArchitectureARM Architecture
SPSR
32-bit bus
Hardwired circuits for
each instruction
ID
IR
Execution Execution unitunit
r0to
r15
CPSR
32-bit r15 functions as PC
Barrel ShifterALU,
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 16
ARM CodesARM Codes� ARM Codes─ Forward compatible with higher
versions. � ARM7 codes ─ Forward compatible with
ARM9, ARM9E and ARM10 processors as well as Intel XScale micro-architecture.
� ARM9E and ARM 10 families use a Vector Floating Point (VFP) ARM coprocessor, which adds full floating point operands.
� VFP also provides fast development in SoCdesign when using tools like MatLab®.
� Applications are in image processing (scaling), 2D and 3D transformations, font generation and digital filters.
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 17
ARM Intelligent Energy Manager (IEM) ARM Intelligent Energy Manager (IEM) technologytechnology
� Advanced algorithms to optimally balance processor workload and energy consumption.
� Maximizes system responsiveness. � IEM works with the operating system and
mobile OS. � Application running on a mobile phone
dynamically adjusts the required CPU performance level.
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 18
ARM processors AHB (AMBA Advanced ARM processors AHB (AMBA Advanced High Performance Bus) interfaceHigh Performance Bus) interface
� AMBA an established open source specification for on-chip interconnects.
� AMBA serves as a framework for SoCdesigns and development of the IP library.
� AHB support in all new ARM cores.
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 19
AHBAHB� Provides a high-performance and fully
synchronous back plane. (Back plane means additional set of controllers, which can access another common bus, which is distinct from system bus in a multilevel buses in the system.)
� Multi-layer AHB in version ARM926EJ-S and all members of the ARM10 family represents a significant advancement. It reduces access latencies and increases the bandwidth available to multi-master systems
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 20
33-- stage pipeline in ARM7stage pipeline in ARM7
Fetch
Decode
ExecuteWrite back
Read Operands
Successive Clock Intervals
I1 I2 I3 I4 I5 I6
I1 I2 I3 I4 I5
I1 I2 I3 I4
Stages
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 21
Pipeline and LatchPipeline and Latch
Fetched an instruction In
Decode In and read operands
Execute In, and mem-oryinputs In and address and Write Result In
Latch Latch
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 22
55-- stage pipeline in ARM 9stage pipeline in ARM 9
Fetch
Decode
Execute
Write back
Read Operands
Successive Clock Intervals
I1 I2 I3 I4 I5 I6
I1 I2 I3 I4 I5
I1 I2 I3 I4
I1 I2 I3
I1 I2
Stages
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 23
Super scaling in ARMSuper scaling in ARM
Fetch
Decode
ExecuteWrite back
Read Operands
Pipeline1
I1
I3
I2
Stages Pipeline 2
I’1
I’3
I’2
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 24
SummarySummaryWe learnt• ARM Architecture• 32- address bus and 64-bit data bus• Programmability as Little endian or Big
endian• Princeton Memory in ARM7 and Harvard
in ARM9 • 16 Registers with R15 as Program counter
2008 Chapter-2 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 25
SummarySummary
We learnt• 16-bit Thumb set for 16-bit
instructions to reduce external memory requirement
• AHB • 3 stage pipeline in ARM7 and 5 in
ARM9