Legacy Processes Getting Better All the Timeserver.semiconchina.org/downloadFile/1365746008157.pdfLegacy Processes Getting Better All the Time 2 © 2010 Mentor Graphics Corp. Company

Semicon China Russell LeeTechnical Director, Asia Pac

Legacy Processes Getting Better All the Time

2 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com

Topics

Semicon China 2013_Mentor_RL

Understanding of Market Tape-out Forecasts Legacy Processes/Advanced Software Solutions

2

http://www.mentor.com

www.mentor.com © 2013 Mentor Graphics Corp. Company Confidential

Understanding of Market Tape-out Forecasts



Learn More Title When

SKO TBD TBD Live AE Training TBD TBD

-out Chart

Tape-outs at advanced nodes are growing

Source: VLSI Research, October 2012

By Line Width 2009 2010 2011 2012F 2013F >=38nm but <55nm 578 845 1,130 1,235 1,309 >=27nm but <38nm 19 76 330 455 596 <27nm 7 61 112 204 TOTAL 12,799 12,958 12,727 12,354 12,136 Source: VLSI Research, October 2012

4 Semicon China 2013_Mentor_RL



It Also say 65nm and Larger Still Account for ~43% of all Wafer Production

Semicon China 2013_Mentor_RL 5

0

200

400

600

800

1,000

1,200

1,400

1,600

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

Waf

er S

tart

s K

WP

W

<27nm

32nm45nm

65nm90nm130nm

180nm>=250nm

43% of Production



It also says Nodes 65nm and Larger Still Account for ~48% of all Wafer Fab Capacity

0

100

200

300

400

500

600

700

800

Fab

Cap

acit

y (M

SI)

22nm32nm

45nm65nm90nm

130nm>=180nm

48% of Capacity




And Nodes 65nm and Larger Accounted for ~85% of all Design Starts


0

5,000

10,000

15,000

20,000

25,000

30,000

35,000

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

Des

ign

Sta

rts

(Un

its)

<27nm32nm45nm65nm90nm130nm180nm250nm350nm>=500nm

85% of Designs



Legacy Processes, But Not Legacy Design Techniques


complex that in prior years, for example:

Have advanced checks and filling routines Include large IP blocks, either internally developed or purchased from 3rd parties Have more reliability constraints due to new market requirements Are part of a 3D or 2.5 D solution

That includes sensors Possibly high speed interface solutions like silicon photonics

perspective, ergo physical verification



Legacy Processes Advanced Software Solutions



Continuously Increasing Physical Verification, Circuit Verification, and DFM Complexity

Dummy Fill Critical Area Critical Area

LVS

PEX

FinFET: PV, CV, DFM

2.5D / 3D-IC

Litho checks: IP

Single-dimension PV

LVS

Single-dimension PV

PEX

LVS

Single-dimension PV

Pattern Match

RDR /On-grid / On-pitch checks

Dummy / SmartFill

Litho checks: IP / full chip

ADP

LVS

Multi-dimension PV

Double Patterning (DP)

Delta-Voltage DRC/PERC checks

2.5D / 3D-IC

Pattern Match

RDR /On-grid / On-pitch checks

SmartFill (DP)

Litho checks: IP / full chip (DP)

ADP (DP)

LVS / Hyper Compare

Multi-dimension PV

Recommended Rule / CFA / MAS

Comprehensive Reliability checks

Recommended Rule / CFA / MAS

Spot Reliability checks

2002 130 nm

2006 90 nm

2008 65 nm

2010 40/28nm

2012 20/14 nm

New Solutions Can Address

Legacy Process Issues




Calibre Pattern Matching Broad Applications at Advanced Process Nodes

P&R w/ Pattern Matching Driven Auto-fixing

Pattern Matching Used for Defining Complex Checks

Identify manufacturing yield detracting patterns

Pattern Matching

nmDRC Deck

Check #1Find:

Operation #1 .

Check #2

Pattern Library

DFM Checking




Pattern Matching Applications in Legacy Nodes


Faster deck enhancements. Replace complex or excluded design rule checks for implementation and runtime performance

Fast Deck Simplification

Source: Design Automation Conference 2010

Methodology Compliance Check

Pattern

Cell_A Cell_B Fillcell_A Endcap

Fillcell_B

Cell_B Cell_

C Fillcell_A Endcap

Cell_C

Fillcell_B

Fillcell_A Endcap

Endcap

Precise Verification of Devices

Pattern

Methodology compliance checking, such as standard cell array end-cap requirement

Verify sensitive devices match exact design specifications for IP blocks



On Grid Placement

Extend cell with specific Pattern

Pitch Checking Pitch Checking

Double Patterning Double Patterning

Fill Stack to Maximize coverage

Fill Stack to Maximize coverage

Net Aware Fill Net Aware Fill

Cell Based Fill Cell Based Fill Cell Based Fill Cell Based Fill

E-Metrology Structure



Analog Fill Analog Fill Analog Fill Analog Fill Analog Fill

Density Driven Fill Min/Max/Gradient

Density Driven Fill Min/Max/Gradient

Density/Perimeter Min/Max/Gradient



Correct by Construction Engine focused on making Deck Creation manageable and solving the Challenges of Fill

Growing Complexity of Fill It is at Legacy Process Nodes Too

SmartFill provides functionality to meet the challenges

Customer can use it as needed Focused on making deck creation easy and understandable

Fill to Spec and minimize the amount of fill Fill to Spec and minimize white space

45/40 nm 250/90 nm 65/55 nm 16/14 nm 28/20 nm




Using Calibre SmartFill to Quickly Create Digital Filling Solutions

Customer Quote

Ease of deck writing: first item to catch their attention Deck developers are the target customers Density rules must be achieved

SmartFill has built in functions for Min, Max, and Gradient density

of code into a single SVRF call

Flexibility to easily modify the deck Process Owner: In the node engagement stages the density targets are changing Design Team: simple addition of new filling routines for competitive advantage




A Different Calibre SmartFill Application Analog Fill Solution

Analysis Engine can be used to create a Correct by Construction Analog Fill Solution

Uniformity of the fill improves the uniformity of the transistor performance Analysis-driven Fill

Multiple layers to consider for analysis Multiple layer fill structures need to be inserted Balancing is done by layer

Specific deck for Inductor Fill

Customers are matching fill around Cell, Net and Device




CSR Case Study Published in Tech Design Forum

Y mirror

X mirror

16

http://www.techdesignforums.com/practice/technique/dummy-fill-analog-designs/

Key Points: Dummy fill has been primarily designed for large, digital SoC Ensuring that fill does not impact device matching symmetry is

important for analog design This is a core issue for analog IP blocks across multiple process

nodes Semicon China 2013_Mentor_RL


http://www.techdesignforums.com/practice/technique/dummy-fill-analog


IP Re-use Is Good, So What is the Issue?

Increased IP reuse beyond intended applications IP life > rule file life

New checks due to design sophistication

Multi-foundry sourcing Forces deeper understanding of IP

This all leads to the question is this a real DRC error or not?

Unnecessary and redundant review at SoC integration time Duplicate communication and negotiation on waiving Ambiguity between SoC and IP designer on who owns fixing




Calibre Automatic Waiver Flow: Allows efficient IP re-use for all process nodes

Semicon China 2013_Mentor_RL

Calibre DRC Cell Level

Calibre

Chip Verification

IP block containing errors to waive

Foundry Golden Rules

Rules from foundry

Waivers merged with IP by IP provider

3rd party IP with waivers embedded into design

DRC Debug

DRC

Calibre RVE

Waived results automatically removed at runtime

Manual Waivers

Auto Waivers

Debug

18

AutoWaiver

as a repository for IP owners and

prior use models/waivers



The General Problem 35% of ESD and latch- -tools The other 65% rules need additional manual-placed marker layers

Advanced Designs using Legacy Processes have the same issue

Reliability Rules are Complex Regardless of Process Node



TowerJazz Releases Calibre PERC Rule Decks for 180nm Process

Ensuring reliable designs at Legacy

Processes




Beyond Baseline Digital



Historical Moore

Source -Than-

Analog RF Passives HV Power

Sensors Actuators Biochips




2.5 and 3D Is Going to Drive Legacy Processes


technologies vs. a single homogenous chip This allows design teams to select the most cost effective process node for each element of the 2.5 or 3D based solution Solutions need to interact with the real world via analog systems, sensors, and high speed interfaces

We project these factors will extend and or grow the demand for tape-outs on Legacy processes

Our objective is to make the verification of 2.3 or 3D designs be as seamless and simple as possible



Calibre 3DSTACK: The Verification Flow for 3D

Base

Stack Interface

3DSTACK Verification

Place

Shift

Rotate

Flip

LVS

RVE

Chip 1

nmDRC All Level Verification Design Layers TSV Layers Micro Pad Layers

nmLVS Complete LVS Verification Top-level layout port names match the corresponding source port names Interface Layers

TSV Micro Pads Text

Chip N

nmDRC All Level Verification Design Layers TSV Layers Micro Pad Layers

nmLVS Complete LVS Verification Top-level layout port names match the corresponding source port names

Standard Verification

PEX

3D Assembly

Stack Interface

DRC

Assembly netlist


One Verification Platform for all

chips Using Sign-Off

decks



Calibre 3DSTACK Physical Verification

DRC: verify micro-bumps physically align LVS: verify proper electrical connectivity through die interfaces




Extraction: calculate electrical parasitics

Option 1 Support front and back metal calibration Parasitic extraction with TSV/micro-ball as an LVS device

Drop in SPICE sub-circuit from the foundry Support SPICE and SPEF (STA) flows

Option 2 Mentor provided TSV model

Characterizing TSV with surrounding impacts - underway

Calibre 3DSTACK Physical Verification




MEMS Market Motion Sensors


YOLE predicts that by 2017, 25% of the total MEMS market will be dominated by motion sensing devices

Highly accurate extraction needed Intentional capacitance modeling for device characterization Parasitic capacitance extraction between anchored and moving parts



MEMS Extraction Challenges: Accuracy, Performance, Deck Support


Mechanical sensors/actuators are complex structures Complex technology recipes Very thick conductor layer sandwiched by very thin adhesive layers 45-degree edges and curved shapes Odd shapes like holes/dimples in the conductor and dielectric layers Non-planar processes

3D structure design specs must be met with field solver accuracy

Designer Concerns Are the extraction results accurate? Does the tool deliver performance and capacity for large structures?

Holes

Dimples

Todays MEMS Almost One Process Per

Design

Field Solvers like Calibre

xACT3D address the concerns



Silicon Photonics Getting the speed of light on a chip

Emerging Market to Address high bandwidth data transfer

Replaces copper wires with light waveguides on chip

2.5 and 3D are best approaches since there are multiple process nodes and technologies involved




Curves, the Common Issue with MEMS and Silicon Photonics

violations using standard DRC methods Results in design teams chasing lost of false errors

eqDRC capability allows Tolerance Determination and easy Debugging




Mentor is Active in Silicon Photonics Beyond DRC

Silicon Photonics offers potential to further improve communication bandwidth and lower power

Mentor is collaborating with research institutions and fabs to develop flows and design kits to move silicon photonics form TCAD to more automated solutions

Are making progress with multiple partners

Element Fab A Fab B Fab C

Calibre DRC Available, optimized Available In progress

Calibre Fill Available, optimized In progress Available

Calibre LVS In progress Planned Planned

Pyxis device library Available Planned TBD




Summary


In a very short time we

Understood market tape-out forecasts and the Strength of Legacy Processes

Showed how advanced software solutions can be applied to Legacy Processes

Thanks!




Documents

Legacy Processes Getting Better All the Timeserver.semiconchina.org/downloadFile/1365746008157.pdfLegacy Processes Getting Better All the Time 2 © 2010 Mentor Graphics Corp. Company