Lecture1 Intro Overview

7/29/2019 Lecture1 Intro Overview

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EE 402Introduction to VLSI Design

Prof. Youngmin Kim

ECE, UNIST2013, 1st


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OutlineLogisticsWhat I expect you to learn in this classCMOS processing sequence

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Logistics Instructor: Prof. Youngmin Kim

l Email: [email protected] Office: EB2, 401-1l Phone: +2115l Office hour: Tue. & Thu. 10:00 ~ 12:00 AM (Other time available by appointment)

Textbookl Digital Integrated Circuits: A Design Perspective, 2nd edition by Rabaey, Chandrakasan, and

Nikolic References

l N. Weste and D. Harris, "CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition",Addison-Wesley, 2005.

l "Design of High-Performance Microprocessor Circuits", edited by A. Chandrakasan, W. Bowhill,and F. Fox, IEEE Press, 2001.

l D.A. Hodges, H.G. Jackson, and R.A. Saleh, "Analysis and Design of Digital Integrated Circuits inDeep Submicron Technology", 3rd edition, McGraw Hill, 2004.

Lecture note will be posted online shortly before class sessions Supplement handouts

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Text Book

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Digital Integrated CircuitsA Design Perspective

Jan M. Rabaey

Anantha ChandrakasanBorivoje Nikolic


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Course SetupTwo 125 min lectures (Tue. & Thu. 1:00~3:05) @ EB2 T-206Prerequisite: Logic design, circuit theory, electronic

devices, computer architecture, and etc

No fixed discussion sessionl TA: Yesung Kang (), @ EB2 402 for CAD supports

HWs & CAD assignmentsl Roughly bi-weekly, 4~5 CAD assignmentsl Custom IC design methodologies

- Circuit design, layout, simulations, and logic design (Verilog HDL)- LVS and DRC- Etc.

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Grading BreakdownHW + CAD assignments: 30% (5+)Midterm Exam: 20%Final Exam: 30%Final Project and Report: 20%

CAD late policy: 25% penalty within 24 hours, 50% 24~48hours, no point after 48 hours (2 days)

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What you will learn in this class The entire process of very large-scale digital design (ASIC)

l Custom integrated circuit layoutl Sub-system design such as adders, register files, program counters, etc.l Synthesis + automated place/route design flow (?)

Advanced circuit design topics such as:l Multipliers, pulsed latches, memory decoder and sense amplifiers, etc.l Current technology issuesl Process variationsl Robust designl SRAMl Power and performance optimizationl Timingl Your interests and etc

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Research Area (NanoDA: Nano-System Design & Automation) Very Large Scale Integration (VLSI)

l Ex., >1 billion transistors in Intels 32nm Computer Aided Design (CAD)

l Efficient and inevitable way of design in VLSIl Still require human (custom) design in certain area

45nm = 45*10-9m = 0.000000045m

Human hair: 50um ~ 100um (x1000)4.5cm

12~30cm

270mm2

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The latest IC news

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8 cores Beckton die

45nm Intel Xeon~ 2.26GHz, 130W$3,692

Phoenix

mm-scale all-in-one computer5nW !! powerEye pressure sensor


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Transistors

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Recent Devices

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More Recent Devices

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More Recent Devices

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SOI (Silicon On Insulator)

High speed, low power


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Sub-5nm FinFET

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FinFET Conducting channel is wrapped by a thin silicon "fin", which forms the

gate of the device.


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Leakage Reduced

Why FinFET?Reduced Short Channel Effect Increase driving current high performanceBetter leakage current control low powerGood for low voltage (power) applicationsCompatible with current CMOS manufacturing and many more


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Carbon-based Transistors

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Major Bottlenecks Researches Managing complexity

l How to design a 10 billion transistor chip?l And what to use all these transistors for?l Mask complexity (e.g., OPC, double exposure, etc)

Cost of integrated circuits is increasingl It takes >$10M to design a chip, >$100M in 1~2 years (e.g., Snapdragon ~ $60M)l Mask costs are more than $3M in 45nm technology

The end of frequency scaling - Power as a limiting factorl Multi-core in a chip (e.g., dual, quad, 6, 8 cores, etc)l Beyond CMOS (?) after


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CMOS Process

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N-well LOCOS isolated CMOS process


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Circuit Under Design and Layout View

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Vin Vout Vout2

VDD

VSS


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The First Computer

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Use decimal

The BabbageDifference Engine

(1832)25,000 parts17,470 (in1834!)


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ENIAC - The first electronic computer (1946)

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Still decimal, ~18,000 vacuum tubes, 63m2, 150kW


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The Transistor Revolution

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First transistor

Bell Labs, 1948


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The First Integrated Circuits (IC)

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Bipolar logic

1960s

ECL 3-input Gate

Motorola 1966

1stIC by J. Kilby@TI, 1958


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Intel 4004 Micro-Processor

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1971~1981

4bit CPU10um pMOS only2300 transistors


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Modern microprocessors

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Pentium 4

180nm~65nm tech.~ 3.8GHz, ~125 mil. Trs.112mm2, 115W TDP (Thermal Design Power)LGA (Land Grid Array) 775

Core i7

45nm & 32nm tech.~ 3.47GHz, 731 mil. Trs.263mm2 , 18 ~ 130W TDPLGA 1366


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Moores Law

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In 1965, Gordon Moore noted that thenumber of transistors on a chip (or die)doubled every 18 to 24 months. (2 yrs 18 mon.)

He made a prediction thatsemiconductor technology will double itseffectiveness (e.g., tr #) every 18 months


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Moores Law

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Electronics, April 19, 1965.


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Evolution in Complexity

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Courtesy, Intel


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Moores law in Microprocessors

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40048008

80808085 8086

286386

486Pentium proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Transisto

rs(MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel


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Die Size Growth

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40048008

80808085

8086286386

486Pentium procP6

1

10

100

1970 1980 1990 2000 2010Year

Dies

ize(mm)

~7% growth per year

~2X growth in 10 years

Die size grows by 14% to satisfy Moores Law

Courtesy, Intel


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Frequency

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Lead Microprocessors frequency doubles every 2 years

But, not true anymore !

P6

Pentium proc486

386286

8086

8085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Frequency(Mhz)

Doubles every2 years

Courtesy, Intel


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Power Dissipation

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P6Pentium proc

486

3862868086

808580808008

4004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Pow

er(Watts)

Lead Microprocessors power continues to increase

Courtesy, Intel


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Power density

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400480088080

8085

8086

286386

486Pentium proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

PowerDensity(W/cm2)

Hot Plate

Nuclear

Reactor

RocketNozzle

Power density too high to keep junctions at low temp

Courtesy, Intel


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Not Only Microprocessors

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Digital Cellular Market

(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435MAnalog

Baseband

Digital Baseband

(DSP + MCU)

Power

Management

SmallSignal RF

PowerRF

(data from Texas Instruments)

CellPhone


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Challenges in Digital Design

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Microscopic Problems

Ultra-high speed designInterconnect Noise, Crosstalk Reliability, Manufacturability

Power Dissipation

Clock distribution.

Everything Looks a Little Different

Macroscopic Issues Time-to-Market Millions of Gates

High-Level Abstractions Reuse & IP: Portability

Predictability

etc.

and Theres a Lot of Them!

DSM 1/DSM

?


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Why Scaling?

Technology shrinks by 0.7/generation (49% smaller area)With every generation can integrate 2x more functions

per chip; chip cost does not increase significantly

Cost of a function decreases by 2xBut

l How to design chips with more and more functions?l Design engineering population does not double every two

years

Hence, a need for more efficient design methodsl Exploit different levels ofabstractionl Divide-and-conquerl CAD

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Design Abstraction Levels

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n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM


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Design Metrics

How to evaluate performance (quality) of a digitalcircuit (gate, block, )?

lCost: Mass productionl

Reliability: Military or MedicallScalabilitylSpeed (delay, operating frequency): serverlPower dissipation: handheld deviceslEnergy to perform a function

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Cost of Integrated Circuits


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Cost of Integrated Circuits

NRE (non-recurrent engineering) costs: fixedl design time and effort, mask generation T/Ol one-time cost factorl Depends on the complexity of the design, the spec. and designersl + R&D costs

Recurrent costs: variablel Silicon manufacturing processing, packaging, testl proportional to volumel proportional to chip area

= / + /41


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NRE Cost is Increasing

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IC design costs for many devices are projected to hit the dreaded $100million level within the next three years. Not long ago (and even today), ICdesign costs ranged between $20-to-$50 millionMentor CEO, EETimes, 3/2/2010

Di C t


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Die Cost

Single die

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Wafer

From http://www.amd.com

Going up to 12 (30cm)775um thickness

Cost per Transistor


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Cost per Transistor

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0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

cost:-per-transistor

Fabrication capital cost per transistor (Moores law)


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Yield

45

%100

per waferchipsofnumberTotal

per waferchipsgoodofNo.=Y

yieldDieper waferDies

costWafercostDie

=

( )

areadie2

diameterwafer

areadie

diameter/2wafer

per waferDies

2

=


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Defects

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processingmanufacturofcomplexityiswhere,

areadieareaunitperdefects1yielddie

+=

is approximately 3 ( ~ # of masks)Defects: 0.5 ~ 1 defects/cm2

4

area)(diecostdie f=


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Some Examples (1994)

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Chip Metal

layers

Line

width

Wafer

cost

Def./

cm2Area

mm2Dies/

wafer

Yield Die

cost

386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC601

4 0.80 $1700 1.3 121 115 28% $53

HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

Reliability


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Reliability

Noise in Digital Integrated Circuits

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i(t)

Inductive coupling Capacitive coupling Power and groundnoise

v(t) VDD

Noise: unwanted variations of (V) and (I) at the logic nodes


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DC OperationVoltage Transfer Characteristic (VTC)

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V(x)

V(y)

V

OH

VOL

VM

VOHVOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels (VDD=1, GND=0)

Vout = f(Vin)VOH = f(VOL)VOL = f(VOH)

VM = f(VM)


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Mapping between analog and digital signals

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VIL

VIH

Vin

Slope = -1 =

Slope = -1

VOL

VOH

Vout

0 VOL

VIL

VIH

VOH

Undefined

Region

1 dVout

dVin

Definition of Noise Margins


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Definition of Noise Margins

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Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate OutputStage M

Gate InputStage M+1

Noise Budget


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Noise Budget

Allocates gross noise margin to expected sources of noiseSources: supply noise, cross talk, interference, offsetDifferentiate between fixed and proportional noise sources

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Key Reliability Properties

Absolute noise margin values are deceptivel a floating node is more easily disturbed than a node driven by a

low impedance (in terms of voltage)

Noise immunity is the more important metric thecapability to suppress noise sources

Key metrics: Noise transfer functions, Output impedance of thedriver and input impedance of the receiver;

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Regenerative Property

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A chain of invertersv0 v1 v2 v3 v4 v5 v6

Simulated response


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Regenerative Property

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Regenerative Non-Regenerative


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Fan-in and Fan-out

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N

Fan-out N Fan-in M

M

Th Id l G t


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The Ideal Gate

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Ri =R

o = 0Fanout =NMH = NML = VDD/2

g=

Vin

Vout

A Old ti I t


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An Old-time Inverter

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NMH

Vin(V)

Vout(V)

NML

VM

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

D l D fi iti


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Delay Definitions

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Vin

Vout

Ri O ill t


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Ring Oscillator

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T = 2tpN

A First-Order RC Network


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vout

v

in

C

R

tp = ln (2) = 0.69 RC

Important model matches delay of inverter

Power Dissipation


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p

62

Instantaneous power:

p(t) = v(t)i(t) = Vsupplyi(t)

Peak power:Ppeak= Vsupplyipeak

Average power:

( ) + +

==Tt

t

Tt

t supplysupply

ave dttiT

Vdttp

TP )(

1

Energy and Energy-Delay


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gy gy y

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Power-Delay Product (PDP) =

E = Energy per operation = Pav tp

Energy-Delay Product (EDP) =

quality metric of gate = E tp

A First-Order RC Network


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E0 1

P t( ) dt

0

T

Vdd isupply t( ) dt

0

T

Vdd CLdV ou t0

Vd d

CL Vdd2= = = =

Eca p

Pca p

t( ) dt

0

T

Vou tica p t( )dt

0

T

CLVou t dVou t0

Vd d

1

2--- C

LV

dd2

= = = =

vout

vin CL!

R

Summary


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Summary

Digital integrated circuits have come a long way and stillhave quite some potential left for the coming decades

Some interesting challenges aheadlGetting a clear perspective on the challenges and potential

solutions is the purpose of this book

Understanding the design metrics that govern digitaldesign is crucial

lCost, reliability, speed, power and energy dissipation

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Looking Ahead


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g Read ch1, ch2Lecture 2: ch2, insert A

l Manufacturing processl Design rulesl Layoutl Etc

Documents

Lecture1 Intro Overview