[Lecture Notes in Computer Science] Advances in Computer Systems Architecture Volume 3740 || A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead

T. Srikanthan et al. (Eds.): ACSAC 2005, LNCS 3740, pp. 805 – 817, 2005. © Springer-Verlag Berlin Heidelberg 2005

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and

Other Adder Architectures

Himanshu Thapliyal and M.B. Srinivas

Center for VLSI and Embedded System Technologies, International Institute of Information Technology,

Hyderabad-500019, India [email protected], [email protected]

Abstract. Reversible logic is emerging as a promising area of research having its applications in quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. In this paper, a new 4 *4 reversible gate called “TSG” gate is proposed and is used to design efficient adder units. The proposed gate is used to design ripple carry adder, BCD adder and the carry look-ahead adder. The most significant aspect of the proposed gate is that it can work singly as a reversible full adder i.e reversible full adder can now be implemented with a single gate only. It is demonstrated that the adder architectures using the proposed gate are much better and optimized, compared to their counterparts existing in literature, both in terms of number of reversible gates and the garbage outputs.

1 Introduction

This section provides a simplified description of reversible logic with definitions and motivation behind it.

1.1 Definitions

Researchers like Landauer have shown that for irreversible logic computations, each bit of information lost, generates kTln2 joules of heat energy, where k is Boltzmann’s constant and T the absolute temperature at which computation is performed [1]. Bennett showed that kTln2 energy dissipation would not occur, if a computation is carried out in a reversible way [2], since the amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation. Reversible circuits are those circuits that do not lose information. Reversible computation in a system can be performed only when the system comprises of reversible gates. These circuits can generate unique output vector from each input vector, and vice-versa. In the reversible circuits, there is a one-to-one mapping between input and output vectors. Classical logic gates are irreversible since input vector states cannot be uniquely reconstructed from the output vector states. Let us consider Fig. 1.a from

806 H. Thapliyal and M.B. Srinivas

which it is obvious that a unique input vector cannot be constructed from the output vector. This is because for output 0, there are two input vectors AB=(00, 11). Now, considering Fig. 1.b, a reversible XOR gate, a unique input vector can be constructed for every output vector.

Fig. 1. (a) Classical XOR gate (b) Reversible XOR gate

1.2 Motivation Behind Reversible Logic

According to Laundauer [1,2], the use of logically irreversible gate, dissipates energy into the environment. In other words, Information Loss=Energy Loss. Whenever a logic operation is performed, the computer erases information. Bennett’s theorem [2] about heat dissipation is only a necessary and not a sufficient condition, but its extreme importance lies in the fact that every future technology will have to use reversible gates to reduce power. The current technologies employing irreversible logic dissipate a lot of heat and thus reduce the life of a circuit. The reversible logic operations do not erase (lose) information and dissipate very less heat. Thus, reversible logic is likely to be in demand in futuristic high-speed power-aware circuits. Reversible circuits are of high interest in low-power CMOS design [10], optical computing [11], nanotechnology [13] and quantum computing [12]. The most prominent application of reversible logic lies in quantum computers. A quantum computer will be viewed as a quantum network (or a family of quantum networks) composed of quantum logic gates; each gate performing an elementary unitary operation on one, two or more two–state quantum systems called qubits. Each qubit represents an elementary unit of information corresponding to the classical bit values 0 and 1. Any unitary operation is reversible hence quantum networks affecting elementary arithmetic operations such as addition, multiplication and exponentiation cannot be directly deduced from their classical Boolean counterparts (classical logic gates such as AND or OR are clearly irreversible).Thus, Quantum Arithmetic must be built from reversible logical components [14].

1.3 Definition-Garbage Output

Garbage output refers to the output that is not used for further computations. In other words, it is not used as a primary output or as an input to other gate. Figure 2 below elucidates the garbage output marked by *. Minimization of garbage outputs is one of the major challenges in reversible logic.

A Novel Reversible TSG Gate and Its Application 807

Fig. 2. Illustration of Garbage Output

1.4 A New Reversible TSG Gate

In this paper, the authors propose a new reversible 4*4 TSG gate and use it to design reversible ripple carry adder, BCD adder and carry look-ahead adder circuits. It is shown that the adder architectures using the proposed TSG gate are better than the existing ones in literature, in terms of number of reversible gates and garbage outputs. The reversible circuits designed in this paper form the basis of an ALU of a primitive quantum CPU [17,18,19].

2 Basic Reversible Gates

There are a number of existing reversible gates in literature. Five most important gates are used to construct the adder circuits along with the proposed TSG gate. A brief description of the gates is given below.

2.1 Fredkin Gate

Fredkin gate [3], a (3*3) conservative reversible gate originally introduced by Petri [4,5]. It is called 3*3 gate because it has three inputs and three outputs. The term conservative means that the Hamming weight (number of logical ones) of its input equals the Hamming weight of its output. The input triple (x1,x2,x3 ) associates with its output triple (y1, y2,y3) as follows:

y1=x1 y2= ~x1x2+x1x3 y3=x1x2+ ~x1x3

Fredkin gate behaves as a conditional switch, that is, FG(1; x2; x3) = (1; x3; x2) and FG(0; x2; x3) = (0; x2; x3). Figure 3 shows Fredkin gate symbol and its operation as a conditional switch.

2.2 New Gate

New Gate (NG) [6] is a 3*3 one-through reversible gate as shown in Fig. 4. The input triple (A,B,C) associates with its output triple(P,Q,R) as follows:

P=A; Q=AB^C; R=A'C'^B';


Fig. 3. Fredkin Gate Symbol and Its working as a Conditional Switch

Fig. 4. New Gate

2.3 R2 Gate

The R2 gate is a 4*4 reversible gate proposed in [20]. Figure 5 shows R2 gate along with input and output mapping.

Fig. 5. R2 Gate

2.4 Feynman Gate

Feynman gate [3,7,8] is a 2*2 one-through reversible gate shown in Fig.6. It is called 2*2 gate because it has 2 inputs and 2 outputs. One through gate means that one input variable is also the output. The input double (x1,x2) associates with its output double (y1,y2) as follows.

Y1=x1; Y2=x1^x2;

Fig. 6. Feynman Gate


3 Proposed 4* 4 Reversible Gate

In this paper, a ‘4*4 one through’ reversible gate called TS gate “TSG” is proposed and is shown in Fig. 7.The corresponding truth table of the gate is shown in Table 1. It can be verified from the truth table that the input pattern corresponding to a particular output pattern can be uniquely determined. The proposed TSG gate can implement all Boolean functions. Figure 8 shows the implementation of reversible XOR gate using the proposed gate and also the implementation of reversible NOT and NOR functions. Since, NOR gate is a universal gate and any Boolean function can be implemented through it, it follows that proposed gate can also be used to implement any Boolean function.

Fig. 7. Proposed 4 * 4 TSG Gate

Table 1. Truth Table of the Proposed TSG Gate

A B C D P Q R S

0 0 0 0 0 0 0 0

0 0 0 1 0 0 1 0

0 0 1 0 0 1 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 0 1

0 1 1 0 0 0 0 1

0 1 1 1 0 0 1 1

1 0 0 0 1 1 1 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 0 0

1 1 0 0 1 0 0 1

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 0

1 1 1 1 1 0 1 0


Fig. 8. (a) TSG Gate as XOR Gate (b) TSG Gate as NOT Gate (c) TSG Gate as NOR Gate

Fig. 9. TSG Gate as Reversible Full Adder

One of the most prominent features of the proposed gate is that it can work singly as a reversible full adder unit. Figure 9 shows the implementation of the proposed gate as a reversible full adder. A number of reversible full adders have been proposed in literature, for example, in [6,7,8,9]. While the reversible full adder circuit in [6] requires three reversible gates (two 3*3 new gate and one 2*2 Feynman gate) and produces three garbage outputs, the same in [7,8] requires three reversible gates (one 3*3 new gate, one 3*3 Toffoli gate and one 2*2 Feynman gate) and produces two garbage outputs. The design in [9] requires five reversible Fredkin gates and produces five garbage outputs. The proposed full adder using TSG in Fig. 9 requires only one reversible gate, that is, one TSG gate and produces only two garbage outputs. Hence, the full-adder design in Fig. 9 using TSG gate can be considered more optimal than the previous full-adder designs of [6,7,8,9]. A comparison of results is shown in Table 2.

Table 2. Comparitive Results of different full adder circuits

Number of Reversible Gates Used

Number of Garbage Outputs Produced

Unit Delay

Proposed Circuit

1 2 1

Existing Circuit[6]

3 3 3

ExistingCircuit [7,8]

3 2 2

Existing Circuit[9]

5 5 5


4 Applications of the Proposed TSG Gate

To illustrate the application of the proposed TSG gate three different types of reversible adders – ripple carry adder, BCD (Binary Code Decimal) adder and carry look-ahead adders are designed. It is shown that the adder circuits derived using the proposed gate are the most optimized ones compared to others mentioned above.

4.1 Ripple Carry Adder

The full adder is the basic building block in a ripple carry adder. The reversible ripple carry adder using the proposed TSG gate is shown in Fig. 10 which is obtained by cascading the full adders in series. The output expressions for a ripple carry adder are:

Si= A^B^Ci; Ci+1= (A^B).Ci ^AB (i=0, 1, 2….)

Fig. 10. Ripple Carry Adder Using the Proposed TSG Gate

Evaluation of the Proposed Ripple Carry Adder. It can be inferred from Fig. 10 that for N bit addition; the proposed ripple carry adder architecture uses only N reversible gates and produces only 2N garbage outputs. Table 3 shows the results that compare the proposed ripple carry adder using TSG gate, with those designed using existing full adders of [6,7,8,9]. It is observed that the proposed circuit is better than existing ones both in terms of number of reversible gates and garbage outputs.

4.2 BCD (Binary Coded Decimal) Adder

A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. Figure 11 shows the conventional BCD adder. A BCD adder must also include the correction logic in its internal construction. The two decimal digits, together with the input carry, are first added in the top 4-bit binary adder to produce the binary sum. When the output carry is equal to zero, nothing is added to


the binary sum. When it is equal to one, binary 0110 is added to the binary sum using another 4-bit binary adder (bottom binary adder). The output carry generated from the bottom binary adder can be ignored. Fig. 12 shows the proposed reversible BCD adder using the proposed reversible TSG gate. For optimized implementation of the BCD adder; New Gate (NG) is also used for producing the best optimized BCD adder.

Table 3. Comparative Results of the Reversible Ripple Carry Adders



Unit Delay

Proposed Circuit

N 2N N

Existing Circuit [6]

3N 3N 3N

Existing Circuit[7,8]

3N 2N 3N

Existing Circuit[9]

5N 5N 5N

Fig. 11. Conventional BCD Adder

Evaluation of the Proposed BCD Adder. The proposed 4-bit BCD adder architecture in Fig. 12 using TSG gates uses only 11 reversible gates and produces only 22 garbage outputs. A reversible BCD adder has been proposed recently [15] but, the BCD adder the proposed TSG gate is better than the architecture proposed in [15], both in terms of number of reversible gates used and garbage output produced. Table 4 shows the results that compare the proposed BCD carry adder using TSG gate with the BCD adder proposed in [15].


Fig. 12. Proposed Reversible BCD Adder Using TSG Gate

Table 4. Comparative Results of Reversible BCD Adders



Existing Reversible BCD Adder[15]

23 22

Proposed Reversible BCD Adder

11 22

4.3 Carry Look Ahead Adder

Carry look-ahead adder is the most widely used technique employed for reducing the propagation delay in a parallel adder. In carry look-ahead adder, we consider two new binary variables:

Pi=Ai^Bi Gi=AiBi

Then, the output sum and carry of full adder can be rewritten as follows:

Si=Ai^Bi^Ci=Pi^Ci Ci+1=AiBi+(Ai^Bi)Ci=AiBi^ (Ai^Bi)Ci=Gi^PiCi


The 4 bit reversible Carry look-ahead adder is created by expanding the above equations.

C1=G0^P0C0 C2=G1^P1C1=G1+P1G0+P1P0C0

C3=G2^P2C2=G2+P2G1+P2P1G0+P2P1P0C0

In the proposed 4-bit reversible carry look-ahead adder, the Pi, Gi and Si are generated from reversible TSG gate and Fredkin gate. The block generating Pi, Gi and Si is called PGA (Carry Propagate & Carry Generate Adder). The structure of PGA is shown in Fig. 13 and the complete structure of the 4-bit carry look-ahead adder is shown in Fig.14. In the complete design of CLA in Fig.14 appropriate gates are used wherever required for generating the function with minimum number of reversible gates and garbage outputs. The unused outputs in the Fig.14 represent the garbage outputs. In the design of a reversible circuit, copies of some of the bits are needed for computation purpose leading to fan-out which is strictly prohibited in reversible computation. In such a case, a reversible gate should be used for copying, but inappropriate selection of gate can lead to generation of garbage outputs. Thus, Feynman gate is used in this work for copying the bits. As there are exactly two outputs corresponding to the inputs of a Feynman gate, a ‘0’ in the second input will copy the first input in both the outputs of that gate. So, Feynman gate is the most suitable gate for single copy of bit, since it does not produce any garbage output.

Evaluation of the Proposed CLA. The proposed 4-bit reversible carry look-ahead adder is the most optimal compared to its existing counterparts in literature. The earlier proposed carry look-ahead adder in [16] has 22 gates while the proposed carry look-ahead adder has only 19 gates. Furthermore, the existing carry look ahead in literature uses two 5*5 reversible C5Not gate while the proposed reversible Carry look Ahead adder does not use any 5*5 reversible gate. Hence, the proposed reversible carry look-ahead adder is also optimized in terms of garbage outputs and number of reversible gate used. Table 5 provides a comparison of results of the reversible carry look-ahead adders.

Fig. 13. PGA Block in CLA generating Sum, Pi and Gi Using TSG and Fredkin Gate(F)


Fig. 14. Reversible CLA Designed with TSG, Fredkin(F), Feynman(FG) and R2 gate

Table 5. A Comparison of Results of Reversible CLA



Proposed Circuit

19 0

Existing Circuit[16]

22 2

5 Conclusions

This paper presents a new reversible 4*4 gate called TSG gate that has been used to design optimized adder architectures like ripple carry adder, BCD adder and carry look ahead adder. It is proved that the adder architectures using the proposed TSG gate are better than the existing ones in literature in terms of reversible gates and garbage outputs. Reversible logic finds its application in areas such as quantum computing, nano-technology, and optical computing and the proposed TSG gate and efficient adder architectures that have been derived thereof are one of the contributions to reversible logic. The proposed circuits can be used for designing


reversible systems that are optimized in terms of area and power consumption. The reversible gate proposed and circuits designed using this gate form the basis of an ALU of a primitive quantum CPU.

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[Lecture Notes in Computer Science] Advances in Computer Systems Architecture Volume 3740 || A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead