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Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Page 1: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Page 2: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Inthislecture,wewillfirstexaminepracticaldigitalsignals.Thenwewilldiscussthetimingconstraintsindigitalsystems.Theimportantconceptsarerelatedtosetup andhold times ofregistersandhowthese,togetherwithdelaytimeofcombinationalcircuit,determinehowfastadigitalsystemcouldrunat.

Page 3: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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ShownhereisadigitalsignalproducedbyanARMmicrocontrollerasmeasuredwithadigitaloscilloscope.ThisARMmicrocontrollerusesthe3.3Vlogicstandard,thesameasweusewiththeDE1-SOCboardinExperimentVERI.Thewaveformhasbothovershootsandundershootsimmediatelyaftertherisingandfallingtransitions.Partoftheovershootsareduetothescopeprobe(andtheinductanceinthegroundlead).However,evenon-chipdigitalsignalshavesomedegreeofovershoots.Furthermore,therecouldalsobespurioussignals(i.e.noise)coupledontoanydigitalsignals.Fortunately,digitalsignalsarecharacterisedaslow(‘0’)orhigh(‘1’)bythresholdvoltages.Shownontherightarethedigitalthresholdsdefinedfor5VTTLlogicand3.3Vlogic.Letusconsiderthehighlogiclevelfor3.3Vlogic.Twothresholdvoltagesaredefined:Voh=outputhighthresholdvoltage– alllogiccircuitswithahighoutputwilldriveacircuitnodeat2.4Vorhigher.Vih=inputhighthresholdvoltage– alllogiccircuitswillregardaninputvoltageashigh(‘1’)ifitis2Vorhigher.ThedifferenceVoh– Vih=0.4Visthemarginoferrorbetweenthedrivingcircuitandtheinputcircuit.Itiscalledthenoisemargin.Itistheamountofovershoot,undershootornoisethatcouldbetoleratedonadigitalsignalwirewithoutitbeinginterpretedwronglybythecircuit.Notethat3.3Vlogicisactuallycompatiblewith5VTTLlogic(i.e.theyhavethesamethresholdvoltages).Most3.3Vinputpinsare5Vtolerant,meaningthatitcanwithstandasignalupto5Vwithoutdamagingtheinternalcircuit.

Page 4: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Registers(D-FFs)areusedeverywhereindigitalcircuits.Usingregistershastheadvantageof:1)synchronisingallactivitiestoaclocksignal;2)isolate differentpartofthedigitalsystemsbetweenregisters(becausetheregistersblockthesignaluntilthenextactiveedgeoftheclock;3)makestimingconsiderationmucheasiertohandle.Inthecircuitshownhere,theD-flipflopistriggeredontherisingedgeoftheclock.ThevalueinDATAissampledandstored,andkeepasoutputQ.However,forreliableoperations,DATAMUSTBESTABLEsometimebeforetherisingedgeofCLOCK.ThistimeisknownassetuptimetS.ThistimeisneededbecausethereisinternalpropagationoftheDATAsignalwhichmustbetakenintoaccount.Asaresult,fortheD-flipfloptowork,suchinternaldelayisspecifiedastheflipflopsetuptimerequirement.Similarly,DATAMUSTBESTABLEandholdsitsvaluesometimeaftertherisingedgeofCLOCK.ThistimeisknownasholdtimetH.Whathappensifdatachangeswithinthesetup/holdtimewindow?TheQoutputbecomesunknown(couldbe‘1’ or‘0’,oratavoltagelevelthatisbetweenthetwo).EventuallyQwillgoto‘0’ or‘1’,butthetimeittakestoreachthestableQvalueisrandom!Suchastateoftheflipflopisknownasa“metastable” state.

Page 5: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Thewaveformsshownhereillustrateswhathappenswhensetuptimeviolationoccurs.TheDataOutsignalbecomesindeterminateforaperiodoftimebeforesettlingdowntoeither0or1.Whywouldthiscausecircuittofail.ThismetastablelogicsignalcouldbecapturedbytwodifferentD-FFs,onecouldresolveitsoutputAto‘1’,andanothercouldresolveitsoutputBto‘0’.Thereforethesamelogicsignalcouldbeinterpretedbythecircuitastwodifferentlogicvalues.MetastabilityisaproblemthatariseswhenanexternalinputNOTsynchronisedtothesystemclockisfedintooursynchronouscircuit.Sincetheinputsignalcouldchangeanytimerelativethetheclockedge,metastabilitywilloccur.Itcouldalsohappenswhenasignalcrossesfromoneclockdomain(Clock1)toanotherclockdomain(Clock2).Toavoidthemetastablesignalcausingerrorinthedigitalsystem,onecoulduseasynchronizationchainasshownbelow.

P could go metastable

Q is synchronised to Clock 2

Setup time of D-FF could be violated

Page 6: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Wehavepreviouslydiscussedthedelayincurredbydigitalgates.Evenwires(orPCBtracks)alsohasdelay.Foragivenwire,thereisacharacteristicinductanceLoandcharacteristiccapacitanceCo perunitlength.ThespeedofpropagationofadigitalsignalalongsuchawireisroughlythesquarerootofLoCo.Anotherway,toexpressthespeedofsignalpropagationalongawireoracoaxialcableisintermsofspeedoflight,c=30cm/ns).Thepropagationspeeddependsonthegeometryofthewireandtherelativepermittivityer ofthewire’sinsulation(orthePCBmaterial).Forcoaxcable,thespeedisaround67%ofthatofspeedoflight.Signaltravelsslightlyslower(57%ofspeedoflight)ontracksonPCBwithagroundplane(aPCBthathasanearthedsurfaceononeside).

Agoodruleofthumbisthatadigitalsignaltakesaround1nstotraveladistanceof15cmonaPCB.

Page 7: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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LetusconsidertwosystemsAandB,andwewanttosenddigitaldatabetweenthem.Theobviousmethodistosendthedigitaldataonebitatatime.Suchserialcommunicationmethodhasmanyadvantages:1)Itisverysimpletodo;2)itonlyneedsveryfewwireslinkingbetweenthetwosystems.Ifthecommunicationisgovernedbyaclocksignal,itisasynchronousbit-serialtransmissionsystem.Hereweneedaclocksignalandadatasignal.Sinceinmostcases,weareinterestedindatathataremorethanonebit(forexample,youmaybeinterestedinablockofdataoccupying,say,134bits).Thisblockofdataisknownasa“frame”.Toidentifywhenaframeofdatastarts,wemayneedanothersignalFRAMEtoindicatewherethefirstbitstarts.

Inthisexample,thesenderistriggeredonthefallingedgeoftheclock,andthereceiver(atB)istriggeredontherisingedgeoftheclock.

Page 8: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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HereisthetimingdiagramforthedatatravellingfromAtoBviaasynchronousseriallink.CAistheclocksignaltomoduleA.ItalsosupplyCB,butCBisdelayedbytC duetothepropagationfromAtoB.DAchangestP afterthefallingedgeoftheclock.ThepropagationdelayofthedatasignalistD.

Page 9: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Inordertoguaranteereliableworkingoftheserialinterfacecircuit,therisingedgeofCBmustbecomestableoutsidethesetuptimewindow(showninlightblue).

Page 10: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Inordertoconsiderthetimingconstraintsforthiscircuit,weonlyneedtofocusonthereceivingFFB.Weaskthequestions:1.WhenDBissampledontherisingedgeofCB,isDBstableornot?Theanswertothisquestionproducesthesetuptimerequirementconstraint.HereweconsiderwhatcausesDBtochange(thefallingedgeofCA),andhowlongittakesforthischangetopropagatetoDB(tP +tD).Thenweaddthesetuptimetothis(becauseCBMUSTBESTABLEtS beforetheclockedge).ThismustthenbeshorterthanthetimeawhichDBissampledbyCB.Thatis,thismustoccurontherisingedgeofCB(whichis½T+tC).

2.AfterDBiscapturedbytheFF,willDBholdsitsvaluelongenough?Wenowexamineaftersampling,whenwillDBchangenext.ThisoccursatT+(tP +tD),andproducestheholdtimeconstraint.

Page 11: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Letusplugsomenumbersintothesystemhere.NotethattimingconstraintssuchastP maybespecifiedasarangeofvalues.Inthiscase0<tP <10ns.Youmustchoosethemaximumvalue(worstcase)forparametersonleftsideof<,andminimumvalueontherightsideof<.

Herewecancalculatetheminimumperiod(andhencethemaximumfrequency)thatthecircuitcanoperatereliabilitywithoutviolatingeitherthesetuptimeortheholdtimeconstraints.

Page 12: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Whendoyouneedtoconsidertheseinequalities?Wheneveryouconsidersequentialcircuitswherethedataand/orclocksignalsarederivedfromthesamesource.

Page 13: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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NowletusconsidertheVerilogspecificationfora16-bitup-counter.TheredarrowshereindicatesthedelaypathsfromtherisingedgeoftheclocktotheQoutput,thenthroughthelogicblockD=Q+1andyoumustalsoaddinthesetuptimeoftheflipflop.NotehowthiscounterisspecifiedinVerilog.

Page 14: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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IfyouimplementthisontheCycloneIIIFPGA,youcanusethetiminganalyser,knownasTimeQuest,inQuartustoworkoutthetimingconstraintsforyou.Thisreportsthatthemaximumoperatingfrequencyofthecounteris498.5MHz.However,duetothelimitationsofthepins,themaximumobservablefrequencyis250MHz.Thisisbecausethepinsandpadsofthechipisratherslowerthantheinternallogic.(Thisyear,wewillbeusingCycloneVFPGAandthemaximumfrequencywillbedifferent.)

Page 15: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Forthiscircuit,italsoreportsthetimingslack.Wearerunningtheclockat20nsperiodor50MHz.Thenthesetuptimeslackis17.721ns.ThatisDsettlestoitsfinalvalue17.721nsearlierthanitisrequired.Slacktimeisameasureofthemarginyouhavebeforethecircuitstopsworkingreliability.(ValueswillbedifferentforCycloneVthisyear.)

Page 16: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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Holdtimeslackisreportedheretobe0.57ns.

Page 17: Lecture 8 - Timing Constraints - Imperial College London 8 - Timing Constraints.pdf · FRAME to indicate where the first bit starts. In this example, the sender is triggered on the

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