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8/14/2019 Lecture 6 Lecture 6 Logic Simulation Logic
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 1
Lecture 6
Logic Simulation
Lecture 6
Logic Simulation
s What is simulation?
s Design verification
s Circuit modeling
s True-value simulation algorithmss
Compiled-code simulations Event-driven simulation
s Summary
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 2
Simulation Definedimulation Defineds
Definition: Simulation refers to modeling of adesign, its function and performance.
s A software simulator is a computer program;
an emulator is a hardware simulator.
s
Simulation is used for design verification:s Validate assumptions
s Verify logic
s Verify performance (timing)
s Types of simulation:s Logic or switch level
s Timing
s Circuit
s Fault
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 3
Simulation for
Verification
Simulation for
Verification
True-value
simulation
Specification
Design
(netlist)
Input stimuliomputed
responses
Response
analysis
Synt hes i s
D e s i g n
c h a n g e s
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 4
Modeling for
Simulation
Modeling for
Simulations Modules, blocks or components described by
s Input/output (I/O) function
s Delays associated with I/O signals
s Examples: binary adder, Boolean gates, FET,
resistors and capacitors
s Interconnects represents ideal signal carriers, or
s ideal electrical conductors
s Netlist: a format (or language) that describes a
design as an interconnection of modules.
Netlist may use hierarchy.
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 5
Example: A Full-
Adder
Example: A Full-
AdderH A ;inputs : a , b ;
ou tputs : c , f ;
AN D : A1 , (a , b ) ,
(c ) ;
AN D : A2 , (d , e ) , ( f ) ;
OR : O1 , (a , b ) , ( d ) ;
NO T : N1 , (c ) , ( e ) ;
a
b
c
d
e
f
H A
F A ;
inputs : A , B , C ;
ou t pu t s : C a r r y , S um ;
HA : HA1 , (A , B ) , (D , E ) ;
HA : H A 2 , (E , C ) , (F , S um ) ;
OR : O2 , (D , F ) , (Car ry ) ;
H A 1
H A 2
A
B
C
D
E F
S u m
C ar r y
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 6
Ca
Logic Model of MOS
Circuit
Logic Model of MOS
Circuit
Cc
Cb
VDD
a
b
c
pMOS FETs
nMOS FETs
Ca
, Cb
a n d Cc
are
parasitic
capacitances
Dc
Da c
a
b
Da and D
b are
interconnect or
propagation
delays
Dc is inertial
delay
of gate
Db
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 7
Options for Inertial
Delay(simulation of a NAND gate)
Options for Inertial
Delay(simulation of a NAND gate)
b
a
c (CMOS)
T i m e un i ts 5
c (zero delay)
c (unit delay)
c (multiple delay)
c (minmax delay) min =2, max =5
rise=5, fall=5
T r ans i en treg ion
Unknown (X)
X
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 8
Signal Statesignal Statess Two-states (0, 1) can be used for purely
combinational logic with zero-delay.s Three-states (0, 1, X) are essential for
timing hazards and for sequential logic
initialization.
s Four-states (0, 1, X, Z) are essential for MOSdevices. See example below.
s Analog signals are used for exact timing of
digital logic and for analog circuits.
00
Z
(hold previous value)
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 9
Modeling Levelsodeling Levels
Circuitdescription
Programminglanguage-like HDL
Connectivity of
Boolean gates,flip-flops andtransistors
Transistor sizeand connectivity,node capacitances
Transistor technologydata, connectivity,node capacitances
Tech. Data, active/passive componentconnectivity
Signalvalues
0, 1
0, 1, X
and Z
0, 1and X
Analogvoltage
Analogvoltage,current
Timing
Clockboundary
Zero-delayunit-delay,multiple-delay
Zero-delay
Fine-graintiming
Continuous
time
Modelinglevel
Function,behavior, RTL
Logic
Switch
Timing
Circuit
Application
Architecturaland functionalverification
Logicverification
and test
Logicverification
Timingverification
Digital timingand analogcircuitverification
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 10
True-Value Simulation
Algorithms
True-Value Simulation
Algorithmss Compiled-code simulation
s Applicable to zero-delay combinational logic
s Also used for cycle-accurate synchronous sequential
circuits for logic verification
s Efficient for highly active circuits, but inefficient for
low-activity circuits
s High-level (e.g., C language) models can be used
s Event-driven simulations Only gates or modules with input events are evaluated
(event means a signal change )s Delays can be accurately simulated for timing
verification
s Efficient for low-activity circuits
s Can be extended for fault simulation
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 11
Compiled-Code
Algorithm
Compiled-Code
Algorithm
s Step 1: Levelize combinational logic and
encode in a compilable programming language
s Step 2: Initialize internal state variables (flip-
flops)s Step 3: For each input vector
Set primary input variables
Repeat (until steady-state or max. iterations)
s Execute compiled code
Report or save computed variables
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 12
Event-Driven
Algorithm
(Example)
Event-Driven
Algorithm
(Example)2
2
4
2
a =1
b =1
c =1
0
d =
0
e
=1
f =0
g =1
Time, t 4 8
g
t = 0
1
2
3
4
5
6
7
8
Scheduledevents
c = 0
d = 1, e = 0
g = 0
f = 1
g = 1
Activitylist
d , e
f , g
g
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 13
Time Wheel (Circular
Stack)
Time Wheel (Circular
Stack)
t=0
1
2
3
4
5
6
7
maxCurrent
time
pointer Event link-list
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 14
Efficiency of Event-
driven Simulator
Efficiency of Event-
driven Simulators Simulates events (value changes) only
s Speed up over compiled-code can be ten
times or more; in large logic circuits about
0.1 to 10% gates become active for an inputchange
Large logic
block withoutactivity
Steady 0
0 to 1 event
Steady 0
(no event)
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Feb. 2, 2001 VLSI Test: Bushnell-Agrawal/Lecture 6 15
Summaryummary
s Logic or true-value simulators are essential
tools for design verification.
s Verification vectors and expected responses
are generated (often manually) from
specifications.
s A logic simulator can be implemented using
either compiled-code or event-driven method.
s Per vector complexity of a logic simulator is
approximately linear in circuit size.
s Modeling level determines the evaluation
procedures used in the simulator.