Lecture-44 EE5325 Power Management Integrated Circuits

11/9/2018

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Lecture-44

EE5325 Power Management Integrated Circuits

Dr. Qadeer Ahmad Khan

Integrated Circuits and Systems Group

Department of Electrical Engineering

IIT Madras

1EE5325 Power Management Integrated Circuits Integrated Circuits and Systems Group, Department of EE, IIT Madras

DC-DC Converter Wish List

High Power Density– Higher efficiency to reduce heat

dissipation

– Smaller passive components to reduce board space

– Shrinking die size by innovative controller and integrating more features on single PMIC

Stable Supply– High performance controller design

2

Source:Vishay

± 5%

Time

Load Current

Output Voltage

EE5325 Power Management Integrated Circuits Integrated Circuits and Systems Group, Department of EE, IIT Madras

11/9/2018

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Technology Trends in PMIC

3

Scaling semiconductor process technology

Higher speed Power FETs

Smaller Size

Low parasitic packaging technologies (WLP, BGA)

Smaller Parasitic

SOP WLPQFN

DIP

0.5µm 0.35µm 0.18µm


3

Power Management Module

Source: TechInsights Inc.

PMIC

Pas

sive

Co

mp

on

ents

(In

du

cto

rs a

nd

Cap

acit

ors

)

PMIC vs Passive Size

4

Samsung Galaxy S8

External Passive components (L and C) occupy 2/3rd of the total power module size


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Passive Size Reduction

Output ripple is a function of inductor (L), capacitor (C) and switching frequency (FSW)

Doubling switching frequency reduces passive components by 4x for the same output ripple

PMIC PMIC PMIC

Increasing FSW

Source: Micrel

LVSW

CO

VO

ILΔVO VO

OSW

OLCF

V11

2Output Ripple:

FSW=1MHz FSW=4MHz

FSW=8MHz


Limitations of Analog Controller

6

PID Compensator

– Area/power inefficient

Error Amplifier (EA)

– Bandwidth limits transient response

Ramp Generator

– Limits switching frequency

PWM Comparator

– Delay limits output range

VREF

CDR1C1

EA

VOL

VPWM Gate Driver

VIN

MP

MN

VSW

RD

CO

Type-III (PID) Compensator

VRAMP

VCTRL

Analog PWM

Voltage-to-Time Conversion


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Limitations of Analog Controller

7

PID Compensator

– Area/power inefficient

Error Amplifier (EA)

– Bandwidth limits transient response

Ramp Generator

– Limits switching frequency

PWM Comparator

– Delay limits output range

Significant power penalty at high FSW

VREF

CDR1C1

EA

VOL

VPWM Gate Driver

VIN

MP

MN

VSW

RD

CO

Type-III (PID) Compensator

VRAMP

VCTRL

Analog PWM

Voltage-to-Time Conversion


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Digital Controller Design Challenges

8

Small controller area at low Fsw

Non-linear loop dynamics– Steady state is a bounded limit

cycle large ripple

ADC res. > reg. accuracy

– 0.1% accuracy 10bit

DPWM res. inverter delay – Large area and power

FCLK >> FSW

VOL

VPWM Gate Driver

VIN

MP

MN

VSW

CO

Digital PWM

Digital-to-Time Conversion

DPWM

DC[M:0]

CLK

VREF

+

-VeADC

PID Compensator

Ki

Kp

Kd

1-z-1

1

-1z-1

DE[N:0]


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Digital Controller Design Challenges

9

Small controller area at low Fsw

Non-linear loop dynamics– Steady state is a bounded limit

cycle large ripple

ADC res. > reg. accuracy– 0.1% accuracy 10bit

DPWM res. inverter delay – Large area and power

FCLK >> FSW

VOL

VPWM Gate Driver

VIN

MP

MN

VSW

CO

Digital PWM

Digital-to-Time Conversion

DPWM

DC[M:0]

CLK

VREF

+

-VeADC

PID Compensator

Ki

Kp

Kd

1-z-1

1

-1z-1

DE[N:0]

Significant power & area penalty at high FSW


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Time Based Controlled DC-DC Converter

10

Preserves benefits of both analog (low power, high accuracy) and digital (process scaling, low voltage operation, area efficient) without using any A/D or error amplifier

Implicit PWM generation Eliminates PWM modulator hence minimum delay

LGate

Driver

Vin

VPWM

SP

SN

VO

CO

VSWVoltage-to-Time

Conversion

VREF

+

- VeTime Domain

Processing

fPWM

Processing is done in

Time Domain

Voltage is directly

converted into TimeSince resultant output is Time, it

doesn’t require any PWM modulator


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Time Based Controlled DC-DC Converter

11

Preserves benefits of both analog (low power, high accuracy) and digital (process scaling, low voltage operation, area efficient) without using any A/D or error amplifier

Implicit PWM generation Eliminates PWM modulator hence minimum delay

LGate

Driver

Vin

VPWM

SP

SN

VO

CO

VSWVoltage-to-Time

Conversion

VREF

+

- VeTime Domain

Processing

fPWM

Processing is done in

Time Domain

Voltage is directly

converted into TimeSince resultant output is Time, it

doesn’t require any PWM modulator

Power and area efficient


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12

VCO as Time-based Integrator

𝝎𝑶𝑼𝑻 = 𝑽𝑰𝑵𝑲𝑽𝑪𝑶 𝝎𝑶𝑼𝑻 =𝒅𝑶𝑼𝑻𝒅𝒕

𝑯𝑽𝑪𝑶 𝒔 =𝑶𝑼𝑻(𝒔)

𝑽𝑰𝑵 𝒔=𝑲𝑽𝑪𝑶𝒔

VIN

OUT

VCO

Frequency

KVCO

ωUGB = KVCO

HVCO(s)

VCO acts as an ideal V-to-Φ integrator


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13

VCO Behavior in Time Domain

𝑫𝑶𝑼𝑻−𝑪𝑳𝑲𝑹𝑬𝑭= 𝑲𝑽𝑪𝑶

𝟎

𝒕

𝑽𝑰𝑵 𝝉 𝒅𝝉

𝑫𝑶𝑼𝑻 =𝑫𝑶𝑼𝑻 − 𝑪𝑳𝑲𝑹𝑬𝑭

𝟐𝝅

PD

CLKREF

DOUT

V-to- -to-D

VCO

VINCLKVCO

VIN

CLKREF

DOUT

CLKVCO

𝑫𝑶𝑼𝑻 =𝑲𝑽𝑪𝑶𝟐𝝅

𝟎

𝒕

𝑽𝑰𝑵 𝝉 𝒅𝝉


Example of Phase Accumulation

𝒇𝒐 =10MHz (free running

frequency of VCO)

Or 𝝎𝒐 = 𝟐𝝅 ∙10MHz

𝑲𝑽𝑪𝑶=𝟐𝝅Mrad/s/V

Then phase difference will

become 𝟐𝝅 every 10th cycle of

the clock

PD

CLKREF

DOUT

V-to- -to-D

VCO

VINCLKVCO

Phase difference becomes 2π


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Opamp-RC vs Time Based Integrator

15

Voltage Based Integrator Input voltage is integrated as

voltage

Integral Gain = 1/RC

Time Based Integrator Input voltage is integrated as phase

(time) by VCO

Integral Gain = KVCO

VREF

R

C

VIN

VOUT

VOUT

VREF

VIN

VCOCLKCTRL

PDCLKREFVREF

VCO

Low-Pass

Filter

PWM

VIN

VOUT

VREF

VIN

VOUT

CLKCTRL

CLKREF

PWM

f1 f2 f1

fREF

f1 > fREF ; f2 < fREF


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Buck w/ Time-based Type-I Controller

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FVCO

L VO

CO

VPWM

PD

VIN

VREF

RVCO

TONVPWM

CTRL

REF

CTRL

REF

2π

TOFF TON


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Time Based PID Controller

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Need 3 functions to realize time based PID compensator:

1. Time based Integrator VCO

2. Time based Proportional (Gain) ?

3. Time based Differentiator ?


17

Time-based Proportional Control

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VCDL acts as an ideal V-to-Φ converter

OUT

VIN

CLKREF

VCDL

Frequency

HVCDL(s)

KVCDL


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Time-based Differentiator

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H.P. filter + VCDL acts as an ideal V-to-Φ differentiator

VIN

RD

CD VD

CLKREF

OUT

VCDL

Frequency

HDIFF(s)

KVCDLRDCD

1


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Buck Converter with T-PID Controller

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• Integral gain KVCO of FVCO

• Proportional gain KVCDL of VCDL1

• Derivative gain RDCD and KVCDL of VCDL2

VCDL1 VCDL2

RDCD

FVCO

VREF

RVCO

ΦI ΦI+ΦP ΦI+ΦP+ΦD

ΦREF

LVO

CO

VPWM

PD

VINΦCTRL

I P D


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Mapping V-PID to T-PID (1)

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VCTRL

VREF

R1

PID Compensator

C3

R2C1

C2

EA

R3

VFB

Ignoring wp and simplifying


21


22

VCTRL

VREF

R1

PID Compensator

C3

R2C1

C2

EA

R3

VFB

Ignoring wp and simplifying

Proportional Integral Derivative


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VCDL1 VCDL2

RDCD

VCO

VFB

CTRL


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T-PID Transfer Function

Phase

Gain-20dB/dec

0°

0dB

wZ1 wZ2 wP

-90°

+

-

+

sCR

sCRK

DD

DDVCDL

1

2

s

K VCO

1VCDLK

2

1

ɸP(s)

ɸI(s)

ɸD(s)

ɸCTRL(s) )(sHLC

VREF

VO

TPID Compensator

Phase

Detector

LC Filter

DD

PCR

w1

w(rad/s)

HTPID(s)

HTPID(s)

wUGB

I

P

D

VIN

Driver

VPWM VSW Ve

+20dB/dec

PM

VO

IVCO KK

21

1

11

zz

IVCDLww

KK21

2

11

zzDD

VCDLwwCR

K

;

;


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Circuit Implementation

25

Phase detector is implemented with SR latch

Fully differential control eliminates reference clock

Shared VCDL for proportional and derivative control

VFB

VCO+

VCO-

RD

CDVD D

GMI

iI

GMP

iP

GMD

iD

VREF

R

S

QD

EA

D

TIM

E

LO

GIC

MP

MN

L

CO

RFB1

VCDL+

VCDL-

VIN

P I

VREF VREF

RFB2

VPWM

VREF

CTRL+

CTRL-

VO

VFB


25

Prototype Buck Converter in 180nm CMOS

26

Controller

Gate Driver &Power FETs

VIN

VFB GNDVREF VOUT

250µ

m

150µm 400µm

450µ

m

2.5

mm

2mm

CCO and CCDL

Gm Cells

PMOS

NMOS

• “A 10–25 MHz, 600 mA buck converter using time-based PID compensator with 2µA/MHz quiescentcurrent, 94% peak efficiency, and 1MHz BW,” Symposium on VLSI Circuits (VLSIC), June 2014.

• "High frequency buck converter design using time-based control techniques," IEEE JSSC, Apr. 2015.


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Steady-State Waveforms (VO = 1V)

27

VVCO+

VPWM

VVCO-

2π

TON TOFF

VO=1V D=TON

TOFF

=58.2%TSW


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Load Transient Response

28

600mA

VO

ILOAD

VUN=60mVTS=3.5µs

VOV=65mV

100mV

20µs

Vripple=3.5mV 2mV

50ns

VO

VPWM100mA


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Oscillator Frequency Spectra

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Closed Loop FVCO+

Open Loop FVCO+

Closed Loop FVCO-

Open Loop FVCO-

FSW = 11MHz


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Efficiency vs. Output Current

30

0 100 200 300 400 500 60060

65

70

75

80

85

90

95

100

Output Current [mA]

Eff

icie

ncy [

%]

Fsw=11MHz@Vo=1V

Fsw=11MHz@Vo=0.6V

Fsw=11MHz@Vo=1.4V

Fsw=15MHz@Vo=1V

Fsw=20MHz@Vo=1V

Fsw=25MHz@Vo=1V


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Performance Summary

31

Publication ISSCC 2014 This Work

Control LoopVoltage mode

PID

Time based

PID

Process 0.13µm CMOS 0.18µm CMOS

Supply Voltage 3.3V 1.8V

Output Voltage 0.37V – 2.85V 0.6V – 1.5V

FSW 10MHz(30MHz) 11-15MHz

L / C 330nH/3.3µF(1uF) 220nH/4.7µF

Max. Load Current 1.5A@VO=2.4V 600mA

Settling Time n/a 3.5µs

Output Ripple n/a 3.5mV

Controller Current n/a 23µA@11MHz

Peak Efficiency 91.8%(86.6%) 94%@VO=1V

Active Area n/a 0.24mm2


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Since VCOs come inherently with multiple phases, different phases from VCOs can be tapped

All phases use common integrator (VCO) but separate VCDLs

Application in Multi-Phase

PDPD

PD

PD

ɸI0

ɸI1

ɸI2

ɸI3

ɸI4

VO

CO

ɸ0

ɸ1

ɸ2

ɸ3

ɸ4

PD

ɸ0

ɸ1

ɸ2

ɸ3

ɸ4

VCDL1VCDL2ɸCTRL0

ɸCTRL1

ɸCTRL2

ɸCTRL3

ɸCTRL4

ɸREF0

ɸCTRL1

ɸREF1

ɸCTRL2

ɸREF2

ɸCTRL3

ɸREF3

ɸCTRL4

ɸREF4

ɸREF1

ɸREF2

ɸREF3

ɸREF4

RD CD

L

MULTI-PHASE

TPID Controller

FVCO

RVCO


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30-70MHz 4-Phase Time-Based Buck

D

0 2

CSDH

LF1

R1

Compensator

Phase

Controller

EN1~4

L1-4

VO

GMPD

VREF

CCOFCCDLF

CCORCCDLR

GMI

CD

RD

VPWM4

PG1

F4 EN4HL

VPWM3

PG1

F3 EN3HL

VPWM2

PG1

F2 EN2HL

VPWM1

PG1

F1

R1

EN1HL

C

R2

R3

R4

F1

F2

F3

F4

RFB1

RFB2

VREFZ

-1

FD

B2T

8

0

2 2

3

0

2 2

3

R1~4

F1~4

MPG

R1

F

R

DAC

D-to-I

FLL

VREF

1mm

1m

m

Gate

Diver

Gate

Diver

Gate

Diver

Cascoded

Output Driver

Gate

Diver

Cascoded

Output Driver

Cascoded

Output Driver

Cascoded

Output Driver

Type-III

Compensator

MPG, CSD

Phase Ctrl

FLL

Number of Phases 4

Input Supply [V] 4-5

Output Voltage [V] 0.86-3.93

FSW[MHz] 25-70

Inductance [nH] 110-220

Load Current [A] 1

Controller Current N/A

Peak Efficiency [%] 83@VO=3.3V

Power Density [W/mm2] 1.2

Control Hysteretic

Process 0.5µm CMOS

JSSC `09P. Li

4

1.8

0.6-1.5

30-70

90

0.8

90µA@30MHz

87@VO=1V

2.5

T-PID PWM

65nm CMOS

This Work

4

1.2/1.4

0.9/1.1

233

2.5

0.3/0.4

N/A

83.2/84.5

1.93/3.14

Hysteretic

90nm CMOS

JSSC `05Hazucha

4

1.5

1

500

1.5

N/A

N/A

68@VO=1V

N/A

Digital PWM

22nm CMOS

VLSI`14Harish

Capacitance [nF] 8-190470 6.8 10

Synchronization DLLMPG Injection DPWM

• A 1.8V 30-to-70MHz 87% Peak Efficiency 0.32mm2 4-Phase Time-Based Buck Converter Consuming 3uA/MHz Quiescent Current in 65nm CMOS, “ ISSCC-2015.

• A 4-phase 30-70 MHz switching frequency buck converter using a time-based compensator," IEEE JSSC, Dec. 2015


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Documents

Lecture-44 EE5325 Power Management Integrated Circuits