Lecture 20: VLSI CAD Tools VLSI System Design Slide 33. Simulation Tools Simulators are probably the

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Text of Lecture 20: VLSI CAD Tools VLSI System Design Slide 33. Simulation Tools Simulators are probably the

  • Lecture 20: VLSI CAD Tools

    Slides courtesy of Deming Chen, Leslie Hwang, Ashutosh Dhar

  • Intro. VLSI System Design

    Last lecture  Alternative design options

    – Microprocessor/DSP – Programmable Logic – Gate Arrays and Sea of Gates – Cell-based Design – Full Custom Design – System on a Chip – Intellectual Property (IP)

    ECE 425 Slide 2

  • Intro. VLSI System DesignECE 425 Slide 3

    Outline  Overview

    – Design Languages – CAD Tools

    • Design Capture Tools • Synthesis Tools • Verification Tools

    – Vivado Design Suite from Xilinx as a case study

     Reading – Part of the lecture comes from Text 14.4

  • Intro. VLSI System DesignECE 425 Slide 4

    Design Systems  As we have seen, a design system is a set of computer-aided design

    (CAD) tools, used to simplify the design and verification tasks.

  • Intro. VLSI System DesignECE 425 Slide 5

    Design Flow  Design flow is a set of procedures designers progress from

    specification for a chip to the final chip implementation in error-free way

    Structural level: gates and registers

    Synthesis: transformation to physical (layout) description

    RTL: logic and memory elements

    ASIC design: flows partitioned between different EDA companies

    Behavioral level: operation of the system without implementation

  • Intro. VLSI System DesignECE 425 Slide 6

    Design Languages

     A design can be described at different levels of abstraction (high- low): – Architectural level – Finite State Machine level – Logic level – Symbolic level, e.g., PLA – Transistor, or switch level – Sticks level – Mask level

  • Intro. VLSI System DesignECE 425 Slide 8

    Architectural Level  Procedural (Architectural Level) Languages

    – Primitives are functions and variables – Gives an algorithmic description of the design

    • Important special case is Register Transfer Languages (RTL)

    • Registers hold the variables • Arithmetic units perform the operations on the variables

  • Intro. VLSI System DesignECE 425 Slide 9

    Logic and FSM Level

     Finite State Machine Languages – A symbolic description of states

    and state transitions – A behavioral description – Not structural, not geometrical – E.g. microprocessor controller – Can be compiled into PLAs or

    logic • The compiler must make

    structural and geometrical decisions.

  • Intro. VLSI System DesignECE 425 Slide 10

    Logic Level  Logic Languages

    – The primitives are logic gates and nodes • Higher level and more versatile than PLA

    – Describes logical structure, but no spatial relationships – Can be transformed, or compiled, into a switch language

  • Intro. VLSI System DesignECE 425 Slide 11

    Transistor, Switch and Symbolic Level

     Transistor, or Switch, Languages – The primitives are transistors and nodes – Specifies electrical topology – No spatial relationships – Not easily transformed to a geometry

    specification – Easily extracted from layout – Suitable for simulation

     Symbolic Languages – Slightly higher level than transistors

    • E.g. PLA dot diagram – Usually specialized for specific layout styles

  • Intro. VLSI System DesignECE 425 Slide 12

    Stick Level  Sticks Languages

    – These are virtual or symbolic layout descriptions • A popular example is the LAVA language

    – Transistors and vias are represented as points on a grid – Wires are represented as zero-width lines – Gives the relative positions of circuit elements

  • Intro. VLSI System DesignECE 425 Slide 13

    Geometry or Mask Level  Geometry Languages

    – Use colored rectangles or shapes as their primitives • A popular example is the Caltech Intermediate Form (CIF)

    – One can directly fabricate a chip from its description

    CIF example

  • Intro. VLSI System DesignECE 425 Slide 14

    CAD Tools  Modern design systems use a variety of CAD tools, including:  Design-capture tools

    – These tools help translate an idea into a high-level design description

     Synthesis tools – These tools translate a higher-level description into a lower-

    level one  Verification tools

    – These tools verify that a lower-level implementation is equivalent to a higher-level one

     Typically, the design process is not completely automated.  Instead, the various CAD tools are used at the designer’s

    discretion to facilitate and validate the design tasks.  CAD tools need to understand both the language and the

    primitives that the language refers to

  • Intro. VLSI System DesignECE 425 Slide 15

    Design Capture Tools

     Design-capture tools are the first tools to be used.  They provide an interface between what the designer

    has in mind and the high-level design description.  There are two general methods of design capture

    Textually: body of code Schematically: graphical

  • Intro. VLSI System DesignECE 425 Slide 16

    Hardware Description Languages

    Many design systems allow designers to use a free mix of code and diagrams.

     In general, schematics are easier to understand, but HDLs may be easier to modify.

     Textual design specification is in terms of a Hardware Description Language (HDL).

     HDLs allow one to specify the circuit structure and behavior.

     The most popular (and standardized) HDLs – Verilog, SystemVerilog – VHDL

  • Intro. VLSI System DesignECE 425 Slide 17

    Schematic Capture Tools  Schematic capture tools allow the user to graphically

    draw and connect components.  A collection of components are grouped into a

    module, for which a symbol may be defined.  This symbol may be used in another module,

    hierarchically, throughout the design.

  • Intro. VLSI System DesignECE 425 Slide 18

    An Example for Schematic Capture

     Here’s a typical module schematic and the corresponding icon:

  • Intro. VLSI System DesignECE 425 Slide 19

    Layout Editors  Design capture tools are typically used at the RTL

    and logic levels.  They can also be used at the lowest (layout) and

    highest (architecture) levels.  Layout editors accept a

    design description in terms of shapes, sizes, and attributes.

     They typically interface with a Design Rule Checking program and an extraction program.

  • Intro. VLSI System DesignECE 425 Slide 20

    Synthesis Tools  Effectively, these tools transform the design specification from

    the abstract (high-level) to the concrete (low-level) – For example: given a Boolean function, find a “good” choice

    and arrangement of logic gates that implement it. – The solution to this problem is called logic synthesis.

     As the name implies, synthesis tools build the design.

  • Intro. VLSI System DesignECE 425 Slide 21

    High-level (or Behavioral) Synthesis Design Flow  Given a description of the behavior of the design, a behavioral compiler

    should: – Schedule the sequence of operations to be performed – Allocate hardware resources to these operations – Create microcode and/or control logic

     This process is technology-independent and is generally very difficult to perform optimally.

    High-level Synthesis

    High-level Verification

  • Intro. VLSI System DesignECE 425 Slide 22

    High-Level (Behavioral) Synthesis

     This process is trying to optimize circuit area, power, and delay, etc.

     Such high-level synthesis has gained popularity especially for FPGA designs – bit-serial digital filters – deep neural networks – signal-processing architectures

     In more general cases, manual synthesis usually still gives better results especially for ASIC designs.

     An increasing important area due to growing design complexity

     Tool suppliers: Cadence Design Systems, Mentor Graphics, Altera, Xilinx, etc.

  • Intro. VLSI System DesignECE 425 Slide 23

    Logic (RTL) Synthesis  Given an RTL description of a design, logic synthesis looks

    for an optimal gate-level implementation, through a two-step process: – Translation

    • Reads an HDL description (e.g., VHDL or Verilog) • Converts the HDL into a set of registers and

    combinational logic • May also need to do state assignment

    – Optimization • Transforms the logic to improve area, power, delay,

    testability, etc.  Tool products:

    – Synopsys: Design Compiler, Synplify Pro, RTL Compiler – Timing – prime time (synopsys) – for STA – Power – Spyglass, prime power, UPF files

  • Intro. VLSI System DesignECE 425 Slide 24

    RTL Synthesis  The solution methods are well understood and mature. It

    involves two phases: – A technology-independent phase

    • The logic is optimized using algebraic and/or Boolean techniques

    – A technology-mapping phase • Specific library cells are chosen to implement the

    optimized

    High-level Synthesis

    High-level Verification