Lecture 17 Compensation of Feedback Amplifiers Two-Stage

EE 435

Lecture 17

Compensation of Feedback Amplifiers

Two-Stage Op Amp Design Strategies

CompensationCompensation is the manipulation of the poles and/or zeros

of the open-loop amplifier so that when feedback is applied,

the closed-loop circuit will perform acceptably

Acceptable performance is often application dependent and somewhat interpretation

dependent

Although some think of compensation as a method of maintaining stability with

feedback, acceptable performance generally dictates much more stringent

performance than simply stability

Compensation criteria are often an indirect indicator of some type of desired (but

unstated) performance

Varying approaches and criteria are used for compensation often resulting in

similar but not identical performance

Acceptable performance should include affects of process and temperature

variations

Over compensation often comes at a considerable expense (increased power,

decreased frequency response, increased area, …)

.• • • • • Review from last lecture .• • • • •

Nyquist Plots

The Nyquist Plot is a plot of the Loop Gain (Aβ) versus jω in the complex plane

for - ∞ < ω < ∞

Theorem: A system is stable iff the Nyquist Plot does not encircle the point

-1+j0.

Note: If there are multiple crossings of the real axis by the Nyquist Plot,

the term encirclement requires a formal definition that will not be presented

here

Review of Basic Concepts.• • • • • Review from last lecture .• • • • •

Nyquist PlotsReview of Basic Concepts

-1+j0 Re

Im

-1+j0 is the image of ALL poles

The Nyquist Plot is the image of the entire imaginary axis and separates

the image complex plane into two parts

Everything outside of the Nyquist Plot is the image of the LHP

Nyquist plot can be generated with pencil and paper

Re

Im

s-plane A(s)β

FBD s = 1+A s β s

Important in the ‘30s - ‘60’s


Nyquist Plots

Review of Basic Concepts

-1+j0 Re

Im

Unit Circle

Phase

Margin

Phase margin is 180o – angle of Aβ when the magnitude of Aβ =1


Nyquist Plots

Review of Basic Concepts

-1+j0 Re

Im

Unit Circle

Gain

Margin

Gain margin is 1 – magnitude of Aβ when the angle of Aβ =180o


Nyquist and Gain-Phase Plots

-40

-30

-20

-10

0

10

20

30

40

50

60

70

Nyquist and Gain-Phase Plots convey identical information but gain-phase

plots often easier to work with

-300

-250

-200

-150

-100

-50

0

Note: The two plots do not correspond to the same system in this slide

ω = -∞

ω = ∞

ω = 0-1+j0

Im

Re

ω

Mag Phase

Mag

Phase

ω

ω


1000A s

ss+1 +1

200

Gain and Phase Margin Examples

Magnitude in d

BA

ngle

in d

egre

es

1β

ω

Phase Margin

ω

β=.031

But is it a good compensation ?Stable !


1000A s

ss+1 +1

200

Gain and Phase Margin Examples

Magnitude in d

BA

ngle

in d

egre

es

1β

ω

Phase Margin

ω

Unstable !

β=.31


In general, the relationship between the phase margin and the

pole Q is dependent upon the order of the transfer function and on

the location of the zeros

In the special case that the open loop amplifier is second-order low-

pass, a closed form analytical relationship between pole Q and phase

margin exists and this is independent of A0 and β..

)sin(φ

)cos(φQ

M

M

24

1

M2Q

1

4Q

11cosφ

The region of interest is invariable only for 0.5 < Q < 0.7

larger Q introduces unacceptable ringing and settling

smaller Q slows the amplifier down too much

Relationship between pole Q and phase margin

Phase Margin vs Q

0

1

2

3

4

5

6

7

0 20 40 60 80 100

Phase Margin

Po

le Q

Second-order low-pass Amplifier

Phase Margin vs Q

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

40 50 60 70 80

Phase Margin

Po

le Q


Phase Margin vs Q

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

40 50 60 70 80

Phase Margin

Po

le Q


Q=.707

Q=0.5

φM ≈65o φM ≈77o

.707< Q <0.5 65o < φM < 75o

Phase Margin vs Q

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

40 50 60 70 80

Phase Margin

Po

le Q

Phase-Margin Compensation Criteria

Q=.707

Q=0.5

φM ≈65o φM ≈77o

.707< Q <0.5 65o < φM < 75o

• This relationship holds only for 2nd-order low-pass open loop amplifiers

• Considerable evidence of use of these phase margin criteria when not 2nd-order

low-pass but not clear what relevance this may have for FB performance

Magnitude Response of 2nd-order Lowpass Function

Q2

1

From Laker-Sansen Text

QMAX for no peaking = 7072

1.

Phase Response of 2nd-order Lowpass Function

From Laker-Sansen TextQ2

1

Step Response of 2nd-order Lowpass Function

QMAX for no overshoot = 1/2

From Laker-Sansen Text

Q2

1

From Laker-Sansen TextQ2

1

Step Response of 2nd-order Lowpass Function

Compensation Summary

• Gain and phase margin performance often strongly dependent upon architecture

• Relationship between overshoot and ringing and phase margin were developed only for 2nd-order lowpass gain characteristics and differ dramatically for higher-order structures

• Absolute gain and phase margin criteria are not robust to changes in architecture or order

• It is often difficult to correctly “break the loop” to determine the loop gain Aβ with the correct loading on the loop (will discuss this more later)

Design of Two-Stage Op Amps

• Compensation is critical in two-stage op amps

• General approach to designing two-stage op

amps is common even though significant

differences in performance for different

architectures

• Will consider initially the most basic two-stage

op amp with internal Miller compensation

Basic Two-Stage Op Amp

04o2odo6o5oo gggandggg

m1md gg

VDD

VSS

M1

M2

M3 M

4M

5

CL

VIN

VOUT

M6M

7

IT

VB2

VB3

VIN

CC

mdmo

mdmo

C

L

gg

gg

C

CQ

2mdmo

mdmo

2

LC

βgg

gg

Q

βCC

where

It can be shown that

m5mo gg

m om dm dm oCLC

2

cm 0m dF B

ggβgβgs CCCs

s Cgg(s )A

What pole Q is desired? .707< Q <0.5

(with Miller compensation)

What phase margin is desired?

odoo

momdO

gg

ggA

C

md

C

gGB

T

C

ISR

C

Basic Two-Stage Op Amp

VDD

VSS

M1

M2

M3 M

4M

5

CL

VIN

VOUT

M6M

7

IT

VB2

VB3

VIN

CC

md m0 c

2

C L C mo oo od

g g sCA (s)

s C C sC g g g

Additional Performance Parameters(from earlier analysis)

od1

g gBW oo

mo C

pg C

What is the SR?Voltage at output of first stage changes little compared to VOUT

4

2 0

C

D T

D

COUT T

I IC

I

dVdV ISR

dt dt C

SNATURAL = {W1, L1, W3, L3, W5, L5, W6, L6, W7, L7, IT, ID6, Cc}

Natural Parameter Space for the

Two-Stage Amplifier DesignVDD

VSS

M1 M2

M3 M4 M5

CL

VIN

VOUT

M6M7

IT

VB2VB3

VIN

CC

Assume VSS,VDD,CL fixed

Design Degrees of Freedom

Total independent variables: 13

Degrees of Freedom: 13

If phase margin is considered a constraint

13 independent variables

1 constraint

12 degrees of freedom

Observation: W,L appear as W/L ratio in almost all characterizing equations

Implication: Degrees of Freedom are Reduced

Degrees of freedom: 7

With phase margin constraint,

NATURAL-REDUCED 1 3 5 6 7 D6 T CS = {(W/L) ,(W/L) ,(W/L) ,(W/L) ,(W/L) ,I ,I ,C }

Common Performance Parameters of

Operational Amplifiers (may be more of interest)

Parameter Description

Ao Open-loop DC Gain

GB Gain-Bandwidth Product

Φm(or Q) Phase Margin (or pole Q)

SR Slew Rate

TSETTLE Settling Time

AT Total Area

AA Total Active Area

P Power Dissipation

VOS Standard Deviation of Input Referred Offset Voltage (often termed the input offset voltage)

CMRR Common Mode Rejection Ratio

PSRR Power Supply Rejection Ratio

Vimax Maximum Common Mode Input Voltage

Vimin Minimum Common Mode Output Voltage

Vomax Maximum Output Voltage Swing

Vomin Minimum Output Voltage Swing

Vnoise Input Referred RMS Noise Voltage

Sv Input Referred Noise Spectral Density

Common Performance

Parameters

Total: 17

System is Generally Highly Over Constrained !

Performance parameters: 17

Degrees of freedom: 7

Small signal design parameters:

SSMALL SIGNAL = {goo, god, gmo, gmd, CC, go2, go4, go5, go6}

Small signal model of the two-stage operational amplifier

Typical Parameter Space for a

Two-Stage Amplifier

gmdVd gOd V2gmOV2 gOO

VOUT

CL

CC

Vd

V+

V-

Signal Swing of Two-Stage Op Amp

5EBDDOUT VVV

6EBSSOUT VVV

SSEBEBTic VVVVV 711

331 EBTTDDiC VVVVV

551 EBTTDDiC VVVVV

M6:

M5:

M1:

M2:

M7:

VDD

VSS

M1 M2

M3 M4 M5

CL

VIN

VOUT

M6M7

IT

VB2VB3

VIN

CC

Sswing/Bias Related = { CC, VEB1Q, VEB3Q, VEB5Q, VEB6Q,VEB7Q, IT}


5EBDDOUT VVV

6EBSSOUT VVV

331 EBTTDDiC VVVVV

VDD

VDD

VSS

VSS

VEB6

5EBV

VOUT

Vic

711 EBEBT VVV

SSEBEBTic VVVVV 711

551 EBTTDDiC VVVVV

)}VVV(

),VVVmax{(

TTEB

TTEB

255

133

Graphical Representation


5EBV

711 EBEBT VVV

VDD

VDD

VSS

VSS

VEB6

VOUT

Vic

)}VVV(

),VVVmax{(

TTEB

TTEB

255

133

Augmented set of design parameters:

SAUGMENTED = {goo, god, gmo, gmd, CC, VEB1Q, VEB3Q, VEB5Q,

VEB6Q,VEB7Q, IT, go2, go4, go5, go6}

Typical Parameter Space for a

Two-Stage Amplifier

gmdVd gOd V2gmOV2 gOO

VOUT

CL

CC

Vd

V+

V-

VDD

VSS

M1 M2

M3 M4 M5

CL

VIN

VOUT

M6M7

IT

VB2VB3

VIN

CC

Parameters in this set are highly inter-related

Performance Parameter Summary for 7T

Miller Compensated Op Amp

5EBDDOMAX VVV 6EBSSOMIN VVV

SSEBEBTinMIN VVVVV 711

)}VVV(),VVVmax{(VV TTEBTTEBDDinMAX 255133

odoo

momdO

gg

ggA

C

md

C

gGB

T

C

ISR

C

2mdmo

mdmo

2

LC

βgg

gg

Q

βCC

Constraint:

SAUGMENTED = {goo, god, gmo, gmd, CC, VEB1Q, VEB3Q, VEB5Q,

VEB6Q,VEB7Q, IT, go2, go4, go5, go6}

odoo

momdO

gg

ggA

C

md

C

gGB

T

C

ISR

C

1

1

Wmd OX TL

1g μC I

2

Parameter Inter-dependence

IT affects

A Set of Independent Design

Parameters is NeededConsider the Natural Reduced Parameter Set

odoo

momdO

gg

ggA

,3 5 61 7T

1 3 6 75

W W WW W, , , , ,I θ

L L L LL

2D6Q

Tot

PIθ=

I P

1 5OX n p

1 5O

2 6 7n p T

7 6

W W2 2C μ μ

L LA =

W Lλ +λ I

W L

6Tot T D QI I I

md

C

gGB

C

2

1

1n

765

765p

7651

7651pn

2

LC

L

Wβ

LLL

WWW2

WLLL

LWWW2

Q

βCC

n OX 1T

1

C

μ C WI

LGB

C

2mdmo

mdmo

2

LC

βgg

gg

Q

βCC

Consider the Natural Reduced Parameter Set

,3 5 61 7T

1 3 6 75

W W WW W, , , , ,I θ

L L L LL

Constraint:

T

C

ISR

C

T 1 T 7imin T1 SS

n OX 1 n OX 7

I L 2I LV V V

μ C W μ C W


Expressions for remainder of signal swings are

particularly complicated !

Consider the Natural Reduced Parameter Set

,3 5 61 7T

1 3 6 75

W W WW W, , , , ,I θ

L L L LL

Observation

• Even the most elementary performance parameters

require very complicated expressions when the natural

design parameter space is used

• Strong simultaneous dependence on multiple natural

design parameters

• Interdependence and notational complexity obscures

insight into performance and optimization

SPRACTICAL = {P, θ, VEB1, VEB3, VEB5, VEB6, VEB7}

• P : total power dissipation

• θ = fraction of total power in second stage

• VEBk = excess bias voltage for the kth transistor

• Phase margin constraint assumed (so CC not shown in DoF)

Practical Set of Design

Parameters

7 degrees of freedom!

Basic Two-Stage Op AmpV

DD

VSS

M1

M2

M3 M

4M

5

CL

VIN

VOUT

M6M

7

IT

VB2

VB3

VIN

CC

,3 5 61 7T

1 3 6 75

W W WW W, , , , ,I θ

L L L LL

{P, θ, VEB1, VEB3, VEB5,VEB6, VEB7}

7 Degrees of Freedom

Relationship Between the Practical Parameters

and the Natural Design Parameters

TDQi T

DD

I θPI I , ,

2 V


,3 5 61 7T

1 3 6 75

W W WW W, , , , ,I θ

L L L LL

2IW DQi2

L μ C Vi i EBiOX

T

DD

P 1-θI

V

|V|Vλλ

4A

EB5EB1

2

pn

O


Parameters is Needed

22

EB1 EB5

2DD EB1 C L EB5 DDEB1

PQ 2θV -β 1-θ VP 1 θGB

V V C C β2θV V V

22

EB1 EB5

L EB5 DDEB1

PQ 2θV -β 1-θ VSR

C β2θV V V

V VC 2θ 1-θ β EB1 EB5LC =C 2 2Q V 2θ-β V 1-θEB1 EB5

Constraint:

Consider Practical Parameter Set {P, θ, VEB1, VEB3, VEB5,VEB6, VEB7}

Observation:

22

EB1 EB5



V V C C β2θV V V

22

EB1 EB5

L EB5 DDEB1

PQ 2θV -β 1-θ VSR

C β2θV V V

GB and SR are inter-related for this Op Amp

EB1SR V GB

Could have made this observation in the other parameter domains as well !

5EBDDOMAX VVV

6EBSSOMIN VVV


)}VVV(),VVVmax{(VV TTEBTTEBDDinMAX 255133


Parameters is Needed


Consider Practical Parameter Set

All expressions are quite manageable in the practical

parameter domain except for the GB expression

• Minimum set of independent parameters

• Results in major simplification of the key

performance parameters

• Provides valuable insight which makes performance

optimization more practical

Characteristics of the Practical Design Parameter Space

• Assume the following system parameters:

VDD = 3.3 V

CL = 1 pF

• Typical 0.35um CMOS process

• Simulation corner: typ/55C/3.3V

Design Assumptions

Given specifications:

A0: 66dB

GB: 5MHz

VOMIN=0.25V

VOMAX=3.1V

VINMIN=1.1V

VINMAX=3V

P=0.17mw

=1 with pole Q=.707

Assume: VTN = 0.6, VTP= –0.7, n=0.04, p=0.18

Example for Design Procedure

7 constraints (in addition to φm) and 7 degrees of freedom

1. Choose channel length

2. VEB3, VEB5, VEB6

Vimax=VDD + VEB3 + VT1 + VT3

Vomax=VDD + VEB5

Vomin=VEB6

3. VEB1

4. VEB7

Vimin=VEB1 + VEB7 + VT1

5. Choose P to satisfy power constraint


{P, θ, VEB1, VEB3, VEB5, VEB6, VEB7}



{P, q, VEB1, VEB3, VEB5, VEB6, VEB7}

O 2

n p EB1 EB5

4A =

λ +λ V |V |

(note this step could have occurred earlier since P is one of the design variables)

6. Choose q to meet GB constraint

7. Compensation capacitance CC

8. Calculate all transistor sizes

9. Implement structure, simulate, and make modifications if necessary guided by

where deviations may occur


{P, q, VEB1, VEB3, VEB5, VEB6, VEB7}

P 1-θ

I =T

VDD

2

EBkOXk

Dk

k

k

VCμ

2I

L

W

Note: It may be necessary or preferable to make some constraints an inequality

Note: Specifications may be over-constrained or have no solution

Note: Sequence of steps may change with different requirements for this amplifier

DD EB1 C

P 1 θGB

V V C

1 5LC 22

1 EB5

C βC = 2θ 1-θ

Q 2θ-βV 1-θ

EB EB

EB

V V

V

Pθ

I =5Q

VDD

(the expression for GB really contains only one unknown at this stage, θ, though expression is not explicit since θ also appears in CC)

Must solve nonlinear equation in θ

6. Choose q to meet GB constraint

7. Compensation capacitance CC

8. Calculate all transistor sizes

9. Implement structure, simulate, and make modifications if necessary

guided by where deviations may occur


Note: Though not shown, this design procedure was based upon looking at the set

of equations that must be solved and developing a sequence to solve these

equations. It may not always be the case that equations can be solved

sequentially.

1. Choose channel length

2. Select: VEB3, VEB5, VEB6

3. Select: VEB1

4. Select: VEB7

5. Choose P to satisfy power constraint

Summary of Design Procedure for This Set of Specifications and this Architecture:

Note: Different specification requirements (constraints) will generally require a

different design procedure

Simulation results:


M1,2 W/L M3,4 W/L M5 W/L M6 W/L M7 W/L P θ CC

13/2 24.5/2 54/2 17.4/2 17.4/2 0.17mW .51 3.7pF

A0 GB P Phase

margin

65dB 5.2MHz .17mW 45.4 degrees

Design results (with L=2µm):

Spreadsheet for Design Space Exploration

Settling Characteristics of Two-Stage Operational AmplifierProcess Parameters

0.01Power0.02ln9E-05uCoxn

1E-12CT0.1lp5E-05uCoxp

4Vdd0.768Vtn

0.774Vtp

Device SizingOutput RangeInput RangeAreaPerformance CharacteristicsDesign Parameters

W/L5W/L2W/L1VmaxVminVmaxVminFactorCT/CCCCISS(mA)GBAoVEB7VEB6VEB5 VEB2 VEB1

148.1148.172.53.50.254.271.524E-121.678.3E+0811110.50.250.250.50.50.5

148.1148.118.13.50.254.272.028.9E-131.671.9E+095560.50.250.250.50.51

148.137.04.53.50.253.773.023.3E-131.672.6E+092780.50.250.250.512

148.137.072.53.50.253.771.524E-121.678.3E+0811110.50.250.250.510.5

148.19.318.13.50.252.772.028.9E-131.671.9E+095560.50.250.250.521

148.19.34.53.50.252.773.023.3E-131.672.6E+092780.50.250.250.522

37.0148.172.530.254.271.52ERR1.67ERR5560.50.250.2510.50.5

37.0148.118.130.254.272.024E-121.674.2E+082780.50.250.2510.51

37.037.04.530.253.773.028.9E-131.679.4E+081390.50.250.25112

37.037.072.530.253.771.52ERR1.67ERR5560.50.250.25110.5

37.09.318.130.252.772.024E-121.674.2E+082780.50.250.25121

37.09.34.530.252.773.028.9E-131.679.4E+081390.50.250.25122

9.3148.172.520.254.271.524E-121.678.3E+082780.50.250.2520.50.5

9.3148.118.120.254.272.02ERR1.67ERR1390.50.250.2520.51

W/L7W/L6W/L5

579.7289.9148.1

579.7289.9148.1

579.7289.9148.1

579.7289.9148.1

579.7289.9148.1

579.7289.9148.1

579.7289.937.0

579.7289.937.0

579.7289.937.0

579.7289.937.0

579.7289.937.0

579.7289.937.0

579.7289.99.3

579.7289.99.3

Device Siz ing

W/L7W/L6W/L5W/L2

1. Determination of Design Space and Degrees of Freedom

Often Useful for Understanding the Design Problem

2. Analytical Expressions for Key Performance Parameters

give Considerable Insight Into Design Potential

3. Natural Design Parameters Often Not Most Useful

for Providing Insight or Facilitating Optimization

4. Concepts Readily Extend to other Widely Used Structures

Summary

Power distribution between stages

F1

P1

VIN F2

P2

VOUT

CC CL

VDD

I

θ I(1-θ) I

How should the power be split between the two stages ?

• Would often like to minimize power for a given speed (GB) requirement

• Optimal split may depend upon architecture


F1

P1

VIN F2

P2

VOUT

CC CL

VDD

I

θ I(1-θ) I

How should the power be split between the two stages ?

Consider basic two-stage with first-stage compensation

Assume compensated with p2=3βA0p1

VDD

M1 M2

M3 M4 M5

CL

VIN

VOUT

M6M9

IT

VB2VB3

VIN

CC

I

θ I

110

01 03

520

05 06

01 031

05 062

01 02 1

m

m

C

L

gA

g g

gA

g g

g gp

C

g gp

C

GB A A p

5 01 03 1 51

01 03 05 06 05 06

m m mm

C C

g g g g ggGB

g g g g C g g C

thus


F1

P1

VIN F2

P2

VOUT

CC CL

VDD

I

θ I(1-θ) I

How should the power be split between the two stages to minimize power for given GB ?

p2=3βA0p1

VDD

M1 M2

M3 M4 M5

CL

VIN

VOUT

M6M9

IT

VB2VB3

VIN

CC

I

θ I

110

01 03

520

05 06

01 031

05 062

m

m

C

L

gA

g g

gA

g g

g gp

C

g gp

C

Since

05 06 5 01 031

01 03 05 06

05 06 1 5

05 06

3

3

mm

L C

m m

L C

g g g g gg

C g g g g C

g g g g

C C g g

05 06

3

3

L

p n

L

g gGB

C

IGB

C

q

1 5

05 06

m m

C

g gGB

g g C

Since

3

p n

DD L

PGB

V C

q

Finally

Thus for given GB, for this structure want θ as close to 1 as is practical


Note: Optimum power split for previous example was for dominant pole

compensation in first stage. Results may be different for Miller compensation

or for output compensation

3

p n

DD L

PGB

V C

q

22

EB1 EB5



V V C C β2θV V V

For first-stage compensation capacitor with compensation criteria :

For Miller Compensation with RHP zero and arbitrary Q compensation criteria:

p2=3βA0p1

By taking derivative of GB wrt θ, it can be easily shown that the derivative is

positive in the interval 0<θ≤1 indicating that for a given P, want to make θ close to

1 to maximize GB

Stay Safe and Stay Healthy !

End of Lecture 17

Documents

Lecture 17 Compensation of Feedback Amplifiers Two-Stage