Lecture 12

Review and Sample Exam Questions

Professor Lei HeProfessor Lei He

EE 201A, Spring 2004EE 201A, Spring 2004

http://eda.ee.ucla.eduhttp://eda.ee.ucla.edu

Partitioning and Clustering

Formulations: min-cut, min ratio cut, two-way partition and N-way Formulations: min-cut, min ratio cut, two-way partition and N-way partitioningpartitioning

Kernighan and Lin AlgorithmKernighan and Lin Algorithm

Fiduccia and Mattheyses AlgorithmFiduccia and Mattheyses Algorithm

Simulated annealing algorithmSimulated annealing algorithm

Lawler’s Labeling AlgorithmLawler’s Labeling Algorithm

Overview of multi-level partitioningOverview of multi-level partitioning

Floorplanning

Stockmeyer algorithmStockmeyer algorithm Dynamic programming to decide optimal orientation for slicing Dynamic programming to decide optimal orientation for slicing

floorplanning (i.e., tree for slicing floorplanning is given)floorplanning (i.e., tree for slicing floorplanning is given)

Simulated annealing algorithm to find slicing Simulated annealing algorithm to find slicing floorplanningfloorplanning

Name and explain at least one data structure for non-Name and explain at least one data structure for non-slicing floorplanningslicing floorplanning

Placement

Simulated AnnealingSimulated Annealing Timberwolf package [JSSC-85, DAC-86]Timberwolf package [JSSC-85, DAC-86] Dragon (multi-level placement) [ICCAD-00]Dragon (multi-level placement) [ICCAD-00]

Partitioning-Based PlacementPartitioning-Based Placement Capo [DAC-00]Capo [DAC-00] Fengshui [DAC-2001]Fengshui [DAC-2001]

Analytical PlacementAnalytical Placement Gordian (Multi-level placement) [TCAD-91]Gordian (Multi-level placement) [TCAD-91] FastPlace [ISPD-04] FastPlace [ISPD-04]

Able to outline Pro’s and Con’s of all above algorithms Able to outline Pro’s and Con’s of all above algorithms Able to outline at least two algorithmsAble to outline at least two algorithms

Power and Thermal Modeling

Power ComponentsPower Components Dynamic power (f * s * C * Vdd**2)Dynamic power (f * s * C * Vdd**2)

• f: clock frequencyf: clock frequency• S: switching possibilityS: switching possibility

Short circuit powerShort circuit power Leakage power = subthreshold + gate tunneling Leakage power = subthreshold + gate tunneling

Power trendsPower trends Relative significance between power componentsRelative significance between power components Which one gains importance in scaled technology and future systemWhich one gains importance in scaled technology and future system Design freedoms to reduce each power component with respect to Design freedoms to reduce each power component with respect to

performance constraintsperformance constraints

Power and Thermal Modeling

Duality between electrical and thermalDuality between electrical and thermal Thermal time constant is much biggerThermal time constant is much bigger

Interdependency between leakage and temperatureInterdependency between leakage and temperature

Thermal quantityThermal quantity UnitUnit Electrical quantityElectrical quantity UnitUnit

PP, Heat flow, Heat flow WW II, Current flow, Current flow AA

TT, Temperature, Temperature KK VV, Voltage, Voltage VV

RRthth, Thermal Resistance, Thermal Resistance K/WK/W RR, Electrical resistance, Electrical resistance ΩΩ

CCthth, Thermal capacitance, Thermal capacitance J/KJ/K CC, Electrical capacitance, Electrical capacitance FF

ττ=R=Rthth*C*Cthth, ,

Thermal RC constantThermal RC constant

ss ττ=R*C,=R*C,

Electrical RC constantElectrical RC constant

ss

Interconnect Modeling

Capacitance characteristics and table based capacitance Capacitance characteristics and table based capacitance modelmodel Capacitance is a local effectCapacitance is a local effect

Inductance characteristics and table based inductance Inductance characteristics and table based inductance modelmodel Inductance is a long-range effectInductance is a long-range effect Partial inductance (PEEC) is independent of current return pathPartial inductance (PEEC) is independent of current return path

Full RCLM model and normalized RCLM modelFull RCLM model and normalized RCLM model

Interconnect Delay Model

Elmore delay model and Elmore delay calculation for RC Elmore delay model and Elmore delay calculation for RC treetree

Definition of moments and overview of moment matchingDefinition of moments and overview of moment matching

Ceff modelCeff model

Steps of delay analysis for a stage containing a driver and Steps of delay analysis for a stage containing a driver and interconnect treeinterconnect tree

Circuit Tuning

TILOS algorithmTILOS algorithm1.1. Find critical pathFind critical path

2.2. Calculate sensitivity of each gate/transistor in the pathCalculate sensitivity of each gate/transistor in the path

3.3. Size up the one with largest sensitivitySize up the one with largest sensitivity

4.4. Goto step 1Goto step 1

Explain why TILOS can achieve good solutionsExplain why TILOS can achieve good solutions Use the concept and property of posynomial program, convex programUse the concept and property of posynomial program, convex program

Extend TILOS to consider power minimization via dual-Vdd, dual-Extend TILOS to consider power minimization via dual-Vdd, dual-Vt, dual-toxVt, dual-tox

Buffer and FF Insertion

Analytical solution to buffer insertion for two-pin netAnalytical solution to buffer insertion for two-pin net Extend to find the FF insertion length for two-pin net *Extend to find the FF insertion length for two-pin net *

Van Ginneken dynamic programmingVan Ginneken dynamic programming Extend to consider buffer type, polarity Extend to consider buffer type, polarity Extend to consider FF insertion*Extend to consider FF insertion*

Buffer block planningBuffer block planning Key ideas, pro’s and con’sKey ideas, pro’s and con’s

Noise Aware Routing

Design freedoms to alleviate capacitive and inductive Design freedoms to alleviate capacitive and inductive crosstalkcrosstalk

Figure of merit for crosstalkFigure of merit for crosstalk LSK modelLSK model Shielding lengthShielding length

Multi-level routingMulti-level routing

Emerging Technologies

Structured ASIC and 3D ICStructured ASIC and 3D IC Motivations and advantages Motivations and advantages

CAD implicationsCAD implications

Sample questions:Sample questions: How to expand partition/floorplan/placement/routing for 3DHow to expand partition/floorplan/placement/routing for 3D