inst.eecs.berkeley.edu/~ee241b

Borivoje Nikolić

EE241B : Advanced Digital Circuits

Lecture 11 – Flip-Flops

February 25, 2020, NY Times: Should robots have a face?

As automation comes to retail industries, companies are giving machines more humanlike features in order to make them liked, not feared.

1EECS241B L11 FLIP-FLOPS

Announcements

• Response to project abstracts sent• Please let me know if you didn’t receive it• Team web pages• Be careful not to leak proprietary info (interface tools via Hammer)

• Assignment 2 posted

2EECS241B L11 FLIP-FLOPS

Outline

• Module 3• Design of latches and flip-flops

3EECS241B L11 FLIP-FLOPS

3. Design for Performance

3.D Latch Design

4EECS241B L11 FLIP-FLOPS

MUX

• 2-input MUX

A

Sel

YSelB

Sel

Sel

SelA

Sel

Sel

B

Y

A

B

Sel

1

0

Y

EECS241B L11 FLIP-FLOPS 5

Transmission Gates

EECS241B L11 FLIP-FLOPS 6

S

A

S

Y

Latch vs. Flip-Flop

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 7

Latches

D

Clk

Clk

Q

Clk

D

Clk

Q

Transmission-Gate Latch C2MOS Latch

EECS241B L11 FLIP-FLOPS 8

Usually without contention

Latches

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 9

Clk-Q Delay

TSetup-1

TClk-Q

Time

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1

EECS241B L11 FLIP-FLOPS 10

Clk-Q Delay

TSetup-1

TClk-Q

Time

Timet=0

ClockDataTSetup-1

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

EECS241B L11 FLIP-FLOPS 11

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

EECS241B L11 FLIP-FLOPS 12

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

EECS241B L11 FLIP-FLOPS 13

Timet=0

ClockDataTSetup-1

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

Clk-Q Delay

TSetup-1

TClk-Q

Time

EECS241B L11 FLIP-FLOPS 14

Setup-Hold Time Illustrations

Hold-1 case

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

0

Clk-Q Delay

THold-1

TClk-Q

Time

EECS241B L11 FLIP-FLOPS 15

Clk-Q Delay

THold-1

TClk-Q

Time

Setup-Hold Time Illustrations

Hold-1 case

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

0

EECS241B L11 FLIP-FLOPS 16

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Setup-Hold Time Illustrations

Hold-1 case

0

EECS241B L11 FLIP-FLOPS 17

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Setup-Hold Time Illustrations

Hold-1 case

0

EECS241B L11 FLIP-FLOPS 18

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockTHold-1

Data

Setup-Hold Time Illustrations

Hold-1 case

0

EECS241B L11 FLIP-FLOPS 19

More Precise Setup Time

tD 2 C

t

t

t

tC 2 Q1.05tC 2 Q

tSu

tH

Clk

D

Q

(a)

Td-clk

1.05(tclk-q)

tclk-q

EECS241B L11 FLIP-FLOPS 20

Generating Complementary Clocks

EECS241B L11 FLIP-FLOPS 21

Latch tD-Q and tClk-Q

EECS241B L11 FLIP-FLOPS 22

tsetup

EECS241B L11 FLIP-FLOPS 23

Key Point

• Two ways to design a flip-flop• Latch pair• Pulsed latch

EECS241B L11 FLIP-FLOPS 24

3. Design for Performance

3.E Flip-Flop Design

25EECS241B L11 FLIP-FLOPS

Latch vs. Flip-Flop

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 26

Flip-Flops

• Performance metrics• Delay metrics

• Insertion delay• Inherent race immunity• ‘Softness’ (Clock skew absorption)• Inclusion of logic• Small (+constant) clock load

• Power/Energy Metrics• Power/energy

• Design robustness• Noise immunity

EECS241B L11 FLIP-FLOPS 27

Scan Test

EECS241B L11 FLIP-FLOPS 28

Types of Flip-Flops

Latch Pair

(Master-Slave)

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

EECS241B L11 FLIP-FLOPS 29

Latch Pair as a Flip-Flop

EECS241B L11 FLIP-FLOPS 30

Sources of Noise

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 31

Master-Slave Latch Pairs

• Example: PowerPC 603 (Gerosa, JSSC 12/94)

Vdd Vdd

Clk

QClk Clkb

Clkb

D

EECS241B L11 FLIP-FLOPS 32

Flip-Flop Clk-Q, setup, hold

EECS241B L11 FLIP-FLOPS 33

D

Clk

Clk

Clk

Q

Clk

Clk Clk

ClkCk

Pulse-Triggered Latches

• First stage is a pulse generator• generates a pulse (glitch) on a rising edge of the clock

• Second stage is a latch• captures the pulse generated in the first stage

• Pulse generation results in a negative setup time

• Frequently exhibit a soft edge property

• Note: power is always consumed in the pulse generator• Often shared by a group (register)

EECS241B L11 FLIP-FLOPS 34

Pulsed Latch

Kozu, ISSCC’96

Simple pulsed latch

EECS241B L11 FLIP-FLOPS 35

Intel/HP Itanium 2

Naffziger, ISSCC’02

EECS241B L11 FLIP-FLOPS 36

Pulsed Latches

Hybrid Latch Flip-Flop, AMD K-6Partovi, ISSCC’96

Vdd

D

Clk

Q

Q

EECS241B L11 FLIP-FLOPS 37

HLFF Operation

1-0 and 0-1 transitions at the input with 0ps setup time

EECS241B L11 FLIP-FLOPS 38

Hybrid Latch Flip-Flop

Partovi et al, ISSCC’96

Skew absorption

EECS241B L11 FLIP-FLOPS 39

Pulsed Latches

AMD K-7

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 40

Pulsed Latches

Partovi, VLSI’12

Used in a synthesized flow

EECS241B L11 FLIP-FLOPS 41

Pulsed Latches

7474, from mid-1960’s

Clk

D

Q

Q

S

R

EECS241B L11 FLIP-FLOPS 42

Pulsed Latches

First stage is a sense amplifier, precharged to high, when Clk = 0After rising edge of the clock sense amplifier generates the pulse on S or RThe pulse is captured in S-R latchCross-coupled NAND has different propagation delays of rising and falling edges

Sense-amplifier-based flip-flop, Matsui 1992.DEC Alpha 21264, StrongARM 110

EECS241B L11 FLIP-FLOPS 43

Sense Amplifier-Based Flip-Flop

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 44

Sampling Window Comparison

Naffziger, JSSC 11/02

EECS241B L11 FLIP-FLOPS 45

Next Lecture

• Memory

EECS241B L11 FLIP-FLOPS 46