1

Lecture 10MPC 555 Interrupt

2

Interrupt System Design: Hardware issues Connect interrupt sources to processor core. Determine ISR addresses using exception

vector table. Help software determine interrupt source. Disable/enable interrupts. Mask interrupts.

3

Interrupt System Design: Software IssuesInterrupt setup Set up interrupt level Set up exception vector

table Set up interrupt mask Enable interrupt Device-specific setup

Interrupt Processing Create/destroy stack frame Save/restore machine

states and EPC Mask interrupt (optional) Enable interrupt (optional) Save/restore registers

contents Determine interrupt source Determine ISR address Device-specific processing

4

MPC555 Interrupt Overview

Internal I/O

Processor Core

USIU

External I/O

MPC555 Interrupt Sources:1. External I/O devices2. Internal I/O device3. From USIU inside (Unified

System Interface unit)

USIU includes interrupt controlhandler

memory

2

1

3

5

PowerPC Internal I/O Modules

TPU3: Time Processor Units, 3rd version; versatile functions, e.g. counting pulses

MIOS1: Modular I/O System; QADC64: Queued Analog-to-digital converter TouCAN: Control Area Network, two-wire, up to 1Mbps

and 40m; e.g. network inside vehicle QSMCM: Queued Serial Multi-channel Module IMB3 bus: Inter-Module Bus

TPU3 TPU3 MIOS1 QADC64 QADC64 TouCAN TouCAN QSMCM

IMB3 Bus 1

6

UIPEND

UIMB: U-bus to IMB Interface

• UIMB: U-bus to IMB interface• UIPEND: Interrupt pending reg.• U-bus: Unified bus, connecting multiple internal buses• UMCR[IRQUX]: Enable level 7-31

IMB3 Bus

U-Bus

addr/data

Other busInterruptcontroller

232

8

UMCR[IRQUX]

7

UIMB: U-bus to IMB Interface

The interface converts 32 interrupt levels on IMB3 Bus to 8 interrupt levels on U-Bus Level 0-6 to U-Bus level 0-6 Level 7-31 to U-Bus level 7 Interrupt handler reads full UIPEND through

memory-mapped I/O

8

External Interrupts

Other I/O device: Hard drive, video card, … IRQ[0]: connect to reset

USIU

U-BUS

88

IRQ[0:7]external

IRQ

ResetTimer

1

1

1

3

2

4

9

Unified System Interface UnitThe USIU controls system start-up, system initialization and

operation, system protection, and the external system bus.

MPC555 USIU functions: System configuration and protection Interrupt controller System reset monitoring and generation Clock synthesizer Power management External bus interface (EBI) control Memory controller Debug support

Internal I/O

Processor Core

USIU

10

Interrupt Controller

USIU 4

Timebase

Clock

PIT

PLL

SW watchdog

Decrementer

SIPEND

SIMASK

SIVEC

Internal I/Othrough U-bus External IRQ

NMI controlIREQreset

Decr timer

Note: External IRQ is controlled by SIEL – triggered by falling edge or low level

11

Interrupt ControllerSIPEND[0:31]: Interrupt pending register

Handler accesses SIPEND for source of interrupt Bits 0-15 record interrupt source; 16-31 reserved External IRQ[0:7]: accessing SIPEND is enough Internal IMB3 device: further accessing UIPEND

SIMASK: mask register If SIMASK[i]= 0, then SIPEND[i] is blocked SIMASK[0] = 0 has no effect

SIVEC: interrupt vector register Index to exception vector table Accessed by interrupt service routine (ISR)

NMI control: non-maskable interrupt control External IRQ[0] is non-maskable SW watchdog is non-maskable

12

USIU Internal Interrupt SourcesMPC 555 has a crystal of 4MHz or 20MHz Time base: timer interrupt based on the clock; cannot be reset Real-time clock: timer interrupt based on real-time clock (like a

watch); cannot be reset PIT: Periodic interrupt timer – goes off every n cycles PLL change of lock: Phase lock loop, used to provide higher

clock frequency; generate interrupt in abnormal situation, e.g. lost the lock of the clock

Software watch dog: Used to monitor help avoid software deadlock

Decrementer: Another timer interrupt, but is processed by a special handler (less overhead)

13

Connecting To PowerPC CoreMSR[EE]

Vector table

n+0x100

n+0x500

n+0x900

&

SSR1SSR0

Inst buffer

instaddrto mem

IREQ

NMI

Decrementer

5

1

2

3inst

Three interrupt lines to processor core: IREQ, NMI, and Decrementer MSR[EE]: Enable external interrupt IREQ: External interrupt NMI: Non-maskable interrupt (e.g. reset button is pushed) Decrementer: fast timer interruptOther processor components not shown

Finally!

14

Connecting To PowerPC CoreRefers to three handlers for

1. Maskable Interrupt2. Non-maskable interrupt3. Decrementer (low-overhead timer)

When an interrupt happens, hardware: Waits for current inst to complete Saves MSR[EE] to SSR0, Clears MSR[EE] Saves PC to SSR1 Transfer control to n+0x100, n+0x500, or n+0x900, respectivelyThe rest is left to software handler

All I/O interrupts share the same interrupt handler

15

MPC555 Interrupt All Together

5

1

4

2

3

16

MPC555 Interrupt Summary

L7 for 7-31 UIPENDL0L1L2L3L4L5L6From IMB3 peripherals

I0

External IRQ[0:7]

I1 I2 I3 I4 I5 I6 I7

I0 L0 I1 L1 I2 L2 I3 L3 I4 L4 I5 L5 I6 L6 I7 L7 reserved16 31SIPEND

I0 L0 I1 L1 I2 L2 I3 L3 I4 L4 I5 L5 I6 L6 I7 L7 reserved16 31SIMASK

IRQ Priority arbiter8-bit vector: SIVEC

17

Recall Software IssuesInterrupt setup Set up interrupt level Set up exception vector

table Set up interrupt mask Enable interrupt Device-specific setup

Interrupt Processing Create/destroy stack frame Save/restore machine

states and EPC Mask interrupt (optional) Enable interrupt (optional) Save/restore registers

contents Determine interrupt

source Determine ISR address Device-specific processing

18

Interrupt Priority And Codes

SIVEC contains a 8-bit interrupt code or vector for each source

Priority Int. source Int. Code0 (highest) IRQ[0] 0x01 Level 0 0x42 IRQ[1] 0x83 Level 1 0xC4 IRQ[2] 0x10… … …15 Level 7 0x3c

Help determine interrupt source

19

USIU Internal interrupts

Come from: PIT, Time Base (TB), Real-time Clock (RTC), Phase lock loop change of lock (PLL).

They can be programmed to come at Level 0-7:

Level 0: 1000 0000 : 0x80Level 1: 0100 0000 : 0x40Level 2: 0010 0000 : 0x20Level 3: 0001 0000 : 0x10Level 4: 0000 1000 : 0x08Level 5: 0000 0100 : 0x04Level 6: 0000 0010 : 0x02Level 7: 0000 0001 : 0x01

20

Use SIVEC and IRQ Table

IRQ_Table_Base IRQ0 ISR addr 0x0

Level0 ISR addr 0x4

IRQ1 ISR addr 0x8

Level1 ISR addr 0xc

IRQ2 ISR addr 0x10

Level2 ISR addr 0x14

IRQ7 ISR addr 0x38

Level7 ISR addr 0x3c

IRQ0 ISR addr

ISR-Address =Mem[IRQ_Table_base + Interrupt code] Interrupt code is in register SIVEC, memory mapped to address SIVEC (0x2F C01C)

lis r3, SIVEC@hlbz r3, SIVEC@l(r3)lis r4, IRQ_Table_Base@Hori r4, r4, IRQ_Table@Ladd r4, r3, r4lwz r4, 0(r4)mtlr r4blrl #branch to ISR

Determine ISR address

21

Machine State Register

Machine State Register (MSR)

LE

LE=0Big-endian

RI

RI=1: recoverable

00DRIRIP0

IP=0: exceptionVector tableStarts at 0x000else 0xfff

PREE0PR=0: supervisor =1: user

EE=ext. interrupt enable =0: disable =1:enable

22

PPC Exception Registers

MSR

LE

RI

IP

EE

PR

On an exception:

ILE

000

mtmsr r2: r2 MSRmfmsr r3: MSR r3

mtspr SRR0, r2: r2 SRR0mfspr r3, SRR1: SRR1 r3

Each exception handler must save SRR0, SRR1, and MSR before enabling exceptions (EE=1).

23

PPC Exception Registers

PC saved here

Machine Status Save/Restore Register 0 (SRR0)

Machine Status Save/Restore Register 1 (SRR1)

MSR

Save MSR bitsException specific info

LE

RI

IP

EE

PR

0000

1-4

000000

10-15

24

Enable Interrupt and Save Exception Registers For nested Interrupts:

Enable interrupt – future interrupts can be handled Use special register EIE – virtual reg for setting EE and RI bits

Must save “machine context” SSR0 and SRR1 first, because they are overwritten on next interrupt

; STEP 1: SAVE "MACHINE CONTEXT"stwu sp, -36 (sp) ; Create stack frame and store back

; chainstw r3, 24 (sp) ; Save working registermfsrr0 r3 ; Get SRR0stw r3, 12 (sp) ; and save SRR0mfsrr1 r3 ; Get SRR1stw r3, 16 (sp) ; and save SRR1

;mtspr EIE, r3 ; make EE=1, RI=1

25

MPC555 Interrupt Example:Periodic Interrupt Timer (PIT)

16-bit counter: counts down to 0.On zero, raise an interrupt.

Driven by a clock from an internal oscillator (usually 4MHz) divided by 4 (or at 1 MHz): 1 microsecond counting interval.

Use following registers• PICSR: Periodic Interrupt Control & Select Register• PITC: PIT Counter• PITR: Periodic Interrupt Timer Register

26

PICSR: Periodic Interrupt Control & Select Register

PIT Enable0: enable decrement counter1: disable decrement counter

PInterrupt Enable0: disable interrupt1: enable interrupt

PIT Freeze0: no effect1: disable decrement counter if internal signal FREEZE is asserted

PIT Status0: no PIT int asserted1: PIT int asserted

0x2F C240

PS PIE PITF PTE

0 1 2 3 4 5 6 7

8 9 10 11 12 13 14 15

PIRQ

Interrupt levelfor PIT

27

PITC: PIT Counter

0

PITC

15

PITC: PIT counter

PIT Time-out period = (PITC+1)/(PIT Frequency);assume 1MHZ oscillatorPIT Period = 1/(1MHz) = 1 microsecondPut 33000 in PITC to get 33 milliseconds interrupt period.

0x2F C244

28

PITR: Periodic Interrupt Timer Register

16Reserved

31

PIT: Leftover (current) count in PIT counter

Writes to PITR have no effect: read only.

If you want to read the current PIT count to estimate time to next PIT interrupt?

0x2F C248

PIT150

29

PIT Block Diagram

PTEPISCR[15]

ClockDisable

PITFPISCR[14]

16-bitModulus Counter

PITC

PSPISCR[8]

PIEPISCR[13]

pitrtclkclock

PITinterrupt

30

PIT Initialization.equ USIU_BASE_UPPER 0x2f.equ PICSR_OFFSET 0xc240.equ PITC_OFFSET 0xc244.equ PITR_OFFSET 0xc248

; r4 base address of SIU regslis r4, USIU_BASE_UPPER

; set PISCR bits: PIRQ=08, PS=PS, PIE=1, PITF=0, PTE=1; so flag is cleared, interrupt is enabled, timer is; enabled, and level is assigned

li r0,0x0805 sth r0,PICSR_OFFSET(r4)

;PITC = 33000 = 0x80e8 and store it in PITC li r5, 0x80e8

sth r5, PITC_OFFSET(r4)

;in order to read PITR lhz r6, PITR_OFFSET(r4)

31

PIT Initialization (corrected).equ USIU_BASE_UPPER 0x2f.equ PICSR_OFFSET 0xc240.equ PITC_OFFSET 0xc244.equ PITR_OFFSET 0xc248

; r4 base address of SIU regslis r4, USIU_BASE_UPPER

; set PISCR bits: PIRQ=08, PS=PS, PIE=1, PITF=0, PTE=0; so flag is cleared, interrupt is enabled, timer is; enabled, and level is assigned

li r0,0x0804 sth r0,PICSR_OFFSET(r4)

;PITC = 33000 = 0x80e8 and store it in PITC li r5, 0x80e8

sth r5, PITC_OFFSET(r4)

;now enable PIT: PTE = 1 lhz r0, PICSR_OFFET(r4) ori r0, r0, 0x1 sth r0, PICSR_OFFSET(r4)