W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Unit processes

Thin Film Deposition

Etching

Ion Implantation

Photolithography

Chemical Mechanical Polishing

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

1. Thin Film Deposition

Layer of materials ranging from fractions of nanometer to several micro-meters in thickness

- Types of Thin Film Deposition

• Physical Vapor Deposition (PVD)

- Vaporized materials bombard onto substrate

• Chemical Vapor Deposition (CVD)

- Gaseous materials react on substrate

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

• Evaporation (Thermal, E-beam)

• Sputtering (DC, RF, Ion beam)

• Aluminum, Copper, Titanium,

Tungsten silicide

Physical Vapor Deposition (PVD)

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Chemical Vapor Deposition (CVD)

• Gases react on the substrate

to form the desired thin films

• LPCVD (Low Pressure)

PECVD (Plasma Enhanced)

LACVD (Laser Assisted)

MOCVD (Metal Organic) …

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

- SiO2 etching by HF- Si3N4 etching by H3PO4- Si etching by KOH

-Wet etching avoided if possible: hazard materials, undercut

2. Etching

Wet Etching

Semiconductor

Solution

Film

ProductsReaction

Reactants

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

- Dry etching: chemical reaction with gases to eliminate desired material- RIE (Reactive Ion Etching), ICP (Inductive Coupled Plama) , IBE (Ion Beam Etching)

Typical parallel-plate reactive ion etching system

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2) 7

3. Ion Implantation

Ion implantation for dopoing

Ex) p+, n+, p-well, n-well etc.

Ions are accelerated by potential difference and implanted into the substrate

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

PR coating

Exposure

Developing

Etching

PR strip

Deposition

Produces patterns on substrate by transferring mask patterns onto the substrate.

Basically lithographic printing

<Flow of Photolithography>

4. Photolithography

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

5. Chemical Mechanical Polishing (CMP)

Makes the wafer surface flat for better lithography

• Chemical Mechanical Planarization(CMP) combines chemical action with

mechanical abrasion to achieve selective material removal through polishing

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Metal 1

GateSource Drain

Invertor

CMOS inverer●

Layout●

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

P-substrate

N-well

SiN Spacersilicide

Metal 1

Dielectric

P+ N+STI

Gate Oxide

Polysilicon

CMOS Structure●

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Active region

SiO

Shallow Trench Isolation(STI)

Silicon dioxide

●

P-substrate

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Well Formation●

P-substrate

N-well

Active region

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Gate

Drain &Source

Poly Silicon Thin Gate Oxide

N+P+

P-substrate

N-well

Gate and Source/Drain Formation●

Gate Oxide Formation Photolithography Ion implantation

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

P-substrate

N-well

Metal 1

SiN Spacersilicide

Metal 1

Dielectric

Contacts and Metallization●

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

P-substrate

N-well

SiN Spacersilicide

Metal 1

Dielectric

P+ N+STI

ThinGateOxide

Polysilicon

CMOS Fabrication Result●

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

- CMOS Circuit Design Process

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Design examaple: CMOS inverter●

<Inverter schematic>

● Schematic Simulation(Synopsis HSPICE, Cadence SPECTRE)

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

● Layout(Cadence VIRTUOSO)

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

● Rule Checking (Mentor CALIBRE, Synopsis HERCULES, Cadence ASSURA)

- Design Rule Checking (DRC)

- Layout vs. Schematic (LVS)

Check no design rules for a given process is violated during layout

Make sure layout is identical to schematic

- These rule checking must be satisfied before fabrication can start

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

● Parasitic RC extraction(Synopsis StarRC)

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

● Post Layout Simulation

Pre-simPo-sim

Pre-simPo-sim

- Modify your design if needed

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

- Complicated Digital Circuit Design

- Impossible to do transistor-level simulation- Impossible to layout by hands

Behavior-level design using Hardware Description Language (Mentor ModelSim)

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

- Automatic Gate-level Synthesis (Synopsis Design_Vision)

-Auto Layout(Synopsis Astro)

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

● Example

<Layout>

<Fabricated chip>

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

SOI (Silicon on Insulator): A thin layer of silicon crystal on top of insulator on the top on insulator

< SOI Wafer >

Silicon Substrate

Buried Oxide

Thin Film Silicon Layer

Why SOI wafer?

MOS devices on SOI is more robust again many short channel effects, leading to faster operation with less power consumption

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

< SOI Wafer >

Silicon Substrate

Buried Oxide

Thin Film Silicon Layer

Used by IBM and Freescale for high-performance microprocessors but lost to Intel's bulk Si technology

Widely used in Si Photonics

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

SIMOX (Separation by Implantation of Oxygen)

1. Deep implantation of a high dose oxygen into silicon wafer the synthesis of BOX 0.2-0.4 μm thick underneath a thin silicon film

2. Low and high temperature annealing low temperature: inhomogeneous silicon film high temperature: improving and simplifying the vertical SOI structure

Silicon Substrate

Oxygen ion implantation

Annealing

Silicon Substrate

Buried Oxide

Silicon overlayer

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

BESOI (Bond-and-Etch-back SOI)

1. Bonding of two oxidized silicon wafer2. Polishing/etching back of one of the wafer

Two bulk wafers are required to achieve one SOI wafer

Si-handle wafer

SiO2

Si wafer(future SOI layer)

SiO2

Bonding

Silicon Substrate

Buried Oxide

Etch-back

Polishing/etching

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Combined two technology Smart-Cut process

W.-Y. Choi

Lect. 2: Basics of Si Technology

Si Photonics (15/2)

Smart-Cut Process

Surface Oxidation onto wafer

Implantation of hydrogen into wafer

Deposition of a thick layer or bonding wafer to another wafer

Heat treatment inducing splitting

Polishing and cutting

Wafer

Wafer

Wafer

H implant

Reuse

Reuse

SOI Wafer

Handle Wafer

Handle Wafer

Surface Oxidation

Flip and bond to handle wafer

Break

CMP and cut