Lec8 Test Power

Tamper Resistance Mechanisms for Secure Embedded SystemsTest Power
Outline
Increasing Test Power Concerns
Power-aware ATPG
Copyright Agarwal & Srivaths, 2007
Test Power Problem*
A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function/application.
Power buses are laid out to carry the maximum current necessary for the function.
Heat dissipation of package conforms to the average power consumption during the intended function.
Manufacturing test mode can be/should be viewed
as another mode of operation for the circuit with
respect to power dissipation.
VLSI chip
VLSI chip
Test vectors:
Scan Testing
During response shift-out, next pattern can be
concurrently shifted in.
Testing Differs from Function: Functional Inputs vs. Test Vectors
Functional inputs:
May have been optimized to reduce logic activity and power
Test vectors:
Can be random or pseudorandom
May be optimized to reduce test time; can have high logic activity
May use testability logic for test application
Terminology*
Design-for-test (DFT): Modifications to the circuit for facilitating test. e.g. scan flip-flop insertion
Automatic Test Pattern Generation (ATPG): Process of automatically generating test patterns that can be applied to the chip
Pattern generation happens on the gate-level netlist of the circuit assuming a certain set of eventual defects/faults
Fault Models: Abstraction of potential defects to ease the task of ATPG
E.g., stuck-at faults, transition faults
Compression: Technology for reduced test data volume/test application time. Compressed patterns are stored on the tester, while on-chip de-compression logic ensures that uncompressed patterns can be applied.
* See [Agarwal00] for more information on basics/
advanced concepts in testing
Outline
Power-aware ATPG
Compression and compaction techniques elevate circuit switching
Tests are run at various stress conditions (voltage and temperature)
Redundant switching in circuit logic during scan shift
Test power is several times higher than normal mode power
Conflicting requirements of test time reduction practices
Increasing test concurrency
Normalized
Power
3.5X
4.1X
Peak test power can affect circuit yield
Example: Ti/Siemens 130nm ASIC design with 1M gates + 300kbits SRAM, 150 MHz clock frequency [Saxena-ITC03]
Some transition fault patterns passed only on or near 1.55V
Failure identified to be due to significant IR drop, caused by increased switching in the launch to capture time window.
Example: Power supply voltage drops during scan shift operations [Matsushita-ITC03]
Test power is a determining factor for packaging and power grid design
Power dissipation constraints can also come from a tester standpoint
Power availability during wafer testing smaller [Intel-ITC04]
(source: Intel)
chip
Outline
Power-aware ATPG
Aspects of Test Power
Average vs peak power
Relevant for reliability issues – temperature effects, EM
Peak Power Dissipation
Max power consumed in a cycle, Instantaneous peak power
Tester implications, packaging implications for field test, IR drop issues can have impact on power grid design
Dynamic power vs Static power
Depends on the PTV corner
At burn-in corner, static power can dominate with low frequency circuit operation!
Leakage power implications
An increasingly major component of static power, that is dependent on the state of the circuit
Glitch power neglected
Arise due to non-zero cell and interconnect delays, imbalance in logic paths
As good as your power analysis flow!
Aspects of Test Power
Low Frequency Shifts: Average Shift power may be a concern
High Frequency Shifts: Peak and Average power becomes a concern
Capture power: Fast capture pulses in transition patterns cause Peak power (IR drop) issues
Structural Breakdown: Memories, Scan FF vs Combinational logic
Memory power consumption can be dominant
Must be aware of this while scheduling test of multiple memories
Scan FF vs Combinational logic
78% of the energy dissipated in the combinational logic [Wunderlich99]
29%-53% of power dissipation seen in combinational logic for industrial designs
Power Analysis Times and Logic Simulation Dump Sizes!
Ideally, you need the toggle activity in every test related cycle
Size of VCD dump file (for the TI/Siemens Design) to infer toggle activity in the launch-to-capture time window is 2M !
PERCENTAGE
POWER
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Outline
Power-aware ATPG
DFT for test power reduction (1) –Blocking Circuitry
Basic Concept: Prevent switching in the comb. logic during shift
Use of blocking circuitry (NOR, MUX) at Q outputs connected
to combinational logic
+ Structured Tech
Q
Q
EN
SD
Q
D
EN
SD
Q
D
(a) Simplest Version: GND Gating
(b) GND Gating with Floating output
fixup
DFT for test power reduction (2) – Scan Segmentation
[Whetsel-ITC00]
+ No significant change to ATPG
+ Test application time (TAT) impact negligible
- Scan segment control implementation needed, routing implications
- Delay test considerations (LOC ok)
Basic Concept: Divide a scan chain into multiple segments, and shift them one at at time, while the other segments have their clocks gated.
Clock gating and by pass multiplexors added to provide acccess
SI1
SO1
SI2
SO2
SIn
SOn
Gated_clk1
Gated_clk2
DFT for test power reduction (3) – Scan chain disable [Sankaralingam02]
If a scan chain is disabled,
It is not clocked, scan chain does not shift/capture
Issue: Deciding on the granularity of scan chain disabling
Inter-core (coarse-grained) versus Intra-core (fine-grained)
Basic Concept: Operate one scan chain at a time (differs from scan segmentation (how?)
Example: Scan Chain Disable in CELL processor [IBM-ITC06]
CELL Processor SPE
Each SPE has
24 scan chains in LBIST mode
Thold signal: When active, it will stop the clock to the latch element
Something to think about ….
Can you think of DFT options that can help reduce test power?
What trade-offs will you usually worry about?
Outline
Power-aware ATPG
Low-Power Design and Test, Lecture 8
Power-aware ATPG: Significance of Care Bits
Test patterns consist of care bits and don’t care bits
E.g., a pattern (0XXX1XX) has 5 don’t care bits and 2 care bits
The way the care bits are populated will affect ATPG quality and also have an impact on power
For e. g., Random Fill (randomly filling care bits) may help in fortuitous detection of faults, but at higher power consumption costs.
Fraction of care bits present
Percentage of Patterns
[source: Butler-ITC04]
Power-aware ATPG: Fill Techniques
Random fill: Fill in randomly
Zero fill: Fill in don’t care bits with ‘0’
One fill: Fill in don’t care bits with ‘1’
Adjacent fill: Fill in don’t care bits with the value of the nearest care bit. (Example: 0XXX1XX will be 0000111)
Module D: 600k gates, 8 scan chains, scan chain length 2970
Module M: 600k gates, 8 scan chains, scan chain length 3271
Fill adjacent performs better than other heuristics along various dimensions [Butler-ITC04].
Fraction of cells switching in 3 of the
first 1000 patterns during launch-to-capture cycle
Fraction of cells switching in 11 from
all patterns during launch-to-capture cycle
Power-aware ATPG: Fill Techniques
Increasing No. of
Inadequacy of Existing Low-Power ATPG Techniques [Ravi-ICCAD07]
Ineffectiveness of fill techniques for compressed and compacted patterns
Compaction increases bit utilization in a pattern for testing more faults
Compression reduces control over don’t care bits due to requirement for driving multiple scan chains
Design A
Power (mW)
Design B
Power (mW)
for Two Designs Supporting Compression
Variation of Power with fill techniques for compacted
patterns for an example module from a TI design
Low Power ATPG Using Activity Threshold Controls [Ravi-ICCAD07]
Goals:
To come up with low power ATPG techniques which are better than fill techniques
No modification to ATPG tool should be required
Benefit the generation of low power patterns even in compressed and compacted scenarios
Toggle Distribution using
Fill Techniques for an Example Circuit
Reduced Activity Toggle Distribution for an Example Circuit Using the Proposed Framework
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General Observations
Power constraints are simple mathematical computations. Example: Thresholded transition count for a scan out operation
Power constraints can be encapsulated as a circuit themselves (aka Power Constraint Circuits or PCC)
Force ATPG tool to generate patterns on a circuit that includes target circuit+PCC
SF1
SF2
SF3
SFN
τ
transition
count
POWER CONSTRAINT CIRCUIT
Low Power ATPG Methodology
Exploits the capabilities of the power constraint circuit (PCC) to perform both pattern filtering and pattern generation
Target Circuit
Generate Power Constraint Circuit (PCC) using a partitioned and LUT based architecture
PCC
Test Patterns
Good Patterns
Power-constrained patterns
Outline
Power-aware ATPG
Background: Status of Test Power Analysis Flows
Several power estimation choices available for functional use cases
Gaps in test power analysis flows
RTL option not available yet
Architecture-level test power calculators way off
Current Status:
Architecture
Level
RTL
Gate-Level
Estimation
Time
Accuracy
Gap
Power
Conventional flow adopted to perform gate-level test power estimation is simulation-based
Four main steps as shown in the figure
Step 3 (dump format conversion) is optional
For average test power consumption, shift power due to a scanout operation is calculated
The time interval of interest can be specified as an input in Steps 1/2/3
Estimation is performed at various PVT corners
Challenges for multi-million gate SoCs:
Time-consuming
Test Pattern
Summary
Test power consumption is a very important aspect of chip design cycle
Four facets of test power consumption
Test preparation/planning: Understanding the requirements
Power-aware DFT
Low-Power ATPG
References
[Agarwal00] Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits by Bushnell and Agrawal, Springer, 2000
Survey Papers/Articles
[Ravi-VDAT07] S. Ravi, “Addressing Test Power Issues in Digitial CMOS Design”, to appear in Proc. VLSI Design and Test Symposium (VDAT), 2007.
[Ravi-ITC07] S. Ravi, “Power-aware Testing: Challenges and Solutions”, (invited lecture series), to appear in Proc. International Test Conference (ITC), 2007.
[Jackson-07] T. Jackson, “Design-with-test for low-power devices”, EE Times-Asia, Jan 2007.
[Butler-ITC04] K. M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain, and J. Lewis, “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques”, Proc. International Test Conference, pp. 355-364, 2004.
DFT
[Wunderlich99] S. Gerstendorfer and H. –J Wunderlich, "Minimized power consumption for scan-based BIST," Proc. International Test Conference, pp.77-84, 1999.
[Whetsel-ITC00] L. Whetsel, Adapting scan architectures for low power operation, Proc. International Test Conference, pp. 863-872, 2000.
[IBM-ITC06] C. Zoellin, H. -J Wunderlich, N. Maeding and J. Leenstraa, “BIST Power Reduction Using Scan-Chain Disable in the Cell Processor,” Proc. International Test Conference, 2006.
[Bhunia05] S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, “Low Power Scan Design Using First Level Supply Gating”, IEEE Trans. onVLSI Systems, March 2005.
[Sankaralingam02] R. Sankaralingam and N. Touba, “Reducing Test Power During Test Using Programmable Scan Chain Disable”, Proc. DELTA, pp. 159-166, 2002.
[Yoshida-ITC03]T. Yoshida and M. Watati, "A new approach for low-power scan testing," Proc. International Test Conference, pp. 480- 487, 2003.
References
Low-Power ATPG
[Saxena-ITC03] J. Saxena et al, “A Case Study of IR-Drop in Structured At-Speed Testing”, Proc. International Test Conference, pp. 1098-1104, 2003.
[Ravi-ICCAD07] S. Ravi, V. Devanathan, and R. Parekhji, “Methodology for Low Power Test Pattern Generation Using Activity Threshold Control Logic”, to appear in Proc. International Conference on Computer-Aided Design (ICCAD), 2007.
Misc
[Intel-ITC04] S. Kundu, T. M. Mak, and R. Galivanche, "Trends in manufacturing test methods and their implications," Proc. International Test Conference, pp. 679- 687, Oct. 2004.
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Lec8 Test Power