1 EE7605 Lecture 2.2

EE7605 Signal Integrity in High-Speed Digital Systems

Lecture 2.2: Timing and

Clocking – Examples

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Chip to Chip Timing • Problem

– Some systems have large synchronous clock domains

– 10s - 100s of chips – 103 - 105 clock loads

per chip – Need to distribute the

clock to – within 10% of tck – 200ps for a 500MHz

clock • Solution: two step process

– Get the clock to each chip with low skew

– Distribute the clock on chip with low skew

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Off Chip Solutions

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Spartan-3 FPGA Clock Network

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Spartan-3 FPGA Clock Network

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Timing in ASIC Design Flow – front end

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Timing Constraints

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Model Source Latency

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Pre/Post Layout Clock

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Multiple Clock Domains

Chip A

Chip B

Chip C

Clock domain 1

Clock domain 4

Clock domain 2

Clock domain 3

Clock domain 5

Clock domain 6

Asynch. channel

• Many large ASICs, and systems built with these ASICs, have several synchronous clock domains connected by asynchronous communication

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Multiple Clock Domains

5.5 input delay

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Clock Tree

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Timing Analysis

• Paths

• Start point: – Clk pin of FF – Primary input

• Endpoint – D pin of FF – Primary output

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Timing Analysis

• Cell Delay

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Timing Analysis

• Cell Delay

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Timing Analysis

• Report

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Timing Analysis

• Report

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Timing in ASIC Design Flow – back end (Cadence based)

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Timing in ASIC Design Flow – back end (Cadence based)

• Clock Tree – Heavy clock net

loading – Long clock insertion

delay – Clock skew – Skew across clocks – Clock to signal

coupling effect – Clock is power hungry – Electromigration on

clock net

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Clock Tree