Lec10 Register Transfer Logic

7/29/2019 Lec10 Register Transfer Logic

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James A. Mynderse ME588 Register Transfer Logic 1

COMMUNICATION LOGIC REGISTER TRANSFER LOGIC

Complex logic system design, although well documented, caneasily bog down the process with the increase in the number ofvariables.

Modularization is necessary to keep the design at a manageablesize as well as maintain efficiency in the debugging, testing andvalidating process.

Synchronous design together with register/bus design is a way to

accomplish modularization.Synchronous logic provided the isolation needed for independentdesign of individual modules. As along as the system clock runssufficiently slow, timing errors can be avoided.

DataBu

s

Module

II

Register AModuleI

Register B


REGISTER

Registers are the basis for general processor design.

Registers isolate sections (modules) of the system. They allowchanges to be made at one section without affecting others.

A register can be thought of as a set of D flip-flops:

Three-state outputs

One D flip-flop represents one bit

N-bit register has N data signals and 2 to 3 control signals.

One controls reading

(often denote L for latch or load)

Can be AND with the master

clock to control data input. Second control is the output-enable

(OE) for the three-state output.

Level trigger. Output is connected

when it is TRUE.

Additional control can be added to

clear the register.

D0

D1

D2

Inputs Outputs

Output Enable

Load

Clock


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DATA BUS AND DATA TRANSFER

Registers are interconnected through a bus (a set of wires.)

All the registers are connected to the same set of wires.

At any given time, only one register can have its output enabled.It will dictate the voltages on all the bus wires. Any number ofregisters can read the data on the bus.

3 step data transfer process: (data from register A to B)

1st Clock Tick: Assert output-enable (OE) on A to 1. After a certain

setup time, data is stable (ready) on the bus.

2nd Clock Tick: Assert input-enable/load (L)

on B to 1. Data on the bus is latched by B.

3rd Clock Tick: Set OE of A to 0 and

input-enable (L) of B to 0. Master Clock

OE (reg. A)

LOAD (reg. B)

Data (bus)


DATA TRANSFER

Practical clock rate: 10 300 MHz

Time needed for the 3 step data transfer: 10 300 nsec.

With proper timing of control signal changes vs clock edges, thetransfer can be accomplished in one clock period.

Assert both OE(reg. A) and LOAD(reg. B) at the same time.

Timing must be such that the output (data on the bus) must be

stable before it is latched.

Additional modules (logic units) attached to the bus provide theneeded processing capability.


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PROCESSOR

Processor, in addition to attaching to the main bus, it can also be

directly attached to several registers.

Operates on the output of one or more registers.

Result can be latched to other registers.

Typical processor data transfer structure (clock is implied):

Da

taBus

Output Register Output Enable

Latch Input

Input Register Output Enable

Latch Input

Processor Output Enable

Latch Input

General

RegisterOutput Enable

Latch Input

I/O

RegisterOutput Enable

Latch Input

MemoryOutput Enable

Latch Input


CONTROL SIGNAL AND INSTRUCTIONS

All control signals of each individual modules are connected to acontrol unit.

The control unitgenerates the desired sequence of control signalsto produce the desired actions.

This structure can be generalized to the operation of and datatransfer between:

CPU, Memory, General Register, Instruction (Program) Counter, Memory

Address Register, Instruction Register, Stack Pointer, Arithmetic Unit, and

Input/Output Bus

Control signals are coded by instructions.

Instructions are taken from memory to the instruction register andthen decoded to the proper sequence of control signals.

Each register and processing unit has more than one controlsignals.

Each of these control signals are wired directly and the set of allcontrol signal is called a control word. (Lots of bits!)


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MICROPROGRAM (MICROCODE)

Control unit can be designed as a state machine. Given certain

instruction input a desired control signal sequence in generated.

The instruction set is designed into (hard coded) into the control

unit.

Alternative design is to place the control word sequence in ROMor RAM Microcode(microprogram)

The control unit is still a state machine. However, instead of

generating the control sequence directly, it generate a sequence of

addresses to pick the correct control word from the microcoded

ROM or RAM.

Microcode can be changed to allow for processor customization.

It is difficult to design a microcoded instruction set.

There are few software tools for design and implementation.


INPUT/OUTPUT BUS

The bus, previously discussed, connecting the register/processoris internal to the processor. It contains only data. The controllines and address lines are themselves separate buses.

Input/Output (I/O) bus is for external (outside the processor)connections (or connections to external devices.)

All the information is on the same bus. No separate control andaddress bus.

The I/O bus carries: data, address, and control signals.

Many configurations are available:

Dedicated control bits, address bits and data bits.

Dedicated control bits, shared address/data bits.

Shared control/address/data bits sequential interpretation.

Device can be added or removed easily. Devices (I/O boards) caneven be plugged-in or unplugged while the system is running hot swapping.


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I/O BUS INTERCHANGE

Typical sequence

Put address on bus - alerts target device

Assert control signal indicating intended operation (read/write).

Put data on bus to complete interaction.

Bus protocol can be synchronousor asynchronous:

Synchronous CLOCK will occupy one bit on the bus and all instruction

must be complete within one clock cycle.

Asynchronous No clock, uses handshake signals to indicate when

operations are complete. Handshake slows the interchange but allows

more flexibility.

Bus Mastering

Single-Master Bus One unit is the bus master, other unit can access the

bus only if the master voluntarily steps down, e.g. DMA.

Multi-Master Bus Several devices can arbitrarily access the bus.Additional circuitry needs to be added to adjudicate conflicts. These type

of bus is the basis for multi-processor computers.


I/O BUS INTERCHANGE

I/O Read Cycle I/O Write Cycle

Typical I/O Timing


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INCREASE BANDWIDTH (THROUGHPUT)

Two ways to increase bus performance (data transfer rate):

Increase clock speed (make the flow faster)

Increase number of data bits (make the pipe bigger)

Clock speed increase can be expensive all associatedcomponents must be upgraded to run with faster clock.

It is often useful to move several pieces of data at the same time.

Example: Separate bus for instruction and data or multiple data

buses.

Architectures with several buses can produce substantial fasterperformance with no clock speed increase.

Digital signal processors often use multiple buses.

Multiple buses in DSP are specialized for use in digital filteringoperations.


MICROCOMPUTER BUSES

PC/XT

1.2 Mbyte/sec

8 data bits and 20 address bits

PC/AT (Industrial Standard Architecture, ISA)

5.3 Mbyte/sec

16 data bits and 24 address bits (additional 8 data and 4 address

bits are added with a second connector.)

4.77 MHz bus clock speed.

Limited multiple bus mastering.

Micro Channel (MCA)

Used in IBM PS/2s, first introduced in 1987. 20 Mbyte/sec

32 bit data and address path.

11 shared level interrupts.

No I/O port address, CPU assign I/O address base on information

stored in ROM of I/O device.


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MICROCOMPUTER BUSES

Extended Industry Standard Architecture (EISA)

First introduced in 1988. 33 Mbyte/sec peak transfer rate, 32 bit data and address path.

Multiple bus masters, programmable level or edge triggered interrupt,

automatic board configuration.

Multibus I and II

Original introduced by Intel and used in SUN-1.

Multibus II has 32 bit multiplexed data and address path.

10 MHz synchronous bus clock speed, 40 Mbyte/sec in block transfer

mode to sequential addresses.

Bus mastership interrupt scheme -- request interrupt by sending message

to processor requesting interrupt.

NuBus

Used in Macintosh and Next computers.

40 Mbyte/sec (block transfer)

Multiplexed 32 bit data and address path.

One dedicated interrupt line per slot, first plug-n-play architecture.


MICROCOMPUTER BUSES

VME

Use in Sun 2 and Sun 3 systems.

40 Mbyte/sec transfer rate, 32 bit dedicated data and address path.

Asynchronous protocol, can mix processor of varying speed.

Conventional IRQ interrupt.

Q-Bus and VAXBI

Proprietary buses used in DEC computers.

Q-bus was evolved from DECs PDP-11 Unibus and is used in

LS-11 and MicroVAX computers.

VAXBI is a high performance multiplexed 32 bit data and address

path bus used in the larger VAX 8600-series machines.

Q-bus peaks at 2 Mbyte/sec where VAXBI peaks at 13.3

Mbyte/sec.


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MICROCOMPUTER BUSES

PCI (Peripheral Component Interconnect)

First introduced in 1993 PCI 2.0

Replacing MCA and EISA

33.33 MHz clock with synchronous transfers

peak transfer rate of 133MB/s for 32-bit bus width

32 or 64 bit bus width

32-bit address space (4G bytes)

Extending to 266 MHz (PCI-X 2.0) with 2133 MB/s

Support bus mastering

Variations: Mini-PCI, Cardbus, PC/104-Plus,

PCI-Express (PCI-E or PCIe)

Established by Intel, IBM, HP and Dell in 2004 1-32 bits serial connection with software compatibility to parallel

PCI


MICROCOMPUTER BUSES


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PARALLEL COMMUNICATION

Centronics (LPT printer port)

Developed in the Wang Lab in 1970s (spun off Centronics) as a

byte-wide unidirectional parallel port with handshaking.

Recently has been extended to bi-directional.

Newer IEEE-1284 (1994) standard enables the traditional

Centronics connection to behave almost like a bus, e.g. daisy-

chained parallel printer, scanner, removable drives, etc.



Small Computer System Interface (SCSI)

Started with an 8-bit parallel cable interface with handshake and protocols

for handling multiple hosts and multiple peripherals.

Has both asynchronous and synchronous modes and defined software

protocols.

Original SCSI support data rate of 1.5 Mbyte/sec (asynchronous) or 4

Mbyte/sec (synchronous), with cable length 20 ft (single ended) or 80 ft

(differential).

Recent extension of SCSI, e.g. SCSI/Ultra and SCSI/UltraWide, have

increased the throughput.

IEEE-488 (HPIB or GPIB)

A byte-wide universal instrument interface with data rate of 1 Mbyte/sec. 15 instruments can be linked to a single bus cable for up to 20 m.

Any connected device can be a talker (source of data) and the remaining

device will be the listener (recipient of data). A controller (dictator) tells

everybody what to do.


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ATA (Advanced Technology Attachment)

Design by Western Digital in 1986

Integrated Drive Electronics (IDE) and Enhanced IED (EIDE)

40 and 80 (Ultra DMA/66, UDMA4) pin connector and cables

UDMA4 at 66 MB/s

Originally use 28-bit addressing (137 GB), extended to 48-bit

Less than 450 mm (18 inches) without signal booster

Largely replaced by sATA(serial)

PCMCIA (Personal Computer Memory Card InternationalAssociation)

Created in 1991

Original a 16-bit bus, Cardbus extend it to 32-bit PCI bus at 133 MB/s

Type I supports memory card, such as DRAM or flash memories Type II added support of other I/O devices

Replaced by ExpressCard (serial) in 2003


PERIPHERAL INTERFACING

Generally can be categorized into parallel and serialcommunication:

Serial Standards: RS232, RS422, RS423, RS485, USB, FireWire

Parallel Standards: Centronics, IDE, SCSI, IEEE-488 (HPIB,GPIB)

Serial Communication

Asynchronous bit transmission protocol with fixed bit rate.

A start bit and a stop bit (sometimes two) are attached to the ends

of each 8 bit data (character), forming a 10-bit group. Sender and

receiver use a fixed bit rate.

Start Sto

p

D0

(LSB)

D1 D2 D7orParity

D6

LOGIC ONE

LOGIC ZERO


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SERIAL COMMUNICATION

RS232C/D (1969/1986)

Designed for connecting DTEs (Data Terminal Equipment) to DCEs (Data

Communication Equipment). A terminal always looks like a DTE and a

modem always looks like a DCE. PCs looks like a DTE with male

connectors, although almost all large computers are DCE.

A null modem (a cable that criss-crosses pins 2 and 3) is needed to

connect two similar devices.


Other Serial Standards

Modem (Modulator/Demodulator)

Converts bit-serial digital quantities into analog signals that can be sentover telephone lines or other transmission paths.



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Null Modem Connector (cable)

Connecting two PCs through the serial port requires a null modem

connector or cable.



Serial ATA (sATA)

Created in 2003 to replace ATA or Parallel-ATA

SATA/150 1.5 GHz clock with 150 MB/s (1.2 gbps)

SATA/300 (rev 2) 3 Ghz clock with 300 MB/s (3 gbps)

NVIDIA nForce4 chipset in 2004

Also called Serial-ATA II (SATA II)

SATA/600 (rev 3) 600 MB/s (6 gpbs)

7 pin connection (3 GNDs, 2 pairs of TX/RX)

Separate power connection

eSATA (External SATA)

Standards published in 2004

2 meter cable length


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IEEE 1394 (FIREWIRE)

Fire on wire high performance serial bus 1995

Supports higher (relative to USB) bandwidth digital audio/videodata at a lower cost than typical parallel buses

Current specification:

100 Mbps 4Q 1994 (fast Ethernet is at 100 Mbps)

200 Mbps 4Q 1995

400 Mbps 4Q 1996

3.2 Gbps 1394b (in draft)

Ten 15 fps audio/video channels may be carried by 400 Mbps

Cable distance limited

1394 15 meters

1394b 100 meters


UNIVERSAL SERIAL BUS (USB)

Define an external expansion bus for PCs, which makes addingperipherals to a PC that supports true plug-n-play functionality.

History

1993 Compaq, Intel, Microsoft, NEC/Digital

1994 Core Team: Compaq, Digital, PC Co, Intel, Microsoft, NEC, Nortel

1995 USB 1.0

1998 USB 1.1

2000 USB 2.0 (480 Mbps)

2008 USB 3.0 (4.8 Gbps)

Standard differential serial communication

High speed: 480 Mbps Full speed: 12 Mbps

Slow speed: 1.5 Mbps

Master (PC, Host Controller) Salve (Device) type protocol

Packet based data transfer Token + Data + Handshake packets


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UNIVERSAL SERIAL BUS (USB)

G

W

BR

Outer Shield >65% Interwoven

Tinned Copper Braid

Polyvinyl Chloride (PVC) Jacket

Inner Shield AluminumMetallized Polyester

28 AWG Tinned Copper Drain Wire

Non Twisted Power Pair:

Red: VBUSBlack: GND

Twisted Signal Pair:

White: Data -

Green: Data +


LOCAL AREA NETWORK

Ethernet (IEEE 802.3)

10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps (2008)

Data sent in packets up to 1 Kbyte+, with a preamble and error

checking.

Sending protocol:

Wait until no activity on network.

Begin sending data (message) packet.

While sending, check simultaneously for interference (collision).

As long as all is clear, continue to send packets.

If interference is detected, jam the network intentionally (so that

everybody will detect collision), then wait for a random period, and

try again.


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LOCAL AREA NETWORK

Token-Ring (IEEE 802.5) Networks

4 Mbps and 16 Mbps, 1 Gbps (approved in 2001)

Any device that owns the token is free to send data (messages).

When the owner of the token is finished, the token is passed

around.

LocalTalk (AppleTalk)

The initial default hardware implementation used the Macintosh's

built-in RS-422 ports at 230.4 Kbps

3.6864 MHz clock was chosen (in part) to support the common

asynchronous baud rates up to 38.4 Kbps internal baud-rate

generator


WIRELESS LAN (IEEE 802.11)

Operating frequency

2.4 2.4835 GHz (interfere with 2.4GHz cordless phone)

IEEE 802.11 (1997) 1 and 2 Mbps raw data rate

IEEE 802.11b,e (1999, 2002) 5.5 and 11 Mbps raw data rate (5.9Mbps throughput)

Distance limited ~ 100 ft

IEEE 802.11g (2003) 54 Mbps raw data rate

IEEE 802.11a (1999) 54 Mbps raw data rate (~25 Mbps throughput)

Operating frequency: 5 GHz

IEEE 802.11n (expected by 2006)

40 MHz channels

540 Mbps throughput


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WIRELESS LAN

WiMAX (Worldwide Interoperability for Microwave Access )

IEEE 802.16 (2004), 802.16e (2005)

Point-to-multipoint broadband wireless access

10 66 GHz (802.16a added 2 11 GHz)

50 km (31 miles) of linear service area, 3 to 5 miles (5 to 8

kilometers) of practical distance

Practical maximum data rates between 500 Kbps and 2 Mbps

Implementation in 2005

Los Angeles, New York, Chicago, Boston, Providence (Rhode

Island), San Francisco Towerstream

Seattle Sprint and Speakeasy.net

Dalian and Chengdu (China) are implementing pre-WiMAX


BLUETOOTH

Named after medieval King of Denmark, Harald "Bluetooth"Gormsson

Bluetooth special interest group (SIG)

Proprietary open wireless short distance protocol (using shortlength radio waves), creating personal area networks (PANs)

Originally conceived as a wireless alternative to RS-232

Connect several devices can achieve device synchronization

79 bands of 1 MHz width in the range 2402-2480 MHz

Potential interference with 802.11

1 Mbps (ver 1.2) and 3 Mbps (ver 2.0+EDR)

Range: 1 (class 3) to 100 (class 1) meters

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Lec10 Register Transfer Logic