Introduction
Integrated circuits: many transistors on one chip. – Very
Large Scale Integration (VLSI): very many
Metal Oxide Semiconductor (MOS) transistor –
Fast, cheap, o!"po!er transistors – #ompementary: mi$ture o%
n" and p"type eads to
ess po!er &oday: 'o! to uid your o!n simpe #MOS
chip
Silicon Lattice
&ransistors are uit on a siicon sustrate Siicon is a +roup IV
materia
Forms crysta attice !ith onds to %our neighors
Si SiSi
Si SiSi
Si SiSi
Dopants
Siicon is a semiconductor ure siicon has no %ree carriers and
conducts poory
-dding dopants increases the conductivity
+roup V: e$tra eectron (n"type) +roup III: missing eectron, caed
hoe (p"type)
-s SiSi
Si SiSi
Si SiSi
p-n Junctions
#urrent %o!s ony in one direction
nMOS ransistor
Four terminas: gate, source, drain, ody +ate – o$ide – ody stac0
oo0s i0e a capacitor
– +ate and ody are conductors
– SiO1 (o$ide) is a very good insuator
– #aed meta – o$ide – semiconductor (MOS)
capacitor
– 2ven though gate is
nMOS Operation
ody is commony tied to ground (4 V) 5hen the gate is at a o!
votage:
– "type ody is at o! votage
– Source"ody and drain"ody diodes are OFF
– 6o current %o!s, transistor is OFF
nMOS Operation
– ositive charge on gate o% MOS capacitor
– 6egative charge attracted to ody
– Inverts a channe under gate to n"type
pMOS ransistor
– ody tied to high votage (V33)
– +ate o!: transistor O6
– +ate high: transistor OFF
SiO1
n
!o"er Supply Voltage
– 'igh V33 !oud damage modern tiny transistors
– Lo!er V33 saves po!er
ransistors as S"itc#es
5e can vie! MOS transistors as eectricay controed s!itches
Votage at gate contros path %rom source to drain
g
s
d
CMOS In$erter
CMOS In$erter
CMOS In$erter
CMOS %&%D 'ate
CMOS %&%D 'ate
CMOS %&%D 'ate
CMOS %&%D 'ate
CMOS %&%D 'ate
CMOS %O( 'ate
)-input %&%D 'ate
)-input %&%D 'ate
-
)
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#
CMOS Fabrication
#MOS transistors are %aricated on siicon !a%er Lithography
process simiar to printing press
On each step, di%%erent materias are deposited or etched
*ell and Substrate aps
Sustrate must e tied to +63 and n"!e to V33
Meta to ighty"doped semiconductor %orms poor connection caed
Shott0y 3iode
n p
In$erter Mas+ Set
#ross"section ta0en aong dashed ine
+63 V33
Detailed Mas+ Vie"s
Fabrication Steps
Start !ith an0 !a%er uid inverter %rom the ottom up
First step !i e to %orm the n"!e
– #over !a%er !ith protective ayer o% SiO1 (o$ide)
– *emove ayer !here n"!e shoud e uit
– Impant or di%%use n dopants into e$posed !a%er
– Strip o%% SiO1
Oidation
– 944 – 7144 # !ith '1O or O1 in o$idation %urnace
p su(strate
!#otoresist
– So%tens !here e$posed to ight
p su(strate
Lit#ograp#y
p su(strate
Etc#
– Seeps through s0in and eats oneC nasty stu%%DDD
Ony attac0s o$ide !here resist has een e$posed
p su(strate
Strip !#otoresist
6ecessary so resist doesn;t met in ne$t step
p su(strate
n-"ell
n"!e is %ormed !ith di%%usion or ion impantation 3i%%usion
– ace !a%er in %urnace !ith arsenic gas
– 'eat unti -s atoms di%%use into e$posed Si Ion
Impanatation
– ast !a%er !ith eam o% -s ions
– Ions oc0ed y SiO1, ony enter e$posed Si
Strip Oide
Strip o%% the remaining o$ide using 'F ac0 to are !a%er !ith
n"!e
Suse@uent steps invove simiar series o% steps
p su(strate
!olysilicon
– E 14 (G"H atomic ayers)
#hemica Vapor 3eposition (#V3) o% siicon ayer
– ace !a%er in %urnace !ith Siane gas (Si'I)
– Forms many sma crystas caed poysiicon
– 'eaviy doped to e good conductor
&hin gate o$ide
,oysiicon
!olysilicon !atterning
,oysiicon
Sel-&ligned !rocess
Ase o$ide and mas0ing to e$pose !here n dopants shoud e di%%used or
impanted
6"di%%usion %orms nMOS source, drain, and n"!e contact
p su(strate
%-diusion
attern o$ide and %orm n regions Self-aligned process !here
gate oc0s di%%usion
oysiicon is etter than meta %or se%"aigned gates ecause it doesn;t
met during ater processing
p su(strate
%-diusion
'istoricay dopants !ere di%%used Asuay ion impantation today
ut regions are sti caed di%%usion
%-diusion
!-Diusion
Simiar set o% steps %orm p di%%usion regions %or pMOS source and
drain and sustrate contact
p. 3i%%usion
Contacts
6o! !e need to !ire together the devices #over chip !ith thic0 %ied
o$ide
2tch o$ide !here contact cuts are needed
p su(strate
Metalli.ation
Sputter on auminum over !hoe !a%er attern to remove e$cess
meta, eaving !ires
p su(strate
Layout
#hips are speci%ied !ith set o% mas0s Minimum dimensions o% mas0s
determine transistor
siJe (and hence speed, cost, and po!er) Feature siJe f 8
distance et!een source and drain
– Set y minimum !idth o% poysiicon Feature siJe improves =4K
every = years or so 6ormaiJe %or %eature siJe !hen descriing
design
rues 2$press rues in terms o% λ 8 f B1
– 2.g. λ 8 4.= µm in 4.G µm process
Simpliied Design (ules
In$erter Layout
&ransistor dimensions speci%ied as 5idth B Length
–
Summary
MOS &ransistors are stac0 o% gate, o$ide, siicon #an e vie!ed
as eectricay controed s!itches
uid ogic gates out o% s!itches
3ra! mas0s to speci%y ayout o% transistors
