Lcd+Profilo Telra+PT1000

26”-32” LCD-TV PT1000

Administrador

Sticky Note

Este LCD es el mismo que el TELEFUNKEN 26TLH7000D

Administrador

Sticky Note

NOTAS: Con el modulo 05TA092 (modulo de TDT) no se ve el TDT ni sale su OSD (TDT),pero no afecta al aparato,funciona correctamente sin bloquearse. Si al entrar en modo de servicio,presionamos OK en el modo DEFAULT,el TDT da problemas,o sea,lo primeor que hace es que en OPTIONS se queda como si fuera un lcd profilo-telra y a parte se pone en un display lg de 32" cuando este es de 26".Al cambiarlo a T KEN (Telefunken) y en LG26",no entra en modo DVB-T.Para solucionarlo hay que reprogramar de nuevo la eeprom U302 (24C32) del chasis que la tengo leida.

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CONTENTS 1. Assembling/Disassembling Procedure .................... 04 2. Safety Instructions and Warnings .................... 09 3. Specifications .................... 12 4. Block Diagrams and Connections .................... 17 5. Menu Structure .................... 30 6. Circuit Diagrams and Printed Circuit Board Layouts .................... 34 7. Troubleshooting .................... 52 8. Data Sheets TECH2949PS40A(D) .................... 53 CAT24WC01/02/04/08/16 1K/2K/8K/16K-Bit Serial EEPROM .................... 55 74HC4066; 74HCT4066 Quad bilateral switches .................... 56 CD4069UBC Inverter Circuits .................... 58 EDD1232AAFA (4M wordsx32 bits) 128M bits DDR SDRAM .................... 59 EN29LV040 4 Megabit (512k x 8-bit) Uniform Sector, CMOS 3.0 Volt-only Flash Memory .................... 61 FDC6326L Integrated Load Switch .................... 63 IL1117A-x 1.0A Low Dropout Positive Voltage Regulator ..................... 64 MST6181LDA SXGA/WXGA LCD Multi-Function Monitor Controller with Dual LVDS transmitter Preliminary Data Sheet Version 0.2 ..................... 66 MTV512M 8051 Embedded Monitor Controller with 64K Flash ROM ..................... 76 RC1117 1A Adjustable/Fixed Low Dropout Linear Regulator ..................... 79

26'' - 32 '' LCD-TV PT1000 Service Manual__________________________________________________________________________________________________________________

2

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TPA3004D2 12-W STEREO CLASS-D AUDIO POWER AMPLIFER WITH DC VOLUME CONTROL .................... 81 TPA6110A2 150-m W STEREO AUDIO POWER AMPLIFIER .................... 85 TW9906 3x10-bit Multi-Standard Comb Filter Video decoder with YcbCr Component Input .................... 87 VCT 49xyl, VCT 48xyl .................... 89 WM8725 99dB Stereo DAC ....................101

26'' - 32'' LCD-TV PT1000 Service Manual

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3

1. Assembling/ Disassembling Procedure

Please follow the assembly instructions explained below; NOTE: Make sure that the power cord is disconnected from the outlet. • Pay special attention not to break or damage the parts. • When removing each board, remove the connectors as required. • Taking notes of the connecting points (connector numbers) makes service procedure manageable. • Make sure that there is no bent or stain on the connectors before inserting, and firmly insert the connectors. • Be sure that all cables are free. If necessary fix the cables firmly to avoid any kind of squeezing while placing the boards back. • If possible before starting every each stage of disassembly take a photo. • Keep all screws and other components in safety place. • Do not store components in a moist , dusty and dirty place.

Disassambly ordering:

1-) Remove Back Cover 2-) Remove Stand Group 3-) Remove DVD Holder and DVD (or wireless holder and PCB) 4-) Remove Switch Box 5-) Remove Power Board and Main Board6-) Remove Board Base Metal (or plastic) 7-) Remove Power Cable 8-) Remove LCD Panel keepers (plastics or metals) 9-) Remove LCD panel 10-) Remove all cables and connectors from Side AV. 11-) Remove Side AV holder and PCB 12-) Remove Multibutton holder and PCB from Cabinet 13-) Remove Multibutton PCB and Multibuttons from Multibutton_Holder 14-) Remove Tweeters and Speakers from Cabinet 15-) Remove Standby&Infrared PCB from its holder 16-) Remove Acrylic standby button, and LED holder from Cabinet. 17-) Remove Eject button and PCB

Assembly ordering:

The assembly ordering is exactly reverse of disassembly ordering. In any doubt, look photos, which you have taken before, and check, exploded view.

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8

2. SAFETY INSTRUCTIONS AND PRECAUTIONS

1. Use only the original spare parts with the same specifications for replacement. 2. Only the original fuse value should be used. 3. Safety components should be replaced by components identical to the original

ones.4. Main leads and connecting leads should be checked for external damage before

connection. Insulation must be checked. 5. Parts contributing to the safety of the product must not be damaged or obviously

unsuitable. This is valid especially for insulators and insulating parts. 6. Thermally loaded solder pads are to be sucked off and re-soldered. 7. Ensure that the ventilation slots are not obstructed. 8. Servicing should not be attempted by anyone who is not thoroughly familiar with

precautions necessary when working on high voltage equipment. Perfectly discharge the high potential of the picture tube before handling it. The picture tube is highly evacuated and if broken. Glass fragments will be violently expelled. Always discharge the picture tube anode to the receiver chassis to keep of the shock hazard before removing the anode cap.

9. Keep wire away from the high voltage or high temperature components. 10. When replacing a wattage resistor, keep the resistor 10mm away from the circuit

board.

HANDLING THE MOS CHIP COMPONENTS

MOS circuit requires special attention with regard to static charges. Static charges may occur with any highly insulated plastics and can be transferred to persons wearing clothes and shoes made of synthetic materials. Protective circuits on the inputs and outputs of MOS circuits give protection to a limited extend only due to time of reaction.

Please observe the following instructions to protect the components against ESD.

1. Keep MOS components in conductive package until they are used. Most components must never be stored in styropor materials or plastic magazines.

2. Personnel must not touch the MOS components to avoid electrostatic discharging.

3. Hold the component by the body touching the terminals. 4. Use only grounded instruments for testing and processing purposes. 5. Remove or connect MOS Ics when operating voltage is disconnected. 6. Personnel in charge must make sure that they are connected with the same

potential as the mass of the set by a wristband with resistance.

2.1. Precautions Please pay attention to the followings when you use this TFT LCD module.

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2.1.1. Mounting Precautions (1) You must mount a module using holes arranged in four corners or four sides.(2) You should consider the mounting structure so that uneven force (ex. Twisted

stress) is not applied to the module. And the case on which a module is mounted should have sufficient strength so that external force is not transmitted directly to the module.

(3) Please attach the surface transparent protective plate to the surface in order to protect the polarizer. Transparent protective plate should have sufficient strength in order to the resist external force. (4) You should adopt radiation structure to satisfy the temperature specification.

(5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former generates corrosive gas of attacking the polarizer at high temperature and the latter causes circuit break by electro-chemical reaction.

(6) Do not touch, push or rub the exposed polarizer with glass, tweezers or anything harder than HB pencil lead. And please do not rub with dust clothes with chemical treatment. Do not touch the surface of polarizer for bare hand or greasy cloth. (Some cosmetics are detrimental to the polarizer.)

(7) When the surface becomes dusty, please wipe gently with absorbent cotton or other soft materials like chamois soaks with petroleum benzine. Normal-hexane is recommended for cleaning the adhesives used to attach front / rear polarizers. Do not use acetone, toluene and alcohol because they cause chemical damage to the polarizer.

(8) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer causes deformations and color fading.

(9) Do not open the case because inside circuits do not have sufficient strength.

2.1.2 Operating Precautions (1) The spike noise causes the mis-operation of circuits. It should be lower than following voltage: V=±200mV(Over and under shoot voltage) (2) Response time depends on the temperature. (In lower temperature, it becomes longer.)(3) Brightness depends on the temperature. (In lower temperature, it becomes lower.) And in lower temperature, response time (required time that brightness is stable after turned on) becomes longer.(4) Be careful for condensation at sudden temperature change. Condensation makes damage to polarizer or electrical contacted parts. And after fading condensation, smear or spot will occur. (5) When fixed patterns are displayed for a long time, remnant image is likely to occur.(6) Module has high frequency circuits. Sufficient suppression to the electromagnetic interference shall be done by system manufacturers. Grounding and shielding methods may be important to minimize the interference.(7) Please do not give any mechanical and/or acoustical impact to LCM. Otherwise, LCM can’t be operated its full characteristics perfectly.(8)A screw, which is fastened up the steels, should be a machine screw. (if not, it

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10

causes metallic foreign material and deal LCM a fatal blow) (9) Please do not set LCD on its edge.

2.1.3. Electrostatic Discharge Control Since a module is composed of electronic circuits, it is not strong to electrostatic discharge. Make certain that treatment persons are connected to ground through wrist band etc. And don’t touch interface pin directly.

2.1.4. Precautions for Strong Light Exposure Strong light exposure causes degradation of polarizer and color filter.

2.1.5. Storage When storing modules as spares for a long time, the following precautions are necessary.(1) Store them in a dark place. Do not expose the module to sunlight or fluorescent

light. Keep the temperature between 5°C and 35°C at normal humidity.(2) The polarizer surface should not come in contact with any other object. It is

recommended that they be stored in the container in which they were shipped.

2.1.6. Handling Precautions for Protection Film (1) The protection film is attached to the bezel with a small masking tape. When the

protection film is peeled off, static electricity is generated between the film and polarizer. This should be peeled off slowly and carefully by people who are electrically grounded and with well ion-blown equipment or in such a condition, etc.

(2) When the module with protection film attached is stored for a long time, sometimes there remains a very small amount of glue still on the bezel after the protection film is peeled off.

(3) You can remove the glue easily. When the glue remains on the bezel surface or its vestige is recognized, please wipe them off with absorbent cotton waste or other soft material like chamois soaked with normal-hexane.

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11

3.Specifications3.1 Technical Specifications

Panel 26" 32"Aspect Ratio 16:9 16:9Resolution (*) 1366 x 768 1366x768Active Area(mm) (*) 284.16 x 213.12Brightness (typ) (*) 500 cd/m2 500 / 550 cd/m2Contrast Ratio (typ) (*) 600:1 / 800:1 800:1 / 1000:1 /1200:1Viewing Angle (H/V degree) (typ) (*) H/V: 140/115Response Time (typ) (*) 8ms(GtG) 8ms(GtG)

PictureFull HD(1080p) supportINVATEK Engine3D DNR (Digital Noise Reduction)3D MADI (Motion Adaptive De-Interlacer)Digital Comb FilterDLTI/DCTIDLC (Dynamic Luminance Control)3/2 - 2/2 motion pull downSTC (Skin Tone Control)BWS (Black & White Stretch)PMR(Picture Mode Recognition)FreezeColor Temperature SelectionPre-set Picture ModesPicture Formats

TuningTuner

TV-Standards PAL BG / DK / I ; SECAM BG/ DK / LL'NTSC 4.43MHz / 3.58MHz PlaybackAuto ProgrammingATS Euro Plus Tuning SystemFine-tuningProgram storage capacityVHF / UHF

Ch. coverage CATV / Hyperband (S1-S41)Teletext

Flof teletextTeletext capability in OSD LanguagesT.Text Page Memory

General FeaturesHD ReadyBitmap GUI (Graphic OSD)OSD Menu in multi languagesOn/Off TimerAuto shut-offProgram LockProgram naming

PIP via PC/Component/HDMI(or DVI)PIP via AVPIP double tunerPAP available w/ PIP double tunerPIP(Analog/ Digital) optional for IDTVPIP size/Position Adjustment

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PIP Optionsavailable with PIP double tuneravailable with PIP double tuner

250 pages

99

PLL

Cool1/2, Warm1/2, NormalStandart-Dynamic-Soft-User16:9, 14:9, Cinema, 4:3, Auto

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SoundA2 + Nicam stereoAuto Volume LevelSound Effect(Spatial Effect)Pre-set sound modesBalanceTrebleBassAudio output power (rms)

ConnectionsSide ConnectionsVideo CVBS In, Audio L/R InHeadphone OutputRear ConnectionsAntenna input ( 75 ohm IEC )1st Scart (RGB, CVBS In/Out, Audio L/R)2nd Scart (CVBS In/Out, , Audio L/R)Video CVBS Out, Audio L/R Out (AV-OUT)YPbPr Video In, Audio L/R In

480i : 59.94/60Hz, 480P : 59.94/60Hz 576i : 50Hz, 576P : 50Hz 720P : 59.94/60Hz, 1080i : 50/59.94/60Hz

S-Video In, Audio L/R In(Cinch)VGA Analog PC Input (D-Sub 15P )HDMI(w/ HDCP)2nd HDMI(w/ HDCP) w/ full hd chassisHDMI / PC Audio InCI Slot (available w/ IDTV)

AccessoriesRemote Control Unit

: standard : optional* These specifications are dependent on the panel brand/ver. & panel manufacturer's changes.Specifications are subject to change without notice.

flat, speech, music, movie, user

2 x 8W (<10%THD)

COMPONENT (YPbPr) Modes

TM3602 / TM64 DVD-TV / TM4901IDTV

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13

3.2Electrical Specifications

Electrical Specifications

No. Item Description Remarks

Min Typ Max

For Audio 11.4 12.0 12.6 V

For Stand-by

4.8 5.0 5.2 V

For Logic 4.8 5.0 5.2 V

Power Supply

For Tuner 32.5 33.0 33.5 V

Power Consumption normal operation

1

Stand-by Power Consumption

DPMS Sync (V/H) VIDEO Power (V/A) LED Stand By, Sleep & Suspend

ModeOff/On & On/Off Off 3W DARK RED 2

POWER OFF - - 3W RED

Typical 10Wrms + 10Wrms ( ± 10%) Volume: Adjust Power

Max 12Wrms + 12Wrms Volume: Max

Response Frequency 100Hz ~ 10KHz

T.H.D 10%

Input 0.700Vrms

3 AudioAMP

S/N 40dB

Type External 4 Speaker

Impedance 8

System PAL/SECAM

Tuning Frequency Synthesizer System

5 TV

System

Channel1) VHF LOW: 46.25~127.25MHz HIGH: 133.25~361.25 2) UHF 367.25~863.75MHz

Video Level 0.7±0.15 V p-p 75Termination

Sync Level 0.286±0.075 V p-p 75Termination

Color Burst 0.214±0.072 V p-p 75Termination

0.7±0.1 V rms PC Input

0.5±0.05 V rms NTSC Audio Level

0.4±0.05 V rms PAL

6 AV

Video Cross-Talk 43 dB

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14

3.3 Supported Resolutions PC Mode

M Item Pol CLOCK [MHz]

Frequency[kHz]/[Hz]

H-Total(E)

Display(A)

FrontPorch(B)

Sync.(D)

Back Porch(F) Res.

1 H(Pixels) + 31.469 800 640 16 96 48

V(Lines) - 25.175 70.8 449 350 37 2 60 640x350

2 H(Pixels) - 31.468 900 720 18 108 54 V(Lines) + 28.321 70.8 449 400 12 2 35

720X400

3 H(Pixels) - 31.469 800 640 16 96 48 V(Lines) - 25.175 59.94 525 480 10 2 33

640x480

4 H(Pixels) - 37.5 840 640 16 64 120 V(Lines) - 31.5 75 500 480 1 3 16

640x480

5 H(Pixels) - 43.269 832 640 56 56 80 V(Lines) - 36.0 85.0 509 480 1 3 25

640x480

6 H(Pixels) + 37.879 1056 800 40 128 88

V(Lines) + 40.0 60.317 628 600 1 4 23 800x600

7 H(Pixels) + 49.5 46.875 1056 800 16 80 160

V(Lines) + 75.0 625 600 1 3 21 800x600

8 H(Pixels) + 53.674 1048 800 32 64 152 V(Lines) + 56.25 85.061 631 600 1 3 27

800x600

9H(Pixels)

+/-49.725 1152 832 32 64 224

V(Lines) +/-

57.28374.55 667 624 1 3 39

832x624

10 H(Pixels) - 48.363 1344 1024 24 136 160 V(Lines) - 65.0 60.0 806 768 3 6 29

1024x768

11 H(Pixels) - 60.123 1312 1024 16 96 176 V(Lines) - 78.75 75.029 800 768 1 3 28

1024x768

12 H(Pixels) + 68.68 1376 1024 48 96 208

V(Lines) + 94.5 85.00 808 768 1 3 36 1024x768

13 H(Pixels) + 44.772 1664 1280 64 128 192

V(Lines) + 74.5 59.855 748 720 3 5 20 1280x720

14 H(Pixels) + 47.72 1776 1360 72 136 208 V(Lines) + 84.75 59.799 798 768 3 5 22

1360x768

15 H(Pixels) + 63.981 1688 1280 48 112 248 V(Lines) + 108.0 60.02 1066 1024 1 3 38

1280x1024

H(Pixels) + 79.98 1688 1280 16 144 248 16 V(Lines) + 135.00 75.02 1066 1024 1 3 38

1280x1024

DTV Mode (Component Video Input: Y/Pb/Pr)- 50Hz: 576i, 576p, 720p, 1080i - 60Hz: 480i, 480p, 720p, 1080i

__________________________________________________________________________


15

__________________________________________________________________________


16

AM00

05 B

LOCK

DIA

GRA

MM

ULT

IBU

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N

LED

/IN

FRA

MAI

N T

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NER

IF1

PIP

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SCAR

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SCAR

T AU

DIO

IN

PUT

SCAR

T RG

B/FB

S-VI

DEO

AU

DIO

S-VI

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AU

DIO

IN

LCD

S-VI

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S-VI

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Y/C

IN

AV O

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PC I

NPU

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PC/D

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HD

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ngle

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VCTi

. MIC

OM

. V

IDEO

DEC

OD

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. AU

DIO

DEC

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. TXT

DEC

OD

ER

. IF

DEM

TW99

06

.VID

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ECO

DER

74H

C405

2

AUD

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/W

PIP

CVBS

PC A

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NPU

T

WM

8725

AUD

IOD

ECO

DER

TPA6

110

HP

AMP

HD

Mi A

UD

IO I

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T

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PR A

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PUT

TPA3

004

AUD

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P

MST

6***

S

CALE

R

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D

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ACE.

PI

P

MTV

512

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MIC

OM

IP P

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12K)

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M)

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AU

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EAV

AUD

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PUT

SID

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CVB

S IN

PUT

MAI

N S

PEAK

ER L

/R

ITU

656

ITU

656

DD

R R

AM

__________________________________________________________________________


17

+5V

S

+5V

_OFF

+12V

AC I

NPU

T POW

ER B

OAR

D

RC1

117_

3.+3

.3V_

SCAL

ER

+5V

_OFF

+3.3

V_VI

D

RC1

117_

2.+2

.5V_

SCAL

ER

+5V

_OFF

+2.5

V_VI

D

RC1

117_

1.+1

.8V_

SCAL

ER

+5V

_OFF

+1.8

V_VC

Ti

7808

+12V

+8

V

7805

+12V

+5

V_TU

NER

RC1

117_

3.+5

VS

+3

.3V_

MIC

OM

4069

+33V

+8

V

TUN

ER

+5V

+33V

DD

C IC

24LC

02

+5VS

EEPR

OM

24LC

32

+3.3

V_VI

D

EE

PRO

M

24LC

32

+3.3

V_VI

D

SWIT

CH

4066

+5VS

DRAM

K6R40

08V1

+3.3

V_VI

D

FLAS

H

EN29

LV04

0

+3.3

V_VI

D

VID

EO/A

UD

IO/M

AIN

MIC

OM

/TXT

PRO

CESS

OR

VCTi

+3.3

V_VI

D

+1.8

V_VC

Ti

+5V_

TUN

ER

+8V

SWIT

CH

4052

+8V

AUD

IO A

MP

TPA3

004

+12V

H.P

AMP

TPA6

11

0A2

+5V_

OFF

SCAL

ER

MST

6181

LDA

+2.5

V_SC

ALER

+1.8

V_SC

ALER

+3

.3V_

SCAL

ER

I2S

AUD

IO

WM

872

5

+5V_

TUN

ER

DD

R R

AM

+2.5

V_SC

ALER

SUB

MCU

MTV

512

+5VS

PIP

VID

EO D

ECO

DER

TW99

06

+2.5

V_VI

D

+3.3

V_VI

D

PO

WER

BLO

CK

DIA

GR

AM

__________________________________________________________________________


18

I2C BLOCK DIAGRAM

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19

1) J916: For IR, LED - Wafer

Pin No. Symbol Description I/O Remarks

1 LED-WARNING

2 LED-RED LED drive for RED Color O

3 GND Ground

4 IR-RCVR IR Receive Signal I

5 5V 5V Power for IR Receiver O

2) J917: For Local Key - Wafer


1 KEY-AD1 Local Key Value Detection I

2 GND Ground

3) J909: For Debugging - Wafer


1 VCT_RXD Receiver Line O

2 VCT_TXD Transmitter Line I

3 GND Ground

4 3.3V_VID 3.3V Power for Debugging Tool O

4) J912: For Debugging - Wafer


1 VCT_SDA Data Line B DPMS AMBER

2 VCT_SCL Clock Line B

3 GND Ground

5) J915: For HDCP Writing - Wafer


1 GND Ground

2 EEPROM_SCL Clock Line B

3 EEPROM_SDA Data Line B DPMS AMBER

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20

6) J924: For DVD interface, Wafer


1 DVD_AR Right Sound Signal of DVD/DVB I

2 GND Ground

3 DVD_AL Left Sound signal of DVD/DVB I

4,5 NC No Connection

6 GND Ground

7 NC No Connection

8 GND Ground

9 DVD_Y Luma signal of DVD/DVB I

10 GND Ground

11 DVD_C Chroma signal of DVD/DVB I

12 GND Ground

7) J925: For DVD/DVB Power Supply, Wafer


1 5V-DVD 5V Power for DVD/DVB

2,3 GND Ground

4 12V-DVD 12V Power for DVD

8) J926: For DVB Upgrade Interface, Wafer


1 GND Ground

2 TXD_DVB Transmitter Line I

3 RXD_DVB Receiver Line O

4 GND Ground

9) J927: For IR, Interface (DVB), Wafer


TV_MENU TV OSD MENU Detect Signal O

DVB_MENU DVB OSD MENU Detect Signal I

GPIO No Connection

DVB_ON DVB PWR ON Status I

GND Ground

IR_RCVR IR Receive Signal I

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21

10) J919: For Headphone Drive, Wafer


1 HP-R Right Sound signal for Headphone O

2 GND Ground

3 HP-L Left Sound signal for Headphone O

4 HP-SENSE

11) J920: For LCD Speaker Output, Wafer


1 LOUT+ Speaker Left Positive Class-D Output Signal O

2 LOUT- Speaker Left Negative Class-D Output Signal O

3 ROUT- Speaker Right Negative Class-D Output Signal O

4 ROUT+ Speaker Right Positive Class-D Output Signal O

12) J922: For PDP Speaker Output, Wafer


1 LOUT+ Speaker Left Positive Class-D Output Signal O

2 LOUT- Speaker Left Negative Class-D Output Signal O

3 GND Ground

4 ROUT- Speaker Right Negative Class-D Output Signal O

5 ROUT+ Speaker Right Positive Class-D Output Signal O

13) J502: For LCD Side AV, Wafer


VCR_ARIN_R Side Right Sound Signal I

GND Ground

VCR_ALIN_L Side Left Sound signal I

GND Ground

VCR_IN Side CVBS Signal Input I

HP-R Right Sound signal for Headphone O

GND Ground

HP-L Left Sound signal for Headphone O

__________________________________________________________________________


22

14) J923: For PDP Side AV, Wafer


1 NC No Connection

2 GND Ground

3 VCR_ALIN_L Side Left Sound signal I

4 GND Ground

5 VCR_ARIN_R Side Right Sound Signal I

6 GND Ground

7 NC No Connection

8 GND Ground

9 VCR_IN Side CVBS Signal Input I

10 GND Ground

15) J701: For Logic Power Supply – LCD, Wafer


1 P_CTRL1 SMPS Power On Control Signal O 3.3V(High) :On

2,3 GND Ground

4 5V_OFF_CD 5V Logic Power Supply I

5 5V_DVD_CD 5V DVD Power Supply I

6 5VS 5V Standby Power Supply I

7,8 GND Ground

9 12V_CD 12V Power Supply I Max 3.0A

10 12V_DVD_CD 12V DVD Power Supply I Max 1.0A

11 INV_DIM Inverter Dimming Control Signal O Max 1.0A

12 INV_CTRL Inverter ON/OFF Control Signal O

16) J702: For Logic Power Supply – SDI PDP, Wafer


1,3,4 GND Ground

2 NC No Connection

5 12V_DVD_SS 12V DVD Power Supply I Max 1.0A

6 12V_AMP_SS 12V Audio Amp. Power Supply I

7 GND Ground

8 12V_SS 12V Power Supply I Max 3.0A

9 GND Ground

10 5V_DVD_SS 5V DVD Power Supply I

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23

17) J921: For Logic Power Supply – SDI PDP, Wafer


1 THD_SS VS On Control Signal

2 5VS 5V Standby Power Supply I

3 GND Ground

4 P_CRTL_SS SMPS Power On Control Signal O 3.3V(High) :On

5 NC No Connection

6,7 GND Ground

8,9 3.3V_OFF_SS 3.3V Logic Power Supply I

10 GND Ground

11 5V_OFF_SS 5V Logic Power Supply I

18) J704: For Logic Power Supply – LG PDP, Wafer


1,2 NC No Connection

3,4 GND Ground

5 12V_LG 12V Power Supply I

6 12V_DVD_LG 12V DVD Power Supply I

7,8,9 GND Ground

10,11 5V_OFF_LG 5V Logic Power Supply I

12 5V_DVD_LG 5V DVD Power Supply I



1,2 GND Ground

3,4 24V_LG 24V Power Supply I



NC No Connection

5V_D 5V Detection I

SW_PANEL_P VS On Control Signal O

GND Ground

5VS 5V Standby Power Supply I

P_CRTL SMPS Power On Control Signal O 3.3V(High) :On

ACD AC Detection I

__________________________________________________________________________


24

21) J913: For LCD VDD Selection – LCD, Wafer


1 12V_CD 12V Power Supply I

2 LCD_VDD Selected LCD_VDD Power Supply O

3 5V_OFF 5V Power Supply I

22) J102: LVDS Interface for LCD - PDP - DLP, Wafer

Pin No Symbol Function Remark

1 PDP_DLP_SCL PDP_DLP Clock Line

2 RA- LVDS A Channel Negative Signal 350mVpp±5%

3 GND Ground

4 RA+ LVDS A Channel Positive Signal 350mVpp±5%

5,6 GND Ground

7 PDP_DLP_SDA PDP_DLP Data Line


8 RB- LVDS B Channel Negative Signal 350mVpp±5%

9 GND Ground

10 RB+ LVDS B Channel Positive Signal 350mVpp±5%

11 LVDS_OPTION LVDS Option selection

12,13 GND Ground

14 RC- LVDS C Channel Negative Signal 350mVpp±5%

15 GND Ground

16 RC+ LVDS C Channel Positive Signal 350mVpp±5%

17,18,19 GND Ground

20 RCLK- LVDS Clock Channel Negative Signal 350mVpp±5%

21 LVDS_MAP_SEL LVDS Map Selection

22 RCLK+ LVDS Clock Channel Positive Signal 350mVpp±5%

23 LCD_VDD LCD Power or Ground

24 GND Ground


26 RD- LVDS D Channel Negative Signal 350mVpp±5%


28 RD+ LVDS D Channel Positive Signal 350mVpp±5%


30 GND Ground

__________________________________________________________________________


25

23) J21: LVDS Interface for LCD-PDP-DLP, Wafer

Pin No Symbol Function Remark

1,2 GND Ground


4 PDP_DLP_SDA PDP_DLP Data Line

5 GND Ground

6 RD+ LVDS D Channel Positive Signal 350mVpp±5%

7 RD- LVDS D Channel Negative Signal 350mVpp±5%

8 GND Ground

9 RCLK+ LVDS Clock Channel Positive Signal 350mVpp±5%

10 RCLK- LVDS Clock Channel Negative Signal 350mVpp±5%

11 GND Ground

12 RC+ LVDS C Channel Positive Signal 350mVpp±5%

13 RC- LVDS C Channel Negative Signal 350mVpp±5%

14 GND Ground

15 RB+ LVDS B Channel Positive Signal 350mVpp±5%

16 RB- LVDS B Channel Negative Signal 350mVpp±5%

17 GND Ground

18 RA+ LVDS A Channel Positive Signal 350mVpp±5%

19 RA- LVDS A Channel Negative Signal 350mVpp±5%

20 GND Ground

21 INV_CTRL Inverter Brightness Control

22 LVDS_MAP_SEL LVDS Map Selection

23, 24 25, 26 GND Ground

27,2829, 30 VDD LCD Power

__________________________________________________________________________


26

24) J905: Full SCART


1 SCART_ROUT SCART Audio Right Output O

2 SCART_ARIN_R1 SCART Audio Right Signal Input I

3 SCART_LOUT SCART Audio Left Output O

4,5 GND Ground

6 SCART_ALIN_L1 SCART Audio Left Signal Input I

7 SCART_VBIN1 SCART Blue Video Signal Input I

8 SCART_AVSW1 ID detection Signal

9 GND Ground

10 NC No Connection

11 SCART_VGIN1 SCART Green Video Signal Input I

12 NC No Connection

13 GND Ground

14 NC No Connection

15 SCART_VRIN1 SCART Red Video Signal Input I

16 SCART_FBLNK1 SCART R/G/B Video FB Signal Input I

17,18 GND Ground

19 SCART_VOUT1 TV Video Signal Output O

20 SCART_VIN1 SCART CVBS Signal Input I

__________________________________________________________________________


27

25) J907: Half SCART


1SCART_ROUT2 Selected Audio Right Output O

2SCART_ARIN_R2 SCART Audio Right Signal Input I

3SCART_LOUT2 Selected Audio Left Output O

4,5GND Ground

6SCART_ALIN_L2 SCART Audio Left Signal Input I

7NC No Connection

8SCART2_AVSW2 ID detection Signal

9GND Ground

10TXD_DVB DVB Upgrade Line

11NC No Connection

12RXD_DVB DVB Upgrade Line

13, 14 GND Ground

15SCART_CIN2 SCART Chroma Signal Input I

16NC No Connection

17,18GND Ground

19SCART_VOUT2 Selected Video Signal Output O

20SCART_VIN2 SCART CVBS or Luma Signal Input I

__________________________________________________________________________


28

Rear Connection

Side AV Connection

Audio / Video In - Video CVBS (1 Vpp / 75 )- Audio L - Audio R - Headphone 3.5 mm

__________________________________________________________________________


29

5. MENU STRUCTURE MAIN Menu PICTURE

SOUNDPIP/PAPFEATURES INSTALLATION

PICTURE Menu COLOR TEMP NORMAL, COOL, WARM PICTURE PRESET DYNAMIC, STANDARD, SOFT, USER Brightness 100 Steps

Contrast 100Steps Colour 100Steps

Sharpness 100Steps TINT -50, +50

SOUND Menu Volume 100 Steps SOUND PRESET FLAT, MUSIC, MOVIE, SPEECH, USER

SURROUND ON / OFF AVL ON / OFF

BALANCE L50,R50 BASS 100Steps TREBLE 100Steps

PIP/PAP Menu ON/OFF OFF/PIP/PAP1/PAP2 SOURCE ALL SOURCE PIP SIZE SMALL/LARGE PIP POSITION

FEATURES Menu Language (English /GERMAN /FRENCH/ITALIAN/ SPANISH/DUTCH/GREEK/DANISH/ SWEDISH/FINNISH/TURKISH/RUSSIAN CZECH/HUNGARIAN/PORTUGISH/ NORWEGIAN/HIRVATSKI/SLOVENCE/ BULGARSKI/ARNAVUT/SLOVAKCA/ POLSKI/SIRPSKI/MAKEDONSKI/ARABIC)

TRANSPARENCY 100 Steps RESET TIMER

CLOCK HH:MM OFF TIME HH:MM ON/OFF ON TIME HH:MM ON/OFF PR NUMBER VOL 100Steps AUTO SHUT OFF ON/OFF

INSTALLATION AUTO TUNNING COUNTRY SELECTION (BELGIUM/FRANCE/GERMANY/ITALY/ NETHERLAND/ SPAIN/SWEDEN/SWITZERLAND/UK/TURKEY POLAND/OTHER) MANUAL TUNING PROGRAMME NUMBER SYSTEM EURO/FRANCE NAME SEARCH FINE TUNE PROGRAM LOCK ON/OFF

__________________________________________________________________________


30

Service Menu(Will be displayed by pressing the digits “1923” while the top level Main menu is active)

Service Main VCTIMSTAR ADJUST AUTO COLOR OPTIONRESET DEFAULTISP

SOFTWARE INFORMATION SOFTWARE DATE THE DATE OF MAKING THE SOFTWARE MAIN VERSION THE MAIN MCU SOFTWARE REVISION NUMBER SUB VERSION THE SUB MCU SOFTWARE REVISION NUMBER DISPLAY DEVICE INFORMATION LCD AUO 32

VCTI ,MSTAR(THIS ITEM MUST NOT CHANGED WHEN SERVICE, ONLY FOR ENGINEERING TEST)

ADJUST(THIS ITEM IS USED WHEN NEED TO ADJUST THE WHITHE BALANCE)

__________________________________________________________________________


31

Administrador

Sticky Note

LCD TELEFUNKEN 26TLH7000D PARAMETROS: *VCTI-BLE-BLE MODE=2 BLE GAIN=2 BLE TILT=8 BLE STATIC=7 -FAC LTI-LTI CORING=1 LTI GAIN=15 -FAC CTI-CTI CORING=4 CTI GAIN=10 -FAC PEAK-PEAK POS=0 PEAK NEG=0 PEAK CORING=0 -SCART RGB-BRI= -90 CONT=43 CB SAT=50 CR SAT=50 TINT=0 RGAIN=34 GGAIN=33 BGAIN=35 -D CONTRAST NO -AGC=3 MSTAR-6C R=1 6C G=5 6C B=0 6C C=0 6C M=3 6C Y=2 6C F=4 SPECTRUM=1 ADJUST-R GAIN=128 G GAIN=128 B GAIN=98 R OFFSET=130 G OFFSET=128 B OFFSET=125 SUB CON=56 SUB BRI=42 OPTION-HOTEL=NO TXT AREA=AUTO TXT TOP=NO LVDS=TI TUNER=1 PIP ON=OFF SIDE AV=YES EXT DEV=DVB CUSTOM=T KEN LCD=LG 26

WE CAN ADJUST THE WHITE BALANCE BY CHANGING THE GAIN/OFFSET. IF ADJUSTING THE HIGH BRIGHTNESS PART, PLEASE CHANGE THE GAIN. IF ADJUSTING THE LOW BRIGHTNESS ,PLEASE CHANGE THE OFFSET.BUT THIS ADJUSTING IS NOT EFFECT IN OTHER SOURCE.

AUTO COLOR

THIS IS USED ONLY IN PC ANALOG OR COMPONENT SOURCE. WHEN ADJUSTING THE AUTO COLOR, WE MUST USED THE SPECIAL COLOR PATTERN.

__________________________________________________________________________


32

= HOTEL MODE ON/OFFOPTION

TXT AREA DON’T TOUCH TXT TOP DON’T TOUCH LVDS TI/NORMAL * WHEN WE HAVE WRONG COLOR, PLEASE CHANGE THIS OPTION TUNER 1/2 * ACCORDING TO 1 TUNER OR 2TUNER MODEL. PIP ON OFF/PC/AC * DEPENDING ON THE TV MODEL SIDE AV ON/OFF * DEPANDING ON THE TV MODEL EXTERNAL NO/DVB/WIRELESS/DVD * DEPENDING ON THE TV MODEL CUSTUM TELRA/GRUNGDIG/PHILIPS * DEPANDING ON THE TV MODEL LCD SELECT THE DISPLAY DEVICE

RESET

WHEN WE FINISH THE SERVICE, PUSH THE RESET THIS FUNCTION INITIALISE THE EEPROM

DEFAULT

DON’T TOUCH THIS ITEM.

ISP

OFF/ISPWHEN WE UDATE THE SOFTWARE, PLEASE THIS ITEM WE NEED THE SPECIAL JIG AND SOFTWARE WHEN UPDATING S/W.

____________________________________________________________________________________________________________________________________________________


33

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DV

I_R

XC

-D

VI_

RX

C+

RX

C+

RX

C-

RX

2+R

X2-

RX

1+R

X1-

RX

0+R

X0-

DV

I_R

X0-

DV

I_R

X0+

DV

I_C

HK

DD

C5V

-DV

I

DD

C_S

CLB

DD

C_S

DA

B

DD

C_S

CLB

DD

C_S

DA

B

BLU

E-

GR

EE

N-

RE

D-

RE

D+

GR

EE

N+

BLU

E+

BLU

E-

GR

EE

N-

RE

D-

RE

D+

GR

EE

N+

BLU

E+

SV

HS

_YIN

SV

HS

_CIN

CO

MP

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-GN

D

CO

MP

-YC

OM

P-P

BC

OM

P-P

R

CO

MP

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D

CO

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ND

CO

MP

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D

CO

MP

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ND

CO

MP

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CO

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CH

K_S

VID

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D

DV

I_R

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I_R

X2-

DV

I_R

X1+

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I_R

X1-

DD

C5V

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I

DV

I_R

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-

DV

I_R

XC

+D

VI_

RX

0-

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I_R

X1-

DV

I_R

X2-

DV

I_R

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I_R

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DD

C_S

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VI_

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HO

T_P

LUG

CO

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CO

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RO

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M

CO

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LUG

HP

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HP

-R

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V_S

CA

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S

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C

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V_S

CA

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R

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R

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ID

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D

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D

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R

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S

+5V

S

+5V

S

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CH

K_D

VI

6

E_D

DC

_CTL

7

E_D

DC

_CTL

7

RX

0-5

RX

0+5

RX

1-5

RX

1+5

RX

2-5

RX

2+5

RX

C-

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XC

+5

DD

C_S

CLA

3D

DC

_SD

AA

3

DD

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C_S

DA

A3

DD

C_S

CLA

3

DD

C5V

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I

DV

I_D

DC

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5D

VI_

DD

C_D

AT

5

PC

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YN

C_I

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PC

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YN

C_I

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DD

C5V

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I

RE

D_I

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GR

EE

N_I

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BLU

E_I

N5

R_G

ND

_S5

G_G

ND

_S5

B_G

ND

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DD

C5V

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CH

K_D

SU

B6

HD

CP

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NTR

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5

CH

K_S

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6S

VH

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8S

VH

S_Y

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8

CO

M_P

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5

CO

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R5

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B_G

ND

5

CO

M_P

B5

CO

M_Y

5

CO

M_Y

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CO

M_S

YN

C5

DTV

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DTV

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PC

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PC

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SC

AR

T_V

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T13

SC

AR

T_FB

LNK

13

SC

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13

SC

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T_V

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13

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T_A

VS

W1

6S

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3

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T_A

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4

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4

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T_LO

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3

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T_R

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T_V

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3

SC

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8

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T_A

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4

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T_A

VS

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6

SC

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T_V

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T23

SC

AR

T_V

IN2

3,8

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T_LO

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3

SC

AR

T_R

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T23

SC

AR

T_A

RIN

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4

LED

RE

D6

VC

T_R

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3V

CT_

TXD

3

DD

C_S

CLB

DD

C_S

DA

B

DV

I_R

X0-

7

DV

I_R

X1+

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VI_

RX

1-7

DV

I_R

X0+

7

DV

I_R

XC

+7

DV

I_R

XC

-7

DV

I_R

X2+

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VI_

RX

2-7

DV

I_R

X0-

2

DV

I_R

X1+

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81.

5nF

C95

81.

5nF

1 2

R23

1*R

231

*

12

R93

110

0R

931

100

Q50

5KS

C16

23Q

505

KSC

1623

R1

14

4.7

KR

11

44

.7K

12

R10

0710

0R

1007

100

R1

15

4.7

K

R1

15

4.7

K

12

R38

2*

R38

2*

12

C52

80.

1uF

C52

80.

1uF

R5

01

10

KR

50

11

0K 1

2

R55

91K

R55

91K

12

+

C36

14.

7UF/

16V

+

C36

14.

7UF/

16V

1 2

R53

447

KR

534

47K

12

+

C92

14.

7UF/

16V

+

C92

14.

7UF/

16V

12R403* R403*

1 2

R54

21KR

542

1K

1 2C52

20.

1uF

C52

20.

1uF

12

L507

HH

-201

2-30

1L5

07H

H-2

012-

301

1 2

R53

68.

2KR

536

8.2K

12

R56

0*R

560

*

12

L503

HH

-201

2-12

1

L503

HH

-201

2-12

1

1 2

+C

515

47uF

/50V

+C

515

47uF

/50V

12

C54

01n

FC

540

1nF

12

+

C51

447

uF/5

0V

+

C51

447

uF/5

0V

12

R54

8

1KR54

8

1K

1 2

C92

21.

5nF

C92

21.

5nF

1 2

C92

61.

5nF

C92

61.

5nF

Q90

7* Q

907

*

12

L508

HH

-201

2-12

1

L508

HH

-201

2-12

1

12

R54

091

KR

540

91K 1

2R

550

5.1K

R55

05.

1K

X0

12X

114

X2

15X

311

Y0

1Y

15

Y2

2Y

34

EN

6

A10

B9

X13

Y3

VD

D16

VE

E7

U30

8

74H

C40

52

U30

8

74H

C40

52

1 2

R53

91K

R53

91K

1 2

C96

41.

5nF

C96

41.

5nF

R5

02

*R

50

2*

1 2

+C

553

47uF

/50V

+C

553

47uF

/50V

12

C54

31n

FC

543

1nF

1 2

C11

5*C

115

*

12

+

C35

34.

7UF/

16V

+

C35

34.

7UF/

16V

12

L502

HH

-201

2-30

1L5

02H

H-2

012-

301

12

C53

21u

FC

532

1uF

12

R54

95.

1KR

549

5.1K

12

R10

0910

0R

1009

100

12

+

C35

74.

7UF/

16V

+

C35

74.

7UF/

16V

1 2

R10

21*R

1021

*

12

R53

110

0R

531

100

12

C54

61n

FC

546

1nF

1 2

C93

91.

5nF

C93

91.

5nF

12

+

C36

34.

7UF/

16V

+

C36

34.

7UF/

16V

12

R54

70/

2012

R54

70/

2012

1 2C52

50.

1uF

C52

50.

1uF

12

R92

2*

R92

2*

12

+

C95

94.

7UF/

16V

+

C95

94.

7UF/

16V

Q50

2KS

C16

23Q50

2KS

C16

23

12R544* R544*

1 2

+C

552

100u

F/16

V+C

552

100u

F/16

V

12

R38

7*

R38

7*

12

R52

90/

2012

R52

90/

2012

12

R93

310

0R

933

100

12

C51

11u

FC

511

1uF

1 2

C54

71n

FC

547

1nF

12

R95

210

0R

952

100

12

R53

00/

2012

R53

00/

2012

12

R40

0*

R40

0*

1 2

C96

01.

5nF

C96

01.

5nF

12

C51

21u

FC

512

1uF

12C

519

0.01

uFC

519

0.01

uF

R3

90

*R

39

0*1 2

R39

2

*

R39

2

*

12

C52

00.

01uF

C52

00.

01uF

12

C54

50.

1uF

C54

50.

1uF

1 2

C92

71.

5nF

C92

71.

5nF

1 2

C34

40.

1uF

C34

40.

1uF

12

R543* R543*

/SD

1R

INN

2R

INP

3V

2P5

4LI

NP

5LI

NN

6A

VD

DR

EF

7V

RE

F8

VA

RD

IFF

9V

AR

MA

X10

VO

LUM

E11

RE

FGN

D12

BSLN 13PVCCL1 14PVCCL2 15LOUTN1 16LOUTN2 17PGNDL1 18PGNDL2 19LOUTP1 20LOUTP2 21PVCCL3 22PVCCL4 23BSLP 24

BSRN48PVCCR147PVCCR246ROUTN145ROUTN244PGNDR143PGNDR242ROUTP141ROUTP240PVCCR339PVCCR438

BSRP37 VC

LAM

PR

36M

OD

E_O

UT

35M

OD

E34

AV

CC

33V

AR

OU

TR32

VA

RO

UTL

31/F

AD

E30

AV

DD

29C

OS

C28

RO

SC

27A

GN

D26

VC

LAM

PL

25

EP

AD

49

TPA3

004

U50

2

TPA3

004

U50

2

Q10

2KS

C16

23Q

102

KSC

1623

12

C54

8*C

548

*

12

+

C93

24.

7UF/

16V

+

C93

24.

7UF/

16V

1 2C52

10.

1uF

C52

10.

1uF

12

+

C36

24.

7UF/

16V

+

C36

24.

7UF/

16V

Q50

7KS

C16

23Q

507

KSC

1623

12

C53

11u

FC

531

1uF

12

R38

3*

R38

3*

1 2

R53

815

KR

538

15K

12

+

C92

84.

7UF/

16V

+

C92

84.

7UF/

16V

12

+

C50

91U

F/16

V

+

C50

91U

F/16

V

1 2

C35

81.

5nF

C35

81.

5nF

12

C53

9*C

539

*

12

C52

730

0PC

527

300P

12

L505

HH

-201

2-30

1L5

05H

H-2

012-

301

1 2

C11

6*C

116

*

12R405* R405*

12

R93

210

0R

932

100

12C

517

0.01

uFC

517

0.01

uF

R5

04

10

KR

50

41

0K

12 R56

10R

561

0

12

R95

310

0R

953

100

1 2

R53

724

KR

537

24K

R5

05

10

KR

50

51

0K

12

R10

0410

0R

1004

100

1 2

R54

610

KR

546

10K

12

R31

0410

0R

3104

100

12

C20

7*C

207

*

12

L509

HH

-201

2-12

1L5

09H

H-2

012-

121 1 2

R53

3*R

533

*

12 R56

2*R

562

*

1 2

C93

81.

5nF

C93

81.

5nF

Q50

3KS

C16

23 Q50

3KS

C16

231 2

C35

5*C

355

*1 2

C96

11.

5nF

C96

11.

5nF

R1

16

4.7

KR

11

64

.7K

12

+

C35

94.

7UF/

16V

+

C35

94.

7UF/

16V

1 2

R22

5*R

225

*

Q50

6KS

C16

23Q

506

KSC

1623

12

R51

0*

R51

0*

12

R10

0210

0R

1002

100

12R

511

*R

511

*

12

C54

91n

FC

549

1nF

1 2

+C

535

100u

F/16

V+

C53

510

0uF/

16V

12

L506

HH

-201

2-30

1L5

06H

H-2

012-

301

12

+

C35

24.

7UF/

16V

+

C35

24.

7UF/

16V

1 2

C34

50.

1uF

C34

50.

1uF

12

C53

81n

FC

538

1nF

12

+

C35

64.

7UF/

16V

+

C35

64.

7UF/

16V

12

R10

0510

0R

1005

100

1 2

C34

71u

FC

347

1uF

1 2

C54

11n

FC

541

1nF

12

R55

81K

R55

81K

12

R55

10/

2012

R55

10/

2012

12

R31

0510

0R

3105

100

1 2

R54

510

KR

545

10K

1 2

+

C365

*

+

C365

*

1 2

C95

61.

5nF

C95

61.

5nF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

FSDQM1

FSD

QM

0

FSC

LK-

VCT6562VCT6561

VCT6564

VCT6563

VCT6560

VCT6567VCT6566VCT6565

FSD

ATA1

FSD

ATA2

FSD

ATA3

FSD

ATA4

FSD

ATA5

FSD

ATA6

FSD

ATA7

FSD

ATA8

FSD

ATA9

FSD

ATA1

0FS

DAT

A11

FSD

ATA1

2FS

DAT

A13

FSD

ATA1

4FS

DAT

A15

FSDATA30FSDATA31

FSDATA17FSDATA18FSDATA19FSDATA20FSDATA21FSDATA22FSDATA23

FSDATA16

FSDATA24FSDATA25FSDATA26FSDATA27

FSDATA28FSDATA29

FSD

ATA0

FSDQS

FSDQS

FSD

QS

FSD

QS

FSAD

DR

10FS

ADD

R9

FSAD

DR

8

FSAD

DR

7FS

ADD

R6

FSAD

DR

5FS

ADD

R4

FSAD

DR

3FS

ADD

R2

FSAD

DR

1FS

ADD

R0

FSC

LK+

FSVR

EFFS

CKE

FSAD

DR

0FS

ADD

R1

FSAD

DR

2FS

ADD

R3

FSAD

DR

4FS

ADD

R5

FSAD

DR

6FS

ADD

R7

FSAD

DR

8FS

ADD

R9

FSAD

DR

10FS

ADD

R11

FSD

ATA0

FSD

ATA1

FSD

ATA2

FSD

ATA3

FSD

ATA4

FSD

ATA5

FSD

ATA6

FSD

ATA7

FSVR

EF

FSD

ATA8

FSD

ATA9

FSD

ATA1

0FS

DAT

A11

FSD

ATA1

2FS

DAT

A13

FSD

ATA1

4FS

DAT

A15

FSD

ATA1

6FS

DAT

A17

FSD

ATA1

8FS

DAT

A19

FSD

ATA2

0FS

DAT

A21

FSBK

SEL0

FSBK

SEL1

FSC

LK-

FSC

LK+

FSD

ATA2

2

FSC

KE

FSD

ATA2

3

/FSR

AS

FSD

ATA2

4

/FSC

AS

FSD

ATA2

5

/FSW

E

FSD

ATA2

6

FSD

QS

FSD

ATA2

7FS

DAT

A28

FSD

ATA2

9FS

DAT

A30

FSD

ATA3

1

FSD

QM

0

FSD

QM

1

FSAD

DR

11

ADC-B7

ADC-B2

ADC-B6ADC-B5

ADC-B1ADC-B0

ADC-B3ADC-B4

ADC

-G7

ADC

-G5

ADC

-G4

ADC

-G3

ADC

-G0

ADC

-G2

ADC

-G1

ADC

-G6

ADC

-R1

ADC

-R2

ADC

-R5

ADC

-R4

ADC

-R3

ADC

-R0

ADC

-R6

ADC

-R7

TXA0

+

TXA1

+TX

A1-

TXA0

-

TXA2

-TX

A2+

TXAC

-TX

AC+

TXA3

+TX

A3-

LCD

_VD

D

+2.5

V_M

EM

+2.5

V_M

EM

+2.5

V_M

EM

+2.5

V_M

EM

+5V_

OFF

+3.3

V_SC

ALER

VDD

_MPL

L

AVD

D_D

VI

AVD

D_D

VIAV

DD

_DVI

AVD

DA

VDD

P

VDD

C

VDDC

VDDP

VDDM

AVD

D_P

LL2

VDD

M

VDD

C

VDD

P

AVD

D_D

VIVD

DP

VDD

CAV

DD

_PLL

2VD

D_M

PLL

AVD

DA

VDD

_MPL

LAV

DD

_DVI

VDD

P

VDD

C

AVD

DA

AVD

D_P

LL2

+3.3

V_SC

ALER

+1.8

V_SC

ALER

VDD

M

VDD

C

+3.3

V_SC

ALER

VDD

M

+5V_

1TU

NER

+2.5

V_SC

ALER

+2.5

V_M

EM

+3.3

V_SC

ALER

+5V_

OFF

+3.3

V_SC

ALER

+2.5

V_M

EM

+5V_

OFF

RX2

-2

RX2

+2

RX1

-2

RX1

+2

RX0

-2

RX0

+2

RXC

-2

RXC

+2

RED

_IN

2

PC_H

SYN

C_I

N2

BLU

E_IN

2PC

_VSY

NC

_IN

2

GR

EEN

_IN

2VCT656_CLK

3

FSAD

DR

[11.

.0]

FSVR

EF

FSBK

SEL0

FSBK

SEL1

FSC

LK-

FSC

LK+

FSC

KE

/FSR

AS/F

SCAS

/FSW

EFS

DQ

S

FSD

ATA[

31..0

]

TXA0-TXA0+

TXA1+TXA1-

TXA2+TXA2-

TXAC+TXAC-

TXA3+TXA3-

TXA0

-

TXA0

+

TXA1

-

TXA1

+

TXA2

-

TXA2

+

TXAC

-

TXAC

+

TXA3

-

TXA3

+

LCD

_VD

D9

B_G

ND

_S2

G_G

ND

_S2

R_G

ND

_S2

CO

M_P

R_G

ND

2C

OM

_PR

2

CO

M_S

YNC

2

CO

M_P

B_G

ND

2C

OM

_PB

2

CO

M_Y

2C

OM

_Y_G

ND

2

VCT6

56[0

..7]

3IN

V_D

IM9

DVI

_DD

C_D

AT2

DVI

_DD

C_C

LK2

ALE_SCALER

3

SCAL

ER_R

ESET

6,7

RD_SCALER

3

WR_SCALER

3

AD0

3

AD1

3

AD2

3

AD3

3

AUD

IO_M

UTE

4AM

P_ST

AND

BY4

FSBK

SEL0

/FSR

AS

/FSC

AS/F

SWE

HD

CP_

CO

NTR

OL

2

FSBK

SEL1

AUD

IO_S

WB

4

AUD

IO_S

WA

4

HEA

DPH

ON

E_M

UTE

HPD

_CO

NTR

OL

7

SUB_

RFS

W3

MST

6_AU

MC

K

HD

MI1

_AU

DIO

L4

HD

MI1

_AU

DIO

R4

MST

6_AU

MU

TE

MST

6_AU

WS

MST

6_AU

SCK

MST

6_AU

SD

MST6_AUMCK

MST6_AUWSMST6_AUSCK

MST6_AUSD

MST6_AUMUTE

ADC-B[7..0]

7,8

ADC

-R[7

..0]

7

ADC

-G[7

..0]

7

FIELD-HDMI7VSYNC-HDMI7

VCLK

-HD

MI

7,8

HSY

NC

-HD

MI

7D

E-H

DM

I7

SW_P

ANEL

9

TXA0

-TX

A0+

TXA1

-TX

A1+

TXA2

-TX

A2+

TXAC

-TX

AC+

LCD

_VD

D4

TXA3

-TX

A3+

INV_

CTR

L9

INV_

CTR

L9

VCT_

SDA

2,6,

7,8

VCT_

SCL

2,6,

7,8

INV_

CTR

L 9

LCD

_VD

D9

DLP

_RES

ET9

UAR

T_BA

LAST

9

ASIC

_REA

DY

2LA

MP_

STAT

US

2

PDP_

DLP

_SC

L2,

6,7,

8

PDP_

DLP

_SD

A2,

6,7,

8

PDP_

DLP

_SC

L2,

6,7,

8PD

P_D

LP_S

DA

2,6,

7,8

DLP

_RES

ET9

UAR

T_BA

LAST

9

HEA

DPH

ON

E-VO

LUM

E

9

FAN

_STA

TUS

2

Title

Size

Doc

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Rev

Dat

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LG32;GND

LVDS_OPTION

LCD

PDP

open

open

short

short

R189

R192

R193

R162

R170

R189

R193

R192

R162

R170

open

open

short

short

R615

R201

R200

* ** *

LCD

PDP

R201

R200

R615

PDP/DLP OPTION

DLP OPTION

add

add

delete

delete

DLP

OTHERS R718

R719

R720

R721

R719

R720

R721

R168

R169

R186

R199

PDP OPTION

R719

R718

R187

R186

R199

R168

R169

R187

R170

R715

R713

R715

R713

1 2 3 45678

RA1

1822

RA1

1822

1 2

C72

9

0.1u

F

C72

9

0.1u

F

1 2 3 45678

RA1

2222

RA1

2222

R14

222

R14

222

1 2

C70

71u

FC

707

1uF

R11

31K

R11

31K

TP48

TP48

R15

91K

R15

91K

12

R17

710

KR

177

10K

R71

810

0R

718

100

TP10

2TP

102

1 2 3 45678

RA1

1922

RA1

1922

C10

80.

1uF

C10

80.

1uF

1 2C15

2

0.1u

F

C15

2

0.1u

F

TP45

TP45

12345

678

RA116

22

RA116

22

1 2

C17

222

pFC

172

22pF

TP42

TP42

R14

9*

R14

9*

Q10

4KS

C16

23Q

104

KSC

1623

R10

439

0R

104

390

R71

910

0R

719

100

TP46

TP46

R141

12K

/1%

R141

12K

/1%

TP36

TP36

1 2C15

7

0.1u

F

C15

7

0.1u

F

TP10

5TP

105

C13

60.

1uF

C13

60.

1uF

GN

D1

1G

ND

22

DV

I_R

+3

DV

I_R

-4

GN

D6

5D

VI_

G+

6D

VI_

G-

7A

VD

D_D

VI0

8D

VI_

B+

9D

VI_

B-

10G

ND

711

DV

I_C

K+

12D

VI_

CK

-13

AV

DD

_DV

I114

RE

XT

15A

VD

D_P

LL0

16G

ND

817

DD

CD

_DA

18D

DC

D_C

K19

GN

D9

20A

VD

D_A

DC

021

HS

YN

C1

22V

SY

NC

123

BIN

1P24

BIN

1M25

SO

GIN

126

GIN

1P27

GIN

1M28

RIN

1P29

RIN

1M30

BIN

0M31

BIN

0P32

GIN

0M33

GIN

0P34

SO

GIN

035

RIN

0M36

RIN

0P37

AV

DD

_AD

C1

38G

ND

1039

HS

YN

C0

40V

SY

NC

041

RM

ID42

RE

FP43

RE

FM44

GN

D11

45G

ND

1246

VD

DP

147

VI_

DA

TA[1

6]48

VI_

DA

TA[1

7]49

VI_

DA

TA[1

8]50

VI_

DA

TA[1

9]51

VI_

DA

TA[2

0]52

VI_

DA

TA[2

1]53

VI_

DA

TA[2

2]54

VI_

DA

TA[2

3]55

VI_

DA

TA[8

]56

VI_

DA

TA[9

]57

VI_

DA

TA[1

0]58

VI_

DA

TA[1

1]59

VI_

DA

TA[1

2]60

VI_

DA

TA[1

3]61

VD

DC

262

GN

D13

63V

I_D

ATA

[14]

64

VI_DATA[15] 65DHSYNC 66DE 67VI_CKA 68VI_DATA[0] 69VI_DATA[1] 70VI_DATA[2] 71VI_DATA[3] 72VI_DATA[4] 73VI_DATA[5] 74VI_DATA[6] 75VI_DATA[7] 76VDDC0 77GND0 78GND28 79VDDP0 80HWRESET 81INT 82ALE 83RDZ 84WRZ 85DBUS[0] 86DBUS[1] 87DBUS[2] 88DBUS[3] 89DBUS[4] 90DBUS[5] 91DBUS[6] 92DBUS[7] 93DDCR_CK 94DVSYNC 95FIELD 96DDCR_DA 97PWM2 98VDDC1 99GND29 100DQS[3] 101MDATA[31] 102MDATA[30] 103MDATA[29] 104MDATA[28] 105VDDM0 106GND3 107MDATA[27] 108MDATA[26] 109MDATA[25] 110MDATA[24] 111MDATA[23] 112MDATA[22] 113MDATA[21] 114MDATA[20] 115MDATA[19] 116MDATA[18] 117MDATA[17] 118MDATA[16] 119DQS[2] 120DQM[1] 121VDDM1 122GND4 123MVREF 124MCLKE 125MCLKZ 126MCLK 127GND5 128

BY

PA

SS

192

NC

019

1P

WM

519

0P

WM

418

9P

WM

318

8N

C1

187

GP

O[6

]18

6G

PO

[5]

185

GP

O[4

]18

4V

DD

P2

183

GN

D14

182

GN

D15

181

VD

DC

318

0G

PO

[3]

179

GP

O[2

]17

8G

PO

[1]

177

GP

O[0

]17

6G

ND

1617

5V

DD

M2

174

DQ

S[0

]17

3M

DA

TA[0

]17

2M

DA

TA[1

]17

1M

DA

TA[2

]17

0M

DA

TA[3

]16

9M

DA

TA[4

]16

8M

DA

TA[5

]16

7M

DA

TA[6

]16

6M

DA

TA[7

]16

5M

DA

TA[8

]16

4M

DA

TA[9

]16

3M

DA

TA[1

0]16

2M

DA

TA[1

1]16

1G

ND

1716

0V

DD

M3

159

MD

ATA

[12]

158

MD

ATA

[13]

157

MD

ATA

[14]

156

MD

ATA

[15]

155

DQ

S[1

]15

4D

QM

[0]

153

GN

D18

152

VD

DC

415

1M

AD

R[1

1]15

0M

AD

R[1

0]14

9M

AD

R[9

]14

8M

AD

R[8

]14

7G

ND

1914

6V

DD

M4

145

MA

DR

[7]

144

MA

DR

[6]

143

MA

DR

[5]

142

MA

DR

[4]

141

MA

DR

[3]

140

MA

DR

[2]

139

MA

DR

[1]

138

MA

DR

[0]

137

WE

Z13

6C

AS

Z13

5G

ND

2013

4V

DD

M5

133

RA

SZ

132

BA

DR

[0]

131

BA

DR

[1]

130

AV

DD

_PLL

212

9

AVDD_PLL1256XIN255

XOUT254PWM1253PWM0252

VI_CKB251NC2250NC3249NC4248NC5247

VDDC5246GND21245

VI_DATA[31]244VI_DATA[30]243VI_DATA[29]242VI_DATA[28]241

BUSTYPE240GND22239VDDP3238

VI_DATA[27]237VI_DATA[26]236VI_DATA[25]235VI_DATA[24]234

NC6233NC7232NC8231NC9230

NC10229NC11228

LVBOM227LVBOP226VDDC6225GND23224GND24223VDDP4222LVB1M221LVB1P220LVB2M219LVB2P218

LVBCKM217LVBCKP216

LVB3M215LVB3P214

VDDC7213GND25212LVA0M211LVA0P210LVA1M209LVA1P208LVA2M207LVA2P206

LVACKM205LVACKP204

GND26203VDDP5202LVA3M201LVA3P200NC12199NC13198NC14197NC15196NC16195NC17194

GND27193

GND266

U10

1A

MST

6181

U10

1A

MST

6181

C11

00.

1uF

C11

00.

1uF

12

R10

2*

R10

2*

R15

422

R15

422

1 2+C

174

10uF

/16V

+C

174

10uF

/16V

R186 0R186 0

1 2

C17

322

pFC

173

22pF

TP10

3TP

103

C36

6*

C36

6*

C10

10.

1uF

C10

10.

1uF

R71

50

R71

50

1 2C14

4

0.1u

F

C14

4

0.1u

F

R12

710

KR

127

10K

C10

20.

1uF

C10

20.

1uF

R15

222

R15

222

1 2C15

0

0.1u

F

C15

0

0.1u

F

1234 5

678

RA127

22

RA127

22

R170 0R170 0

R72

010

0R

720

100

R14

022

R14

022

12

C13

50.

1uF

C13

50.

1uF

TP37

TP37

R162 0R162 0

12

R39

6 *R

396 *

R71

21KR

712

1K

1 2 3 45678

RA1

2122

RA1

2122

1 2 3 45678

RA1

2322

RA1

2322

LRC

IN1

DIN

2B

CK

IN3

NC

04

CA

P5

VO

UTR

6G

ND

7V

DD

8V

OU

TL9

MU

TE10

NC

111

DE

EM

PH

12FO

RM

AT

13S

CK

I14

U10

3

WM

8725

U10

3

WM

8725

1234 5

678

RA125

22

RA125

22A

031

A1

32A

233

A3

34A

447

A5

48A

649

A7

50A

851

A9

45A

1036

A11

37

BA

029

BA

130

/CLK

54C

LK55

CK

E53

/CS

28/R

AS

27/C

AS

26/W

E25

DQ

S94

DM

023

DM

156

DM

224

DM

357

NC

038

NC

139

NC

240

NC

341

NC

442

NC

543

NC

644

NC

787

NC

888

NC

989

NC

1090

NC

1191

NC

1293

VDDQ02VDDQ18VDDQ214VDDQ322VDDQ459VDDQ567VDDQ673VDDQ779VDDQ886VDDQ996

VDD015VDD135VDD265VDD395

VREF58 DQ

097

DQ

198

DQ

210

0D

Q3

1D

Q4

3D

Q5

4D

Q6

6D

Q7

7

DQ

860

DQ

961

DQ

1063

DQ

1164

DQ

1268

DQ

1369

DQ

1471

DQ

1572

DQ

169

DQ

1710

DQ

1812

DQ

1913

DQ

2017

DQ

2118

DQ

2220

DQ

2321

DQ

2474

DQ

2575

DQ

2677

DQ

2778

DQ

2880

DQ

2981

DQ

3083

DQ

3184

VSSQ0 5VSSQ1 11VSSQ2 19VSSQ3 62VSSQ4 70VSSQ5 76VSSQ6 82VSSQ7 92VSSQ8 99

VSS0 16VSS1 46VSS2 66VSS3 85

MCL 52

U10

2H

Y5D

U28

3222

Q4H

U10

2H

Y5D

U28

3222

Q4H1 2+

C36

722

uF/1

6V+

C36

722

uF/1

6V

1 2

C17

022

pFC

170

22pF

1 2

C11

81u

FC

118

1uF

TP10

1TP

101

C11

30.

1uF

C11

30.

1uF

R11

46*

R11

46*

12

R17

322

R17

322

C10

30.

1uF

C10

30.

1uF

12

C13

00.

1uF

C13

00.

1uF

TP41

TP41

C13

80.

1uF

C13

80.

1uF

12

R17

610

KR

176

10K

12345

678

RA117

22

RA117

22

TP70

1TP

701

C10

40.

1uF

C10

40.

1uF

TP50

TP50

R18

3*

R18

3*

12

R17

822

R17

822

TP10

4TP

104

R11

450

R11

450

12

C14

2*

C14

2*

TP10

7TP

107

R18

9*

R18

9*

R17

14.

7KR

171

4.7K

1 2

C16

80.

1uF

C16

80.

1uF

1 2C14

5

0.1u

F

C14

5

0.1u

F

R11

40*

R11

40*

R17

510

R17

510

TP10

6TP

106

R14

522

R14

522

TP44

TP44

TP10

9TP

109

R71

4*

R71

4*

12

R31

031K

R31

031K

TP39

TP39

C94

90.

047u

FC

949

0.04

7uF

1 2C14

7

0.1u

F

C14

7

0.1u

F

12

R15

822

R15

822

C13

40.

1uF

C13

40.

1uF

1 2C15

8

0.1u

F

C15

8

0.1u

F

1 2

C16

61u

FC

166

1uF

1 2

C10

71u

FC

107

1uF

R168 0R168 0

TP40

TP40

R40

8*

R40

8*

1 2C15

5

0.1u

F

C15

5

0.1u

F

12

C10

622

pFC

106

22pF

R15

522

R15

522

R10

1*

R10

1*

C14

10.

1uF

C14

10.

1uF

R15

322

R15

322

R15

622

R15

622

C16

50.

1uF

C16

50.

1uF

R18

4*

R18

4*

12345

678

RA115

22

RA115

22

R72

110

0R

721

100

12

C11

40.

1uF

C11

40.

1uF C

951

0.04

7uF

C95

10.

047u

F C13

20.

1uF

C13

20.

1uF

R11

41*

R11

41*

12

C12

90.

1uF

C12

90.

1uF

R11

42*

R11

42*

R13

5*

R13

5*

12

R17

422

R17

422

TP47

TP47

R15

722

R15

722

1 2+C

176

10uF

/16V

DC

AP_5

0D25

0

+C

176

10uF

/16V

DC

AP_5

0D25

0

TP43

TP43

1 2C14

9

0.1u

F

C14

9

0.1u

F

C13

90.

1uF

C13

90.

1uF

R14

322

R14

322

TP49

TP49

P1

1P

22

P3

3P

44

P5

5P

66

P7

7P

88

P9

9P

1010

P11

11P

1212

P13

13P

1414

P15

15P

1616

P17

17P

1818

P19

19P

2020

P21

21P

2222

P23

23P

2424

P25

25P

2626

P27

27P

2828

P29

29P

3030

P31

31

P32

32

J102

MO

LEX

J102

MO

LEX

TP11

3TP

113

R71

1*

R71

1*

C95

40.

047u

FC

954

0.04

7uF

R16722 R16722

1 2

Y101

14.3

18M

HZ

Y101

14.3

18M

HZ

12

R17

222

R17

222

R43

8*

R43

8*

C41

30.

1uF

C41

30.

1uF

C16

70.

1uF

C16

70.

1uF

12

R39

9*R

399

*

R18

1*

R18

1*

R71

30

R71

30

C11

10.

1uF

C11

10.

1uF

TP10

8TP

108

R13

910

0R

139

100

C16

2*

C16

2*

R13

7*

R13

7*

TP38

TP38

C13

70.

1uF

C13

70.

1uF

C16

40.

1uF

C16

40.

1uF

C95

21n

FC

952

1nF

C16

30.

1uF

C16

30.

1uF

1 2C15

9

0.1u

F

C15

9

0.1u

F

1 2C14

6

0.1u

F

C14

6

0.1u

F

1 2 3 45678

RA1

1422

RA1

1422

C17

5

0.1U

F

C17

5

0.1U

F

R16

3*

R16

3*

R71

0*

R71

0*

1 2C15

4

0.1u

F

C15

4

0.1u

F

1 2C16

1

0.1u

F

C16

1

0.1u

F

12

C14

0*

C14

0*

R15

122

R15

122

R40

9*

R40

9*

R13

6*

R13

6*

TP11

1TP

111

C12

70.

1uF

C12

70.

1uF

R11

81K

R11

81K

C13

30.

1uF

C13

30.

1uF

R11

44*

R11

44*

C10

90.

1uF

C10

90.

1uF

R20

0*

R20

0*

Q20

8KS

C16

23Q

208

KSC

1623

1 2

C14

3

0.1u

F

C14

3

0.1u

F

1 2C14

8

0.1u

F

C14

8

0.1u

F

12345

678

RA113

22

RA113

22

R44

0*

R44

0*

R199 0R199 0

R144

10K

/1%

R144

10K

/1%

1 2C15

1

0.1u

F

C15

1

0.1u

F

R169 0R169 0

1234 5

678

RA126

22

RA126

22

C16

90.

1uF

C16

90.

1uF

R20

1*

R20

1*

R14

622

R14

622

R14

722

R14

722

R10

34.

7KR

103

4.7K

1 2 3 45678

RA1

2022

RA1

2022

R15

022

R15

022

R14

822

R14

822

1 2C16

0

0.1u

F

C16

0

0.1u

F

1 2C15

3

0.1u

F

C15

3

0.1u

F

1 2

C17

122

pFC

171

22pF

TP11

0TP

110

R61

5*

R61

5*

12

C10

522

pFC

105

22pF

C11

20.

1uF

C11

20.

1uF

R16622 R16622

R27

5

1KR27

5

1K

P1

1P

22

P3

3P

44

P5

5P

66

P7

7P

88

P9

9P

1010

P11

11P

1212

P13

13P

1414

P15

15P

1616

P17

17P

1818

P19

19P

2020

P21

21P

2222

P23

23P

2424

P25

25P

2626

P27

27P

2828

P29

29P

3030

P31

31

P32

32 J21

DF1

4A_3

0P_1

25H

J21

DF1

4A_3

0P_1

25H

R13

410

KR

134

10K

12

R31

021K

R31

021K

R16

4*

R16

4*

R12

11MR

121

1M

R16

5*

R16

5*

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

X2

X1

X1X2

CH

K_D

VI

CH

K_D

SU

B

AS

IC_R

EA

DY

LAM

P_S

TATU

SD

TV_I

DE

NT

AC

D

KE

Y_A

D2

KE

Y_A

D1

ISP

_CTL

1IS

P_C

TL2

THD

_SS

5V_D

+3.3

V_M

ICO

M

+3.3

V_M

ICO

M

+3.3

V_M

ICO

M

+3.3

V_M

ICO

M

+3.3

V_M

ICO

M

+3.3

V_M

ICO

M

+3.3

V_M

ICO

M

+5V

_OFF

+5V

SS

CA

LER

_RE

SE

T5,

7

VC

T_S

DA

2,3,

7,8

VC

T_S

CL

2,3,

7,8

LED

RE

D2

IRR

CV

R2,

3

KE

Y_A

D2

2,3

KE

Y_A

D1

2,3SW

_RE

G_E

N9

FAN

_STA

TUS

2M

_DD

C_C

TL2

TW_R

ES

ET

8

SC

AR

T_A

VS

W2

2S

CA

RT_

AV

SW

12

CH

K_D

SU

B2

CH

K_D

VI

2

DTV

_ID

EN

T

AC

D

5V_D

VC

T_R

ES

ETQ

3

LED

WA

RN

ING4

LAM

P_S

TATU

S2

ISP

_CTL

12

ISP

_CTL

22

THD

_SS

DV

B_O

N2

GP

IO2

IRR

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TE2

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>A

4AM

0005

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0256

487

Dae

il P

laza

#60

2, 5

28-3

, Cho

nchu

n-D

ong,

Jan

gan-

Gu,

Suw

on, K

youn

ggi-D

o, 4

40-3

30, K

orea

06. M

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sday

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il 20

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ote

<Doc

>A

4AM

0005

INS6

0256

487

Dae

il P

laza

#60

2, 5

28-3

, Cho

nchu

n-D

ong,

Jan

gan-

Gu,

Suw

on, K

youn

ggi-D

o, 4

40-3

30, K

orea

06. M

ICO

MA

4

68

Thur

sday

, Apr

il 20

, 200

6Ti

tleS

ize

Doc

umen

t Num

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AL

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rN

ote

<Doc

>A

4AM

0005

INS6

0256

487

Dae

il P

laza

#60

2, 5

28-3

, Cho

nchu

n-D

ong,

Jan

gan-

Gu,

Suw

on, K

youn

ggi-D

o, 4

40-3

30, K

orea

06. M

ICO

MA

4

68

Thur

sday

, Apr

il 20

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6

SDI PDP ONLY

SDI PDP

OTHER

C208 1nF

DELETE C208

12

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4*

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4*

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110

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251

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239

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ote

<Doc

>A4

AM00

05

INS6

0256

487

Dae

il P

laza

#60

2, 5

28-3

, Cho

nchu

n-D

ong,

Jan

gan-

Gu,

Suw

on, K

youn

ggi-D

o, 4

40-3

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orea

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Cus

tom

78

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ay, A

pril

07, 2

006

Title

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<Doc

>A4

AM00

05

INS6

0256

487

Dae

il P

laza

#60

2, 5

28-3

, Cho

nchu

n-D

ong,

Jan

gan-

Gu,

Suw

on, K

youn

ggi-D

o, 4

40-3

30, K

orea

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PA

GE

Cus

tom

78

Frid

ay, A

pril

07, 2

006

Title

Size

Doc

umen

t Num

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Rev

Dat

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NFI

DE

NTI

AL

Addr

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igne

rN

ote

<Doc

>A4

AM00

05

INS6

0256

487

Dae

il P

laza

#60

2, 5

28-3

, Cho

nchu

n-D

ong,

Jan

gan-

Gu,

Suw

on, K

youn

ggi-D

o, 4

40-3

30, K

orea

2 TU

NER

PA

GE

Cus

tom

78

Frid

ay, A

pril

07, 2

006

ADDR

ESS:

C6

2 TUNER

1 TUNER

DELETE : THIS PAGE & POWER OPTION

CHANGE : U639 TECH2949PG40B(D)

DELETE :

CHANGE : U639 TECH2949PS40A(D), U602 TCPW3001PC29A(H)

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<Org

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A2

88

Wed

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12, 2

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LCD 9-1 SS PDP 9-2

LG PDP 9-3

DELETE THIS WHEN THE SS PDP 9-4

2 TUNER 9-5

MOLE

X

MOLE

X

IDTV

LCD

5V

LG P

DP

ADD

ADD

DELE

TEDE

LETE

U701

AP1

501

ADJ

U701

AP1

501

ADJ

R192

0 O

HMR1

93 0

OHM

R193

R202

0 O

HMR2

02

R701

9.1

K 1%

R701

9.1

K 1%

OHM

R702

1K

1% O

HM

LCD

12V

DELE

TEAD

D

LCD 9-7

IDTV LCD 5V PANEL, LG PDP 9-6

R192

R702

3K

1%J9

13

R203

0 O

HMR2

03R2

29

C524

:IDT

V_on

lyC5

24 4

7uF/

50V

NORM

ALI_

DTV

SMW2

50SM

AW25

0

1 2

C62

5

220u

F/16

V

C62

5

220u

F/16

V

1 2+C

714

100u

F/16

V+

C71

410

0uF/

16V

R256

1K

R256

1K

Q20

4K

SC

1623

Q20

4K

SC

1623

C73

70.

1uF

C73

70.

1uF

12

R22

90

R22

90

1 2

C77

90.

1uF

C77

90.

1uF

12

C77

60.

1uF

C77

60.

1uF

1 2+C

791

100u

F/16

V+

C79

110

0uF/

16V

GND 1

OU

T2

VC

C3

TAB

4

U70

6

RC

1117

-3.3U70

6

RC

1117

-3.3

P1

1P

22

P3

3P

44

J705

CO

ND

4P_S

MW

250

J705

CO

ND

4P_S

MW

250

1 2

C71

5

0.1u

F

C71

5

0.1u

F

R257

1K

R257

1K

R702

1K

1%

R702

1K

1%

Q20

3K

SC

1623

Q20

3K

SC

1623

S1

1S

22

S3

3G

4

D1

8D

27

D3

6D

45

U30

9

IRF7

404

U30

9

IRF7

404

R701

9.1

K 1

%

R701

9.1

K 1

%

21

3

D70

2B

AV

99D

702

BA

V99

1 2

C72

422

0uF/

16V

C72

422

0uF/

16V

1 2+C

719

100u

F/16

V

+C

719

100u

F/16

V

1 2

C79

40.

1uF

C79

40.

1uF

12

R19

10

R19

10

P1

1P

22

P3

3P

44

P5

5P

66

P7

7P

88

P9

9P

1010

P11

11

J921

CO

ND

11P

_351

55-1

000

J921

CO

ND

11P

_351

55-1

000

12

R19

4*

R19

4*

R16

147

0R

161

470

1 2

C70

60.

1uF

C70

60.

1uF

12

C77

80.

1uF

C77

80.

1uF

1 2+C

723

220u

F/16

V

+C

723

220u

F/16

V

1 2

C72

1

0.1u

F

C72

1

0.1u

F

12 R193

*

R193

*

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

U71

2

4069

U71

2

4069

1 2

C78

40.

1uF

C78

40.

1uF

R775

0R

775

0

1 2

C78

70.

1uF

C78

70.

1uF

12 R202

*

R202

*

1 2C

731

0.1u

F

C73

1

0.1u

F

21

3

D70

1B

AV

99D

701

BA

V99

P1

1P

22

P3

3P

44

P5

5P

66

P7

7P

88

P9

9P

1010

J702

CO

ND

10P

_351

55-1

000

J702

CO

ND

10P

_351

55-1

000

R17

90

R17

90

12

R19

7*R

197

*

1 2+C

716

100u

F/16

V

+C

716

100u

F/16

V

R18

0*

R18

0*

1 2+C

712

100u

F/16

V+

C71

210

0uF/

16V

R770

10K

R770

10K

C72

20.

1uF

C72

20.

1uF

21

3

D70

3B

AV

99D

703

BA

V99

1 2

C71

8

0.1u

F

C71

8

0.1u

F

P1

1P

22

P3

3P

44

P5

5P

66

P7

7P

88

P9

9P

1010

P11

11P

1212

J704

CO

ND

12P

_SM

W25

0

J704

CO

ND

12P

_SM

W25

0

1 2+C73

2

470U

/16V

+C73

2

470U

/16V

P1

1P

22

P3

3P

44

P5

5P

66

P7

7P

88

P9

9P

1010

P11

11P

1212

J701

CO

ND

12P

J701

CO

ND

12P

OU

T2

IN3

GND 1

TAB

4

U71

6R

C11

17-3

.3

SO

T-22

3

U71

6R

C11

17-3

.3

SO

T-22

3

12

R18

20

R18

20

GND 1

OU

T2

VC

C3

TAB

4

U96

RC

1117

-5

U96

RC

1117

-5

R772

4.7

KR

772

4.7

K

P1 1P2 2P3 3P4 4P5 5P

66

U70

1A

P15

01_A

DJ

U70

1A

P15

01_A

DJ

R706

47K

R706

47K

Q20

6K

SC

1623

Q20

6K

SC

1623

123

J913

CO

ND

3PJ9

13C

ON

D3P

12

C78

10.

1uF

C78

10.

1uF

12

R18

8*

R18

8*

IN1

OU

T3

G 4

U70

278

M08

U70

278

M08

R778

*

R778

*

R263

*R

263

*

1 2

C79

20.

1uF

C79

20.

1uF

1 2C79

5

0.01

uF

C79

5

0.01

uF

1 2

C17

90.

1uF

C17

90.

1uF

R777

0R

777

0

R707

47K

R707

47K

P1

1P

22

P3

3P

44

P5

5P

66

P7

7

J706

CO

ND

7P_S

MW

250

J706

CO

ND

7P_S

MW

250

12

R20

30

R20

30

1 2

C78

01n

FC

780

1nF

OU

T2

IN3

GND 1

TAB

4

U71

4R

C11

17-2

.5

SO

T-22

3

U71

4R

C11

17-2

.5

SO

T-22

3

1 2+C

717

100u

F/16

V

+C

717

100u

F/16

V

Q20

7K

SC

1623

Q20

7K

SC

1623

12

R18

7*

R18

7*

1 2

C70

5

0.1u

F

C70

5

0.1u

F

R268

*R

268

*

1 2

+C

524

47uF

/50V

+C

524

47uF

/50V

1 2

C71

30.

1uF

C71

30.

1uF

1 2C61

50.

1uF

C61

50.

1uF

ZD70

7

UD

Z33B

ZD70

7

UD

Z33B O

UT

2IN

3

GND 1

TAB

4

U71

3R

C11

17-2

.5

SO

T-22

3

U71

3R

C11

17-2

.5

SO

T-22

3

12

C77

7

0.1u

F

C77

7

0.1u

F

1 2C79

6

0.00

1uF

C79

6

0.00

1uF

1 2

+C

530

*+

C53

0*

R26

2 1K

R26

2 1K

R266

0R

266

0

1 2+C

793

100u

F/16

V+

C79

310

0uF/

16V

R264

*R

264

*

12

R19

5*R

195

*

12

R19

8*R

198

*

1 2

C17

80.

1uF

C17

80.

1uF

12

R19

6*

R19

6*

R771

100K

R771

100K

1 2

C71

1

0.1u

F

C71

1

0.1u

F

12

R19

00

R19

00

1 2

C15

60.

1uF

C15

60.

1uF

OU

T2

IN3

GND 1

TAB

4

U70

4R

C11

17-1

.8

SO

T-22

3

U70

4R

C11

17-1

.8

SO

T-22

3

1 2+

C73

3* +

C73

3*

R776

*

R776

*

R267

0R

267

0

1 2

C78

30.

1uF

C78

30.

1uF

1 2+C

725

220u

F/16

V

+C

725

220u

F/16

V

Q10

3K

SC

1623

Q10

3K

SC

1623

OU

T2

IN3

GND 1

TAB

4

U71

5R

C11

17-3

.3

SO

T-22

3

U71

5R

C11

17-3

.3

SO

T-22

3

1 2

C77

50.

1uF

C77

50.

1uF

1 2

C72

8

0.1u

F

C72

8

0.1u

F

1 2

C62

6

220u

F/16

V

C62

6

220u

F/16

V

2 1

ZD70

1

MB

RS

340

ZD70

1

MB

RS

340

1 2+C

785

100u

F/16

V

+C

785

100u

F/16

V

1 2+C

786

100u

F/16

V

+C

786

100u

F/16

V

12

C11

71u

FC

117

1uF

R614

4.7

KR

614

4.7

K

1 2+

C72

6

220u

F/16

V

+

C72

6

220u

F/16

V

12

C78

20.

1uF

C78

20.

1uF 1 2

C73

0

0.1u

F

C73

0

0.1u

F

GND 1

OU

T2

VC

C3

TAB

4

U95

RC

1117

-5

U95

RC

1117

-5

12

R19

2*

R19

2*

R70

8 1KR

708 1K

ZD60

1U

DZ3

3BZD

601

UD

Z33B

12

L701

33U

HL7

0133

UH

12

R18

50

R18

50

R255

1k

R255

1k

IN1

OU

T3

G 4

U70

378

M08

U70

378

M08

OU

T2

IN3

GND 1

TAB

4

U70

5R

C11

17-1

.8

SO

T-22

3

U70

5R

C11

17-1

.8

SO

T-22

3

1 2

C17

70.

1uF

C17

70.

1uF

1 2

C71

00.

1uF

C71

00.

1uF

C72

00.

1uF

C72

00.

1uF

R120

10k

R120

10k


41


42


43


44

1 2 3 4 5 6 7 8 9 10 11 12

A

B

C

D

121110987654321

D

C

B

A

1

2

S303

POWER

F300

T3.15AL/250V

C339

1nF 400VAC

C337

100nF 275VAC

C340

2.2nF 400VAC

C324

270uF/400V

C3292200uF/25V

C330

1000uF/16V

VCC 8

PCS2

RZI3

SRC4 OFC 5

GND 6

OUT 7

NC1IC30

ICE1QS01

C325680pF 2000V

D300

1N4148

R307

33R

R306

100R

R302

1M

C302330pF

R3141K

R315

470R

C30147nF

C30010pF

R3008.2K

R30156K

D303TL431

C34247pF

C34415nF

C32247uF/50V

R32133K

R322

5.6K 1%

D301

BYV36C

C3201nF/1KV

C3211nF/1KV

C318

1nF/1KV

C319

1nF/1KV

C948

1000uF 16V

C315100nF

C3341000uF/16V

C316100nF

C314100nF

C312100nF

C3321000uF/25V

12V

C34310uF

R303

4.7M 1/2W

L307

20uH 2.5AC3511000uF/25V C347

100nF

VB

1 1

2 2

3 344

55

66IC37

TCDT1101G

L302

BEAD

L303

BEAD

D308BYW76

R329

68K 1W

C34133nF 630V

1 1

2 2

3 344

55

66IC20

TCDT1101G

R2011K

R202

470R

VB2

D202TL431

1

23

T300

SPP07N60

C20747pF

C20815nF

R20533K

1

23

4

IC36

RS406

C20047nF

D200

STPS5L40C210

470uF/35V

L308

10uH 7A

C205100nF

L200

20uH 2.5A

C211470uF/16V

C204

100nF

5VSTBY

R31012K

C206

1nF 400VAC

T301

BC848B

R317

1K

C35847nF

C359100nF

1

2 3

4

L310

2X27mH

C357

100nF 275VAC

C338

1nF 400VAC

VR30V320

R2002.4K 1%

C308100nF 275VAC

R3191.2M

C354100nF/50V

1 2J309

OPS.

R3272.2K

VCC 8

PCS2

RZI3

SRC4 OFC 5

GND 6

OUT 7

NC1IC40

ICE1QS01

C413680pF 2000V

D400

1N4148

R405

33R

R404

100R

R320

100R

D201BYV36C

R20468K 1W

R403

1M

C202

2.2nF 400VAC

C403330pF

C336220pF

C401100nF

R203

1K

C40010pF

R4008.2K

1 6

3 4

L311PFC

R40256K

C41047uF/50V

D401

BYV36C

R4161K

R417

470R

5VMAIN

6

5

3

1

14

16

9

13

11

15

10

12

13

11

TR30

SMPS LCD MAIN

D403TL431

1

2

3

4

5

6

7

8

9

10

S302

CON10_W

C41847pF

24V

C41915nF

R41833K

R41930K 1%

1

2

3

4

5

6

7

8

9

10

11

12

13

14

S305

CON14

BGND

24V

C405100nF

C317100nF

C420470uF/35V

C406100nF

R333

4.7K

C42110uF

C35610uF/25V

L400

BEAD

L401

BEAD

D402BYW76

R41068K 1W

C41133nF/630V

Q300BC337

1

23

T401SPP07N60

D3182.4V

1 1

2 2

3 344

55

66IC41

TCDT1101G

BL_ON/OFF

L402

10uH 7A

5VOC

R3361K 1%

T400

BC848B

R304

150K

R414

1K

R305

150K

STB

C4142200uF/35V

C40947nF

C408100nF

D404

MBR20200CT

R412

10R

R413

10R

C4161nF 1KV

D31512V

C4171nF 1KV

C21333uF

1

4

10

6TR20

SMPS STANDBY LCD

24V

C345

33pF

3

4

1

6

12

7

11

8

TR40

SMPS LCD BL

A_DIM

GN

D1

GN

D2

GN

D3

VFB

4V

CC

5

VST

8

D7

IC21FSD200

R3261K

5VMAIN

D306BAT85

5VSTBY

D304BAT85

D3091N4148

R3352.7K

5VOC

D3205.1V

R3383.4K 1%

R3372.4K 1%

24V

C335100nF

R334

4.7K

C36010uF/25V

Q301BC337

D3192.4V

R316

150K

R332

150K

D31712V

C203100nF

C3288.2nF 400V

5VOC

C3618.2nF 400V

C304

22pF

R4151K

1

2 3

4L800

2X27mH

Q302BC848B

R339

4.7KR341270R

D32212V

D32133V

D3251N4007

R34447R

R34547R

C4028.2nF 400V

R342270R

D3248.2V

D32333V

C4048.2nF 400V

VB3

Q303BC848B

R340

4.7K

D3261N4007

C362

100uF/400V

R3431.2M

T302BC848B

R346

3.3KSTDBY

STB

R34733K

J301

J300

J303

J311

J313

J314

J315

J305

J302J304

J312

J316

J317

1 2

HS33SMPS HEATSINK

1 2

HS34SMPS HEATSINK

1 2

HS32POWER HEATSINK

1 2

HS35POWER HEATSINK

1 2

HS30POWER HEATSINK

1

2

3

4

5

6

7

8

9

10

11

12

S300

POWER

J310 J318J306

GND

J320 J322

J324

J325

J327

J328 J326

FD1 FD2 FD3

J308

J323

TP56

TP57

TP58

TP60

TP59

TP62

TP61

TP5

TP63

TP12

TP65

TP64

TP4

TP3

TP2

TP6

TP9 TP13

TP1

TP7

TP10

TP18

TP14

TP11

TP15

TP20

TP19

TP25

TP21

TP16 TP22

TP23 TP24

TP17

TP8

TP26

TP27

TP34 TP38 TP41

TP36TP32

TP31TP28

TP29

TP130

TP131

TP132 TP134

TP133

TP100

TP101 TP111

TP105

TP114TP106

TP107

TP108

TP104

TP102

TP103

TP136 TP137TP135

TP109

TP115

TP138

TP139 TP140

TP143 TP147

TP145

TP148

TP142 TP149

TP141

TP119

TP144

TP121

TP120

TP146

TP124 TP129

TP128

TP127

TP126

TP125

TP123

TP122TP118

TP117

TP116

TP87TP82TP73

TP112

TP110

TP66

TP113

TP68

TP67

TP69 TP71

TP70

TP84 TP86

TP81TP77

TP80

TP89

TP88

TP85

TP83TP72

TP79TP75

TP76

TP74 TP78

TP97

TP98

TP55

TP96

TP99

TP93

TP92

TP53

TP95

D302MBR20200CT

R308

100R

R309

100R

C305220pF

C303220pF

TP30

TP37

TP35

5VMAIN

12V

5VSTBY

BL_ON/OFF

STDBY

A_DIM

TP50

TP43 J329

J330 J331

J307

R33022K 1%

R331

4.7K 1%

D305

MBR1045

D310

MBR1045

J319Comment

F301

5A

1

2

3

4S301

CON4

12V

5VMAIN

L304

BEAD

L305

BEAD

L301

BEAD

L306

BEAD

C30610pF

C30710pF

Power B

oard

__________________________________________________________________________

26'' - 32 '' LCD

-TV P

T1000 Service M

anual__________________________________________________________________________________________________________________

45

__________________________________________________________________________


46

__________________________________________________________________________


47

____________________________________________________________________________________________________________________________________________________


48

12

34

56

ABCD

65

43

21

D C B A

123456789101112S1

03

CON

5

L107

BEA

D

AV

_CV

BS

C115

1nF

L110

BEA

D

C111

10pF

R102

15K

AV

_L

C109

1nF

C113

1nF

L111

BEA

D

R103

15K

AV

_R

C110

1nF

C114

1nF

C116

1nF

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

21

S102

V

21

S104

L

21

S105

R

AG

ND

L R

AG

ND

L100

22uH

L101

22uH

C100

220n

F

AG

ND

C101

220n

F

AG

ND

C102

100n

F

AG

ND

C103

100n

F

AG

ND

R100

4.7R C1

0410

nF

AG

ND

R101

4.7R C1

0510

nF

AG

ND

C100

47pF

R104

75R

1

2 3

4

5 6

S106

S_V

HS

C101

47pF

R105

75R

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

781 54 32

S100

HEA

DPH

ON

E 7P

Side AV

__________________________________________________________________________


49

12

34

BCD

43

21

D C B A

12S0

01

To m

ain

pcb

C001

100n

F

R002

5.6K

1/6

WR0

032.

7K 1

/6W

R004

1.5K

1/6

WR0

0582

0R 1

/6W

R007

220R

1/6

WR0

0647

0R 1

/6W

SW02

MEN

USW

03SO

URC

ESW

04V

(-)SW

05V

(+)

SW06

P(-)

SW07

P(+)

MU

LTI B

UTT

ON

GN

D

12S0

02

To in

fra

pcb

C002

100n

F

__________________________________________________________________________


50

12

34

ABCD

43

21

D C B A

1 2 3 4

S001

INFRA REDR0

01

33R

1/4W

C001

100u

FG

ND

R003

470R

R004

15K

1/6

W

SW01

STBY

12S0

02

To mbutton pcb

C002

100n

F

IR 3

VCC 2

GND 1

IR01

IR

LED

1LE

D

Infraled

__________________________________________________________________________


51

FAULT TRACING DIAGRAM FOR POWER SUPPLY

Check 220 V AC Mains

Check C 020 Voltage

Check 5VSTBY

Check 5V_OFF

Check 24V,33V,12V8V

Check 3.3V,2.5V and 1.8V

POWER IS OK

NO

NO

NO

NO

NO

Check AC Power Cable is Plugged

Check X102 Fuse

Check T530 and PeripheralComponents

Check P_CTRL Pin

Check Related Components

StandByMode

Normal ModeCheck Components For 5V

Check Related Components for Defective Outputs

YES

YES

YES

LOW HIGHYES

NO

YES

YES

7. TROUBLESHOOTING

__________________________________________________________________________


52

8.DATA SHEETS Tuner Data Sheets

Specification

specification : PAL FST TU SEM Model No. TECH2949PS40A(D)

1. General Characteristics

1-1. Receiving System : CCIR Standard system

1-2. Channel

BAND START CH FREQ END CH FREQ

VHF Low E2 45.75 S6 140.25

VHF High S7 147.25 S36 423.25

UHF S37 431.25 E69 855.25

1-3. Intermediate Frequency

SYSTEM PICTURE COLOR SOUND

B/G 38.9 34.47 33.4

1-4. Input/Output Impedance

Input Impedance 75 Unbalanced

Output Impedance 1 Balanced

For Aymmetrical use of IF output, IF2 must be connected with 56 load to ground.

1-5. Tuning System : Frequency Synthesized Type

1-6. Band Change Over System : PLL System

1-7. Terminals for External Connection

NO TERMINAL NAME DESCRIPTION

1 AGC AGC Voltage input

2 NC No Internal connection

3 SAS Serial Address Selection

4 SCL Serial Clock Line

5 SDA Serial Data Line

6 NC No Internal connection

7 BP B+ for Internal IC

8 ADC Analog/Digital Converter input

9 BT Tuning Voltage supply

10 IF2 IF output 2

11 IF1 IF output 1

12 ANT VHF/UHF signal input

13 SUB P/J VHF/UHF signal output for PIP sub-tuner.

________________________________________________________________________________________________________________________________________________


53

specification : PAL FST TU SEM Model No. TECH2949PS40A(D)

Specification

2. Limiting Values

2-1. Environmental condition

PAR DESCRIPTION MIN TYP MAX UNIT

TS Storage Temperature -20 +80

TO Operation Temperature -15 +65

RH Relative Humidity for operation 90 %

2-2. Electrical conditions

PAR DESCRIPTION MIN TYP MAX UNIT

VB+ B+ Supply Voltage 4.75 5.0 5.5 V

IB+

B+ Supply Current (LNA OFF) 90 120

B+ Supply Current (LNA ON) 120 150

VFM 2nd Input activationg voltage 4.75 5.0 5.5 V

VAGC AGC Input Voltage 4.0 4.5 V

VT Tuning Supply voltage 30 33 35 V

VRIPPLE Permissible ripple (20 to 500 ) 5 P-P

VSCL Serial clock input Voltage (see Note1) 5.5 V

VSDA Serial data input Voltage (see Note1) 5.5 V

Note 1. I2C bus electrical requirements for operation are in 7-2.

3. Internal Semiconductors

3-1. Tuner section

PARTS MAIN SUB EQUIVALENCE

Mixer+Oscillator+PLL IC SN761672A

RF amplifier UHF BF1202 BF909 BF2030

VHF BF904 BF904WR, BF909WR

Tuning diode UHF BB555 BB179 HVU202A, 1SV214

VHF BB659C, BB689 HVU300A, HVU306A

Tuning correction diode BB555 BB179 HVU202A, 1SV214

3-2. LNA section

PARTS MAIN SUB EQUIVALENCE

Pre-amplifier NE34018 NE38018

_________________________________________________________________________________________________________________________________________________


54

CAT24WC01/02/04/08/161K/2K/4K/8K/16K-Bit Serial EEPROM

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

PIN CONFIGURATION BLOCK DIAGRAM

PIN FUNCTIONS

Pin Name Function

A0, A1, A2 Device Address Inputs

SDA Serial Data/Address

SCL Serial Clock

WP Write Protect

VCC +1.8V to +6.0V Power Supply

VSS Ground

DIP Package (P, L)

24WCXX F03

SOIC Package (J, W)

5020 FHD F01

FEATURES

■ 400 KHz I2C Bus Compatible*

■ 1.8 to 6.0Volt Operation

■ Low Power CMOS Technology

■ Write Protect Feature— Entire Array Protected When WP at VIH

■ Page Write Buffer

■ Self-Timed Write Cycle with Auto-Clear

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ 8-pin DIP, 8-pin SOIC or 8 pin TSSOP

(Also available in new Lead-Free packages)

■ Commercial, Industrial, Automotive and Extended Temperature Ranges

DESCRIPTION

The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-bit Serial CMOS EEPROM internally organized as 128/256/512/1024/2048 words of 8 bits each. Catalyst’sadvanced CMOS technology substantially reduces de-vice power requirements. The the CAT24WC01/02/04/

08/16 feature a 16-byte page write buffer. The deviceoperates via the I2C bus serial interface, has a specialwrite protection feature, and is available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP.

TSSOP Package (U, Y)(MSOP and TSSOP available for CAT24WC01,CAT24WC02 and CAT24WC04 only)

DOUTACK

SENSE AMPSSHIFT REGISTERS

CONTROLLOGIC

WORD ADDRESSBUFFERS

START/STOPLOGIC

STATE COUNTERS

SLAVEADDRESSCOMPARATORS

E2PROM

VCC

EXTERNAL LOAD

COLUMNDECODERS

XDEC

DATA IN STORAGE

HIGH VOLTAGE/TIMING CONTROL

VSS

WP

SCL

A0A1A2

SDA

A2

A0A1

VSS

1

2

3

4

8

7

6

5

VCCWP

SCL

SDA

A0 VCCWP

SCL

SDA

1

2

3

4

8

7

6

5

A1A2

VSS

MSOP Package (R, Z)

8

7

6

5

VCCWP

SCL

SDA

A2

A0A1

VSS

1

2

3

4

VCC

SCL

SDA

1

2

3

4

8

7

6

5VSS

NC

NC

NC WP

__________________________________________________________________________


55

Philips Semiconductors Product specification

Quad bilateral switches 74HC4066; 74HCT4066

FEATURES

• Very low ON-resistance:

– 50 Ω (typical) at VCC = 4.5 V

– 45 Ω (typical) at VCC = 6.0 V

– 35 Ω (typical) at VCC = 9.0 V.

• Complies with JEDEC standard no. 8-1A

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 to +85 °C and −40 to +125 °C.

GENERAL DESCRIPTION

The 74HC4066 and 74HCT4066 are high-speed Si-gateCMOS devices and are pin compatible with theHEF4066B. They are specified in compliance with JEDECstandard no. 7A.

The 74HC4066 and 74HCT4066 have four independentanalog switches. Each switch has two input/output pins(pins nY or nZ) and an active HIGH enable input pin(pin nE). When pin nE = LOW the belonging analog switchis turned off.

The 74HC4066/74HCT4066 is pin compatible with the74HC4016/74HCT4066 but exhibits a much loweron-resistance. In addition, the on-resistance is relativelyconstant over the full input signal range.

QUICK REFERENCE DATAGND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC2 × fi × N + Σ[(CL + CS) × VCC

2 × fo] where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

CS = maximum switch capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ[(CL + CS) × VCC2 × fo] = sum of the outputs.

2. For 74HC4066 the condition is VI = GND to VCC.

For 74HCT4066 the condition is VI = GND to VCC − 1.5 V.

SYMBOL PARAMETER CONDITIONSTYPICAL

UNIT74HC4066 74HCT4066

tPZH/tPZL turn-on time nE to Vos CL = 15 pF; RL = 1 kΩ; VCC = 5 V 11 12 ns

tPHZ/tPLZ turn-off time nE to Vos CL = 15 pF; RL = 1 kΩ; VCC = 5 V 13 16 ns

CI input capacitance 3.5 3.5 pF

CPD power dissipationcapacitance per switch

notes 1 and 2 11 12 pF

CS maximum switchcapacitance

8 8 pF

__________________________________________________________________________


56

Philips Semiconductors Product specification

Quad bilateral switches 74HC4066; 74HCT4066

FUNCTION TABLESee note 1.

Note

1. H = HIGH voltage level.

L = LOW voltage level.

ORDERING INFORMATION

INPUT nE SWITCH

L off

H on

TYPE NUMBERPACKAGE

TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE

74HC4066N −40 to 125 °C 14 DIP14 plastic SOT27-1

74HCT4066N −40 to 125 °C 14 DIP14 plastic SOT27-1

74HC4066D −40 to 125 °C 14 SO14 plastic SOT108-1

74HCT4066D −40 to 125 °C 14 SO14 plastic SOT108-1

74HC4066DB −40 to 125 °C 14 SSOP14 plastic SOT337-1

74HCT4066DB −40 to 125 °C 14 SSOP14 plastic SOT337-1

74HC4066PW −40 to 125 °C 14 TSSOP14 plastic SOT402-1

74HCT4066PW −40 to 125 °C 14 TSSOP14 plastic SOT402-1

74HC4066BQ −40 to 125 °C 14 DHVQFN14 plastic SOT762-1

74HCT4066BQ −40 to 125 °C 14 DHVQFN14 plastic SOT762-1

PINNING

PIN SYMBOL DESCRIPTION

1 1Y independent input/output

2 1Z independent input/output



5 2E enable input (active HIGH)


7 GND ground (0 V)







14 VCC supply voltage

handbook, halfpage

MGR253

4066

1

2

3

4

5

6

7 8

14

13

12

11

10

9

1Y

1Z

2Z

2Y

2E

3E

GND 3Y

3Z

4Z

4Y

4E

1E

VCC

Fig.1 Pin configuration DIP14, SO14 and(T)SSOP14.

__________________________________________________________________________


57

October 1987

Revised April 2002

CD

4069UB

C In

verter Circu

its

CD4069UBCInverter Circuits

General DescriptionThe CD4069UB consists of six inverter circuits and is man-ufactured using complementary MOS (CMOS) to achievewide power supply operating range, low power consump-tion, high noise immunity, and symmetric controlled riseand fall times.

This device is intended for all general purpose inverterapplications where the special characteristics of theMM74C901, MM74C907, and CD4049A Hex Inverter/Buff-ers are not required. In those applications requiring largernoise immunity the MM74C14 or MM74C914 Hex SchmittTrigger is suggested.

All inputs are protected from damage due to static dis-charge by diode clamps to VDD and VSS.

Features■ Wide supply voltage range: 3.0V to 15V

■ High noise immunity: 0.45 VDD typ.

■ Low power TTL compatibility: Fan out of 2 driving 74Lor 1 driving 74LS

■ Equivalent to MM74C04

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.

Connection Diagram Schematic Diagram

Order Number Package Number Package Description

CD4069UBCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4069UBCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4069UBCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

__________________________________________________________________________


58

DATA SHEET

128M bits DDR SDRAM EDD1232AAFA (4M words × 32 bits)

Description�� !� "�� ×� � � �� ×� �� #�$��"� ��%�� %��&��'�� (��%� �� &� �� )*� �� +)*$� �� ,�%�� &�� - �� .� �� %��&��(�,% %�- ��(� ��(�/��$� � �� 0�1�2� �� &�� "� ��3� -��-��&�� %��- ��-��/�� $�4.�� 5��'�� ,(� %��-�.�6�(#��6��%�0�662�(��-�� -�$�7�� %�(#�� ,% ��%-�� (�61�8�%�(#��$�

Features• 8�"��/%%-.9��:��1�;�$�:�±��$:�� 9��:��;�$�:�±��$:�

• ��9��%�+!!��%��0'�5$2�• ��/�-��(� ��(�/��<��"��&��%��(-�(#�(.(-��

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• �� %/��/�%/��.�(�� " ��1��

• �� -��#��&��(��(/��%�� • �1�� - ��" ��&��<�(��- ��" ��&��=�7��

• �� &&�� -�(-�(#� �%/��0)*��+)*2�• ��66��- ��1��1�� " ��)*��

• �)�''��(��%�� 3��)*��<��'��#��&��(��&��1��

• ��'��#�0��2�&��"� ��• �/��%��(��%� ��&��(��/��((��• ��6>�(�'%�� -��7+?�• 8��''��-��/��-��04629��• 8��''��-��+)��-��(.�0)629��$��• 8��''��-��/�%/�� 3��9��-&+"��#�• ��&��(.(-��9��@!��&��(.(-��+'��⎯ $�μ��'�5 '/'��3��%�� (��&�� 3�-�• �3�� &��&��⎯ �/��&��⎯ ��-&��&��• 61�8�%�(#��" ��-��&��-��0��,4 2�⎯ ��A��(�'%- ��

__________________________________________________________________________


59

EDD1232AAFA

Pin Configurations ��

A7A6A5A4VSSA9NCNCNCNCNCNCNCA11A10VDDA3A2A1A0

5049484746454443424140393837363534333231

DQ29VSSQDQ30DQ31

VSSVDDQ

NCNCNC

VSSQNC

DQSVDDQ

VDDDQ0DQ1

VSSQDQ2

81828384858687888990919293949596979899100

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

100-pin plastic LQFP

(Top view)

DQ

28V

DD

QD

Q27

DQ

25D

Q24

VD

DQ

DQ

15

DQ

13D

Q12

DQ

10V

SS

Q

VD

DQ

VR

EF

DM

3D

M1

CK

EM

CL

A8

(AP

)

DQ

26V

SS

Q

DQ

14

VS

SQ

DQ

9

DQ

8

CK

/CK

VS

S

DQ

11

VD

DQ

VD

D

DQ

3V

DD

QD

Q4

DQ

6D

Q7

VD

DQ

DQ

16

DQ

18D

Q19

DQ

21V

SS

Q

VD

DQ

DM

0D

M2

/WE

/CS

BA

0B

A1

DQ

5V

SS

Q

DQ

17

VS

SQ

DQ

22

DQ

23

/CA

S

/RA

S

VD

D

DQ

20

VD

DQ

VS

S

NC

NC20 × 14mm2

0.65mm pin pitch

��

��

�� !�""��

!#��!#$�� !%�� &� ��'��

!#(� )��'�� *+&�� )��"��

��(� �,�� *!!� ��"��

�+�(� +��'�� *((� -��"��

��(� ��'�� *!!#� ��"��!#��

�.&� .��'�� *((#� -��"��!#��

!/��!/$� )�� /�0� /��'��,�*((�

1�� 1��

�

__________________________________________________________________________


60

EN29LV040

da0.

FEATURES

Single power supply operation - Full voltage range: 2.7-3.6 volt read and write operations for battery-powered applications. - Regulated voltage range: 3.0-3.6 volt read and write operations for high performance 3.3 volt microprocessors.

High performance - Access times as fast as 45 ns

Low power consumption (typical values at 5 MHz)

- 7 mA typical active read current - 15 mA typical program/erase current - 1 A typical standby current (standard access time to active mode)

Flexible Sector Architecture: - Eight 64 Kbyte sectors - Supports full chip erase - Individual sector erase supported - Sector protection and unprotection: Hardware locking of sectors to prevent

program or erase operations within individual sectors

High performance program/erase speed - Byte/Word program time: 8μs typical - Sector erase time: 500ms typical

JEDEC Standard program and erase commands

JEDEC standard DATA polling and toggle bits feature

Single Sector and Chip Erase

Embedded Erase and Program Algorithms

Erase Suspend / Resume modes: Read or program another Sector during Erase Suspend Mode

triple-metal double-poly triple-well CMOS Flash Technology

Low Vcc write inhibit < 2.5V

>100K program/erase endurance cycle

Package options - 8mm x 20mm 32-pin TSOP (Type 1) - 8mm x 14mm 32-pin TSOP (Type 1) - 32-pin PLCC

Commercial and industrial Temperature Range

GENERAL DESCRIPTION

The EN29LV040 is a 4-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 524,288 bytes. Any byte can be programmed typically in 8μs. The EN29LV040 features 3.0V voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems.

The EN29LV040 has separate Output Enable ( OE), Chip Enable (CE ), and Write Enable (WE) controls, which eliminate bus contention issues. This device is designed to allow either singleSector or full chip erase operation, where each Sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.

EN29LV0404 Megabit (512K x 8-bit ) Uniform Sector, CMOS 3.0 Volt-only Flash Memory

__________________________________________________________________________


61

EN29LV040CONNECTION DIAGRAMS

TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAM

Pin Name Function A0-A18 Addresses

DQ0-DQ7 8 Data Inputs/Outputs

WE# Write Enable

CE# Chip Enable

OE# Output Enable

Vcc Supply Voltage

Vss Ground

EN29LV040

DQ0 – DQ7A0 - A18

WE#

CE#

OE#

__________________________________________________________________________


62

August 1998

FDC6326LIntegrated Load Switch

General Description Features

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter FDC6326L Units

VIN Input Voltage Range 3 - 20 V

VON/OFF On/Off Voltage Range 2.5 - 8 V

I L Load Current - Continuous (Note 1) 1.8 A

- Pulsed (Note 1 & 3) 5

PD Maximum Power Dissipation (Note 2) 0.7 W

TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C

ESD Electrostatic Discharge Rating MIL-STD-883D Human BodyModel (100pf/1500Ohm)

6 kV

THERMAL CHARACTERISTICS

RθJA Thermal Resistance, Junction-to-Ambient (Note 2) 180 °C/W

RθJC Thermal Resistance, Junction-to-Case (Note 2) 60 °C/W

This device is particularly suited for compact powermanagement in portable electronic equipment where 3V to20V input and 1.8A output current capability are needed.This load switch integrates a small N-Channel powerMOSFET (Q1) which drives a large P-Channel powerMOSFET (Q2) in one tiny SuperSOTTM-6 package.

VDROP=0.20V @ VIN=12V, IL=1.5A.RDS(ON) = 0.125 ΩVDROP=0.20V @ VIN=5V, IL=1A.RDS(ON) = 0.20 Ω.

SuperSOTTM-6 package design using copper lead frame forsuperior thermal and electrical capabilities.

I N O U T

O N / O F F

E Q U I V A L E N T C I R C U I T

V D R O P+ -

SOT-23 SuperSOTTM-8 SOIC-16SO-8 SOT-223SuperSOTTM-6

SuperSOT -6TM

.326

pin 1

See Appl icat ion Ci rcui t

1

5

6

3

2

Vin ,R1 Vout ,C1

R2

O N / O F F

R1,C1

Q 2

Q 1

Vout ,C1

4

__________________________________________________________________________


63

TECHNICAL DATA

Features Adjustable and Fixed of 1.25, 1.5, 1.8, 2.5, 2.85, 3.3, 5.0V Space saving SMD types of SOT-223 1.2V Drop-out Voltage 1.0A Output Current Line Regulation Typically at 0.2% max Current Limiting and Thermal Protection

General DescriptionThe IL1117A is a series of low dropout voltage regulators which can provideup to 1A of output current. The IL1117A is available in seven fixed voltage,1.25, 1.5, 1.8, 2.5, 2.85, 3.3 and 5.0V. Additonally it is also available inadjustable version. On chip precision trimming adjusts the reference/output voltage to within ± 2%. Current limit is also trimmed to ensurespecified output current and controlled short-circuit current.The IL1117A series is available in SOT-223 packages.A minimum of 10uF tantalum capacitor is required at the output toimprove the transient response and stability.

Applications Post Regulator for switching DC/DC Converter High Efficiency Linear Regulator Battery Chargers PC Add on Card Motherboard clock supplies LCD Monitor Set-top Box

Absolute Maximum Ratings Maximum Input Voltage ~ 15.0V Operating Junction Temperature Range -25 ~ 125 Storage Temperature Range -50 ~ 150

1.0A Low Dropout Positive Voltage Regulator

IL1117A-x

IL1117A-x

__________________________________________________________________________


64

TECHNICAL DATA

Electrical Characteristics(Vin = 5V, Co = 10uF, Ta = 25 , unless otherwise specified)

IL1117A-x

__________________________________________________________________________


65

MST6181LDASXGA/WXGA LCD Multi-Function Monitor Controller with Dual LVDS Transmitter

Preliminary Data Sheet Version 0.2

FEATURES� Input supports up to UXGA & 1080P� Panel supports up to SXGA/WXGA� Integrated 8-bit triple-ADC/PLL� Integrated DVI/HDCP/HDMI compliant receiver� RGB/YUV 444 and YUV422 digital video input

ports� Dual high-quality scaling engines� Built-in 3-D video de-interlacer� Video-over-graphic PIP� Video-by-graphic split screen� MStarACE-2 picture/color processing engine� Embedded On-screen display controller (OSD)

engine� Digital audio I/O & sync processor� Built-in dual-link LVDS transmitter� 5 Volt tolerant inputs� Low EMI and power saving features� Supports PWM & GPO controls� 256-pin LQFP� Analog RGB Compliant Input Ports

� Dual analog ports support up to 165Mhz� Supports PC RGB input up to UXGA@60Hz� Supports HDTV RGB/YPbPr/YCbCr up to 1080P� On-chip high-performance PLLs� Supports Composite Sync and SOG

(Sync-on-Green) separator� Automatic color calibration

� DVI/HDCP/HDMI Compliant Input Port� Operates up to 165 MHz (up to UXGA @60Hz)� Single link on-chip DVI 1.0 compliant receiver� High-bandwidth Digital Content Protection

(HDCP) 1.1 compliant receiver� High Definition Multimedia Interface (HDMI)

1.0 compliant receiver with I2S and S/PDIFdigital audio outputs

� Long-cable tolerant robust receiving� Video Input Port

� One RGB/YUV 4:4:4 24-bit and one 4:2:2ITU656 8-bit digital video input ports

� 24-bit port supports 8/16-bit YUV 4:2:2 or 24-bit RGB/YUV 4:4:4 interlaced/ progressivevideo input up to 1080i/720P

� Auto-Configuration/Auto-Detection� Auto input signal format (SOG, Composite,

Separated HSYNC, VSYNC, and DE), and inputmode (all VESA & IBM modes w/ resolutionand polarity) detection

� Auto-tuning function including phasing,positioning, offset, gain, and jitter detection

� Sync Detection for H/V Sync� Dual High-Performance Scaling Engine

� Fully Programmable shrink/zoom capabilities� Nonlinear video scaling supports various

modes including Panorama� Flexible independent control of sharpness for

TV and graphic windows� Video Processing & Conversion

� 3-D motion adaptive video de-interlacer withupgraded edge-oriented adaptive algorithm forsmooth low-angle edges

� Automatic 3:2 pull-down & 2:2 pull-downdetection and recovery

� PIP with programmable size and location,supports multi-video applications

� Video-over-graphic overlay� Video-by-graphic split screen� Frame rate conversion for both main window

and sub window� MStar 2nd Generation Advanced Color Engine

(MStarACE-2) automatic picture enhancementgives:� Brilliant and fresh color� Intensified contrast and details� Vivid skin tone� Sharp edge� Enhanced depth of field perception� Accurate and independent color control

� Independent picture control for main and subwindows

� sRGB compliance allows end-user toexperience the same colors as viewed on CRTsand other displays

� Programmable 10-bit RGB gamma CLUT� 3-D video noise reduction

__________________________________________________________________________


66



� On-Screen OSD Controller� 16/256 color palette� 256/512 1-bit/pixel font� 128/256/512 4-bit/pixel font� Supports texture function� Supports 4K attribute/code� Horizontal and vertical stretch of OSD menus� Supports button function� Pattern generator for production test� Supports OSD MUX and alpha blending

capability� Supports blinking and scrolling for closed

caption applications� LVDS Panel Interface

� Supports dual link up to 135MHz dot clock forSXGA

� Supports 2 data output formats: Thine & TIdata mappings

� Compatible with TIA/EIA� With 6/8 bits options� Reduced swing for LVDS for low EMI� Supports flexible spread spectrum frequency

with 360Hz~11.8MHz and up to 25%modulation

� External Connection/Component� Support 8051 parallel MCU bus� Supports 4-wire double-data-rate direct MCU

bus� 32-bit data bus for external frame buffer (SDR

or DDR DRAM)� All system clocks synthesized from a single

external clock

GENERAL DESCRIPTIONThe MST6181LDA is a high performance and fully integrated graphics processing IC solution for multi-functionLCD monitor/TV with resolutions up to SXGA/WXGA. It is configured with an integrated triple-ADC/PLL, anintegrated DVI/HDCP/HDMI receiver, a video de-interlacer, two high quality scaling engines, an on-screendisplay controller, and a built-in output clock generator. By use of external frame buffer, PIP is provided formultimedia applications. It supports de-interlaced full-screen video, video-on-graphic overlay, split screen,frame rate conversion, and aspect ratio conversion for various video sources. To further reduce system costs,the MST6181LDA also integrates intelligent power management control capability for green-mode requirementsand spread-spectrum support for EMI management.

__________________________________________________________________________


67



PIN DIAGRAM (MST6181LDA)

Pin 1

1314

17

18

21

23

25

27

28

30

32

34

36

39

41

43

15

16

19

20

22

24

26

29

31

33

35

37

38

40

42

44

45

46

47

48

50

51

52

49

GNDDVI_R+DVI_R-

GNDDVI_G+DVI_G-

AVDD_DVI

GND

DVI_CK-

REXT

GND

DDCD_CK

AVDD_ADC

VSYNC1BIN1P

DVI_B+DVI_B-

DVI_CK+

AVDD_DVI

AVDD_PLL

DDCD_DA

GND

HSYNC1

BIN1MSOGIN1

GIN1PGIN1MRIN1PRIN1MBIN0MBIN0PGIN0MGIN0P

SOGIN0RIN0MRIN0P

AVDD_ADCGND

HSYNC0VSYNC0

RMIDREFPREFMGNDGND

VDDPVI_DATA[16]VI_DATA[17]VI_DATA[18]VI_DATA[19]

12

3

4

5

7

9

11

6

8

10

12

53

5455

56

57

59

61

63

58

60

62

64

VI_DATA[22]VI_DATA[23]VI_DATA[8]VI_DATA[9]

VI_DATA[10]VI_DATA[11]VI_DATA[12]VI_DATA[13]AVDD_APLL

GNDVI_DATA[14]

77 78 81 82 85 87 89 91 92 94 96 98 100

103

105

107

79 80 83 84 86 88 90 93 95 97 99 101

102

104

106

108

109

110

111

112

114

115

116

113

VI_C

KAVI

_DAT

A[0]

VI_D

ATA[

1]VI

_DAT

A[0]

VI_D

ATA[

3]VI

_DAT

A[4]

VI_D

ATA[

5]VI

_DAT

A[6]

GN

D

VDD

P

INT

RD

Z

DBU

S[0]

DBU

S[2]

DBU

S[3]

VI_D

ATA[

7]VD

DC

GN

D

HW

RES

ET ALE

WR

Z

DBU

S[1]

DBU

S[4]

DBU

S[5]

DBU

S[6]

DBU

S[7]

DD

CR_C

KD

VSYN

CFI

ELD

VDD

CG

ND

DQ

S[3]

MD

ATA[

31]

MD

ATA[

30]

MD

ATA[

29]

MD

ATA[

28]

VDD

MG

ND

MD

ATA[

27]

MD

ATA[

26]

MD

ATA[

25]

MD

ATA[

24]

MD

ATA[

23]

MD

ATA[

22]

MD

ATA[

21]

MD

ATA[

20]

65 66 67 68 69 71 73 7570 72 74 76 117

118

119

120

121

123

125

127

122

124

126

128

MD

ATA[

19]

MD

ATA[

18]

MD

ATA[

17]

MD

ATA[

16]

DQ

S[2]

DQ

M[1

]

MCL

KZ

MVR

EFM

CLKE

MCL

K

180179

176

175

172

170

168

166

165

163

161

159

157

154

152

150

178

177

174

173

171

169

167

164

162

160

158

156

155

153

151

149

148

147

146

145

143

142

141

144

GND

DQS[0]

MDATA[1]

MDATA[3]

MDATA[5]

MDATA[7]MDATA[8]

VDDM

MDATA[0]

MDATA[2]

MDATA[4]

MDATA[6]

MDATA[9]MDATA[10]MDATA[11]GNDVDDMMDATA[12]MDATA[13]MDATA[14]MDATA[15]DQS[1]DQM[0]GNDVDDCMADR[11]MADR[10]MADR[9]MADR[8]GNDVDDMMADR[7]MADR[6]MADR[5]MADR[4]MADR[3]MADR[2]MADR[1]

192191

190

189

188

186

184

182

187

185

183

181

140

139138

137

136

134

132

130

135

133

131

129

MADR[0]WEZCASZGNDVDDMRASZBADR[0]BADR[1]AVDD_PLL2

244

243

240

239

236

234

232

230

229

227

225

223

221

218

216

214

242

241

238

237

235

233

231

228

226

224

222

220

219

217

215

213

212

211

210

209

207

206

205

208

AVD

D_M

PLL

XIN

XOU

TPW

M1

PWM

0

AIW

SAI

SCK

AISD

AIM

CK

256

255

254

253

252

250

248

246

251

249

247

245

204

203

202

201

200

198

196

194

199

197

195

193

MST6181LD

AXXXXXXXXXXXXXXXX

DE

VI_DATA[20]VI_DATA[21]

GND

GN

D

VDD

MG

ND

PWM

2D

DCR

_DA

BYPASS

PWM5PWM4PWM3

NC

VDDPGNDGNDVDDC

LVB0

MLV

B0P

VDD

CG

ND

GN

DVD

DP

LVB1

MLV

B1P

LVB2

MLV

B2P

LVBC

KMLV

BCKP

LVB3

MLV

B3P

VDD

CG

ND

LVA0

MLV

A0P

LVA1

MLV

A1P

LVA2

MLV

A2P

LVAC

KMLV

ACKP

GN

DVD

DP

LVA3

MLV

A3P

NC

NC

GN

D

NC

NCGN

D

VDD

P

VDD

C

BUST

YPE

GN

D

VI_C

KB

GPO[6]GPO[5]GPO[4]

GPO[3]GPO[2]GPO[1]GPO[0]

VI_D

ATA[

31]

NC

NC

NC

DH

SYN

CVI

_DAT

A[15

]

VI_D

ATA[

30]

VI_D

ATA[

29]

VI_D

ATA[

28]

VI_D

ATA[

27]

VI_D

ATA[

26]

VI_D

ATA[

25]

VI_D

ATA[

24]

SPD

IFO

AUM

UTE

AUW

SAU

SCK

AUSD

AUM

CK

__________________________________________________________________________


68



PIN DESCRIPTIONMCU Interface

Pin Name Pin Type Function Pin

HWRESET Schmitt Trigger Inputw/ 5V-tolerant

Hardware Reset, active high 81

DBUS[7:0] I/O w/ 5V-tolerant MCU Direct bus; 4mA driving strength 93-86

ALE I w/ 5V-tolerant MCU Bus ALE, active high 83

RDZ I w/ 5V-tolerant MCU Bus RDZ, active high 84

WRZ I w/ 5V-tolerant MCU Bus WDZ, active high 85

INT Output MCU Bus Interrupt; 4mA driving strength 82

BUSTYPE Input (not 5V-tolerant) MCU bus type selection� Low (0V): 4-bit (DBUS[3:0]) DDR Direct Bus� High (3.3V): 8-bit (DBUS[7:0]) Direct Bus

240

Analog Interface


RMID Mid-Scale Voltage Bypass 42

REFP Internal ADC Top De-coupling Pin 43

REFM Internal ADC Bottom De-coupling Pin 44

REXT Analog Input External Resister 390 ohm to AVDD_DVI 15

HSYNC0 Schmitt Trigger Inputw/ 5V-tolerant

Analog HSYNC Input from Channel 0 40

VSYNC0 Schmitt Trigger Inputw/ 5V-tolerant

Analog VSYNC Input from Channel 0 41

BIN0M Analog Input Reference Ground for Analog Blue Input from Channel 0 31

BIN0P Analog Input Analog Blue Input from Channel 0 32

GIN0M Analog Input Reference Ground for Analog Green Input from Channel 0 33

GIN0P Analog Input Analog Green Input from Channel 0 34

SOGIN0 Analog Input Sync On Green Input from Channel 0 35

RIN0M Analog Input Reference Ground for Analog Red Input from Channel 0 36

RIN0P Analog Input Analog Red Input from Channel 0 37

HSYNC1 Schmitt Trigger Inputw/ 5V-tolerant

Analog HSYNC Input from Channel 1 22

VSYNC1 Schmitt Trigger Inputw/ 5V-tolerant

Analog VSYNC Input from Channel 1 23

BIN1M Analog Input Reference Ground for Analog Blue Input from Channel 1 25

__________________________________________________________________________


69




BIN1P Analog Input Analog Blue Input from Channel 1 24

SOGIN1 Analog Input Sync On Green Input from Channel 1 26

GIN1M Analog Input Reference Ground for Analog Green Input from Channel 1 28

GIN1P Analog Input Analog Green Input from Channel 1 27

RIN1M Analog Input Reference Ground for Analog Red Input from Channel 1 30

RIN1P Analog Input Analog Red Input from Channel 1 29

DVI/HDMI Interface


DVI_R+ Input DVI/HDMI Input Channel Red + 3

DVI_R- Input DVI/HDMI Input Channel Red - 4

DVI_G+ Input DVI/HDMI Input Channel Green + 6

DVI_G- Input DVI/HDMI Input Channel Green - 7

DVI_B+ Input DVI/HDMI Input Channel Blue + 9

DVI_B- Input DVI/HDMI Input Channel Blue - 10

DVI_CK+ Input DVI/HDMI Input Clock + 12

DVI_CK- Input DVI/HDMI Input Clock - 13

Video Interface


VI_CKA Input w/ 5V-tolerant Digital Video Input Clock for VI_DATA[23:0] 68

VI_CKB Input w/ 5V-tolerant Digital Video Input Clock for VI_DATA[31:24] 251

VI_DATA[23:0] Input w/ 5V-tolerant Digital Video Input Data[23:0] 55-48, 65, 64,61-56, 76-69

VI_DATA[31:24] Input Digital Video Input Data[31:24] 244-241, 237-234

FIELD Input w/ 5V-tolerant FIELD Input 96

DVSYNC Input w/ 5V-tolerant Digital VSYNC Input 95

DHSYNC Input w/ 5V-tolerant Digital HSYNC Input 66

DE Input w/ 5V-tolerant DE Input 67

Digital Audio Interface


AUMCK Output Audio Master Clock Output 228

AUSD Output Audio Serial Data Output; 4mA driving strength 229

AUSCK Output Audio Serial Clock Output; 4mA driving strength 230__________________________________________________________________________


70




AUWS Output Word Select Output; 4mA driving strength 231

AUMUTE Output Audio Output Mute Control 232

SPDIFO Output S/PDIF Audio Output; 4mA driving strength 233

AIMCK Input w/ 5V-tolerant Audio Master Clock Input 247

AISD Input w/ 5V-tolerant Audio Serial Data Input 248

AISCK Input w/ 5V-tolerant Audio Serial Clock Input 249

AIWS Input w/ 5V-tolerant Word Select Input 250

LVDS Interface


LVA0M Output A-Link Negative LVDS Differential Data Output 211

LVA0P Output A-Link Positive LVDS Differential Data Output 210







LVACKM Output A-Link Negative LVDS Differential Data Output 205

LVACKP Output A-Link Positive LVDS Differential Data Output 204

LVB0M Output B-Link Negative LVDS Differential Data Output 227

LVB0P Output B-Link Positive LVDS Differential Data Output 226







LVBCKM Output B-Link Negative LVDS Differential Data Output 217

LVBCKP Output B-Link Positive LVDS Differential Data Output 216

__________________________________________________________________________


71



GPO Interface


PWM0 Output PWM; 4mA driving strength 252



PWM3/GPO[7] Output GPO with PWM Function; 6mA driving strength 188



GPO[6:0] Output GPO; 6mA driving strength 186-184,179-176

DRAM Interface


MVREF Input Reference Voltage for DDR SDRAM Interface 124

MCLKE Output DRAM Memory Clock Enable 125

MCLKZ Output DRAM Memory Clock Complementary / Input(for differential clocks)

126

MCLK Output DRAM Memory Clock 127

RASZ Output Row Address Strobe, active low 132

CASZ Output Column Address Strobe, active low 135

WEZ Output Write Enable, active low 136

DQM[1:0] Output Data Mask Byte Enable 121, 153

DQS[3:0] Output Data Strobe 101, 120, 154, 173

BADR[1:0] Output Memory Bank Address 130, 131

MADR[11:0] Output Memory Address 150-147, 144-137

MDATA[31:0] I/O Memory Data 102-105, 108-119,155-158, 161-172

Misc. Interface


DDCD_DA I/O w/ 5V-tolerant HDCP Serial Bus Data / DDC Data of DVI Port; 4mA drivingstrength

18

DDCD_CK Input w/ 5V-tolerant HDCP Serial Bus Data / DDC Clock of DVI Port 19

DDCR_CK Input w/ 5V-tolerant DDC Clock for ROM 94

DDCR_DA I/O w/ 5V-tolerant DDC Data for ROM 97

BYPASS For External Bypass Capacitor 192

__________________________________________________________________________


72




XIN Crystal Oscillator Input Xin 255

XOUT Crystal Oscillator Output Xout 254

Power Pins


AVDD_DVI 3.3V Power DVI/HDMI Power 8, 14

AVDD_ADC 3.3V Power ADC Power 21, 38

AVDD_PLL 3.3V Power PLL Power 16

AVDD_PLL2 3.3V Power PLL Power 129

AVDD_APLL 1.8V Power Audio PLL Power 62

AVDD_MPLL 3.3V Power PLL Power 256

VDDM 3.3V Power (SDRAM) /2.5V Power (DDR)

Memory Interface Power 106, 122, 133, 145, 159,174

VDDP 3.3V Power Digital Output Power 47, 80, 183, 202, 222,238

VDDC 1.8V Power Digital Core Power 77, 99, 151, 180, 213,225, 246

GND Ground Ground 1, 2, 5, 11, 17, 20, 39,45, 46, 63, 78, 79, 100,107, 123, 128, 134, 146,152, 160, 175, 181, 182,193, 203, 212, 223, 224,239, 245

No Connects


NC No connect. Leave these pins floating. 187, 191, 194-199

__________________________________________________________________________


73



ELECTRICAL SPECIFICATIONS

Analog Interface CharacteristicsParameter Min Typ Max Unit

Resolution 8 Bits

DC ACCURACY

Differential Nonlinearity ±0.5 +1.50/-1.0 LSB

Integral Nonlinearity ±1 LSB

No Missing Codes Guaranteed

ANALOG INPUT

Input Voltage Range

Minimum 0.5 V p-p

Maximum 1.0 V p-p

Input Bias Current 1 uA

Input Full-Scale Matching 1.5 %FS

Brightness Level Adjustment 62 %FS

SWITCHING PERFORMANCE

Maximum Conversion Rate 165 MSPS

Minimum Conversion Rate 12 MSPS

HSYNC Input Frequency 15 200 kHz

PLL Clock Rate 12 165 MHz

PLL Jitter 500 ps p-p

Sampling Phase Tempco TBD ps/°C

DIGITAL INPUTS

Input Voltage, High (VIH) 2.5 V

Input Voltage, Low (VIL) 0.8 V

Input Current, High (IIH) -1.0 uA

Input Current, Low (IIL) 1.0 uA

Input Capacitance 5 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) VDDP-0.1 V

Output Voltage, Low (VOL) 0.1 V

Duty Cycle

DCK, /DCK 45 50 55 %

Output Coding Binary

DYNAMIC PERFORMANCE

Analog Bandwidth, Full Power 250 MHz

Channel to Channel Matching 0.5% Full-Scale

Specifications subject to change without notice.

__________________________________________________________________________


74



Absolute Maximum Ratings

Parameter Symbol Min Typ Max Units

3.3V Supply Voltages VVDD_33 -0.3 3.6 V



Input Voltage (5V tolerant inputs) VIN5Vtol -0.3 5.0 V

Input Voltage (non 5V tolerant inputs) VIN -0.3 VVDD_33 V

Ambient Operating Temperature TA 0 70 °C

Storage Temperature TSTG -40 150 °C

Junction Temperature TJ 150 °C

Thermal Resistance (Junction to Air) NaturalConversion

θJA 18 °C/W

Thermal Resistance (Junction to Case) NaturalConversion

θJC 1.2 °C/W

Note: Stress above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is astress rating only; functional operation of the device at these or any other conditions outside of those indicated in theoperation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods mayaffect device reliability.

ORDERING GUIDEModel Temperature

Range

Package

Description

Package

Option

MST6181LDA 0°C to +70°C LQFP 256

MST6181LDA-LF 0°C to +70°C LQFP 256

Note: Product suffix “LF” represents lead-free version.

MARKING INFORMATIONMST6181LDA

Operation Code BDate Code (YYWW)

Lot NumberOperation Code A

Part Number

DISCLAIMERMSTAR SEMICONDUCTOR RESERVES THERIGHT TO MAKE CHANGES WITHOUTFURTHER NOTICE TO ANY PRODUCTS HEREINTO IMPROVE RELIABILITY, FUNCTION ORDESIGN. NO RESPONSIBILITY IS ASSUMEDBY MSTAR SEMICONDUCTOR ARISING OUT OFTHE APPLICATION OR USER OF ANY PRODUCTOR CIRCUIT DESCRIBED HEREIN; NEITHERDOES IT CONVEY ANY LICENSE UNDER ITSPATENT RIGHTS, NOR THE RIGHTS OFOTHERS.

REVISION HISTORYDocument Description Date

MST6181LDA_ds_v01 � Initial release Jul 2005

MST6181LDA_ds_v02 � Updated Features / On-Screen OSD Controller� Updated Register Table

Aug 2005

Electrostatic charges accumulate on both test equipment and human body and can dischargewithout detection. MST6181LDA comes with ESD protection circuitry; however, the device may bepermanently damaged when subjected to high energy discharges. The device should be handledwith proper ESD precautions to prevent malfunction and performance degradation.

__________________________________________________________________________


75

MTV512M

8051 Embedded Monitor Controller with 64K Flash ROM GENERAL DESCRIPTIONS

The MTV512M micro-controller is an 8051 CPU core embedded device especially tailored for flat panel display applications. It includes an 8051 CPU core, 768-byte SRAM, 4 channels of 6-bit ADC, 3 external counters/timers, 6 channels of PWM DAC, VESA DDC interface, and a 64K-byte internal program Flash-ROM memory.

FEATURES• 8051 core, CPU operating frequency up to 24MHz • 3.3V power supply • 768-byte RAM; 64K-byte program Flash memory • Maximum 6 channels of PWM DAC • Compliant with VESA DDC1/2B/2Bi/2B+/CI

standard

• Watchdog timer with programmable interval • Support external counters/timers, T0, T1, and ET2 • Single/double frequency clock output • Two clock output ports • Two external interrupts, INT1 is shared with Slave

IIC interrupt source • Maximum 4 channels of 6-bit ADC • Flash-ROM code protection selection • Hardware ISP (In System Programming), no Boot

Code required • Embedded Dual Ports DDCRAM (128-byte x 2) • 40-pin PDIP, 42-pin SDIP, or 44-pin PLCC/QFP

package • Green products like Pb-Free Packages or All

Green Packages available

BLOCK DIAGRAM

**This datasheet is the confidential information of MYSON CENTURY, INC. and is subject to various privileges against unauthorized disclosure. Recipient shall not disclose this confidential information to any other person, nor shall one use the confidential information for the purpose of competing with MYSON CENTURY, INC.

P0.0-7

P2.0-3RDWRALEINT18051

CORE

P1.0-7

P3.0-3.4

RSTX1X2

ADCAD0-3

PWM DACDA0-5

XFR

P0.0-7

P2.0-7RDWRALEINT1

AUXRAM & DDCRAM1 & DDCRAM2

DDC & IIC INTERFACE

HSCL1HSDA1HSCL2HSDA2

P6.0-7

P5.0-6

AUXI/O

P7.6-7

CKO

__________________________________________________________________________


76

MTV512M

PIN CONNECTION DIAGRAMS

DA0/P5.0DA1/P5.1DA2/P5.2DA3/P5.3DA4/P5.4DA5/P5.5

P5.6/HSCL2P5.7/HSDA2

RSTHSCL1/P3.0/RXDHSDA1/P3.1/TXD

P3.2/INT0P3.3/INT1

P3.4/T0P3.5/T1

P7.6/CLKO2P7.7

X2X1

VSS

VCCP1.0/ET2P1.1P1.2P1.3P1.4P1.5P1.6P1.7NCNCVSYNCP6.7P6.6/CLKO1P6.5P6.4P6.3/AD3P6.2/AD2P6.1/AD1P6.0/AD0

4039383736353433323130292827262524232221

123456789

1011121314151617181920

MTV

512M

N 4

0-pi

n PD

IP

424140393837363534333231302928272625242322

123456789

101112131415161718192021

MTV

512M

S 4

2-pi

n SD

IP

NCDA0/P5.0DA1/P5.1DA2/P5.2DA3/P5.3DA4/P5.4DA5/P5.5

P5.6/HSCL2P5.7/HSDA2

RSTHSCL1/P3.0/RXDHSDA1/P3.1/TXD

P3.2/INT0P3.3/INT1

P3.4/T0P3.5/T1

P7.6/CLKO2P7.7

X2X1

VSS

VCCP1.0/ET2P1.1P1.2P1.3P1.4P1.5P1.6P1.7NCNCNCVSYNCP6.7P6.6/CLKO1P6.5P6.4P6.3/AD3P6.2/AD2P6.1/AD1P6.4/AD0

__________________________________________________________________________


77

MTV512M

VC

C

P6.2/A

D2

P6.3/A

D3

P6.4

P7.7

DA

4/P5.4

DA

3/P5.3

P1.0/E

T2

DA

2/P5.2

DA

1/P5.1

DA

0/P5.0N

C

P1.1

P1.2

P1.3

MTV512MF44-pinQFP

123456789

1011

3332313029282726252423

P6.0/A

D0

18P

6.1/AD

1

NC

P7.6/C

LKO

2

X2

X1

VS

S17161514 22212019

44 43 42 41 40 39 38 37 36 35 34

1312

DA5/ P5.5P5.6/HSCL2

RSTHSCL1/RXD/P3.0

NCHSDA1/TXD/P3.1

P3.2/INT0P3.3/INT1

P3.4/T0P3.5/T1

P5.7/HSDA2

P6.6/CLKO1P6.5

P6.7VSYNC

P1.4P1.5P1.6

NC

P1.7

NC

NC

VC

C

NCP

6.2/AD

2P

6.3/AD

3P

6.4

DA

4/P5.4

DA

3/P5.3

P1.0/E

T2

DA

2/P5.2

DA

1/P5.1

DA

0/P5.0N

C

P1.1

P1.2

P1.3

MTV512MV44-pinPLCC

789

1011121314151617

3938373635343332313029

P6.0/A

D0

24P

6.1/AD

1

NC

P7.6/C

LKO

2

X2

X1

VS

S23222120 28272625

6 5 4 3 2 1 44 43 42 41 40

1918

DA5/P5.5P5.6/HSCL2

RSTHSCL1/RXD/P3.0

NCHSDA1/TXD/P3.1

P3.2/INT0P3.3/INT1

P3.4/T0P3.5/T1

P5.7/HSDA2

P6.6/CLKO1P6.5

P6.7VSYNC

P1.4P1.5P1.6

NC

P1.7

NC

P7.7

__________________________________________________________________________


78

www.fairchildsemi.com

Features• Low dropout voltage• Load regulation: 0.05% typical• Trimmed current limit• On-chip thermal limiting• Standard SOT-223, TO-263, and TO-252 packages• Three-terminal adjustable or fixed 2.5V, 2.85V, 3.3V, 5V

Applications• Active SCSI terminators• High efficiency linear regulators• Post regulators for switching supplies• Battery chargers• 5V to 3.3V linear regulators• Motherboard clock supplies

DescriptionThe RC1117 and RC1117-2.5, -2.85, -3.3 and -5 are low dropout three-terminal regulators with 1A output current capability. These devices have been optimized for low voltage where transient response and minimum input voltage are critical. The 2.85V version is designed specifically to be used in Active Terminators for SCSI bus.

Current limit is trimmed to ensure specified output current and controlled short-circuit current. On-chip thermal limiting provides protection against any combination of overload and ambient temperatures that would create excessive junction temperatures.

Unlike PNP type regulators where up to 10% of the output current is wasted as quiescent current, the quiescent current of the RC1117 flows into the load, increasing efficiency.

The RC1117 series regulators are available in the industry-standard SOT-223, TO-263 (D2PAK), and TO-252 (DPAK) power packages.

Typical Applications

VIN = 3.3V VIN VOUT

ADJ

1.5V at 1A

RC1117

10μF 22μFR1124Ω

R224.9Ω

VIN = 5V VIN VOUT

GND

2.85V at 1A

RC1117-2.85

10μF+ +

+ +

22μF

VOUT = VREF(1+R2/R1) + IAdj • R2

RC11171A Adjustable/Fixed Low Dropout Linear Regulator

__________________________________________________________________________


79

PRODUCT SPECIFICATION RC1117

Pin Assignments

*With package soldered to 0.5 square inch copper area over backside ground plane or internal power plane.,

ΘJA can vary from 30°C/W to more than 50°C/W. Other mounting techniques may provide better thermal resistance than 30°C/W.

Absolute Maximum Ratings

Parameter Min. Max. Unit

VIN 7.5 V

Operating Junction Temperature Range 0 125

°CStorage Temperature Range -65 150

°CLead Temperature (Soldering, 10 sec.) 300

°C

Front View

4-Lead Plastic SOT-223ΘJC = 15°C/W*

3-Lead Plastic TO-252ΘJC = 3°C/W*

Tab isVOUT

Tab isVOUT

1

ADJ/GND

IN

2 3

3-Lead Plastic TO-263ΘJC = 3°C/W*

Tab isVOUT

1

ADJ/GND

INOUT

2 3

3

2

1

IN

OUT

ADJ/GND

__________________________________________________________________________


80

��SLOS407D − FEBRUARY 2003 − REVISED AUGUST 2004

��

��

FEATURES� 12-W/Ch Into an 8-Ω Load From 15-V Supply� Efficient, Class-D Operation Eliminates

Heatsinks and Reduces Power SupplyRequirements

� 32-Step DC Volume Control From −40 dB to36 dB

� Line Outputs For External HeadphoneAmplifier With Volume Control

� Regulated 5-V Supply Output for PoweringTPA6110A2

� Space-Saving, Thermally-EnhancedPowerPAD™ Packaging

� Thermal and Short-Circuit Protection

APPLICATIONS� LCD Monitors and TVs� Powered Speakers

DESCRIPTION

The TPA3004D2 is a 12-W (per channel) efficient, Class-Daudio amplifier for driving bridged-tied stereo speakers.The TPA3004D2 can drive stereo speakers as low as 4 Ω.The high efficiency of the TPA3004D2 eliminates the needfor external heatsinks when playing music.

Stereo speaker volume is controlled with a dc voltageapplied to the volume control terminal offering a range ofgain from –40 dB to 36 dB. Line outputs, for drivingexternal headphone amplifier inputs, are also dc voltagecontrolled with a range of gain from –56 dB to 20 dB.

An integrated 5-V regulated supply is provided forpowering an external headphone amplifier.

Cs

Cs10 nF

Cbs

Cs

Cs 10 nF

Cbs

PVCC PVCC

Cs

Cs10 nF

Cbs

Cs

Cs 10 nF

Cbs

PVCC PVCC

220 pF

Cosc

Rosc

Ccpl

100 nF

Cvdd

Ccpr

Crinp

Crinn

Clinn

ClinpLINP

LINN

RINN

RINP

SYSTEM CONTROL

VOL

VARDIFF

VARMAX

BS

LP

PV

CC

L

PV

CC

L

LOU

TP

LOU

TP

PG

ND

L

PG

ND

L

LOU

TN

LOU

TN

PV

CC

L

PV

CC

L

BS

LN

TPA3004D2

VCLAMPRSD

V2P5

RINP

LINN

LINP

AVDDREF

VREF

VARDIFF

VARMAX

VOLUME

REFGND

MODE

MODE_OUT

VAROUTR

VAROUTL

AVDD

AGND

COSC

ROSC

AVCC

VCLAMPL

BS

RP

PV

CC

R

PV

CC

R

RO

UT

P

RO

UT

P

PG

ND

R

PG

ND

R

RO

UT

N

RO

UT

N

PV

CC

R

PV

CC

R

BS

RN

RINN

AVDD

AVCCC2p5

FADE

10 μF10 μF

0.1 μF 0.1 μF

1 μF

1 μF

1 μF

1 μF

1 μF

0.1 μF 0.1 μF

10 μF 10 μF

1 μF

120 kΩ

1 μF

10kΩ 10

kΩ

Cs0.1 μF

Cvcc10 μF

MODE_OUT

RLINE_OUT

LLINE_OUT

SYSTEM CONTROL

SYSTEM CONTROL

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

PowerPAD is a trademark of Texas Instruments.


81


www.ti.com

AVAILABLE OPTIONS

TAPACKAGED DEVICE

TA 48-PIN HTQFP (PHP)(1)

−40°C to 85°C TPA3004D2PHP

(1) The PHP package is available taped and reeled. To order a taped andreeled part, add the suffix R to the part number (e.g., TPA3004D2PHPR).

PIN ASSIGNMENTS

PHP PACKAGE

(TOP VIEW)

13 14 15 16 17 18 19 20 21 22 23 24

25

26

27

28

29

30

31

32

33

34

35

36

48 47 46 45 44 43 42 41 40 39 38 37

1

2

3

4

5

6

7

8

9

10

11

12

BS

RN

PV

CC

R

PV

CC

R

RO

UT

N

RO

UT

N

PG

ND

R

PG

ND

R

RO

UT

P

RO

UT

P

PV

CC

R

PV

CC

R

BS

RP

VCLAMPR

MODE_OUT

MODE

VAROUTR

VAROUTL

FADE

COSC

ROSC

AGND

VCLAMPL

SD

RINN

RINP

V2P5

LINP

LINN

VREF

VARDIFF

VARMAX

VOLUME

REFGND

BS

LN

PV

CC

L

PV

CC

L

LOU

TN

LOU

TN

PG

ND

L

PG

ND

L

LOU

TP

LOU

TP

PV

CC

L

PV

CC

L

BS

LP

TPA3004D2

AVCC

AVDD

AVDDREF

__________________________________________________________________________


82


www.ti.com

Terminal Functions

TERMINALI/O DESCRIPTION

NO. NAMEI/O DESCRIPTION

AGND 26 − Analog ground for digital/analog cells in core

AVCC 33 − High-voltage analog power supply (8.5 V to 18 V)

AVDD 29 O 5-V Regulated output capable of 100-mA output

AVDDREF 7 O 5-V Reference output—provided for connection to adjacent VREF terminal.

BSLN 13 I/O Bootstrap I/O for left channel, negative high-side FET

BSLP 24 I/O Bootstrap I/O for left channel, positive high-side FET

BSRN 48 I/O Bootstrap I/O for right channel, negative high-side FET

BSRP 37 I/O Bootstrap I/O for right channel, positive high-side FET

COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5

FADE 30 I Input for controlling volume ramp rate. A logic low on this pin places the amplifier in fade mode. A logic high onthis pin allows a quick transition to the desired volume setting when cycling SD or during power-up.

LINN 6 I Negative differential audio input for left channel

LINP 5 I Positive differential audio input for left channel

LOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channel

LOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel

MODE 34 I Input for MODE control. A logic high on this pin places the amplifier in the variable output mode and the Class-Doutputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputsare enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used asline-level outputs for external amplifiers.

MODE_OUT 35 O Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUTpin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is intendedfor MUTE control of an external headphone amplifier. Leave unconnected when not used for headphoneamplifier control.

PGNDL 18, 19 − Power ground for left channel H-bridge

PGNDR 42, 43 − Power ground for right channel H-bridge

PVCCL 14, 15 − Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AVCC.

PVCCL 22, 23 − Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AVCC.

PVCCR 38,39 − Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AVCC.

PVCCR 46, 47 − Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AVCC.

REFGND 12 − Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DACground to this terminal.

RINP 3 I Positive differential audio input for right channel

RINN 2 I Negative differential audio input for right channel

ROSC 27 I/O Current setting resistor for ramp generator. Nominally equal to 1/8*VCC

ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channel

ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel

SD 1 I Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.

VARDIFF 9 I DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to GND orAVDDREF if VAROUT outputs are unconnected.

VARMAX 10 I DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDDREF if VAROUToutputs are unconnected.

VAROUTL 31 O Variable output for left channel audio. Line level output for driving external HP amplifier.

__________________________________________________________________________


83


www.ti.com

Terminal Functions (Continued)


NO. NAMEI/O DESCRIPTION

VAROUTR 32 O Variable output for right channel audio. Line level output for driving external HP amplifier.

VCLAMPL 25 − Internally generated voltage supply for left channel bootstrap capacitors.

VCLAMPR 36 − Internally generated voltage supply for right channel bootstrap capacitors.

VOLUME 11 I DC voltage that sets the gain of the Class-D and VAROUT outputs.

VREF 8 I Analog reference for gain control section.

V2P5 4 O 2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs.

— ThermalPad

− Connect to AGND and PGND—should be center point for both grounds.

ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range unless otherwise noted(1)

UNIT

Supply voltage range: AVCC, PVCC −0.3 V to 20 V

Load impedance, RL ≥ 3.6 Ω

MODE, VREF, VARDIFF, VARMAX, VOLUME, FADE 0 V to 5.5 V

Input voltage range, VI SD −0.3 V to VCC + 0.3 VInput voltage range, VIRINN, RINP, LINN, LINP −0.3 V to 7 V

Supply currentAVDD 120 mA

Supply currentAVDDREF 10 mA

Output current VAROUTL, VAROUTR 20 mA

Continuous total power dissipation See Dissipation Rating Table

Operating free-air temperature range, TA −40°C to 85°C

Operating junction temperature range, TJ(2) −40°C to 150°C

Storage temperature range, Tstg −65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The TPA3004D2 incorporates an exposed PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermallydissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that could permanentlydamage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package.

PACKAGE DISSIPATION RATINGSPACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C

PHP 4.3 W 34.7 mW/°C(1) 2.7 W 2.2 W

(1) The PowerPAD must be soldered to a thermal land on the printed circuit board. Please refer to the PowerPADThermally Enhanced Package application note (SLMA002

__________________________________________________________________________


84

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TPA6110A2150-mW STEREO AUDIO POWER AMPLIFIER

SLOS314 – DECEMBER 2000

1

150 mW Stereo Output

PC Power Supply Compatible– Fully Specified for 3.3 V and 5 V

Operation– Operation to 2.5 V

Pop Reduction Circuitry

Internal Mid-Rail Generation

Thermal and Short-Circuit Protection

Surface-Mount Packaging– PowerPAD™ MSOP

Pin Compatible With LM4881

description

The TPA6110A2 is a stereo audio power amplifier packaged in an 8-pin PowerPAD™ MSOP package capableof delivering 150 mW of continuous RMS power per channel into 16-Ω loads. Amplifier gain is externallyconfigured by means of two resistors per input channel and does not require external compensation for settingsof 1 to 10.

THD+N when driving a 16-Ω load from 5 V is 0.03% at 1 kHz, and less than 1% across the audio band of 20Hz to 20 kHz. For 32-Ω loads, the THD+N is reduced to less than 0.02% at 1 kHz, and is less than 1% acrossthe audio band of 20 Hz to 20 kHz. For 10-kΩ loads, the THD+N performance is 0.005% at 1 kHz, and less than0.5% across the audio band of 20 Hz to 20 kHz.

typical application circuit

AudioInput

BiasControl

6

7

5

2

VO1

VO2

VDD

3

8

1

4

IN1–

BYPASS

SHUTDOWN

VDD/2

Ci

Ri

Rf

325 kΩ 325 kΩ

C(B)

C(S)

AudioInput

Ci

Ri IN2–

Rf

VDD

From ShutdownControl Circuit

–+

–+

C(C)

C(C)

Copyright © 2000, Texas Instruments Incorporated

1

2

3

4

8

7

6

5

BYPASSGND

SHUTDOWNIN2–

IN1–VO1VDDVO2

DGN PACKAGE(TOP VIEW)

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

__________________________________________________________________________


85

TPA6110A2150-mW STEREO AUDIO POWER AMPLIFIER

SLOS314 – DECEMBER 2000

2

AVAILABLE OPTIONS

TAPACKAGED DEVICE MSOP

TAMSOP† Symbolization

–40°C to 85°C TPA6110A2DGN TI AIZ† The DGN package is available in left-ended tape and reel only (e.g.,

TPA6110A2DGNR).

Terminal Functions


NAME NO.I/O DESCRIPTION

BYPASS 1 I Tap to voltage divider for internal mid-supply bias supply. Connect to a 0.1 μF to 1 μF low ESR capacitor forbest performance.

GND 2 I GND is the ground connection.

IN1– 8 I IN1– is the inverting input for channel 1.

IN2– 4 I IN2– is the inverting input for channel 2.

SHUTDOWN 3 I Puts the device in a low quiescent current mode when held high.

VDD 6 I VDD is the supply voltage terminal.

VO1 7 O VO1 is the audio output for channel 1.

VO2 5 O VO2 is the audio output for channel 2.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)‡

Supply voltage, VDD 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI –0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C

POWER RATINGDERATING FACTORABOVE TA = 25°C

TA = 70°CPOWER RATING

TA = 85°CPOWER RATING

DGN 2.14 W§ 17.1 mW/°C 1.37 W 1.11 W§ Please see the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report

(literature number SLMA002), for more information on the PowerPAD™ package. The thermal data wasmeasured on a PCB layout based on the information in the section entitled Texas Instruments RecommendedBoard for PowerPAD on page 33 of the before mentioned document.

recommended operating conditions

MIN MAX UNIT

Supply voltage, VDD 2.5 5.5 V

Operating free-air temperature, TA –40 85 °C

High-level input voltage, VIH, (SHUTDOWN) 60% x VDD V

Low-level input voltage, VIL, (SHUTDOWN) 25% x VDD V

__________________________________________________________________________


86

www.techwellinc.com

TechwellTechwellMixed Signal Semiconductor SolutionsMixed Signal Semiconductor Solutions

NTSC/PAL/SECAM Video Decoder for Multimedia ApplicationsNTSC/PAL/SECAM Video Decoder for Multimedia Applications

Target Applications

FeaturesFeatures

Analog Video Decoder

Techwell's TW9906 is a high quality NTSC/PAL/SECAM video decoderthat is designed for multimedia applications. It uses the mixed-signal2.5V/3.3V CMOS technology to provide a low-power integrated solution.

The TW9906 analog front-end is equipped with three separate analogchannels that enable it to accept all three possible analog video signalstandards: composite, S-video or YCbCr component video. All channelsinclude an analog multiplexer (MUX) for maximum flexibility in softwarecontrolled input selection. It is possible to connect up to five compositeinputs at one time and allow the software to switch between them.Alternatively several combinations of composite inputs and S-Videocomponent inputs may be switched under software control. (Four inputchannels of any format can be accommodated with but there is amaximum of 2 S-Video inputs or 2 component inputs.)

The front-end contains all the necessary circuits to simplify the systemdesign. The built-in three high quality 10-bit analog-to-digital converters(ADCs) convert inputs into digital signals for processing.

The TW9906 uses proprietary adaptive 4H comb filter for chroma and lumaseparation to achieve high video quality. The image enhancementincludes horizontal and vertical peaking, CTI and BCS control.

The advanced synchronization processing can produce stable pictures fornon-standard signal such as those produced by VCR trick mode.

The high quality scaler uses multi-tap poly-phase decimation filter toaccurately scale down the image with minimum phase error. It can beprogrammed to scale-down the output picture to an arbitrary ratio with

The TW9906 supports flexible pixel interface. It outputs YCbCr (4:2:2) datastream over 10-bit or 20-bit data path. It also supports both free-running

A 2-wire serial MPU interface is used to simplify system integration. All the

TW9906

NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, Ncombination), PAL (60), SECAM support withautomatic format detectionAdvanced synchronization processing for VCRfast forward, backward, and pause modeSoftware selectable analog inputs

Up to five composite video inputsFour composite, one S-video or one YCbCr

Two composite, two S-Video or two YCbCr

Three composite, one S-Video and one YCbCr

Three 10-bit ADCs with analog clamping circuitand anti-aliasing filter built inFully programmable static gain or automaticgain control for the Y channelProgrammable white peak control for the Ychannel


cropping.

clock and line-locked clock output.

functions can be controlled through this interface.

CRT, LCD, PDP and Projection TVMultifunction LCD Monitor (Monitor TV)DVD-RecorderPC TV Capture CardCCTV Digital Video Recorder

input

inputs

inputs

3x10-bit Multi-Standard Comb Filter Video Decoderwith YCbCr Component Input

* Pin to Pin with TW9909

TECHWELLVIDEO

DECODERS

__________________________________________________________________________


87

TECHWELL INC. TEL 1-408-435-3888 www.techwellinc.com


TW9906 Block Diagram

Miscellaneous

Two wire MPU serial bus interfacePower-down modeTypical power consumption 0.25WSingle 27MHz crystal for all standardsSupports 24.54MHz and 29.5MHz crystalfor high quality square pixel format3.3V / 5V tolerant I/O2.5V / 3.3V Power Supply80 pin TQPF package

Video Processing

Adaptive 4H comb filter for the best imagequalityPAL delay line for color phase error correctionDigital sub-carrier PLL for accurate colordecodingDigital Horizontal PLL and advancedsynchronization processing for non-standardvideo signalsProgrammable hue, brightness, saturation,contrast, and sharpnessBlue stretchImage enhancement with 2D peaking and CTI.Automatic color control and color killerIF compensation filterDetection of level of copy protectionaccording to Macrovision standardYCbCr input supports 480i/576i and sub-sampled 480p/576p with auto-detection.

Video Output

Supports both free-running and line-locked clock outputsProgrammable output croppingHigh quality horizontal filtered scaling with arbitrary scale downratioVMI 1.4 compatible 10-bit or 20-bit pixel interfaceITU-R 601 or ITU-R 656 compatible output YCbCr(4:2:2) outputformatVBI slicer supporting industrial standard data services with datapacket filter capabilityBuilt-in VBI FIFO for convenient access through host interfaceVBI data pass through, raw ADC data for Intercast™Field locked audio clock generator

Anal

ogVi

deo

In

MU

X AGC

/Cla

4-H

adap

tive

com

bfilt

erY/

Cse

para

tion

Chr

oma

Dem

odul

atio

n

Lum

a/C

hrom

apr

oces

sor

Sync

Vide

oou

tput

Inte

rface

VBI SlicerVBI FIFO

2W

ireSe

rial

Bus

MUX0

CIN (1)

DVALID

FIELD

HSYNC

VSYNC

MPOUT

VD(19:0)

CIN (0)

SCLKSDAT

SIAD0

10-b

itAD

C

U

V

MU

X

VIN (1)/MUX4VIN (0)

MU

X

MUX3

Cla

mp

10-b

itAD

C10

-bit

ADC

H/V

Dow

nSc

aler

/Cro

ppin

g

Filte

rFi

lter

Filte

rYBOUT

VBIP

ass

thro

ugh

Clo

ck

27 Mhz PDN

CLKX2CLKX1

Y

Audi

oC

lock

AMXCLK

AMCLK

ASCLK

ALRCLK

INTREQ

Anti-

alia

sFi

lter

Cla

mp

Anti-

alia

sFi

lter

Anti-

alia

sFi

lter

Line

-lock

cloc

kG

ener

ator

TW99063x10-bit Multi-Standard Comb Filter Video Decoder

with YCbCr Component Input* Pin to Pin with TW9909

For more information on Techwell, please contact us at 1-408-435-3888

© 2005 Techwell Inc. All rights reserved.All other trademarks are property of their respective owners

NTSC/PAL/SECAM Video Decoder for Multimedia ApplicationsNTSC/PAL/SECAM Video Decoder for Multimedia Applications

About Techwell

Techwell designs and sells mixed signal semiconductor solutions for digital video applications.The company's products enable theconversion of analog video sources to digital form and facilitate the display, storage and transport of digital video, HDTV, and personalcomputer display information. Headquartered in San Jose, CA,Techwell currently has over 50 employees in the U.S., Korea, and Taiwan.

__________________________________________________________________________


88

VCT 49xyI, VCT 48xyI ADVANCE INFORMATION

Volume 1: General Description

General Description

Release Note: This data sheet describes functionsand characteristics of the VCT 49xyI, VCT 48xyI-C4.

1. Introduction

The VCT 49xyI, VCT 48xyI is an IC family of high-qual-ity single-chip TV processors. Modular design anddeep-submicron technology allow the economic inte-gration of features in all classes of single-scan TVsets. The VCT 49xyI, VCT 48xyI family is based onfunctional blocks contained and approved in existingproducts like DRX 396xA, MSP 34x5G, VSP 94x7B,DDP 3315C, and SDA 55xx.

Each member of the family contains the entire IF,audio, video, display, and deflection processing for 4:3and 16:9 50/60-Hz mono and stereo TV sets. The inte-grated microcontroller is supported by a powerful OSDgenerator with integrated Teletext & CC acquisitionincluding on-chip page memory.

Fig. 1–1: Single-chip VCT 49xyI, VCT 48xyI

1.1. Features

The VCT 49xyI, VCT 48xyI family offers a rich featureset, covering the whole range of state-of-the-art 50/60-Hz TV applications.

– PSSDIP88-1/-2 package

– PMQFP144-2 package

– Submicron CMOS technology

– Low-power standby mode

– Single 20.25 MHz reference crystal

– 8-bit 8051 instruction set compatible CPU

– Up to 256 kB on-chip program ROM

– WST, PDC, VPS, and WSS acquisition

– Closed Caption and V-chip acquisition

– Up to 10 pages on-chip teletext memory

– Multi-standard QSS IF processing with single SAW

– FM Radio and RDS with standard TV tuner

– TV-sound demodulation:• all A2 standards• all NICAM standards• BTSC/SAP with MNR (DBX optional)• EIA-J

– Baseband sound processing for loudspeaker chan-nel:• volume and balance• bass/treble or equalizer• loudness and spatial effect (e.g. pseudo stereo)• Micronas AROUND (virtual Dolby optional)• Micronas BASS• further optional and licence requiring sound

enhancements as BBE, SRS Wow and Micronas VOICE

– CVBS, S-VHS, YCrCb and RGB inputs

– 4H adaptive comb filter (PAL/NTSC)

– multi-standard color decoder (PAL/NTSC/SECAM)

– Nonlinear horizontal scaling “panorama vision”

– Luma and chroma transient improvement (LTI, CTI)

– Non-linear color space enhancement (NCE)

– Dynamic black level expander (BLE)

– Scan velocity modulation output

– Soft start/stop of H-drive

– Vertical angle and bow correction

– Average and peak beam current limiter

– Nonlinear and dynamic EHT compensation

– Black switch off procedure (BSO)

Video & Sound IFDRX 396xA

Audio ProcessingMSP 34x5G

Video ProcessingVSP 94x7B

Control, OSD, TextSDA 55xx

Display & DeflectionDDP 3315C

VCT 49xyI


89



1.2. Chip Architecture

Fig. 1–2: Block diagram of the VCT 49xyI, VCT 48xyI

XTAL1

IFFrontend

Slicer

VideoBackend

IFProcessor

SoundDemodulator

AudioProcessor

DisplayGenerator

BusArbiter

20kB XRAM256kB

Prog ROMClock

Generator

Reset & TestLogic

I2C Master/Slave

24kBChar ROM TEST

RESETQ

XTAL2

I2C

Pxy

CVBS in

IFIN-

IFIN+

TA

GC

SIF

YCrCb in

CVBS out

RGB in

AO

UT

SP

EA

KE

R

RGB out

SVM

RGB in

SENSE

RSW

VERT

EW

HOUT

PROT

HFLB

PanoramaScaler

Display &DeflectionProcessor

TimerCRTPWMADC

UARTWatchdog

RTC

I/O-PortsMemoryInterface

ADB, DB, PSENQ,PSWEQ, WRQ, RDQ

CPU8051

AIN

VideoFrontend

ColorDecoder

ComponentInterface

CombFilter

__________________________________________________________________________


90



4.2. Pin Connections and Short Descriptions

NC = not connectedLV = if not used, leave vacantOBL = obligatory; connect as described in circuit diagramIN = Input PinOUT = Output PinSUPPLY = Supply Pin

Pin No. Pin Name Type Connection Short Description

PS

SD

IP88

-1

PS

SD

IP88

-2

PM

QF

P14

4-2

(If not used)

1 88 128 GND SUPPLY OBL Ground Platform

2 87 129 VSUP5.0BE SUPPLY OBL Supply Voltage Analog Video Back-end, 5.0 V

3 86 130 TEST IN GND Test Input, reserved for Test

4 85 131 VERT+ OUT GND Differential Vertical Sawtooth Output

5 84 132 VERT- OUT GND Differential Vertical Sawtooth Output

6 83 133 EW OUT GND Vertical Parabola Output

7 82 134 RSW2 OUT LV Range Switch 2 Output

8 81 135 RSW1 OUT LV Range Switch 1 Output

9 80 136 SENSE IN GND Sense ADC Input

10 79 137 GNDM IN GND Reference Ground for Sense ADC

11 78 138 FBIN IN GND Fast Blank Input, Back-end

12 77 139 RIN IN GND Analog Red Input, Back-end

13 76 140 GIN IN GND Analog Green Input, Back-end

14 75 141 BIN IN GND Analog Blue Input, Back-end

15 74 142 SVMOUT OUT VSUP5.0BE Scan Velocity Modulation Output

16 73 143 ROUT OUT VSUP5.0BE Analog Red Output

17 72 144 GOUT OUT VSUP5.0BE Analog Green Output

18 71 1 BOUT OUT VSUP5.0BE Analog Blue Output

19 70 2 VRD OBL Reference Voltage for RGB DACs

20 69 3 XREF OBL Reference Current for RGB DACs

21 68 4 VSUP3.3BE SUPPLY OBL Supply Voltage Analog Video Back-end, 3.3 V



24 65 7 VSUP3.3IO SUPPLY OBL Supply Voltage I/O Ports, 3.3 V(main and standby supply)

25 64 8 VSUP3.3DAC SUPPLY OBL Supply Voltage Video DACs, 3.3 V

26 63 9 GNDDAC SUPPLY OBL Ground Video DACs__________________________________________________________________________


91

ADVANCE INFORMATION VCT 49xyI, VCT 48xyIVolume 1: General Description

27 62 10 SAFETY IN GND Safety Input

28 61 11 HFLB IN HOUT Horizontal Flyback Input

29 60 12 HOUT OUT LV Horizontal Drive Output

30 59 13 VPROT IN GND Vertical Protection Input

37 PWMV OUT LV PWM Vertical Output

38 DFVBL OUT LV Dynamic Focus Vertical Blanking Output

31 58 39 SDA IN/OUT OBL I2C Bus Data Input/Output

32 57 40 SCL IN/OUT OBL I2C Bus Clock Input/Output

33 56 41 P21 IN/OUT LV Port 2, Bit 1 Input/Output










43 46 53 VSUP3.3FE SUPPLY OBL Supply Voltage Analog Video Front-end, 3.3 V(main and standby supply)



46 43 56 VSUP1.8FE SUPPLY OBL Supply Voltage Analog Video Front-end, 1.8 V(main and standby supply)

47 42 57 VOUT3 OUT LV Analog Video 3 Output



50 39 60 VIN1 IN GND Analog Video 1 Input








PS

SD

IP88

-1

PS

SD

IP88

-2

PM

QF

P14

4-2

(If not used)


92









63 26 100 XTAL2 OUT OBL Analog Crystal Output

64 25 101 XTAL1 IN OBL Analog Crystal Input

65 24 102 VSUP1.8DIG SUPPLY OBL Supply Voltage Digital Core, 1.8 V(main and standby supply)



68 21 105 VSUP3.3DIG SUPPLY OBL Supply Voltage Digital Core, 3.3 V

69 20 106 VSUP5.0IF SUPPLY OBL Supply Voltage IF ADC, 5.0 V

70 19 107 VSUP5.0FE SUPPLY OBL Supply Voltage Analog IF Front-end, 5.0 V

71 18 108 RESETQ IN/OUT OBL Reset Input/Output

72 17 109 IFIN+ IN VREFIF Differential IF Input

73 16 110 IFIN- IN VREFIF Differential IF Input

74 15 111 VREFIF OBL Reference Voltage, IF ADC

75 14 112 TAGC OUT LV Tuner AGC Output

76 13 113 AIN1R /SIF

IN/OUT GND Analog Audio 1 Input, RightAnalog 2nd Sound IF Output

77 12 114 AIN1L IN GND Analog Audio 1 Input, Left

78 11 115 AIN2R IN GND Analog Audio 2 Input, Right

79 10 116 AIN2L IN GND Analog Audio 2 Input, Left

117 AIN3R IN GND Analog Audio 3 Input, Right

118 AIN3L IN GND Analog Audio 3 Input, Left

119 AOUT2R OUT LV Analog Audio 2 Output, Right

120 AOUT2L OUT LV Analog Audio 2 Output, Left

80 9 AIN3R /AOUT2R

IN /OUT

LV Analog Audio 3 Input, RightAnalog Audio 2 Output, Right

81 8 AIN3L /AOUT2L

IN /OUT

LV Analog Audio 3 Input, LeftAnalog Audio 2 Output, Left

82 7 121 AOUT1R OUT LV Analog Audio 1 Output, Right

83 6 122 AOUT1L OUT LV Analog Audio 1 Output, Left


PS

SD

IP88

-1

PS

SD

IP88

-2

PM

QF

P14

4-2

(If not used)


93


84 5 123 SPEAKERR OUT LV Analog Loudspeaker Output, Right

85 4 124 SPEAKERL OUT LV Analog Loudspeaker Output, Left

86 3 125 VREFAU OBL Reference Voltage, Audio

87 2 126 VSUP8.0AU SUPPLY OBL Supply Voltage Analog Audio, 8.0 V


71 P37 /656IO7

IN/OUT LV Port 3, Bit 7 Input/OutputDigital 656 Bus 7 Input/Output

72 P36 /656IO6


73 P35 /656IO5


74 P34 /656IO4


75 P33 /656IO3


76 GNDEIO SUPPLY OBL Ground Extended I/O Ports

77 VSUP3.3EIO SUPPLY OBL Supply Voltage Extended I/O Ports, 3.3 V

78 P32 /656IO2


79 P31 /656IO1


80 P30 /656IO0


81 P26 /656VIO

IN/OUT LV Port 2, Bit 6 Input/OutputDigital 656 Vsync Input/Output

82 P25 /656HIO

IN/OUT LV Port 2, Bit 5 Input/OutputDigital 656 Hsync Input/Output

83 P24 /656CLKIO

IN/OUT LV Port 2, Bit 4 Input/OutputDigital 656 Clock Input/Output

31 ADB19 OUT LV Address Bus 19 Output









PS

SD

IP88

-1

PS

SD

IP88

-2

PM

QF

P14

4-2

(If not used)


94















88 DB0 IN/OUT LV Data Bus 0 Input/Output








32 RDQ OUT LV Data Read Enable Output

33 WRQ OUT LV Data Write Enable Output

34 OCF OUT LV Opcode Fetch Output

35 ALE OUT LV Address Latch Enable Output

36 RSTQ OUT LV Internal CPU Reset Output

97 PSENQ OUT LV Program Store Enable Output

20 PSWEQ OUT LV Program Store Write Enable Output

51 XROMQ IN OBL External ROM Enable Input

52 EXTIFQ IN LV Enable External Interface Input

24 STOPQ IN LV Stop CPU Input

25 ENEQ IN LV Enable Emulation Input


PS

SD

IP88

-1

PS

SD

IP88

-2

PM

QF

P14

4-2

(If not used)


95


4.3. Pin Descriptions

4.3.1. Supply Pins

VSUP1.8DIG − Supply Voltage 1.8 VThis pin is main and standby supply for the digital corelogic of controller, video, display and deflection pro-cessing.

VSUP1.8FE − Supply Voltage 1.8 VThis pin is main and standby supply for the analogvideo front-end.

VSUP3.3FE − Supply Voltage 3.3 VThis pin is main and standby supply for the analogvideo front-end.

VSUP3.3IO − Supply Voltage 3.3 VThis pin is main and standby supply for the digital I/O-ports.

VSUP3.3DIG − Supply Voltage 3.3 VThis pin is main supply for the digital core logic of IFand audio processing and digital video back-end.

VSUP3.3BE − Supply Voltage 3.3 VThis pin is main supply for the analog video back-end.

VSUP5.0FE − Supply Voltage 5.0 VThis pin is main supply for the analog IF front-end.

VSUP5.0IF − Supply Voltage 5.0 VThis pin is main supply for the IF ADC.

VSUP5.0BE − Supply Voltage 5.0 VThis pin is main supply for the analog video back-end.

VSUP8.0AU − Supply Voltage 8.0 VThis pin is main supply for the analog audio process-ing.

GND − Ground PlatformThis pin is main ground for all above supplies.

VSUP3.3DAC − Supply Voltage 3.3 VThis pin is main supply for the video DACs.

GNDDAC − Ground for 3.3 V Video DAC Supply

VSUP3.3EIO − Supply Voltage 3.3 VThis pin is main and standby supply for the extendeddigital I/O-ports available in QFP package only. It isinternally connected to VSUP3.3IO.

GNDEIO − Ground for 3.3 V Extended I/O SupplyIt is internally connected to GND.

Application Note:All GND pins must be connected to a low-resistiveground plane underneath the IC. All supply pins mustbe connected separately with short and low-resistive

lines to the power supply. Decoupling capacitors fromVSUPxx to GND have to be placed as closely as pos-sible to these pins. It is recommended to use morethan one capacitor. By choosing different values, thefrequency range of active decoupling can be extended.

4.3.2. IF Pins

VREFIF − Reference Voltage for analog IF (Fig. 4–6)This pin must be connected to GND via a circuitryaccording to the application circuit. Low inductancecaps are necessary.

IFIN+, IFIN- − Balanced IF Input (Fig. 4–4)These pins must be connected to the SAW filter out-put. The SAW filter has to be placed as close as possi-ble. The layout of the IF input should be symmetricalwith respect to GND.

SIF − 2nd Sound IF Output (Fig. 4–7)Output level is set via I2C-Bus. An appropriate soundprocessor (e.g. MSP) can be connected to this pin.This pin is also configurable as audio input (seeFig. 4–8).

TAGC − Tuner AGC Output (Fig. 4–5)This pin controls the delayed tuner AGC. As it is anoise-shaped-I-DAC output, it has to be connectedaccording to the application circuit.

4.3.3. Audio Pins

VREFAU – Reference Voltage for Analog Audio (Fig.4–12)This pin serves as the internal ground connection forthe analog audio circuitry. It must be connected to theGND pin with a 3.3 μF and a 100 nF capacitor in paral-lel. This pins shows a DC level of typically 3.77 V.

AIN1 L – Audio 1 Inputs (Fig. 4–8)The analog input signal for audio 1 is fed to this pin.Analog input connection must be AC coupled.

AIN1 R – Audio 1 Inputs (Fig. 4–8)The analog input signal for audio 1 is fed to this pin.Analog input connection must be AC coupled. This pinis also configurable as sound IF output (see Fig. 4–7).

AIN2 R/L – Audio 2 Inputs (Fig. 4–8)The analog input signal for audio 2 is fed to this pin.Analog input connection must be AC coupled.

AIN3 R/L – Audio 3 Inputs (Fig. 4–8)The analog input signal for audio 3 is fed to this pin.Analog input connection must be AC coupled.


96



AOUT1 R/L – Audio 1 Outputs (Fig. 4–9)Output of the analog audio 1 signal. Connections tothese pins are intended to be AC coupled.

AOUT2 R/L – Audio 2 Outputs (Fig. 4–9)Output of the analog audio 2 signal. Connections tothese pins are intended to be AC coupled.

SPEAKER R/L – Loudspeaker Outputs (Fig. 4–11)Output of the loudspeaker signal. A 1 nF capacitor toGND must be connected to these pins. Connections tothese pins are intended to be AC-coupled.

4.3.4. Video Pins

VIN 1–11 − Analog Video Input (Fig. 4–13)These are the analog video inputs. A CVBS, S-VHS,YCrCb or RGB/FB signal is converted using the luma,chroma and component AD converters. The input sig-nals must be AC-coupled by 100nF. In case of an ana-log fast blank signal carrying alpha blending informationthe input signal must be DC-coupled.

VOUT 1-3 − Analog Video Output (Fig. 4–14)The analog video inputs that are selected by the videosource select matrix are output at these pins.

RIN, GIN, BIN − Analog RGB Input (Fig. 4–15)These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can beswitched to the analog RGB outputs with the fast blank signal. Separate brightness and contrast settings forthe external analog signals are provided.

FBIN − Fast Blank Input (Fig. 4–16)This pin is used to switch the RGB outputs to the exter-nal analog RGB inputs. The active level (low or high)can be selected by software.

ROUT, GOUT, BOUT − Analog RGB Output (Fig. 4–17)These pins are the analog Red/Green/Blue outputs ofthe back-end. The outputs are current sinks.

SVMOUT − Scan Velocity Modulation Output (Fig. 4–17)This output delivers the analog SVM signal. The D/Aconverter is a current sink like the RGB D/A convert-ers. At zero signal the output current is 50% of themaximum output current.

VRD − DAC Reference Decoupling (Fig. 4–18)Via this pin the RGB-DAC reference voltage is decou-pled by an external capacitor. The DAC output currentsdepend on this voltage, therefore a pulldown transistorcan be used to shut off all beam currents. A decouplingcapacitor of 4.7 μF in parallel to 100 nF (low induc-tance) is required.

XREF − DAC Current Reference (Fig. 4–18)External reference resistor for DAC output currents,typical 10 kΩ to adjust the output current of the D/Aconverters. (see recommended operating conditions).This resistor has to be connected to ground as closelyas possible to the pin.

4.3.5. CRT Pins

HOUT − Horizontal Drive Output (Fig. 4–19)This open source output supplies the drive pulse forthe horizontal output stage. An external pulldownresistor has to be used. The polarity and gating withthe flyback pulse are selectable by software.

HFLB − Horizontal Flyback Input (Fig. 4–20)Via this pin the horizontal flyback pulse is supplied to the VCT 49xyI, VCT 48xyI.

VPROT − Vertical Protection Input (Fig. 4–20)The vertical protection circuitry prevents the picturetube from burn-in in the event of a malfunction of thevertical deflection stage. If the peak-to-peak value ofthe sawtooth signal from the vertical deflection stage istoo small, the RGB output signals are blanked.

SAFETY − Safety Input (Fig. 4–20)This input has two thresholds. A signal between thelower and upper threshold means normal function. Asignal below the lower threshold or above the upperthreshold is detected as malfunction and the RGB sig-nals will be blanked.

VERT+, VERT− − Vertical Sawtooth Output (Fig. 4–21)These pins supply the symmetrical drive signal for thevertical output stage. The drive signal is generatedwith 15-bit precision. The analog voltage is generatedby a 4 bit current-DAC with an external resistor of6.8 kΩ and uses digital noise shaping.

EW − East-West Parabola Output (Fig. 4–22)This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bitprecision. The analog voltage is generated by a 4 bitcurrent-DAC with an external resistor of 6.8 kΩ anduses digital noise shaping.

PWMV − PWM Vertical Output (Fig. 4–19)This pin provides an adjustable vertical parabola with 7bit resolution and approx. 79.4 kHz PWM frequency.

DFVBL − Dynamic Focus Vertical Blanking (Fig. 4–19)This pin supplies the blank pulse for dynamic focusduring vertical blanking period or a free programmablehorizontal pulse for horizontal dynamic focus genera-tion. Alternatively it can be programmed as FIELD out-put, delivering even/odd field information.


97


SENSE − Measurement ADC Input (Fig. 4–25)This is the input of the analog to digital converter forthe picture and tube measurement. Three measure-ment ranges are selectable with RSW1 and RSW2.

GNDM − Measurement ADC Reference InputThis is the reference ground for the measurement A/Dconverter. Connect this pin to GND.

RSW1 − Range Switch1 for Measuring ADC (Fig. 4–23) These pin is an open drain pull-down output. Duringcutoff and white drive measurement the switch is off.During the rest of time it is on. The RSW1 pin can beused as second measurement ADC input for picturebeam current measurement.

RSW2 − Range Switch2 for Measuring ADC (Fig. 4–24) These pin is an open drain pull-down output. Duringcutoff measurement the switch is off. During whitedrive measurement the switch is on. Also during therest of time it is on. It is used to set the range for whitedrive current measurement.

4.3.6. Controller Pins

XTAL1 − Crystal Input and XTAL2 Crystal Output (Fig.4–26)These pins connect a 20.25 MHz crystal to the internaloscillator. An external clock can be fed into XTAL2.

RESETQ − Reset Input/Output (Fig. 4–27)A low level on this pin resets the VCT 49xyI, VCT48xyI. The internal CPU can pull down this pin to resetexternal devices connected to this pin.

TEST − Test Input (Fig. 4–28)This pin enables factory test modes. For normal opera-tion, it must be connected to ground.

SCL − I2C Bus Clock (Fig. 4–29)This pin delivers the I2C bus clock line. The signal canbe pulled down by external slave ICs to slow downdata transfer.

SDA − I2C Bus Data (Fig. 4–29)This pin delivers the I2C bus data line.

P10−P13, P20−P23 − I/O Port (Fig. 4–30)These pins provide CPU controlled I/O ports.

P14−P17 − I/O Port (Fig. 4–31)These pins provide CPU controlled I/O ports. Addition-ally they can be used as analog inputs for the control-ler ADC.

P24−P26, P30−P37 − I/O Port (Fig. 4–32)These pins provide CPU controlled I/O ports.

ADB0−ADB19 − Address Bus Output (Fig. 4–33)These 20 lines provide the CPU address bus output toaccess external memory.

DB0−DB7 − Data Bus Input/Output (Fig. 4–34)These 8 lines provide the bidirectional CPU data busto access external memory.

WRQ − Data Write Enable Output (Fig. 4–33)This pin controls the direction of data exchangebetween the CPU and the external data memorydevice (SRAM).

RDQ − Data Read Enable Output (Fig. 4–33)This pin is used to enable the output driver of theexternal data memory device (SRAM) for read access.

PSENQ − Program Store Enable Output (Fig. 4–33)This pin is used to enable the output driver of theexternal program memory device (ROM/FLASH) forread access.

PSWEQ − Program Store Write Enable Output (Fig. 4–33)This pin is used to write into the external program flashmemory device.

XROMQ − External ROM Enable Input (Fig. 4–35)This pin must be pulled low to access the external pro-gram memory. XROMQ has an internal pull-up resis-tor.

EXTIFQ − Enable External Memory Interface Input(Fig. 4–35)This pin must be pulled low to enable the externalmemory interface. EXTIFQ has an internal pull-upresistor.

STOPQ − Stop CPU Input (Fig. 4–35)Applying a low level during the input phase freezes thereal-time relevant internal peripherals such as timersand interrupt controller. STOPQ has an internal pull-upresistor.

ENEQ − Enable Emulation Input (Fig. 4–35)Only if this pin is set to low level, STOPQ and OCF areoperational. ENEQ has an internal pull-up resistor.

ALE − Address Latch Enable Output (Fig. 4–33)This signal indicates changes on the address bus.

OCF − Opcode Fetch Output (Fig. 4–33)A high level driven by the CPU during output phaseindicates the beginning of a new instruction.

RSTQ − Internal CPU Reset Input/Output (Fig. 4–36)This pin is used for emulation purpose only. A low levelon this pin resets the CPU. It also indicates an internalreset of the CPU. RSTQ has an internal pull-up resis-tor.


98



4.4. Pin Configuration

Fig. 4–1:PSSDIP88-1 package Fig. 4–2:PSSDIP88-2 package (pinning mirrored)

VCT

49xy

I PY

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

25

26

27

28

29

30

31

32

33

34

35

36

24

38

44

43

42

41

40

39

37

GOUT

GINBINSVMOUT

RINFBIN

VRDXREFVSUP3.3BEGND

BOUT

ROUT

VSUP3.3IOGND

HFLBHOUT

SAFETY

VPROT

GNDDACVSUP3.3DAC

SDASCLP21

P17P20

P16P15P14P13P12P11

VSUP3.3FEGND

GNDMSENSE

GNDVSUP5.0BETESTVERT+VERT-EWRSW2RSW1

P10

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

64

63

62

61

60

59

58

57

56

55

54

53

65

51

45

46

47

48

49

50

52

SIF / AIN1R

RESETQ

TAGCVREFIF

VREFAUSPEAKERL

VSUP5.0IF

XTAL2

VSUP3.3DIGGND

IFIN-

VSUP5.0FE

VSUP1.8DIGGND

XTAL1

VIN11

VIN9VIN10

VIN7VIN8

VIN6VIN5VIN4VIN3

VIN1VIN2

P22P23

VOUT1VOUT2VOUT3

VSUP1.8FEGND

SPEAKERRAOUT1L

GNDVSUP8.0AU

AIN1LAIN2RAIN2L

AIN3R / AOUT2RAIN3L / AOUT2L

AOUT1R

IFIN+

VCT

49xy

I PZ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

25

26

27

28

29

30

31

32

33

34

35

36

24

38

44

43

42

41

40

39

37

GOUT

GINBIN

SVMOUT

RINFBIN

VRDXREF

VSUP3.3BEGND

BOUT

ROUT

VSUP3.3IOGND

HFLBHOUT

SAFETY

VPROT

GNDDACVSUP3.3DAC

SDASCLP21

P17P20

P16P15P14P13P12P11

VSUP3.3FEGND

GNDMSENSE

GNDVSUP5.0BE

TESTVERT+VERT-

EWRSW2RSW1

P10

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

64

63

62

61

60

59

58

57

56

55

54

53

65

51

45

46

47

48

49

50

52

SIF / AIN1R

RESETQ

TAGCVREFIF

VREFAUSPEAKERL

VSUP5.0IF

XTAL2

VSUP3.3DIGGND

IFIN-

VSUP5.0FE

VSUP1.8DIGGND

XTAL1

VIN11

VIN9VIN10

VIN7VIN8

VIN6VIN5VIN4VIN3

VIN1VIN2

P22P23

VOUT1VOUT2VOUT3VSUP1.8FEGND

SPEAKERRAOUT1L

GNDVSUP8.0AU

AIN1LAIN2RAIN2LAIN3R / AOUT2RAIN3L / AOUT2LAOUT1R

IFIN+


99


Fig. 4–3: PMQFP144-2 package

VCT 49xyI

VIN9VIN8

VIN10

VIN7VIN6

VIN3VIN2VIN1VOUT1VOUT2VOUT3VSUP1.8FEGND

VIN5VIN4

GNDVSUP3.3FE

XROMQP10P11P12P13P14P15P16

P20

P17

SDADFVBL / FIELDPWMV

P21SCL

EXTIFQ

VIN11P37 / 656IO7P36 / 656IO6

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

66

65

67

68

69

70

71

72109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

133

134

135

136

137

138

139

140

141

142

143

144

132

737475767778798081828384858687888990919293949596979899100

101

102

103

104

105

106

107

108

GINRIN

FBINGNDM

BINSVMOUT

RSW2EW

VERT-VERT+

RSW1SENSE

VSUP5.0BETEST

GNDGND

VREFAUVSUP8.0AU

SPEAKERRSPEAKERL

AOUT1LAOUT1RAOUT2LAOUT2R

AIN3RAIN3L

AIN2LAIN2RAIN1L

AIN1R / SIFTAGC

VREFIFIFIN-IFIN+

ROUTGOUT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

BO

UT

VRD

XREF

VSU

P3.3

BE

GN

DG

ND

VSU

P3.3

IOVS

UP3

.3D

AC

GN

DD

AC

SAFE

TYH

FLB

HO

UT

VPR

OT

AD

B11

AD

B9

AD

B13

AD

B14

AD

B18

AD

B16

AD

B15

PSW

EQA

DB

17

STO

PQEN

EQA

DB

12A

DB

7

RST

Q

AD

B5

AD

B4

AD

B19

RD

QW

RQ

OC

FA

LE

AD

B6

AD

B8

VSU

P5.0

FE

P25

/ 656

HIO

P26

/ 656

VIO

P30

/ 656

IO0

P31

/ 656

IO1

P32

/ 656

IO2

VSU

P3.3

EIO

GN

DEI

OP3

3 / 6

56IO

3P3

4 / 6

56IO

4P3

5 / 6

56IO

5

RES

ETQ

VSU

P3.3

DIG

GN

DG

ND

VSU

P1.8

DIG

XTA

L1XT

AL2

P22

P23

PSEN

QA

DB

10D

B7

DB

6D

B5

DB

4D

B3

DB

2D

B1

AD

B3

AD

B2

DB

0A

DB

0

VSU

P5.0

IF

AD

B1

P24

/ 656

CLK

IO


100

�� WM8725

99dB Stereo DAC

DESCRIPTION

WM8725 is a high-performance stereo DAC designed for use in portable audio equipment, video CD players and similar applications. It comprises selectable normal or I2S compatible serial data interfaces for 16 to 24-bit digital inputs, high performance digital filters, and sigma-delta output DACs, achieving an excellent 99dB signal-to-noise performance.

The device is available in a 14-pin SOIC package that offers selectable mute and de-emphasis functions using a minimum of external components.

FEATURES

• 99dB SNR performance • Stereo DAC with input sampling from 8kHz to 96kHz • Additional mute feature • Normal or I2S compatible data format • Sigma-delta design with 64x oversampling • System clock 256fs or 384fs • Supply range 3V to 5V • 14-pin SOIC package

APPLICATIONS • Portable audio equipment • Video CD players

BLOCK DIAGRAM

__________________________________________________________________________


101

WM8725 Production Data

��PD Rev 4.1 August 2004

PIN CONFIGURATION

10

9

8

14

13

12

11WM8725

5

6

7

1

2

3

4

VDD

VOUTL

MUTE

NC

DEEMPH

SCKI

FORMAT

GND

VOUTR

CAP

NC

BCKIN

LRCIN

DIN

ORDERING INFORMATION

DEVICE TEMPERATURE RANGE

PACKAGE MOISTURE SENSITIVITY LEVEL

PEAK BODY TEMPERATURE

WM8725ED -25oC to +85oC 14-pin SOIC MSL1 240oC

WM8725ED/R -25oC to +85oC

14-pin SOIC

(tape and reel) MSL1 240oC

WM8725GED/V -25oC to +85oC

14-pin SOIC (lead free)

MSL2 260oC

WM8725GED/RV -25oC to +85oC

14-pin SOIC

(lead free tape and reel) MSL2 260oC

Note:

Reel quantity: 3,000


102

WM8725 Production Data

��PD Rev 4.1 August 2004

PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 LRCIN Digital input Sample rate clock input

2 DIN Digital input Serial data input

3 BCKIN Digital input Bit clock input

4 NC No connect No internal connection

5 CAP Analogue output Analogue internal reference

6 VOUTR Analogue output Right channel DAC output

7 GND Supply 0V supply

8 VDD Supply Positive supply

9 VOUTL Analogue output Left channel DAC output

10 MUTE Digital input Mute control, high = muted. Internal pull-down

11 NC No connect No internal connection

12 DEEMPH Digital input De-emphasis select, high = de-emphasis ON. Internal pull-up

13 FORMAT Digital input Data input format select, low = normal, high = I2S. Internal pull-up

14 SCKI Digital input System clock input (256fs or 384fs)


103

Documents

Lcd+Profilo Telra+PT1000