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7/24/2019 Layout Details
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STICK DIAGRAMS
VLSI design aims to translate circuit conceptsonto silicon
stick diagrams are a means of capturing
topograph and laer information ! simplediagrams
Stick diagrams con"e laer informationthrough color codes #or monochromeencoding$
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Stick Encoding Layer Mask LayoutEncoding
Thinox
Polysilicon
Metal1
Contact cut
&'T applica(le Overglass
Implant
uried contact
Encoding !or nMOSprocess
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Stick Encoding Layer Mask LayoutEncoding
P"#i$usion
&ot Sho)n in StickDiagram
P% Mask
Metl&
'I(
#emarcation Line P")ell
'dd or *+#CO+T(CT
Encoding !or pMOSprocess
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*or reference + an nM'S In"erter coloured stickdiagram
Vout
Vdd
, -V
Vin
* Note the depletion modedevice
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Only metal and polysilicon cancross the dimarcation line,
CM'S In"erter coloured stick diagram%C%A
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Vout
Vdd
, -V
Vin
Vout
Vdd
, -V
Vin
pM'S
nM'S
Stick diagram !/ CM'S transistor circuit
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am a " asedesign rules
All paths in all laers )ill (edimensioned in 0 units andsu(se1uentl 0 can (e allocated an
appropriate "alue compati(le )iththe feature si2e of the fa(ricationprocess3
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T(+SISTO #ESI*+ 2LES
n!di4usion p!di4usion
Thino5
6 0
6 0
7 0
7 0
7 0
7 0
80
8 0
8 06 0
6 0
9olsilicon
Metal :
Metal 6
6 0
Minimum distance rules (et)een de"icelaers; e3g3;
•
polsilicon↔
metal• metal ↔ metal• di4usion ↔ di4usion and• minimum laer o"erlaps
are used during laout
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gate
drainsource
nM'S transistor mask representation
polsilicon
metal
Contact holes
di4usion #acti"eregion$
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Contact Cuts
• Three possi(le approaches <
:3 9ol to Metal
63 Metal to Di4usion73 =uried contact #pol to di4$ or
(utting contact #pol to di4 usingmetal$
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• Minimi2e spared di4usion• >se minimum pol )idth #6λ$ •?idth of contacts , 6λ
•Multipl contacts
6λ
Laout Design rules @ Lam(da #λ$
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3
&
3
&
4
All de"ice mask dimensions are (ased on multiples of λ; e3g3;
polsilicon minimum )idth , 6λ3 Minimum metal to metalspacing , 7λ
Laout Design rules @ Lam(da #λ$
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Laout Design rules @ Lam(da #λ$
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CM'S Laout
N diff
Poly
P diff
Contacts
Metal
P Substrate
N Well
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Laout Design rules @Lam(da #λ$
• Same & and 9 alters smmetr • L min• ?pmos,6 ?nmos
Width of pMOSshould be twicethe width ofnMOS
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Lam(da =ased Design Rules
• Design rules (ased on single parameter; 0
• Simple for the designer
• ?ide acceptance
• 9ro"ide feature si2e independent )a of settingout mask
• Minimum feature si2e is defined as 6 0
• >sed to preser"e topological features on a chip
• 9re"ents shorting; opens; contacts from slippingout of area to (e contacted
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CM'S In"erter Mask Laout
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CM'S Laout Design
• CM'S IC are designing using stick diagrams3
• Di4erent color codes for each laer3
• Lamdamicron grid3%C%A
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CM'S A&6 #6 ip A&D gate$ Mask Laout
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nM'S In"erter coloured stick diagram
* Note the depletion
mode device
Vout
Vdd
, -V
Vin
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T)o!)a selector )ith ena(le
%
B
A
A
ono$
on
%,EA,EF:
on
on
o$
o$
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Static CM'S &A&D gate
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Static CM'S &'R gate
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Static CM'S Design %5ample Laout
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Laout 6 #Di4erent laout stle to pre"ious (ut same function
(eing implemented$
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Comple5 logic gates laout
• %5*,A=H%HCD
• %ulerpaths
•Circuit to graph #con"ert$:$ Vertices are sourceDrainconnections
6$ %dges are transistors
•)*ind p and n %ulerpaths
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Virtuoso*a(
• 7D fa(rication process simulator)ith cross sectional "ie)er3
• Step!(!step 7!D "isuali2ation offa(rication for an portion of laout3
Touch the deep su-microntechnology
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6D Cross Section&M'S Transistor
& Di4usion
Metal Laer
Contacts
9ol
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