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Lab1 Introduction toFPGA, Nexys4, Questasim, & VivadoEE354
Introduction to FPGA
FPGA Architecture▪Field Programmable Gate Array
▪CLBs (Configurable Logic Blocks)▪ Slices of LUT’s, Muxes, Flip Flops to realize logic
▪IOBs (Input/Output Blocks)▪ Buffers and Tri-state gates to bring signals on/off
the chip
▪Programmable Interconnect Points▪ Configurable routing paths for the CLB’s and IOB’s
CLB (Configurable Logic Block)
• Look-up-Tables store the truth tables for the logic to be implemented
• LUT’s can be re-configured based on the design
• Flip Flops in the CLB’s allow for sequential logic
• Building Blocks of all logic in the FPGA
FPGA Design Flow (for EE354)
1. Design Entry in Verilog
◦ Our designs will typically include a core design (state machine) and a top design (integrates I/O with core design)
2. Behavioral Simulation of core design
3. Synthesize design into a netlist
4. Implementation
◦ Reads the constraints we assign (.xdc file)
◦ Optimizes, places the design on the specified board, routes the design
5. Generate Bitstream
Synthesis, Implementation, Bitstream Generation are all done in Vivado
Introduction to Nexys-4
Nexys4_Basic_IO_Introduction.pdf
Nexys_4_documentation/
Handling Nexys-4ESD (Electrostatic Discharge)
-- Electrostatic discharge can damage chips! So, please do not touch PCB traces or component pins. Hold the board between fingers on the edges.
-- The storage box has antistatic black foam. That is for storage only.You should not power the board while it is in the box.
-- Do not alter the jumpers.
Demonstration of Questasim on VDI
Demonstration of Questasim on VDI (MyDesktop)
Example design: Middle_Finder.zip
Steps to run QuestasimModelSim_Questasim_Testing.pdf
Demonstration of Vivado on VDI
Demonstration of Vivado on VDI (MyDesktop)Example design: test_nexys4_verilog_sources_onlytest_nexys4_verilog.zip
Transferring files between your laptop and VDIProject directories under temporary C:\Xilinx_projects\
Transferring the .bit file to your N4 board through the Hardware Manager tool on Vivado