Lab IIILab III

Real-Time EmbeddedReal-Time EmbeddedOperating System for a SoCOperating System for a SoC

SystemSystem

Startup Flow ChatStartup Flow Chat

Reset

BuildingException Handler

Initiation Stack Pointer for Exception mode and SPSR

Execution C_function

initialization Stack

LDR r7, #RAMBased

MRS r4, cpsr

ORR r4, r4, #NoIRQ

ORR r4, r4, #NoFIQ

BIC r4, r4, #ModeMask Clear Mode

MOV r2, #User32Mode

;--------------------------------------------------ORR r5, r4, #IRQ32ModeMSR cpsr_c, r5MSR spsr_c, r2MOV sp, r7 ; Initial IRQ stack pointer...SUB r7, r7, #IRQStackSize....;;Set SVC Mode Stack pointer ;;Set User Mode Stack pointer

Set INTMSK ;Disable IRQClear INTPND

ARM ExceptionARM Exception

ARM Exception EventsARM Exception Events

Install an Exception Handler: Method

Vector_Init_Blockb Reset_Addrb Undefined_Addrb SWI_Addr b Prefetch_Addrb Abort_AddrNOP ;Reserved vectorb IRQ_Addrb FIQ_Addr

Reset_Addr …Undefined_Addr …

B .For loopSWI_Addr …Prefetch_Addr … B . For loopAbort_Addr …IRQ_Addr …FIQ_Addr …

Install an Exception Handler: Method

Vector_Init_BlockLDR PC, Reset_AddrLDR PC, Undefined_AddrLDR PC, SWI_AddrLDR PC, Prefetch_AddrLDR PC, Abort_AddrNOP ;Reserved vectorLDR PC, IRQ_AddrLDR PC, FIQ_Addr

Reset_Addr DCD Start_BootUndefined_Addr DCD Undefined_HandlerSWI_Addr DCD SWI_HandlerPrefetch_Addr DCD Prefetch_HandlerAbort_Addr DCD Abort_Handler

DCD 0 ;Reserved vectorIRQ_Addr DCD IRQ_HandlerFIQ_Addr DCD FIQ_Handle

Start_Boot LDR …Undefined_Handler

B . (for loop)

SWI Exception and HandlerSWI Exception and Handler

Top-Level SWI Handlers The SWI number is stored in bits 0-23 of t

he instruction Save all other r0~r12 and lr to the stack Calculate the SWI number Jump Your Handler Return

void __swi(n) SWI_Name(void); for C Call

SWI_Handler FlowSWI_Handler ; top-level handler

STMFD sp!,{r0-r12,lr} ; Store registers.LDR r0,[lr,#-4] ; Calculate address of SWI

instruction; and load it into r0.

BIC r0,r0,#0xff000000 ; Mask off top 8 bits of instruction

;to give SWI number.;; Use value in r0 to determine which SWI routine to exe

cute.; BNE after

; Branch You Handler ; ; Branch your Handler LDMFD sp!, {r0-r12,pc}^ ; Restore registers and return

IRQ Handler Flow

IRQ_HandlerIRQ_Handler ; top-level handler; top-level handlerSTMFD sp!,{r0-r12,lr} STMFD sp!,{r0-r12,lr} ; Store registers.; Store registers.BL ISR_IRQBL ISR_IRQLDMFD sp!, {r0-r12,pc} LDMFD sp!, {r0-r12,pc} ; Restore registers and return; Restore registers and returnSUBS pc, lr, #4SUBS pc, lr, #4

S3C4510B Interrupt Sources

S3C4510B Interrupt Sources

Samsung S3C4510B Samsung S3C4510B InterruptInterruptControllerController

Five special registers used to control the interrupt generation and handling Interrupt mode register

Defines the interrupt mode, IRQ(0) or FIQ(1), for each interrupt source.

Interrupt pending register Indicates that an interrupt request is pending

Interrupt mask register The current interrupt is disabled if the corresponding mask

bit is "1“ If the global mask bit (bit 21) is set to "1", no interrupts

are serviced. Interrupt priority registers Interrupt offset register

Determine the highest priority among the pending interrupts.

Interrupt Mask Register Interrupt Mask Register (INTMSK)(INTMSK)

If global mask bit (bit 21) is 1, no interrupts are serviced

If bit is 1, the interrupt is not serviced by the CPU when the corresponding interrupt is generated

Interrupt pending Interrupt pending registerregister

Each of the 21 bits corresponds to an Each of the 21 bits corresponds to an interrupt sourceinterrupt source The service routine must then clear the pe

nding condition by writing a 1 to the appropriate pending bit at start.

#define Clear_PendingBit(n) INTPND_REG=(1<<n)#define Clear_PendingBit(n) INTPND_REG=(1<<n)

Interrupt offset registerInterrupt offset register

Contains the interrupt offset address of the interrupt Hold the highest priority among the pending inHold the highest priority among the pending in

terruptsterrupts The content of the interrupt offset address is "b

it position value of the interrupt source << 2“ You can read this register to get the IRQNumbe

r #define INTOFFSET REG32(SYS_BASE+0x4024)

int currentIRQnumber=INTOFFSET >> 2;

32-BIT TIMERS

INTERVAL MODE OPERATIONINTERVAL MODE OPERATION fTOUT = fMCLK / Timer data value Example. 2 = 50 MHz /25 MHz 25MHz=2FAF080

TOGGLE MODE OPERATION fTOUT = fMCLK / (2 * Timer data value)

TIMER MODE REGISTERTIMER MODE REGISTER

The timer mode register, TMOD, is used to control the operation of the two 32-bit timers

[0] Timer 0 enable (TE0)0 = Disable timer 01 = Enable timer 0[1] Timer 0 mode selection (TMD0)0 = Interval mode1 = Toggle mode[2] Timer 0 initial TOUT0 value (TCLR0)0 = Initial TOUT0 is 0 in toggle mode1 = Initial TOUT0 is 1 in toggle mode

#define TMOD REG32(SYS_BASE+0x6000)

TIMER DATA REGISTERS

#define TDATA0 REG32(SYS_BASE+0x6004) #define TDATA0 REG32(SYS_BASE+0x6004)

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ReferenceReference

Samsung S3C4510B User’s ManualSamsung S3C4510B User’s Manual http://www.samsung.com/Products/Semic

onductor/SystemLSI/Networks/PersonalNTASSP/CommunicationProcessor/S3C4510B/S3C4510B.htm

Chapter 7 ARM Exceptions ARM 原理與實作 – 以網路 SOC 為例