BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

First Semester 2011-2012

Computer Organization & Architecture (IS C351)

Lab Sheet – 9 [Data Flow Modeling]

Data Flow modeling: For small circuits, the gate-level modeling approach works

very well because the number of gates is limited and the designer can instantiate and connect every gate individually. Also, gate-level modeling is very intuitive to a designer with a basic knowledge of digital logic design. However, in complex designs the number of gates is very large. Thus, designers can design more effectively if they

concentrate on implementing the function at a level of abstraction higher than gate level. Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a

design processes data rather than instantiation of individual gates.

Continuous Assignment: A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net. This assignment replaces gates in the description of the circuit and describes the circuit at a higher level of abstraction. The assignment statement starts with the keyword assign.

Syntax:

assign <net> <delay> = <list of assignments>

Example: assign out = in1 & in2;

//any change in values of in1 and in2, force to compute the RHS expression and assigned to out assign #10 out = in1 & in2;

// any change in the values of in1 and in2 will result in a delay of 10 time units before re-computation of the expression on RHS, and result will be assigned to out

Operators: The various operators that are conventionally used in C language namely binary operators ( +, -, *, /, %) , unary arithmetic operator (-), relational operators ( >, < , >=, <=, ==, !=), logical operator ( ! , &&, || ), bitwise operators ( ~, & , |, ^, ~&, ~|, ~^ or ^~), can be used in Verilog with the exception of ++

and –- operator. Unary reduction operators ( & , |, ^, ~&, ~|, ~^ ) are also used. The difference between the two is given in the following example. The bitwise operator ‘&’ act on 2 operands finding the bitwise logical and of the 2 values whereas the unary reduction operator ‘&’ operates on one operand finding the logical

and of all the bits of that single operand. The other operators present in Verilog are:

=== Case equality which bitwise comparison of x and z values also. All bits must match for equality. Returns either TRUE or FALSE.

!== Case inequality { , } Concatenation that joins bits together with 2 or more comma-separated

expressions, e.g. {A [0], B [1:7]} concatenates the zero bit of A to bits 1 to 7 of B.

<< Shift left which fills vacated bit positions with zeros,

e. g. A = A << 2; //shifts A two bits to left with zero fill. >> Shift right that fills vacated bit positions with zeros.

?: Conditional operator that assigns one of two values depending on the conditional expression. Ex: A = C>D ? B+3: B-2 means if C greater than D, the value of A is

B+3 otherwise B-2. Data Types: In addition to data types like reg and wire, Verilog also supports some abstract data types like integer and time for programming purpose. Verilog also

supports integer and real declarations as in C language. Single-dimensional arrays of integers, reg and wire can be used. Multi-dimensional arrays are not permitted.

e.g. integer count[0:7], reg count[0:7], wire count[0:7].

Delays: Delay values control the time between the change in a right-hand-side operand and when the new value is assigned to the left-hand side. Three ways of specifying delays in continuous assignment statements are regular assignment delay,

implicit continuous assignment delay, and net declaration delay.

Regular assignment delay: The first method is to assign a delay value in a continuous assignment statement. The delay value is specified after the keyword assign. Any change in values of in1 or in2 will result in a delay of 10 time units before re-computation of the expression in1 & in2, and the result will be assigned to

out. If in1 or in2 changes value again before 10 time units when the result propagates to out, the values of in1 and in2 at the time of re-computation are considered. This property is called inertial delay. An input pulse that is shorter than

the delay of the assignment statement does not propagate to the output.

assign #5 out = a & b; // Delay in a continuous assign Implicit continuous assignment delay: An equivalent method is to use an implicit continuous assignment to specify both delay and an assignment on the net.

e.g. wire #5 out = in1 & in2; //implicit continuous assignment delay Same as

wire out; assign # 10 out = in1& in2; Net Declaration Delay: A delay can be specified on a net when it is declared

without putting continuous assignment on the net. If a delay is specified on a net out, then any value change applied to the net out is delayed accordingly. Net declaration delays can also be used in gate-level modeling. Net delays

wire # 10 out; assign out = in1 & in2; The above statement has the same effect as following.

wire out; assign #10 out= in1 & in2; Expression: Dataflow modeling describes the design in terms of expressions instead

of primitive gates. Expressions, operators, and operands form the basis of dataflow modeling.

Expressions are constructs that combine operators and operands to produce a result.

// Examples of expression Combines operands and operators

a ^ b; addr1[20:17] + addr2[20:17]; in1 | in2;

Example1:

The 2:1 Multiplexer can be written as F= (S&A)|(~S&B);

Or F = S ? A : B; Code:

module mux2to1_df (a,b,s,f); input a,b,s; output f;

assign f = s ? a : b; endmodule Simulation

module muxdftestbench; reg a,b,s;

wire f; mux2to1_df mux_df (a,b,s,f); initial

begin $monitor(,$time," a=%b, b=%b, s=%b f=%b",a,b,s,f); #0 a=1'b0;b=1'b1; #2 s=1'b1;

#5 s=1'b0; #10 a=1'b1;b=1'b0; #15 s=1'b1;

#20 s=1'b0; #100 $finish; end endmodule

S

F B

A

Example2

D flip-flop

1) module D_FF(Q,Q_bar,D,Clk);

2) input D,Clk; 3) output Q,Q_bar; 4) wire Temp1,Temp2;

5) assign Temp1 = ~(D & Clk),

Temp2 = ~(Clk & Temp1), Q = ~(Temp1 & Q_bar),

Q_bar = ~(Temp2 & Q);

6) endmodule

7) module DFFTestbench; 8) reg D,Clk; 9) wire Q,Q_bar;

10) D_FF D_FF1(Q,Q_bar,D,Clk);

11) initial

12) begin 13) $monitor($time,"Clk=%b, D=%b, Q=%b, Q_bar=%b",Clk, D, Q, Q_bar); 14) end

15) initial 16) begin 17) D=1'b1; 18) #5 D=1'b0;

19) #5 D=1'b1; 20) end

21) initial 22) begin 23) Clk=1'b1; 24) forever #1 Clk=~Clk;

25) end

26) initial 27) begin 28) #12 $finish; 29) end

30) endmodule In the above code Clk is clock to drive the circuit. Now look at line number 24, this statement toggle the clock i.e. this statement makes clock input 0 and 1

continuously after 1 time unit. Another notable statement is in line number 28, it bound the program run time means program will run for 12 time units. If we don’t write this statement then program will run infinitely because of line number 24.

Lab Exercise:

1) Implement BCD to gray code conversion using Dataflow modeling. Write a test bench which includes all cases and checks the correctness of the design.

2) Implement a 1-bit full adder using Data flow model. Write a test bench which includes all cases and checks the correctness of the design.

3) Design a 4-bit adder by using 1-bit adder. Write a test bench which checks the correctness of the design.

4) Design a 4 – bit Adder / Subtractor with a select line S. Write a test bench which checks the correctness of the design.

5) Implement a 4 bit magnitude comparator using Dataflow modeling. Write a test bench to check the correctness of the design.

Circuit Diagrams

(1) 4 bits Binary to Gray Code

(2)4 bit magnitude comparator

(3)1 bit full adder

(4)4bit full adder

(5)A 4-bit adder/ subtractor

______________________