GIF-4201/GEL-7016 (Micro-électronique)

Lab 1: An Introduction to Cadence

Schematic, simulation and layout

Gabriel Gagnon-Turcotte, Mehdi Noormohammadi Khiarak and

Benoit Gosselin

Department of Electrical & Computer Engineering

Laval University, Quebec City, Canada

January 2018

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Version history

Version Description Authors Date

2 Major revision

G. Gagnon-Turcotte, M.

Noormohammadi Khiarak

and Benoit Gosselin

Nov. 23 2017

1 Original version

Farhad S.H. Lori and

Benoit Gosselin Jan. 21 2012

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Contents Introduction ..................................................................................................................................... 2

Objectives of this Lab ..................................................................................................................... 2

Setting your environment for running Cadence remotely............................................................... 2

The Library manager....................................................................................................................... 4

Create a new library ........................................................................................................................ 5

Part One: Schematic design and simulation.................................................................................... 5

Create a new schematic ............................................................................................................... 6

Draw a new schematic ................................................................................................................ 7

Perform a DC simulation ............................................................................................................ 9

DC parameters of the nfet and pfet transistors inside the inverter ............................................ 11

Plot the Vi-Vo curve of the inverter ......................................................................................... 12

Parametric simulation (part 1) .................................................................................................. 14

Parametric simulation (part 2) .................................................................................................. 15

Transient Simulation ................................................................................................................. 18

Part Two: Symbol View................................................................................................................ 19

Creating the schematic view ..................................................................................................... 19

Creating the symbol view from the schematic view ................................................................. 21

Part three: Layout and extraction .................................................................................................. 22

Create a new layout cell view ................................................................................................... 22

Drawing a nfet transistor ........................................................................................................... 24

Design Rule Checking (DRC) .................................................................................................. 28

Drawing a pfet transistor ........................................................................................................... 28

Connect the inverter and add pins ............................................................................................. 31

Layout extraction ...................................................................................................................... 32

Post layout simulation ............................................................................................................... 33

Create a layout from a schematic .............................................................................................. 35

Layout Versus Schematic (LVS) .............................................................................................. 37

Report ............................................................................................................................................ 40

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Introduction

Cadence is an Electronic Design Automation (EDA) environment that integrates several design

tools in a single design suite.

This course includes four lab exercises in which you will use the Cadence tools to design CMOS

integrated circuits. The lab exercises will guide you through mastering schematic entry, layout,

simulation, post layout simulation and layout versus schematics. Each lab will consist in

designing and simulating different microelectronic building blocks that you will reuse during this

course. So, make sure to carefully achieve all the requested items. The teaching assistant (TA)

will assist you in the PLT-0105 during the time period assigned to this practical work.

Objectives of this Lab

This first Lab will give you an introduction to the Cadence Custom IC Design Environment, and

will describe all the steps for running the Cadence tools at the Department of Electrical and

Computer Engineering, Laval University, computer Lab PLT-0105.

In the first part, you will learn how to use the schematic editing tool to create and simulate a

basic circuit schematic using the CMOS 180-nm TSMC design kit. Secondly, you will learn

about MOS transistor model parameters inside a digital circuit. In the second part, you will learn

how create a symbol from a schematic view. Then, in the third part you will learn to use the

layout editing tool to draw circuits and to generate netlists. In this part, you will draw an inverter

using the Virtuoso layout editor, extract the transistors characteristics, and create test benches.

Setting your environment for running Cadence remotely

This section will guide you through all the steps to run Cadence remotely over SSH through a

Linux terminal. Do the following steps:

Step 1: Start a Linux session in the computer Lab PLT-0105 and logon to your Linux account

using your U. Laval IDUL/NIP.

Step 2: Open a new terminal window. Select Applications-> System Tools -> terminal

Step 3: In the terminal window, type

bash-4.0$ ssh -X cmc-node-1.gel.ulaval.ca -l your_username

and press the Enter key. If you get the following message: “Are you sure you want to continue

connecting (yes/no)?” type yes and then press the Enter key.

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Step 4: Enter your password and press the Enter key. You should now be connected to cmc-

node-1 over SSH.

Step 5: Create a working directory by typing the following commands into the terminal:

bash-4.0$ mkdir Labs

bash-4.0$ cd Labs

bash-4.0$ mkdir Lab1

bash-4.0$ cd Lab1

and press the Enter key.

Step 6: For Launching Cadence, type “startCds” in the terminal window and press the Enter key.

From the cmc_kits_view pop-up window, choose the180-nm technology kit and click run.

The Command Interpreter Window (CIW) is opening. The CIW gives an access to the multiple

tools of the Cadence suite.

Fig 1: Select the TSMC 180-nm technology kit and click “run”.

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Fig. 2: The CIW window.

The Library manager

A library is a collection of cells, such as NOT, AND, NAND, etc. These cells contain several

views, including “schematic”, “layout”, “extracted” and “symbol”.

The simplest way to navigate through and manage the default kit libraries or the user custom

libraries is to use the Library Manager.

Open the Library manager: In the CIW window, go to tools -> library manager. The library

manager window opens, has shown in Fig. 3. The left column is listing the available libraries for

the current kit. The “analogLib” and the “cmosp18” libraries contain all the necessary

components to complete this Lab. The center column is listing the available cells for each

library. A cell is a specific building block i.e. a circuit that belongs to a specific library. The right

column is listing the several available views of each cell (extracted, layout, schematic, etc.).

Extracted view: contains a representation of the netlist that has been extracted from a

layout view.

Layout view: contains the mask representations of the silicon devices and wiring.

Schematic view: contains the schematic representation of a cell.

Symbol view: contains a symbolic representation of a cell to be instantiated in a top-level

schematic view.

Behavioural view: contains a HDL description of the cell.

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Fig.3: Library Manager Window.

Create a new library

After having opened the Library manager, do the following steps to create your new library:

Step 1: In the Library manager, go to file -> new library. Then, type in the name of the new

library, for example Lab1, and click OK.

Step 2: Select “attach to an existing techfile”, and click OK.

Step 3: In the new pop-up window, select “cmosp18” as the technology file, and then click OK.

The library Lab1 is now listed in the Library manager.

Part One: Schematic design and simulation

In this part, you will learn how to create a simple schematic with the Schematic editor and how

to simulate a digital inverter using Spectre. You will learn how to simulate the characteristics of

a CMOS circuit and how to obtain its parameters. In order to work efficiently with the Schematic

editor, pay attention to memorize the shortcuts for the most frequently used commands shown in

Table 1.

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Table 1. Shortcut keys for the Schematic editor.

Shortcut key Function

i add instance

w wire up

p add pin

f fit all

q edit properties

c copy

l wire label

r rotate

u undo

U redo

m move

Esc cancel previous command

Create a new schematic

Do the following steps to create a new schematic cell view:

Step 1: In the Library manager, select your new Library (Lab1), then go to File -> new -> cell

view.

Step 2: In the pop-up window, type in a new cell name, like cmos_inv_schem, make sure to

select composer-schematic (selected by default), and click Ok.

Step 3: A schematic editor window appears (Fig. 4).

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Fig.4: A new schematic editing window.

Draw a new schematic

We will instantiate a nfet and a pfet transistor to create the inverter and build a simple test bench

in order to obtain its parameters and DC characteristics. Do the following steps to create the new

schematic:

Step 1: For adding an nfet transistor in the new schematic, type "i" with the schematic window

opened. A new pop-up window appears.

Step 2: Click Browse. The Library manager pops up. Select the “cmops18” library. Select the

nfet cell, and choose the symbol view.

Step 3: Go back into the schematic window and place the component with a left click of the

mouse.

Step 4: Select this nfet in the schematic, and press “q”. In the “instance properties” window,

change W to 1.8um and keep L to 180nm (Fig.5 left), then press Esc to deselect the nfet

transistor.

Step 5: Repeat steps 1-3 to add a pfet transistor. Select this pfet in the schematic, and press “q”.

In the “instance properties” window, change W to 2.52um and keep L to 180nm (Fig.5 right),

then press Esc to deselect the pfet transistor.

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Step 6: Add DC voltage sources to the schematic and wire them up. First, press “i” and click

Browse in the “add new instance” window. In the “cmosp18” library select the “vdc” cell and its

symbol view. In the “property” window, type in “1.8 V” for the parameter “dc voltage”. Add two

voltage sources in the schematic, like in Fig. 6. Press Esc to deselect any component from the

schematic. Click “w” and start wiring up the circuit. For drawing wires, click on each terminal

(red square) and move the mouse to the other desired terminal.

Step 7: Add a tie down to the common node (Fig. 6). Type “i” or use and add select the

“tiedown” cell, symbol view, from the “cmosp18” Library.

Step 8: Add a net name between the nfet and the pfet. To do so, select the icon in the left

menu and type “Vo“ in the “name“ field. Click “Hide“, and place the net in the schematic. Add

the net "Vi" between the gates of the transistors and the input source using the same procedure.

Step 9: Make sure that your schematic is identical to Fig. 6 and press “x” to save your work, or

alternatively, select design -> save and check.

Fig.5: Change W and L of the transistor in the properties window (left: nfet, right: pfet).

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Fig. 6: Schematic of the test bench circuit.

Perform a DC simulation

We will perform a DC simulation to study the basic DC parameters of the MOSFETs.

Step 1: With the schematic window of the test bench opened, go to tool -> analog environment.

The Analog design environment (ADE) window pops up. The important sections of this tool are

indicated in Fig. 7 and described in Table 2.

Table 2. Frequently used menus in the Analog design environment window.

Menu Description

Session This menu allows saving and loading your simulation settings, so you do not need to it

setup again next time you open the ADE. For saving the simulation settings, go to session-

>save state, write the session name in the save as box and press Ok. For loading a saved

state, go to session->load state select the state to load and press Ok.

Setup Select your simulator and load your model library from this menu.

Analyses Choose the different analyses to enable, or disable from this menu.

Variables This menu allows copying your variables from the cellview in order to print, edit, delete,

find or save them.

Tools The menu contains useful tools such as the Parametric and the Corner analyses. The

Calculator is available from this menu.

Step 2: Choose a model file in order to simulate the nfet with the right parameters. In the Analog

design environment window, go to the Setup menu, select “model library”, and type in

CMC/kits/cmosp18.5.2/models/spectre/spectre445_mixed/mm018.csc

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Step 3: Type in “tt” in the section box and click the add button. Then, click OK before closing

the windows.

Step 4: Go to session -> options and choose AWD for waveform tool. Analog waveform display

(AWD) is a waveform display tool that is included with the spectre simulator in order to print

simulation results.

Step 5: Go to the Analyses menu, select Analyses -> choose. In the Choosing Analyses window,

click dc at Analysis and select save DC operating point. Click OK.

Step 6: Click the traffic green light button to run the simulation. Messages will appear in the

CIW window indicating that the simulation has completed successfully (Fig. 8).

Fig.7: The Analog design environment window.

Fig. 8: The CIW indicates that the simulation has completed successfully.

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DC parameters of the nfet and pfet transistors inside the inverter

This section shows how to obtain transistor parameters such as Vth, Vds and the operating region

in the Virtuoso schematic editor.

Step 1: From the schematic editor window, go to edit -> component display. The “Edit

component display” window appears. Select the “nfet” transistor in the schematic window. The

name of the selected transistor now appears in the top of the “Edit component display” window.

Step 2: Choose “parameter” in the “Select Label” section. Selecting “model parameter” in the

“Parameter Labels” section will give access to the several Spectre parameters of the transistor.

Selecting “operating point” will give access to the DC parameters of the transistor. Change ids to

vth and vgs to region in the “Display Value Only” section (Fig. 9). Before clicking OK, select the

“pfet” transistor in the schematic window. Again, change ids to vth and vgs to region in the

“Display Value Only” section and click OK. Back in the schematic window, the values of the

selected type of parameters are printed besides each device of the schematic.

Answer these questions in your report:

Put a screenshot of your schematic into your report.

Q1: Report the DC parameters Vth, Vds and the operating region of the simulated

transistors (Tips: see Fig. 9, the operating region are as follow: 0: cut-off, 1: triode (or

linear), 2: saturation, 3: subthreshold and breakdown).

Q2: Explain why the transistors are in their respective region. Your answer should refer to

Vth, Vds and Vgs (see section 2.3.2 of your reference book).

Q3: In the schematic window, change the parameter "DC voltage" of the source connected

to the gates to 0 V and re-run the DC simulation (green light button, don't forget to save

the schematic before simulating). Report the new DC parameters Vth, Vds and the

operating region of the simulated transistors. Comment the changes of Vds and the

operating region.

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Fig. 9: Display the DC operating point of the transistor.

Plot the Vi-Vo curve of the inverter

In order to plot the Vi-Vo curve of the inverter you should perform a DC simulation and sweep

the voltage of the input source (Vi) to obtain the voltage transfer curve (VTC). Follow these

steps:

Step 1: In the Analog design environment window, go to Analyses -> choose. Select the dc

Analysis, click "Component Parameter" in the "Sweep Variable" field and click the “Select

Component” button. In the schematic window, select with the mouse the voltage source that is

connected to gate of the transistors (i.e., the V1 component in Fig. 6). Select dc voltage in the

pop up window, and click Ok. Under “Sweep Range”, indicate the values for the Start and Stop

voltages (Fig. 10).

Step 2: In the Analog design environment window, go to outputs -> to be plotted -> select on

schematic, and then click on the "Vo" net. The color of the net will change. Press "Esc" to exit

the net selection mode.

Step 3: In the Analog design environment window, click on the “Run Simulation” button on the

right (the green light) or go to Simulation -> Run. After the simulation finishes, a “waveform

window” pops up showing a curve of Vo versus Vi (Fig. 11).

Q4: Report the VTC waveform in you report and identify where the nfet and pfet switch in

subthreshold region (Tips: use the Vth find at Q1).

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Q5: Find the Vi voltage that gives Vo = 0.9 V. Go in the schematic window and change the

"DC voltage" of the source connected to the gates to this voltage and re-run the DC

simulation. Report the operating regions of the transistors and the power consumed by the

inverter with this input voltage (Tips: the current should be displayed beside the V0

source). Note that the dynamic power consumed by the logic gates when connecting VDD to

VSS across the transistors during the switching states is called "dynamic cell internal

power".

Fig. 10: DC sweep simulation setup.

Fig. 11: The Vi-Vo curve of the inverter printed in a waveform window.

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Parametric simulation (part 1)

A parametric simulation is very useful in order to obtain the Vi-Vo curve of the inverter for

different transistor sizes.

Step 1: In the schematic editing window, select the pfet and press “q” to open its “object

properties” window. Put “2.52u*Factor” has width, and click ok.

Step 2: In the Analog design environment window, go to variables -> copy from cell view. The

variable "Factor" appears in variable list. Double click on it and put 1 as initial value. Then, click

OK. This means the width of the pfet transistor will be multiplied by 1.

Step 3: In the Analog design environment window, select tools -> parametric analysis. The

parametric analysis window appears. Go to setup -> pick name for variable -> sweep 1. Select

"Factor" and click OK. Configure the “Range Type” as indicated in Fig. 12. Click “Analysis”

and select “Start”.

The parametric simulation is running. When the simulation is finished, you can plot the Vi-Vo

curves for different value of transistor sizes (Fig. 13).

Q6: What causes the voltage drift in Fig. 13. (Tips: look at the Id formula in the active

region, i.e, formula 2.34 in your reference book. Be aware that β is proportional to the ratio

width/length of the transistors and don't forget that Id is the same for the pfet and nfet).

Fig. 12: Parametric analysis setup window.

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Fig. 13: Vi-Vo curve of the inverter for different pfet sizes.

Parametric simulation (part 2)

You will use a parametric simulation in order to obtain the Current-Vi curve of the inverter for

different transistor sizes.

Step 1: In the schematic editing window, select the nfet and press “q” to open its “object

properties” window. Put “1.8u*Factor” has width, and click ok.

Step 2: In the Analog design environment window, select the Vo output to be plotted and click

the icon to remove it. Go to outputs -> to be plotted -> select on schematic, and then

click on the red square under the V0 source. A circle around it should appears, it means the

current flowing through the source (and the transistors) will be plotted. Press "Esc" to exit the net

selection mode.

Step 3: In the Analog design environment window, select tools -> parametric analysis. The

parametric analysis window appears. Go to setup -> pick name for variable -> sweep 1. Select

"Factor" and click OK. Again, configure the “Range Type” as indicated in Fig. 12. Click

“Analysis” and select “Start”.

The parametric simulation is running. When the simulation is finished, you can plot the Current-

Vi curves for different value of transistor sizes (Fig. 14).

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Q6: Plot the power consumption characteristics of the inverter for different values of Vi

and transistor sizes by using the Calculator.

Tip: There are different ways of plotting the results after a simulation. After running the

simulation, choose Tools -> Calculator in the Analog design environment window. The

Calculator window appears. A summary of the buttons available in the Calculator is provided in

Fig. 15 and described in Table 3. To plot a waveform, first select the type of waveform to print

by clicking the corresponding button. Then in the schematic view, click on the wire (voltages) or

terminal (currents) to plot the selected waveform. Finally, select the “plot” button in the

Calculator to print the selected waveform.

For example, for plotting the plot Power-Vi curve with the Calculator after having run the

necessary simulation detailed above, select the button "is" in the calculator (the parameter is

belongs to a sweep dc simulation). Then click on the on the red square under the V0 source in the

schematic. In the calculator input form, enter *1.8 (it should be IS("/V0/MINUS")*1.8). Finally

click “erplot” in the calculator to print the results. Be careful, the calculator is by default in RPN

mode, to switch in normal mode select Options -> Set Algebraic.

Table 3. Summary of the main buttons in the Calculator.

Buttons Description

Vt Nodal voltage (transient analysis)

It Terminal current (transient analysis)

Vf Nodal voltage (AC analysis)

If Terminal current (AC analysis)

Vs Nodal voltage (DC sweep)

Is Terminal current (DC sweep)

vdc Nodal voltage (quiescent value)

Idc Terminal current (quiescent value) plot To plot the waveform without removing already displayed waveforms

erplot To remove displayed waveforms and plot the selected one

Special Functions Perform different functions on the selected waveform (multiply, divide, dB

calculation, DFT, THD calculation, bandwidth, maximum and minimum

calculation, etc).

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Fig. 14: Current-Vi curve of the inverter for different transistor sizes.

Fig. 15: The Calculator window.

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Transient Simulation

Step 1: In the schematic windows, select the "V1" source and click the icon to remove it.

Then, click "i", click browse, search for the "vpulse" source in the "cmosp18" library and select

"symbol" in the right column. Replace the V1 symbol by the "vpulse" symbol and press "Esc".

Step 2: Select the "vpulse" source and press "q". Change "Rise time" and "Fall time" to 100p,

"Pulse width" to 1n and "Period" to 2n. Then, click "OK".

Step 3: Select the "pfet" transistor and press "q". Change "Length" to 180n*Factor. Then, click

"OK". Do the same for the "nfet".

Step 4: Create a new inverter by adding a pfet and a nfet symbols. Change the pfet and nfet

width to 2.52u and 1.8u respectively. Place this new inverter in a way that your schematic looks

like Fig. 16. Your circuit is now a digital buffer.

Step 5: In the Analog design environment window, select the "dc" analyses and click the

icon to remove it. Select Analyses -> Choose. Select "tran" (if not already selected), change

"Stop Time" to 5n and select "conservative" in the "Transient Analysis" section. Then, click

"OK". Info: A transient simulation can take a lot time to be simulated depending on the

complexity of the circuit. To reduce the simulation time, the accuracy of the simulation can be

lowered to "moderate" or "liberal". For simple circuits, always use "conservative".

Step 6: In the Analog design environment window, go to outputs -> to be plotted -> select on

schematic, and then click on the "Vi" net. The color of the net will change. Press "Esc" to exit

the net selection mode. Your Analog design environment window should looks like Fig. 17.

Step 7: In the Analog design environment window, select tools -> parametric analysis. The

parametric analysis window appears. Go to setup -> pick name for variable -> sweep 1. Select

"Factor" and click OK. Configure the “Range Type” from 1 to 8. Click “Analysis” and select

“Start”.

The parametric simulation is running. When the simulation is finished, you can plot the Vi and

the Vo curves for different value of transistor sizes.

Q7: Report the Vi and the Vo waveforms. Explain the phenomenon you are seeing. What

impact the size of the transistors can have on the speed of a digital circuit? (Tips: refer to

the "Simple MOS Capacitance Models" section of you reference book (p. 68))

Q8: Determine the gate capacitance (Cg) of the nfet and pfet transistors having W/L of

1.8u/180n and 2.52u/180n respectively. Refer to page 65 of the reference book, and use

tox=4.08n.

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Fig. 16: Schematic of the test bench circuit with a pulsed input.

Fig.17: The Analog design environment window for the transient simulation.

Part Two: Symbol View

In this part, you will create the symbol view of a CMOS inverter.

Creating the schematic view

Step 1: In the Library manager, select your new Library (Lab1), then go to File -> new -> cell

view.

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Step 2: In the pop-up window, type in a new cell name, like cmos_inv_w_symbol, make sure to

select composer-schematic (selected by default), and click Ok.

Step 3: Add the symbol views of an nfet and a pfet cell from the cmosp18 library. Make sure the

MOSFETs have the following properties:

Table 1. Parameters of transistors.

Nfet Pfet

Name M1 Name M0

Width 1.8 µm Width 2.52 µm

Length 180 nm Length 180 nm

Step 4: Click the icon and enter the pin name "Vin". Select the direction "input". Make sure

"Attach Net Expression" is set to "No". Then, click "Hide" and place the pin in the schematic.

Step 5: Repeat step 3 to generate the pins listed in table 2.

Table 2. List of pins in the schematic.

Pin name Direction

Vin input

Vout output

Vdd inputoutput

Vss inputoutput

Step 6: Wire up the transistors and the pins as shown in Fig. 18. Your inverter schematic is now

ready. To save your schematic, click on “design-> check and save”

Fig. 18: Wire up components in schematic view

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Creating the symbol view from the schematic view

To make a symbol from a schematic view, select design -> create cellview -> from cellview in

the Virtuoso schematic editor with your schematic of the inverter opened. Click Ok after the

“cellview from cellview” dialog box appears. Rearrange pins in the “symbol generation options”

dialog box as follow and click Ok.

Table 3. Pin position of the schematic.

Pin position Pin name

left pin Vin

right pin Vout

top pin Vdd

bottom pin Vss

A symbol of the inverter has been created. The default symbol is a rectangle. Edit your symbol

accordingly to the symbol shown in Fig. 19.

Tip: In order to create the symbol of the inverter, separate the pins from the default symbol.

Then, delete the rectangle. After that, use Add -> shape -> line to draw a triangle, and then, Add

-> shape -> circle to draw a circle. Finally, connect the pins to the triangle and to the circle.

Fig. 19: Symbol view of an inverter.

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Part three: Layout and extraction

In this part you will learn the basics of physical design through the implementation of the layout

of an inverter. You will learn how to use the Cadence Virtuoso layout editor to draw MOS

transistors, to generate a circuit netlists and to create test benches. For more details about CMOS

layers, refer to your reference book. Also, the complete TSMC 180-nm documentation including

design rules and layer definitions is available at:

/CMC/kits/cmosp18/doc/CMOSP18designRulesLogic.pdf.

In order to work efficiently with the layout editor, pay attention to memorize the shortcuts for the

most frequently used commands shown in Table 4.

Table 4. Shortcut keys for the Layout editor.

Shortcut key Function

del Delete

s Stretch

c Copy

u Undo

U Redo

z + left click Zoom in

i Add instance

p Add pin

k Ruler

K Remove ruler

Shift + z Zoom out

o Contact

Esc Cancel previous command

Create a new layout cell view

Add a new layout cell view to your inverter designed in Part 2.

Step 1: In the CIW window, select Tools -> Library Manager and go to your Lab1 library.

Step 2: Select file -> new cell view in the Library Manager. In the pop-up window, select your

library, select the cell cmos_inv_w_symbol and select Virtuoso for the tool. Click OK. The

Layout editor opens along with the Layer Select Window (LSW). The LSW window is listing all

the available CMOS layers for a given process. Also, it let the user select the current layer in use

in the layout editor. In fact, the layout of a CMOS circuit is drawn layer by layer. The LSW can

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also be used to restrict the type of layers that are visible (AV, NV) or selectable (AS, NS). To

select a layer, simply click on the desired layer listed in the LSW.

WARNING: Only layers with the drw property will be fabricated. Other types of layers are for

labelling, highlighting errors, and documentation. Be sure to always select the layer with the

"drw" property before drawing.

The TSMC 180-nm process is using a P-type substrate. It means the black background in the

layout window is for the P-substrate. Thus, you can draw nfet transistors directly in it, but pfet

transistors must be placed inside an Nwell layer. Fig.20 shows the different layers required to

build a pfet and an nfet transistor. They are described below:

Table 5. Description of the layers of the TSMC CMOS 180-nm kit.

Layer Description

Nwell The N-well layer is used to create pfet in p substrate process.

Active Silicon devices are built on active area. This layer defines an oxide-free

region, where will be implemented a MOSFET.

Poly1 This layer defines the polysilicon gate of the transistor.

Nplus The Nplus layer defines a n+ doped silicon region. It is used to define the

drain and the source of an nfet and the body connection of a pfet.

Metal1 The Metal1 layer is the first metal layer. There are six different metal layers

in the TSMC 180 nm process.

Contact The Contact layer is used to connect different types of layers together.

Pplus The Pplus layer defines a p+ doped silicon region. It is used to define the

drain and the source of a pfet and the body connection of an nfet.

Fig.20: The LSW includes all the necessary layers to draw the mask.

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Drawing a nfet transistor

To draw an nfet transistor, you must first select the active layer from the LSW window (Fig. 20)

and use the create rectangle command (Create -> Rectangle) to draw the area circumscribed by

the transistor in the editor window. The steps to draw the nfet transistor are detailed bellow and

illustrated in Fig. 21.

Step 1: Select the Option -> Layout Editor, make sure "Gravity On" is NOT selected. Click

"OK".

Step 2: Draw the active layer to circumscribe the drain and source area

a) Select the active layer from the LSW window.

b) Select the Create -> Rectangle (or click the Rectangle icon from the side toolbar).

c) Using your mouse, draw the active layer in the Virtuoso layout editing window. The exact size

is not important but make sure it has a height of 1.8um (Fig. 21a). Once your rectangle is drawn,

select it and press "q". Then, you can precisely change its dimensions (the units are in um).

Step 3: Draw the Nplus layer to specify that it is a nfet device

a) Select the Nplus layer from the LSW window.

b) Select the Create -> Rectangle (or click the Rectangle icon from the side toolbar).

c) Using your mouse, draw the Nplus layer on the virtuoso layout editing window. It should

extend wider than the active layer to cover it completely (Fig. 21b).

Step 4: Draw a layer of poly to implement the gate terminal

a) Select the poly layer from the LSW window.

b) Select the Create -> Rectangle (or click the Rectangle icon from the side toolbar).

c) Using your mouse, draw a narrow layer of poly over the active and Nplus layers (Fig. 21c).

The poly layer must extend wider than both layers as shown in (Fig. 21c). This layer is

implementing the gate of the transistor. It separates the active layer into two parts which areas

will be the source and drain of the transistor, respectively. Make sure the width of the rectangle

is of 0.18um.

Step 5: Place contacts for gate, drain, and source terminals

a) Select the contact layer from the LSW window.

b) Select Create ->Rectangle (or click the Rectangle icon from the side toolbar).

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c) Using the mouse, draw contacts on both sides of the active layer (drain and source terminals),

as shown in Fig. 21d. The number of contacts should be as large as possible. The minimum size

of the contacts is determined by a design rule. It is 0.22µm × 0.22µm in the TSMC 180-nm

process (Fig. 21d). Use an M1-POLY contact to connect the gate of the nfet to a metal1 layer. To

place a contact, hit “o” while in the Layout editor. The “Create contact” dialog appears. Change

the contact type to M1-POLY and place the gate contact by clicking at the tip of the poly layer.

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Fig. 21: a) Drawing the active layer. b) covering the active layer with a Nplus layer. c) Drawing

the gate. d) Adding a contact layer.

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Step 6: Create the body terminal of the nfet transistor

To create the body of the nfet transistor, first put an active layer near the drawn transistor.

Second, cover it with a Pplus layer. Finally, put contacts. Refer to Fig. 22 for details.

Step 7: Connections to Metal1 layers

Connect the transistor terminals using Metal1 layer

a) Put a rectangle of metal1 on the gate contact (Metal1-Poly contact).

b) Connect the source contacts to the body contacts with a metal1 layer (It means source and

body of transistor connect internally. In next section, one pin (source-body) will be used

for them).

c) Put a rectangle of metal1 on the drain contacts.

Fig. 22: Layout of the nfet transistor.

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Design Rule Checking (DRC)

Before going any further with the layout, perform a Design Rule Check and correct any errors.

IC foundries have a set of design rules that ensure a design can be manufactured reliably. Run a

DRC check to verify that your layout does not violates any of these rules. Select Verify -> DRC

from the layout window and click the “Set Switches button”. Choose “no_antenna check” and

“ignore_substrate/well_soft_connectclick” and click OK. Refer to Fig. 23 for the correct

configuration. Click OK, in the DRC dialog to run the DRC check. Any errors will be reported in

the CIW window. Correct any error before going to the next step. The CIW console must report

0 error before moving forward, as shown in Fig. 24.

Drawing a pfet transistor

To draw an pfet transistor, you must first select the nwell layer from the LSW window (Fig. 20)

and use the create rectangle command (Create -> Rectangle) to draw the area circumscribed by

the transistor in the editor window. The steps to draw the nfet transistor are detailed bellow and

illustrated in Fig. 23.

Step 1: Draw the nwell layer to circumscribe the pfet transistor.

a) Select the nwell layer from the LSW window.

b) Select the Create -> Rectangle (or click the Rectangle icon from the side toolbar).

c) Using your mouse, draw the active layer in the Virtuoso layout editing window. The exact size

is not important, but make sure it is big enough to circumscribe the nfet transistor (Fig. 23a).

Step 2: Draw the active layer to circumscribe the drain and source area

a) Select the active layer from the LSW window.

b) Select the Create -> Rectangle (or click the Rectangle icon from the side toolbar).

c) Using your mouse, draw the active layer in the Virtuoso layout editing window. The exact size

is not important but make sure it has a height of 2.52um (Fig. 23a). Once your rectangle is

drawn, select it and press "q". Then, yoZu can precisely change its dimensions (the units are in

um).

Step 3: Draw the pplus layer to specify that it is a pfet device

a) Select the Pplus layer from the LSW window.

b) Select the Create -> Rectangle (or click the Rectangle icon from the side toolbar).

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c) Using your mouse, draw the Pplus layer on the virtuoso layout editing window. It should

extend wider than the active layer to cover it completely (Fig. 23b).

Step 4: Draw a layer of poly to implement the gate terminal

a) Select the poly layer from the LSW window.

b) Select the Create -> Rectangle (or click the Rectangle icon from the side toolbar).

c) Using your mouse, draw a narrow layer of poly over the active and Nplus layers (Fig. 23c).

The poly layer must extend wider than both layers as shown in (Fig. 23c). This layer is

implementing the gate of the transistor. It separates the active layer into two parts which areas

will be the source and drain of the transistor, respectively. Make sure the width of the rectangle

is of 0.18um.

Step 5: Place contacts for gate, drain, and source terminals

a) Select the contact layer from the LSW window.

b) Select Create ->Rectangle (or click the Rectangle icon from the side toolbar).

c) Using the mouse, draw contacts on both sides of the active layer (drain and source terminals),

as shown in Fig. 23d. The number of contacts should be as large as possible.

Step 6: Create the body terminal of the pfet transistor

To create the body of the pfet transistor, first put an active layer near the drawn transistor.

Second, cover it with a Nplus layer. Finally, put contacts. Refer to Fig. 24 for details.

Step 7: Connections to Metal1 layers

Connect the transistor terminals using Metal1 layer

a) Put a rectangle of metal1 on the gate contact (Metal1-Poly contact).

b) Connect the source contacts to the body contacts with a metal1 layer (It means source and

body of transistor connect internally. In next section, one pin (source-body) will be used

for them).

c) Put a rectangle of metal1 on the drain contacts.

Again, before going any further with the layout, perform another Design Rule Check and correct

any errors.

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Fig. 23: a) Drawing the active layer. b) covering the active layer with a Pplus layer. c) Drawing

the gate. d) Adding a contact layer.

Fig. 24: Layout of the pfet transistor.

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Connect the inverter and add pins

Step 1: Connect the gates of the nfet and pfet together using "metal1" layer as shown in Fig. 26.

Step 2: Connect the drain of the nfet and pfet together using "metal1" layer as shown in Fig. 26.

Step 3: In order to complete the layout of the inverter, you need to place pins to identify the

input (Vin), the output (Vout), and the power supply (VDD and VSS). Select Create -> Pin and

configure the “Create Shape Pin” dialog as shown in Fig. 25. In the “Terminal Names” box,

enter the name of the pin (or the pins separated by a space) that you want to place in the layout

view (Fig. 25). Select the “input” I/O type for all pins. Then, click on the metal1_T to place the

pin of Vin, and proceed similarly for the other pins. After completing these steps, your layout

should look like Fig. 26.

Fig.25: Create Shape Pin window for Vin, Vout, VDD and VSS.

Fig. 26: Layout of the inverter.

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Perform a final Design Rule Check and correct any errors. After fixing all errors, put the layout

of the inverter in your report.

Layout extraction

In order to extract the electrical parameters from the layout, select Verify -> extract. The

Extractor window appears. In this form, set the “Switch Names” to “parasitic_caps”. Click OK to

run the extractor. The CIW window should report 0 errors.

Fig. 27: The DRC window and the Set Switches dialog.

Fig. 28: The messages in the CIW window after the DRC check.

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Post layout simulation

You will create a test bench in order to simulate the extracted inverter. Create a new schematic

cell entitled “testbench” into your library and open it. You will instantiate the symbol of the

inverter along with the required voltage sources in this schematic view in order to test your

circuit. Add an instance of the symbol of the inverter. Add a capacitor ("cap") from the

"analogLib" library and a vdc and a vpulse source from the "cmosp18" library. Set the

capacitance of the "cap" instance to 1f (dummy capacitor) and configure the sources the same as

in the "Transient Simulation" section. Then, wire-up the circuit using the “w” key or by selecting

Add -> Wire. Make sure that your test bench look like in Fig. 29 and save your design with

Design -> Check and save.

Fig. 29: Schematic of the test bench circuit.

Perform a post-layout simulation of the inverter. In the library manager, select the "testbench"

cell, then select File->New->Cell view... In "Tool", select "Hierarchy-Editor", like in Fig. 30,

and click OK. Two windows will open. In the "New Configuration" window, write "schematic"

beside "view:". Then, click "Use Template" and select "spectre" in the pop-up window. Click

OK to close the pop-up windows and add "extracted" in the "View List". The "New

Configuration" window should looks like Fig. 31, then click OK. The "hierarchy editor" window

allows to select which model will be used by the simulator for each cells in your test bench

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(extracted, schematic, VHDL, Verilog, ...). Right click the "View to use" column beside the

"cmos_inv_w_symbol" row and select Set Cell View->extracted. The "hierarchy editor"

window should looks like Fig. 32. Save (File->Save) and close the "hierarchy editor" window.

Open the "config" view of the "testbench" cell, select "yes" for both question in the pop-up

window and click OK. Both the schematic and the hierarchy editors will open. Select tools ->

analog environment in the schematic editor. You can now simulate the extracted inverter

similarly as you did with the schematic of the inverter in Part one.

Fig. 30: Creation of the config view.

Fig. 31: Configuration of the config view.

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Fig. 32: Hierarchy editor window

Q9: Obtain the Vi and Vo transient simulation of the extracted inverter and put it in your

report.

Create a layout from a schematic

Hopefully, there is a more convenient way to draw a without drawing each layers of each

transistors. Indeed, it is possible to import the transistors layout directly from the schematic

view.

Step 1: In the Library manager, select your new Library (Lab1) and select the

cmos_inv_w_symbol cell. Right click on it, and select "Copy...". In the box "To", change the cell

name to cmos_inv_w_symbol_2. Then, click "OK".

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Step 2: Select the newly created cell and right click on the "layout" view. Select "Delete..." and

click "OK" in the pop-up window, and after "YES". Do the same for the "extracted view".

Step 3: Open the schematic view of the newly created cell. Select Tools->Design Synthesis->

Layout XL. Select "Create New" and click "OK". In the pop-up window click "OK" again. The

layout view will open.

Step 4: In the layout window, select Connectivity->Update->Components and Nets. In the

pop-up window, click "OK". The layout will look like Fig. 33.

Step 5: In the layout window, select the pfet and press "q". In the pop-up window, select

"Parameter" and, then, select "Add substrate contact?". This will automatically add the body

contact to the pfet. Do the same procedure for the nfet.

Step 6: Put the pfet inside an nwell layer.

Fig. 33: Imported layout from the schematic.

Step 7: Route the inverter and put the layout in your report. Make sure there are no DRC errors.

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Layout Versus Schematic (LVS)

When making complex layout, it is useful to compare the routed layout and the schematic to

make sure that no connexions are missing. Sometime, small layout errors leads to chip

malfunction, thus, wasting everything. LVS is a tool that helps you prevent that:

Step 1: Close any opened layout and/or schematic. Then, open the layout view of the

"cmos_inv_w_symbol_2".

Step 2: Select Verify -> Extract..., set the switches to "parasitic_caps" and clic "OK". Make

sure there are no extraction errors in the CIW window.

Step 3: Select Verify -> LVS..., a "Artist LVS" and "Artist LVS Form" windows should

appears, click "OK" to close the "Artist LVS Form" only. In the "Artist LVS" window, put

"divaLVS.rul" in the "Rule File" box, then click "Run", as shown in Figure 34. The LVS is now

running. Wait until a pop-up window tells you that LVS has finished and click "OK".

Step 4: In the "Artist LVS" window click on "Output". A report will open telling you the LVS

details, as seen in Figure 35.

Q9: Close the "Artist LVS" window, and go back to the layout view. Voluntarily induce a

layout error in your design. For instance, disconnect the connexion between the gates of the

pfet and nfet. Do steps 2-4 again and put the LVS report in your lab report. Highlight in

the LVS report the section describing the error.

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Fig. 34: Diva LVS window.

Fig. 35: LVS report window.

39

40

Report

Write a report that will include the following parts:

o An introduction

o Your answers to the questions

o All the requested curves and screenshots

o A conclusion

Print the last page of this document and use it as the first page of your report. Make sure to

submit your report before the deadline.

GIF-4201 (Micro-électronique)

Lab 1: An Introduction to Cadence

Nom Matricule

1.

2.

Signature de l’assistant :

Date :