L3 Hardware Flowcharts

BITS Pilani, Pilani Campus

The inputs required for the flow chart are

-Instruction set summary-Execution unit specification-Rules of operation

To use the method first postulate an initial version of the EU with operational rules of EU.


Clock gen

Inst-Decoder

Control store State sequencer

Control word decoder

Execution unit

Bus controller

0

6

2

3

4

51


0. With architecture specification as input begin with initial execution unit-refinement- final execution unit

1. Once flowcharts are fairly complete derive control word format using flowchart states.

2. After defining control word formats assign bit patterns to the control fields that minimizes control word decoders between control store and execution unit

3. Instruction decoders are defined by flowcharts and architecture specification

4. Completed flowcharts, control word format and initial bus specification – bus controller

5. Define logic of state sequencer (which tells what to do next)


Specifications of a Processor

-Programmers Registers( Index and pointer registers, GPRs)

-Instruction Types(data movement instructions, arithmetic and logic instructions, program control instructions)

-Addressing Modes(immediate addressing, direct addressing, register addressing, implied addressing.)


Instruction Format

Opcode Rx Mode Ry

displacement

Optional depending on addressing mode

Rx- First operand registerRy- second operand registerMode- Second operand addressing mode.

MIN Processor


Addressing Modes

AB - Base ( RY) plus displacement

A I - Register Indirect. RY holds the operand address

AR – Register Direct. Result stored in RY, for two operand instructions RY is an operand source


R0

R1

R2

R3

R4

:

:

RN

Programmers Register Set


Operations

ADD, AND, SUB, AND, OR, XOR

BZ - Branch if zero bit set

LOAD – Second operand source and RX

destination

STORE

POP - Post increment with register indirect only

PUSH- Pre decrement with register indirect only

TEST


A0 PC T2 RN T2 ALU

DO

DI

K

IRE IRF

R0

Internal A Bus

Internal B Bus

Ext add busExt data bus

Execution Unit


Making a flow chart

- Register transfer notation is used to describe the operation of the execution unit

- Each statement in this notation is called a task(notation has s source-bus-destination)

- Each state comprises of one or more tasks.- Use rectangles for states

( In a micro coded implementation each state becomes a control word and a control word sequence is succession of states)


ADD RX AR RY( Register- Register)

rx a alury b alu

t1 b ry

Time

Parallel tasks are listed in alphabetical orderIn a micro coded implementation each state is one micro cycle

R R ADD


ADD RX AI (RY)( Register- Memory)

edb diry b ao

ry b aot1 a do

Time

R M ADD

di b alu

rx a alu


Flow charts till now does not show PC incrementing and Instruction fetch


edb irfpc b ao

rx a alury b alu

t1 b ry

pc a alu+1 alu

t1 b pc

Pre fetch of next

instruction

Current instructionexecution

PC Incrementing


In a microcoded controller the control word specifies the tasks in

a single state

Tasks are commands to external bus controller, the execution unit

and state sequencer

Flowcharts usually emphasize changes in sequence and

concurrency for whatever the controller is doing

Flowcharts show sequential state flow made up of concurrent

tasks

Shows address calculation sequences and operation sequences.


edb irfpc b ao

edb diry b ao

t1 b pc

pc a alu+1 alu

ry b aot1 a do

di b alurx a alu

R M ADD


Rules of Operation

-A transfer from source to bus to destination takes one statetime

-A source can drive upto three destination loads. For ex: thetask T1 B ALU, AO, PC has three destination loads

-Input to ALU are from the A (internal) bus and either K (values0, +1, -1) or the B bus

-When ALU is destination T1 automatically loaded from the ALUoutput at the end of state time

-A transfer to AO bus activates on-chip external bus controller.


Level 1 flowcharts

Separate an instruction’s execution into operation tasks andhouse keeping tasks.

Operation tasks are required to perform an instruction –unique to particular instruction

House keeping tasks, such as PC increment, next instructionfetch are common to all instructions.


rx a alury b alu

t1 b ry

edb irfpc b ao

pc a alu+1 alu

irf iret1 b pc

Operation tasks House keepingtasks

ADD RX AR RY

R R ADD


edb irfpc b ao

pc a alu+1 alu

irf iret1 b pc

Operation tasks House keepingtasks

ADD RX AI (RY)

R M ADD

edb diry b ao

di b alurx a alu

ry b aot1 a do


Level 2 Flowcharts

Housekeeping tasks merged with the operation tasks to form level 2 flowcharts.


rx a alury b alu

edb irf pc a alu, aot1 b ry+1 alu

irf iret1 b pc

R R ADD


di b alurx a alu

irf iret1 a dot2 b ao

R M ADD

edb irfpc a alu, ao+1 alu

edb diry b ao, t2 t1 a pc

In the register to register ADD example, if AO had not been accessible from A bus

-feedback on the EU


Feedback on controller design

doing flowcharts for entire instruction set

- 20 address mode sequences- 50 instruction types- 8 states per instruction

50 * 20 * 8

- size.


Divide the sequence into

address mode sequence ( calculates address mode )

Execution sequence ( completes the instruction )

Share the address mode sequence

Pay for time


edb diry b ao , t2

edb dipc a alu , ao+1 alu

t1 a pc

di b alury a alu

edb dit1 b ao, t2

Register IndirectBase plus displacement


At the beginning of instruction execution, IRE is assumed tocontain the current instruction.

It must be loaded by the previous instruction, each instruction’scontrol word sequence fetch the next instruction.

Instruction execution begins with address mode sequence andimplicitly branches into execution sequence


rx a alury b alu

t1 a ry

edb irf pc a alu, ao+1 alu

irf iret1 a pc

ADD

rx a alury b alu

t1 a ry


irf iret1 a pc

SUB

EXECUTION SEQUENCEFOR REG-REGOPERATIONS


Execution sequence for standard dualoperand instructions ( ADD, AND, SUB …)are identical except for the (implied) ALUfunction.

They can use a common executionsequence if the opcode directly specifiesthe ALU operation


rx a alury b alu

edb irfpc a alu , aot1 b ry+1 alu

irf iret1 b pc

ADD, AND, SUB


di b alurx a alu

t1 a dot2 b ao


irf iret1 b pc

ADD

EXECUTION SEQUENCEWITH MEMORYOPERANDS

di b alurx a alu


irf iret1 a pc

AND

t1 a dot2 b ao


di b alurx a alu

ADD, AND, SUB

t1 a dot2 b ao

edb irfpc a alu , ao+1 alu

irf ire

t1 b pc


ry a alu, rx0 alu


irf iret1 a pc

LOAD


rx a alu, ry0 alu

irf iret1 a pc

STORE

EXECUTION SEQUENCEFOR REG-REGOPERATIONS


edb irfpc a alu , aory b rx, t2+1 alu

irf iret1 b pct2 a alu0 alu

LOAD


edb irfpc a alu , aorx b ry, t2+1 alu


STORE


di b rx, t2 edb irf pc a alu, ao+1 alu

irf iret1 a pc

LOAD

EXECUTION SEQUENCEWITH MEMORYOPERANDS


di b rx, t2edb irfpc a alu , ao+1 alu


LOAD


rx a alu, dot2 b ao0 alu


irf iret1 b pc

STORE


edb diry a alu,ao+1 alu

di b rxt1 a ry


irf iret1 a pc

POP


ry a alu-1 alu

rx a dot1 b ao,ry


irf iret1 a pc

PUSH



irf ire

t1 b pc

edb diry a alu , ao+1 alu

di b rxt1 a ry

POP



irf ire

t1 b pc

ry a alu-1 alu

rx a dot1 b ao, ry

PUSH


edb irfry a alu,ao+1 alu

irf iret1 a pc

irf iret1 b pc

Z =1 (branch) Z =0 (no branch)

Branch Instruction



di b t2 edb irf pc a alu, ao+1 alu

irf iret1 b pc

TEST

EXECUTION SEQUENCEWITH MEMORYOPERANDSt2 a alu

0 alu

Documents

L3 Hardware Flowcharts