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L - Edit Tutorial
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L-EDIT tutorial (Layout Editor)
Iran University of Science and Technology By : Eng. Bahram Roshan nezhad
Fall 2012
LOGO
Introduction
L-Edit is an Integrated Circuit Layout
Tool used to draw the two dimensional
geometry of the masks or layers to
fabricate an integrated circuit.
Different layers are represented by
by different colors and patterns.
Manufacturing constraints can be defined
in L-Edit as design rules.
L-Edit files are saved as file_name.tdb
(Tanner Database).
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LOGO
L-Edit Modules
L-Edit: The layout editor.
L-Edit/DRC: The Design Rule Checker.
L-Edit /Extract: The layout extractor to
SPICE.
L-Edit /SPR: an automatic standard cell.
placement and routing package.
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LOGO
L-Edit Window
File and cell name Location
Toolbars
Layer Palette
Drawing
windows
Mouse
Buttons
L-Edit v8.30
Menu Bar
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LOGO
L-Edit Toolbars
Edit>
Duplicate
Draw>
Rotate
Draw>
Flip>
Horizontal
Draw>
Flip>
Vertical
Draw>
Nibble
Draw>
Slice>
Horizontal
Draw>
Slice>
Vertical
Draw>
Merge
Draw>
Group
Draw>
Ungroup
Edit>
Edit
Object
Draw>
Move
By
Tool>
DRC
Tool>
DRC Box
DRC
Setup
Edit>
Find
Edit>
Find
Next
Edit>
Find
Previous
View>
Goto
Tools>
Clear Error
Layers
Tool>
Extract
File>
New
File>
Open
File>
Save
File>
File>
Cut
File>
Copy
File>
Paste
File>
Undo
File>
Redo
Edit>
Edit-in
Place>
Push Into
Edit>
Edit-in
Place>
Pop Out
view>
Cell
Browser
Edit>
Find
view>
Zoom>
Mouse
View>
Insides>
Toggle
insides
Cell>
Open
Cell>
Copy
Tool>
Cross
Section
Help>
L-Edit
User Guid Hierarchy level
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LOGO
Selection
tool
Rectangular
Box
Polygon
(90 deg.)
Wire
(90 deg.)
Polygon
(all-angle)
Polygon
(45deg.)
Wire
(35 deg.)
Wire
(all-angle)
Circle
Arc
Torus
Port
Ruler
(all angle)
Ruler
(45 deg.)
Ruler
(90 deg.)
Instance
Wire Width
L-Edit Toolbars
Selected
Layer name
Layer Palette
Layer Palette
scrollbar
Layer Palette
5/23
LOGO
Things to know
Lambda Definition (𝝀(
L: The channel length of the MOSFET, i.e, half
the size of technology used.
Exp) L=180nm 1Lambda=90nm
Note: You must set the length of the square
to represent One lambda or one Locator Unit.
L = 2 ∗ 𝜆
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LOGO
Design Parameters Setups
Create a name for
your fabrication
process
Relationship between L-Edit
internal units.
one internal unit is1nm
(1/1000lambda)
Technology
unit
B) Technology
From: Menu> Setup> Design> Technology
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LOGO
Design Parameters Setups
These are just the
dots shown on the
screen.
This is where your
mouse will snap to.
To set
One locator Unit=lambda
B) Grid
From: Menu> Setup> Design> Grid
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LOGO
Design Parameters Setups
C) Editing Objects
From: Edit> Edit Object (Ctrl+E)
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LOGO
Layout Example Draw the layout of a CMOS inverter given the following:
L= 0.5µm, Wn= 1.0µm, and Wp= 2.5µm.
V in
PmosL=0.5µ m
Wp=2.5µ m
NmosL=0.5µ m
Wp=1.0µ m
Vout
VDD
VSS
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n
LOGO
Create new Layout file File > New.
In the following open window, Browse and choose ‘mamin08.tdb’ in
‘‘Copy TDB setup from file’’ area. It usually locates in setup directory.
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Example
LOGO
Design Setup As mentioned before from: From Menu> Setup> Design >
Establishing
l=0.25mm,
therefore
2l=0.5mm.
Click OK: Now the technology is setup!
Example
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LOGO
Example
Pmos Choose N-Well in the left palette and draw a box
In the N-Well area, draw P-Select (for D&S) and
N-Select (for Body). Notice that the size and position
should obey Design Rule, which can be found at:
http://www.mosis.com/files/scmos/scmos.pdf.
It is a good idea to run DRC
at each stage of your design
so that you can fix any error
along the way
Draw Active.
Draw Poly (Gate).
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2𝝀
10𝝀
N-Select P-Select
Active
N-Well
Poly
LOGO
Example
4𝝀
Nmos Do not need to draw P-Well (Why?).
Draw N-Select and P-Select.
Draw Active.
Draw Poly.
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P-Select N-Select
LOGO
Example
Connect Poly of PMOS and NMOS.
Connect source of PMOS to VDD
by Metal1.
Connect source of NMOS to GND
by Metal 1.
Connect Drain of PMOS and NMOS
by Metal 1.
Add an input connect between
Metal1 and Poly.
Label the INPUT, OUTPUT, VDD
and GND.
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LOGO
L-Edit Design Rule Check From Tools> DRC (or the DRC box in the toolbar)
Run DRC for the total layout.
Fix the errors listed.
Once there is no DRC error
shown, the layout is ready to be
extracted.
Example
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LOGO
L-Edit can be used to generate SPICE-compatible circuit file listings using
the Extract option in the setup window of the menu bar menu bar.
Example
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LOGO
L-Edit Extractor
General
Enter the name of the
extractor definition file
Enter the name of the
SPICE output file.
• name.cir for PSPICE
• name.sp for HSPICE
Example
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LOGO
L-Edit Extractor
Output Select :
Comments: Write Nodes
Names.
Write Nodes as: Integers
Write Node parasitic
Capacitance.
Place device labels on
layer: Metal1.
Then Click Run
Example
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LOGO
The generated SPICE file
Example
* NODE NAME ALIASES
* 1 = VIN (-7.5,-6.5)
* 2 = VOUT (27.5,-6)
* 3 = GND (-7.5,-31)
* 4 = VDD (-6,30)
Cpar1 2 0 C=1.72875E-015
Cpar2 3 0 C=1.0445E-015
Cpar3 4 0 C=1.69675E-015
M2 2 1 4 4 PMOS L=5E-007 W=2.5E-006 AD=4.375E-012
+ PD=8.5E-006 AS=4.375E-012 PS=8.5E-006
M1 2 1 3 3 NMOS L=5E-007 W=1E-006 AD=2.5E-012
+ PD=6.5E-006 AS=2.5E-012 PS=6.5E-006
* Total Nodes: 4
* Total Elements: 5
* Extract Elapsed Time: 0 seconds
.END
The Nodes corresponding integers
The generated parasitic capacitors
The generated two MOSFETs
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