Kundanpassade kretsar Custom Designed Integrated Circuits

joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

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Kundanpassade kretsar Custom Designed Integrated Circuits

Lecture 4-5

Libraries

FSM (State machines)


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Library

• At compilation the components are stored in work work

• Compiled components are stored in libraries

library• Default libraries: work, std (You don’t have to write these!)library work;library std; -- definition for e.g. time and integeruse std.standard.all;

• Standard_logic packages:library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;


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Packages

• For large designs, common definitions (constants and types) and subprograms can be stored in packages.

• Used in the same way as standard packages (e.g. ieee). library my_project; use my_project.my_pack.all;

• A package can contain e.g. functions or procedures, types, constants, attributes and components.

• A package has two parts: Declaration and Body.


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Packages cont’d

package mypack is function min(a,b: in std_logic_vector) return std_logic_vector; constant max: integer:=16#FFFF#;end mypack;

package body mypack is function min(a,b: in std_logic_vector) return std_logic_vector is begin if a<b then return a; else return b; end if; end min;end mypack;


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architecture rtl of ex is procedure max(…) is begin …. end max;beginprocess procedure min(..) is begin …. end min; begin min(…); end process; max(..);end rtl;

Subprograms

• Two types of subprograms: procedures and functions.

• A procedure has input and output parameters.

• A function has input parameters and returns a value.

• Subprograms can be defined in package, architecture and process.

• Only sequential VHDL commands are allowed in subprograms. NB! processes can’t be used in subprograms!

• The declaration part of subprograms is sequential, i.e. only variables can be declared in a subprogram.

You can’t save hardware by using subprograms. New hardware is created for every new call.


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entity comp is port( x,y: in std_logic_vector(7 downto 0); z: out std_logic_vector(7 downto 0)) end;architecture rtl of comp is procedure max(signal a,b: in std_logic_vector; signal q: out std_logic_vector) is begin if a>b then q<=a; else q<=b; end if; end max;begin max(x,y,z);end rtl;

Subprograms. Procedures• A procedure can change its

arguments. It accepts constant, variable and signal as an object class.

• A procedure has input and output parameters.

• The allowable modes for parameters are in, out and inout.

• Variable parameters are not allowed in concurrent procedure calls.


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entity comp is port( x,y: in std_logic_vector(7 downto 0); z: out std_logic_vector(7 downto 0)) end;architecture rtl of comp is function max(signal a,b: std_logic_vector) return std_logic_vector is variable int: std_logic_vector(7 downto 0); begin if a>b then int:=a; else int:=b; end if; return int; end max;begin z<=max(x,y);end rtl;

Subprograms. Functions

• A function has input parameters and returns a value.

• Functions can be defined in package, architecture and process.

• A function can’t change its arguments.

• The only allowable mode for parameters is in;

• The only allowed object classes are constant and signal.


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Resolution function

function resolved (s: std_ulogic_vector) return std_ulogic is variable result: std_ulogic := ’Z’; -- weakest state default begin if s’lengt=1 then return s(s’low); else for i in s’range loop result:=resolution_table(result, s(i)); end loop; end if; return result; end resolved;

• std_ulogic is defined as {’U’,’X’,’0’,’1’,’Z’,’W’,’L’,’H’,’-’ }• std_logic is defined as:

type std_logic is resolved std_ulogic a resolution function is called when there are several drivers for a signal. Function declared in ieee.std_logic_1164


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Resolution function

CONSTANT resolution_table: stdlogic_table:=(-- ---------------------------------------------------------- | U X 0 1 Z W L H - | |-- -------------------------------------------------------- ( ’U’ ’U’ ’U’ ’U’ ’U’ ’U’ ’U’ ’U’ ’U’ ), --| U | ( ’U’ ’X’ ’X’ ’X’ ’X’ ’X’ ’X’ ’X’ ’X’ ), --| X | ( ’U’ ’X’ ’0’ ’X’ ’0’ ’0’ ’0’ ’0’ ’X’ ), --| 0 | ( ’U’ ’X’ ’X’ ’1’ ’1’ ’1’ ’1’ ’1’ ’X’ ), --| 1 | ( ’U’ ’X’ ’0’ ’1’ ’Z’ ’W’ ’L’ ’H’ ’X’ ), --| Z | ( ’U’ ’X’ ’0’ ’1’ ’W’ ’W’ ’W’ ’W’ ’X’ ), --| W | ( ’U’ ’X’ ’0’ ’1’ ’L’ ’W’ ’L’ ’W’ ’X’ ), --| L | ( ’U’ ’X’ ’0’ ’1’ ’H’ ’W’ ’W’ ’H’ ’X’ ), --| L | ( ’U’ ’X’ ’X’ ’X’ ’X’ ’X’ ’X’ ’X’ ’X’ ) --| - |);

• std_ulogic is defined as {’U’,’X’,’0’,’1’,’Z’,’W’,’L’,’H’,’-’ }• std_logic is defined as:

type std_logic is resolved std_ulogic a resolution function is called when there are several drivers for a signal. Function declared in ieee.std_logic_1164


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Overloading• The logical operators for std_logic are overloaded the built in operators for bit

data types.

CONSTANT and_table : stdlogic_table := (-- ----------------------------------------------------- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |);

-- overloaded logical operators ( with optimizing hints )FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 ISBEGIN RETURN (and_table(l, r));END "and";


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Overloading• VHDL is a strongly

typed language. If a function is declared with integers as input parameters it’s not allowed to call the function with std_logic_vector.

• The solution to this situation is to make multiple declarations of a function with different parameters. This is called overloading.

signal a_int: integer;…..if a_int>6 then…– both left and right param is integer. OK

--***************************************function ”>” (L:integer,R:integer) return boolean;

signal a_int: std_logic_vector(7 downto 0);…..if a_int>6 then…– missmatch if overloading is not used!!!(compiler selects the correct function)--***************************************function ”>” (L:integer,R:integer) return boolean;function ”>” (Lstd_logic_vector,R:integer) return boolean;function ”>” (L:integer,R:std_logic_vector) return boolean;function ”>” (L:std_logic_vector,R:std_logic_vector) return boolean;

From std_logic_unsigned


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Overloading (example)

function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is

constant length: INTEGER := maximum(L'length, R'length);

variable result : STD_LOGIC_VECTOR (length-1 downto 0);

begin

result := UNSIGNED(L) + UNSIGNED(R);

return std_logic_vector(result);

end;

function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is

variable result : STD_LOGIC_VECTOR (L'range);

begin

result := UNSIGNED(L) + R;

return std_logic_vector(result);

end;

Two functions with the same name but different arguments


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Type conversion

• Type conversion is another way to solve the problem with argument missmatch.

• In the package ieee.std_logic_unsigned there is a type conversion function from std_logic to integer.

function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is variable result : UNSIGNED(ARG'range);begin result := UNSIGNED(ARG); return CONV_INTEGER(result);end;

-- function callmy_int:=CONV_INTEGER(my_std_logic);


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ieee.std_logic_unsigned and ieee.std_logic_signed

• Choose std_logic_unsigned if mainly unsigned arithmetic's shall be used in the component

• Choose std_logic_signed if mainly signed arithmetic’s shall be used in the component

• Conversion to signed is done with (SIGNED)• Conversion to unsigned is done with (UNSIGNED)

Look at examples of libraries


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Shift and shift operator• In VHDL-93 shift operators are defined. sll (shift left), srl(shift right), rol(rotate left), ror(rotate right), sla(shift left and keep

value’right), sra(shift right and keep value’left). Example: q<=a sll 3;

• Shift functions can also be used e.g. in package ieee.std_logic_unsigned. function shl(arg: std_logic_vector; count: std_logic_vector) return std_logic_vector; Example: q<=shl(a,3);

• Shift can also be done by VHDL statements e.g. :• Direct form q(7)<=q(6); q(6)<=q(5); ….. q(1)<=q(0);

• Short formq(7 downto 1)<=q(6 downto 0); -- shift left one step


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Structural VHDL. Components• Remember: components are represented by the VHDL-entities!

• VHDL-components can be used to create hierachi!

-- Component declaration In architecture declaration part.component <entity_name> port(<port_list>);end component;

-- Component specification In architecture declaration part.for label: <component_name> use entity <library>.<entity.name>(architecture_name>);Note: Can’t be used by synthesis tools!

-- Component instance In architecture.port map(<port_association_list>);• The order of the interconnections is one way to control the signal connections.• Explicit connections between signals is a second way.


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Componentsentity 4_and is port(a,b,c,d: in std_logic; e: out std_logic);end;

architecture rtl of 4_and is component and_gate port(x,y: in std_logic; z: out std_logic); end component; signal s1,s2: std_logic; (for u1,u2,u3 use entity work.ex; Not for synthesis)begin u1: and_gate port map(a,b,s1); u2: and_gate port map(c,d,s2); u3: and_gate port map(s1,s2,e);end rtl;

component and_gate port(x,y: in std_logic; z: out std_logic); end component;

u1: and_gate port map(a,b,s1); u2: and_gate port map(c,d,s2); u3: and_gate port map(s1,s2,e); alternative:

order decides connection

&x

yz

&

&&

a

b

c

d

s1

s2e

U1

U2U3


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Componentsentity 4_and is port(a,b,c,d: in std_logic; e: out std_logic);end;

architecture rtl of 4_and is component and_gate port(x,y: in std_logic; z: out std_logic); end component; signal s1,s2: std_logic; (for u1,u2,u3 use entity work.ex; Not for synthesis)begin u1: and_gate port map(x=>a,y=>b,z=>s1); u2: and_gate port map(x=>c,y=>d,z=>s2); u3: and_gate port map(x=>s1,y=>s2,z=>e);end rtl;

component and_gate port(x,y: in std_logic; z: out std_logic); end component;

u1: and_gate port map(x=>a,y=>b,z=>s1); u2: and_gate port map(x=>c,y=>d,z=>s2); u3: and_gate port map(x=>s1,y=>s2,z=>e);

alternative:direct connections

&x

yz

&

&&

a

b

c

d

s1

s2e

U1

U2U3


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Direct instantiation (VHDL-93)

architecture rtl of top_level isbegin U1: entity work.c1(rtl) port map (a,b,q);end;


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Unused inputs and outputs in port map

• If an output is unused it can be connected to open.…… port map (a,b,open);……

• If an input shall have a fixed value (e.g. ’0’ or ’1’) then create a signal, set it to the value and connect.

architecture ….. signal S1: std_logic;

begin s1<=’1’;

U1: gate port map(a,b,c,s1);• VHDL-93:

U1: gate port map(a,b,c,’1’);


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Generate commandIf the same component shall be instanced several times the port map command can be placed in a loop.

entity top is port(a,b: in std_logic_vector(4 downto 0); q: out std_logic_vector(4 downto 0));end;architecture rtl of top is component c1 port(a,b: in std_logic; q: out std_logic; end component;begin c_gen: for i in 0 to 4 generate U: c1 port map (a(i), b(i), q (i)); end generate c_gen;end;

c_gen: for i in 0 to 4 generate U: c1 port map (a(i), b(i), q (i)); end generate c_gen;


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Components in a packageIt is possible to define a component in a package. One of the advantages is that no component declaration is needed in the architecture when the component is instantiated.

package mypack -- placed in mylib component mycomp port(clk,reset,din: in std_logic; q: out std_logic; end component;end mypack;


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Components in a packagelibrary ieee, mylib;use ieee.std_logic_1164.ALL;use mylib.mypack.ALL;………architecture rtl of ex isbegin U1: mycomp port map(clk,reset,din,dout);end rtl;


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Generics• Generics can be used to put

information into a model.• Generics shall be declared in the

Entity before the port command.

entity and_gate is generic (delay: time:=10 ns); port(a,b: in std_logic; c: out std_logic);end and_gate;

architecture behav of and_gate isbegin c<=a and b after delay;end behav;

Instantiation of the component to the left.

architecture x_beh of xx isbegin component and_gate generic(delay: time); port(a,b: in std_logic; c: out std_logic); end component;begin u1: and_gate generic map(delay=>5 ns) port map(a=>s1,b=>s2,c=>s3);end behav;


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FSM State Machines


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FSM Finite State Machines• State machines (FSM=Finite State Machines) are a practical way to describe

sequential logic (clocked logic). When HDL and synthesis is used the state machines can be described with graphical input (state diagrams) and the HDL code can be generated automatically.

• Two basic types of state machines:

Moore: The outputs are a function of the present state only.Mealy: The outputs are a function of the present state and all

inputs.

Logic

Register

Clock

Next state

Current state


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FSM Moore machine

• In a Moore machine the next state is calculated from the current state and the inputs (B1). The outputs are calculated from the current state (B2).

Logic B1

RegisterClock

Next state

Current state

Logic B2

InputsOutputs


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FSM Moore machine cont’d• In a Moore machine the outputs are only dependent on the actual state. The

state and the corresponding outputs are shown in the state circle. On the state transition arrow the event that causes the transition (input changes) is shown.

S00000

S11001

S21100

S31111

State

Output

State transition event

1

0

1

0


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FSM Moore machine cont’dExample Toggle-F-F

• A Toggle-flip-flop has two states and the corresponding outputs are 0 and 1.• When T=1 the flip-flop toggles on every clock.• When T=0 the flip-flop remains in the previous state.

S00

S11 T=0

Reset T=1

T=1T=0


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FSM Moore machine cont’dExample Toggle-F-F

The T-ff can be described with two processes. The clocked process (B1+R) including next state calculations and the output process (B2). The Boolean equations for B1 and B2 are shown below.

Logic B1

Register RClock

Logic B2

T

Combinational process

Clocked process


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FSM Moore machine cont’d

Example Toggle-F-F

entity t_ff isbegin port(T,clk,reset: in std_logic;

q: out std_logic);end t_ff;architecture rtl of t_ff is type state_type is (s0,s1); signal state: state_type;begin R_B1:process(reset,clk) begin

if reset='1' then state<=s0;elsif clk'event and clk='1' then case state is

when s0 => if T='1' then state<=s1;end if;

when s1 => if T='1' then state<=s0;end if;

end case;end if;

end process;

B2: process(state) begin

case state is when s0 => q<='1'; when S1 => q<='0';end case;

end process;end rtl;


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FSM Mealy machine

• In a Mealy machine the next state is calculated from the current state and the inputs (B1). The outputs are calculated from the current state and all inputs (B2).

Logic B1

RegisterClock

Next state

Current state

Inputs

Outputs


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FSM Mealy machine

• In a Mealy state diagram the outputs are shown on the transition arrows because the states only don’t decide the outputs

S0 S1

S2S3

State

in=01/y=1001

11/1100

10/1111

00/0000

rest/y=000010/1011rest/1001

rest/110111/1100

10/1111rest/1010

Event (input)

Outputs


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Logic B1

Register

Clock

Next state

Current state

InputsOutputs

FSM Output=State type• The simplest FSM is when the outputs correspond to the states. Only

one process is needed. The states are coded as std_logic_vectors (not enumerated).

Logic B

1

Register

Clock

Next state

Current state

InputsO

utputs

architecture rtl of o_is_s is type state_type is array (1 downto 0) of std_logic; -- subtype state_type is std_logic_vector(1 downto 0); constant s0: state_type :="00"; constant s1: state_type :="11"; signal state: state_type; begin OeqS:process(reset,clk) begin

if reset='1' then state<=s0;elsif clk'event and clk='1' then case state is

when s0 => if inp='1' then state<=s1;end if;

when s1 => if inp='1' then state<=s0;end if;

end case;end if;

end process; outp<=state;end rtl;

”output procerss”


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FSM Moore machinesSynchronous outputs (no glitches)

If the combinational output process is replaced with a clocked process the outputs can be synchronous and free of transition glitches. Note that the outputs are delayed one clock cycle compared to the standard Moore machine.

Logic R

egister

Clock

Logic

Inputs

Clocked processClocked process

Register

Clock

Ouputs


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FSM State coding• If not all states are used then end the case statement with when others.

• Different types of state coding:

Sequential: s0=0, s1=1, s2=2 etc. Gray: s0=0, s1=1, s2=3, s3=2 etc. One-hot: s0=”0001”, s1=”0010”, s2=”0100”, s3=”1000”.

• The synthesis tools make the decisions.

• The type declaration is independent of the state coding:type state_type is (s0,s1,s2,s3);……..signal state: state_type;

• The ”output=state” machine is an exception:type state_type is array (2 downto 0) of std_logic;-- subtype state_type is std_logic_vector(2 downto 0);constant s0: state_type := ”00”;constant s1: state_type := ”01”;signal state: state_type;

This state coding is done

as the state shall be used as outputs.


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Residual states

S1S0

S2

If one-hot is not used we must have 2 bits to represent the three states. One state is unused. Cover that state in the case statements or with when others!

(if one-hot is used three bits are required)


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FSM VHDL Template 1

Process p0 Process p1Process p2

Logic B1

RegisterClock

Next state

Current state

Logic B2

InputsOutputs

Code template for a three process Moore machine


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FSM VHDL Template 2-- Moore FSM with three processesentity demo is port(clk,reset, in1: in std_logic; out1: out std_logic);end demo;architecture rtl of demo is type state_type is (s0,s1,s2); -- state declarations signal current_state, next_state: state_type;begin p0: process(current_state, in1)–- next state process begin case current_state is when s0 => if in1=1 then next_state<=s1; end if; when s1 => if in1=1 then next_state<=s2; end if; when s2 => if in1=1 then next_state<=s0; end if; end case; end process page 1


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FSM VHDL Template 3-- state register process p1: process(clk,reset) begin if reset=’1’ then current_state<=s0; elsif clk’event and clk=’1’ then current_state<=next_state; end if; end process;

-- state to output decoder p2: process(current_state) begin case current_state is when s0 => out1<=”0000”; when s1 => out1<=”1001”; when s2 => out1<=”1100”; end case; end process;end rtl;

page 2


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FSM VHDL Template 4

Code template for a two process Mealy machine

Process p0 Process p1

Outputs

Current state

Logic B1

Register

ClockInputs

Logic B2


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FSM VHDL Template 5-- Mealy FSM with two processesentity demo is port(clk,reset, in1: in std_logic; out1: out std_logic);end demo;architecture rtl of demo is type state_type is (s0,s1,s2); -- state declarations signal state: state_type;begin

P0: process(state, in1)–- output process begin case state is when s0 => if in1=’1’ then out1<=”1001”; else out1<=”0000”; end if; when s1 => if in1=’0’ then out1<=”1100”; else ouyt1<=”1001”; end if; when s2 => if in1=’1’ then out1<=”1111”; else out1<=”1001”; end if; when s3 => if in1=’0’ then out1<=”0000”; else out1<=”1111”; end if; end case; end process page 1


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FSM VHDL Template 6-- state register process p1: process(clk,reset) begin if reset=’1’ then state<=s0; elsif clk’event and clk=’1’ then case state is when s0=> if in1=’1’ then state<=s1; end if; when s1=> if in1=’0’ then state<=s2; end if; when s2=> if in1=’1’ then state<=s3; end if; when s3=> if in1=’0’ then state<=s0; end if; end case; end if; end process;end rtl; page 2


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FSM VHDL Template

Use templates when designing state machines!!


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Pure Moore or Mealy only?

Must FSMs always be of pure Moore or Mealy type?

Answer: No, it’s possible to combine Moore and Mealy and even clocked outputs for some signals


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Advanced FSMs (intro)

• FSMs have normally only Boolean inputs as conditions.

• How can we include arithmetic in a FSM?

• How can we include “data” in a FSM?

• One answer is to use a FSMD


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Advanced FSMs (FSMD=FSM with Data path)

X<Y X>Y

Y=Y-X X=X-Y Data path(ALU etc)

Control path(FSM)

FSMD

Control signals

Status signals


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LAST TIME WE LEARNED WHAT?


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Signals and variablesprocess(data) variable cnt: integer range 0 to 15;begin cnt:=0; for i in 0 to 15 loop -- only comb. logic if data(i)=’1’ then cnt:=cnt+1; -- must be variable end if; end loop; if cnt>8 then maj<=’1’; else maj<=’0’; end if;end process;

• Information can only be transferred by signals.

• Variables are used inalgorithms that will besynthesised to comb. logic.

• Signals are declared in the concurrent part and used in concurrent and sequential part.

• Variables are declared and used in the sequential part.

for i in 0 to 15 loop -- only comb. logic if data(i)=’1’ then cnt:=cnt+1; -- must be variable end if;end loop;

Typical use of variables


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Sequential VHDL

architecture rtl of ex is concurrent declaration part begin concurrent VHDL concurrent VHDL concurrent VHDLend;

process(….) sequential declaration part begin sequential VHDL sequential VHDL end process;

Sequential statements are executed when the simulation clock is stopped.Like “normal” programming (e.g. C).


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Sequential VHDL. Combinational Process• Combinational processes are intended to generate combinational

logic.

• If simulation and hardware after synthesis shall correspond all input signals (used on the right side in assignments) must be in sensitivity list.

• If only combinational logic (no latches) shall be generated then all output signals must be assigned values every time the process is executed.

process(a,b)begin q<= a and b;end process; ? &

ab

c

process(a,b)begin if b=’1’ then q<= a; end if;end process;

?En

a

b

c

latch


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Sequential VHDL. Clocked Processes• Clocked processes can be clocked by a common clock, e.g. they

are synhronous.

• All signals that are assigned a value in a clocked process will result in a flip-flop.

• Variables that are read before they are assigned values will result in flip-flops.

process(clk)begin if clk’event and clk=’1’ then dout<= din; end if ;end process;

?FF

clkclk

din dout


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Sequential VHDL. Clocked processes.

With asynchronous reset the flip-flops will be reset as soon as the reset signal is applied.

process(clk,reset) – asynchronous resetbegin if reset=’1’ then data=”00”; elsif clk’event and clk=’1’ then data<=data_in; end if;end process;

Use these templates!

process(clk) -- synchronous reset begin if clk’event and clk=’1’ then if reset=’1’ then data=”00”; else data<=data_in; end if; end if;end process;


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Sequential VHDL contra Sequential Logic

Sequential VHDL is part of the VHDL-language. In sequential VHDL we can create combinational processes and clocked processes. Clocked processes is used in sequential logic. !

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Kundanpassade kretsar Custom Designed Integrated Circuits