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BoS Chairman 34 : M.E. APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM K.S.Rangasamy College of Technology - Autonomous Regulation R 2007 Department Electronics and Communication Engineering Programme Code & Name 34 : M.E. Applied Electronics

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BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology - Autonomous Regulation

R 2007

Department Electronics and Communication

Engineering

Programme Code amp Name 34 ME Applied Electronics

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode - 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

THEORY

07340101S Applied Mathematics 3 1 0 4 50 50 100

07340102C Advanced Digital Signal Processing 3 1 0 4 50 50 100

07340103S Advanced Digital System Design 3 0 0 3 50 50 100

07340104C VLSI Design Techniques 3 0 0 3 50 50 100

07340105C Advanced Microprocessors 3 0 0 3 50 50 100

0734++E Elective I 3 0 0 3 50 50 100

PRACTICAL

07340107P Electronics Design Laboratory I 0 0 3 2 50 50 100

Total 18 2 3 22 700

Semester II

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

THEORY

07340201S Analysis and Design of Analog Integrated Circuits

3 0 0 3 50 50 100

07340202S CAD of VLSI Circuits 3 0 0 3 50 50 100

07340203C Digital control engineering 3 1 0 4 50 50 100

07340204S Embedded Systems 3 0 0 3 50 50 100

073402E Elective II 3 0 0 3 50 50 100

073402E Elective III 3 0 0 3 50 50 100

PRACTICAL

07340207P Electronics Design Laboratory II 0 0 3 2 50 50 100

07340208P Technical Seminar I 0 0 3 2 100 00 100

07340209P Technical Report Preparation amp Presentation I

0 0 3 2 50 50 100

Total 18 1 9 25 900

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode ndash 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name 34 ME Applied Electronics

Semester III

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

THEORY

073403E Elective IV 3 0 0 3 50 50 100

073403E Elective V 3 0 0 3 50 50 100

073403E Elective VI 3 0 0 3 50 50 100

PRACTICAL

07340304P Project Work - Phase I 0 0 3 6 100 00 100

07340305P Technical Report Preparation amp Presentation II

0 0 3 2 100 00 100

Total 9 0 6 17 500

Semester IV

Course Code Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

PRACTICAL

07340401P Project Work - Phase II 0 0 30 20 50 50 100

Total 30 20 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode - 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name

34 ME Applied Electronics

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

List of Electives

073441E High Performance Communication Networks

3 0 0 3 50 50 100

073442E Wavelet transforms and applications

3 0 0 3 50 50 100

073443E Neural Networks and Applications 3 0 0 3 50 50 100

073444E Design of Semiconductor Memories

3 0 0 3 50 50 100

073445E Computational Intelligent Techniques

3 0 0 3 50 50 100

073446E Advanced Microprocessors and Microcontrollers

3 0 0 3 50 50 100

073447E Low Power VLSI Design 3 0 0 3 50 50 100

073448E Analog VLSI Design 3 0 0 3 50 50 100

073449E ASIC Design 3 0 0 3 50 50 100

073450E DSP Integrated Circuits 3 0 0 3 50 50 100

073451E Electromagnetic Interference and Compatibility in System Design

3 0 0 3 50 50 100

073452E Speech And Audio Signal Processing

3 0 0 3 50 50 100

073453E Reliability Engineering 3 0 0 3 50 50 100

073454E DSP Processor Architecture and programming

3 0 0 3 50 50 100

073455E Physical Design of VLSI Circuits 3 0 0 3 50 50 100

073456E Digital Image Processing 3 0 0 3 50 50 100

073457E Robotics 3 0 0 3 50 50 100

073458E Design and Analysis of Algorithms 3 0 0 3 50 50 100

073459E VLSI Signal Processing 3 0 0 3 50 50 100

073460E Internet Technologies and application

3 0 0 3 50 50 100

073461E Internetworking Multimedia 3 0 0 3 50 50 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340101S APPLIED MATHEMATICS 3 1 0 4 50 50 100

Objective(s) To develop efficient algorithms for solving numerical methods and to learn the basics and gained the skill for specialized studies and research To acquire skills in handling situation involving random variable

1 LINEAR ALGEBRAIC EQUATION AND EIGEN VALUE PROBLEMS

Total Hrs 12

System of equations- Solution by Gauss Elimination Gauss-Jordan and LU decomposition method- Jacobi Gauss-Seidal iteration method- Eigen values of a matrix by Jacobi and Power method

2 WAVE EQUATION Total Hrs 12

Solution of initial and boundary value problems- Characteristics- DlsquoAlembertlsquos Solution - Significance of characteristic curves - Laplace transform solutions for displacement in a long string - a long string under its weight - a bar with prescribed force on one end- free vibrations of a string

3 SPECIAL FUNCTIONS Total Hrs 12

Bessellsquos equation - Bessel Functions- Legendrelsquos equation - Legendre polynomials - Rodriguelsquos formula - Recurrence relations- generating functions and orthogonal property for Bessel functions - Legendre polynomials

4 RANDOM VARIABLES Total Hrs 12

One dimensional Random Variable - Moments and MGF ndash Binomial Poisson Geometric Normal Distributions- Two dimensional Random Variables ndash Marginal and Conditional Distributions ndash Covariance and Correlation Coefficient - Functions of Two dimensional random variable

5 QUEUEING THEORY Total Hrs 12

Single and Multiple server Markovian queueing models - Steady state system size probabilities ndash Littlelsquos formula - Priority queues - MG1 queueing system ndash PK formula

Total hours to be taught 60

Reference(s)

1 Sankara RaoK ―Introduction to Partial Differential Equation ― PHI 1995

2 Taha HA ―Operations Research- An Introduction ―6th Edition PHI 1997

3 Jain MK Iyengar SRK amp Jain RK ―International Methods for Scientific and Engineering Computation New Age International (P) Ltd Publlishers 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340102C ADVANCED DIGITAL SIGNAL PROCESSING

3 1 0 4 50 50 100

Objective(s) To learn spectrum estimation linear estimation prediction and adaptive filtering concepts

1 DISCRETE RANDOM SIGNAL PROCESSING Total Hrs 12

Discrete random process ndash stationary process ensemble averages auto correlation auto covariance matrices mean ergodic process and correlation ndash ergodic process Parsevallsquos theorem ndash Wiener Khintchine relation ndash power density spectrum ndash low pass and high pass filters

2 SPECTRUM ESTIMATION AND ANALYSIS Total Hrs 12

Principles ndash Traditional methods pitfalls windowing periodogram modified periodogram Blackman ndash Tukey method fast correlation method AR model ndash Yule- Walker method Burg method ndash MA model ndash ARMA model

3 LINEAR PREDICTION Total Hrs 12

Forward and backward predictions Solution of the normal equations ndash Levinson- Durbin algorithms Least mean squared error criterion ndash FIR Wiener filter and Wiener IIR filters ndash Wiener filter for filtering and prediction

4 ADAPTIVE FILTER Total Hrs 12

Concepts of adaptive filter ndash FIR adaptive filters ndash LMS adaptive algorithm ndash Adaptive recursive filters ndash design by time domain and frequency domain equivalence criterion ndash Adaptive noise and echo cancellation ndash AR lattice and ARMA lattice ndash ladder filters

5 MULTIRATE DIGITAL SIGNAL PROCESSING Total Hrs 12

Mathematical description of sampling rate ndash Interpolation and Decimation by integer factor ndash Sampling rate conversion by rational factor- Filter design for sampling rate conversion direct form FIR structures Polyphase structures time-varient structures Multistage implementation of multirate system Applications ndash High quality analogue to digital conversion for digital audio efficient implementation of narrowband digital filters

Total hours to be taught 60

Reference(s)

1 John G Proakis Dimitris GManolakis ―Digital Signal Processing Principles Algorithms and Applications PHI 12th Indian reprint 2001

2 Emmanuel C Ifeachor Barrie N Jervis ―Digital Signal Processing ndash A Practical approach Addison ndash Wesley publishing company 2002

3 SK Mitra ―Digital Signal Processing ndash A computer based approach Tata McGraw HillNew Delhi 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340103S

ADVANCED DIGITAL SYSTEM DESIGN Common to ME (Applied Electronics amp VLSI Design )

3 0 0 3 50 50 100

Objective(s) To learn how to design programmable logic circuits logic synthesis compiler based on VHDL To determine the types of fault that occur in digital circuits

1 SEQUENTIAL LOGIC OPTIMIZATION Total Hrs 12

Sequential Circuit Optimization Using State Based Models Sequential Circuit Optimization Using Network Models Implicit Finite State machine Traversal Methods Testability Considerations for Synchronous Circuits

2 ASYNCHRONOUS FINITE STATE MACHINES Total Hrs 12

Scope Asynchronous Analysis Design of Asynchronous Machines Cycle and Races Plotting and Reading the Excitation Map Hazards Essential Hazards Map Entered Variable MEV Approaches to Asynchronous Design Hazards in Circuit Developed by MEV Method

3 DIGITAL SYSTEM TESTING Total Hrs 12

Fault Models Fault Equivalence Fault Location Fault Dominance Single and Multiple Stack Faults Testing for Single Stack Faults Algorithms Random test Generation Adhoc Design for Testability Techniques Classical Scan Designs Boundary Scan Standards Built-In-Self-Test Test Pattern Generation BIST Architecture examples

4 HIGH SPEED DIGITAL DESIGN Total Hrs 12

Frequency Time and Distance Capacitance and Inductance Effects High Speed Properties of Logical Gates Speed And Power Measurement Techniques Rise Time and Bandwidth of Oscilloscope probes Self Inductance Signal pickup and loading effects of probes clock distribution clock skew and methods to reduce skew Controlling crosstalk on clock lines Delay adjustments Clock oscillators and clock jitter

5 SYSTEM DESIGN USING VHDL Total Hrs 12

Specification of combinational systems using VHDL Basic language element of VHDL Types of Modeling Design of serial adder with accumulator State graph for Control network Design of Binary Multiplier and Binary Divider Flip-Flops Registers Counters Sequential Machines Combinational Logic Circuits

Total hours to be taught 60

Reference(s)

1 Fletcher An Engineering Approach to Digital Design PHI 2004

2 Parag K Lala Digital Circuit Testing And Testability Academic 1997

3 Miron Abramovici et al Digital System Testing And Testable Design Jaico Publishing House 2001

4 Howard Johnson and Martin Graham High Speed Digital Design Handbook of Black Magic PHI PTR

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340104C VLSI DESIGN TECHNIQUES 3 0 0 3 50 50 100

Objective(s) To learn the CMOS processing technology and basic CMOS circuits CMOS transistor theory and logic design To study about verilog HDL programming

1 OVERVIEW OF VLSI DESIGN TECHNOLOGY Total Hrs 12

The VLSI design process ndash Architectural design ndash Logical design ndash physical design ndash Layout styles ndash Full custom ndash Semi custom approaches Basic electrical properties of MOS and CMOS circuits Ids versus Vds relationships ndash Transconductance ndash pass transistor ndash nMOS inverter ndash Determination of pull up to pull down ratio for an Nmos inverter ndash CMOS inverter ndash MOS transistor circuit model

2 VLSI FABRICATION TECHNOLOGY Total Hrs 12

Overview of wafer fabrication ndash wafer processing ndash oxidation ndash patterning ndash Diffusion ndash Ion implantation ndash Deposition ndash Silicon gate nMOS process ndash nwell CMOS process ndash pwell CMOS process ndash Twintub process ndash Silicon on insulator

3 MOS AND CMOS CIRCUIT DESIGN PROCESS Total Hrs 12

MOS layers ndash Stick diagrams ndash nMOs design style ndash CMOS design style ndash Design rules and layout ndash Lambda based design rules ndash Contact cuts ndash Double metal MOS process rules ndash CMOS lambda based design rules ndash Sheet resistance ndash Inverter delay ndash Driving large capacitive loads ndash Wiring capacitance

4 SUBSYSTEM DESIGN Total Hrs 12

Switch logic ndash pass transistor and transmission gates ndash Gate logic ndash inverter ndash Two input NAND gate ndash NOR gate ndash other forms of CMOS logic ndash Dynamic CMOS logic ndash Clocked CMOS logic ndash CMOS domain logic ndash simple combinational logic design examples ndash Parity generator ndash Multiplexers

5 SEQUENTIAL CIRCUITS Total Hrs 12

Two phase clocking ndash Charge storage ndash Dynamic shift register ndash precharged bus ndash General arrangement of a 4 bit arithmetic processor ndash Design of a 4 bit shifter ndash FPGAs and PLDs

Total hours to be taught 60

Reference(s)

1 E Eshranghian DA Pucknell and S Eshraghian ―Essentials of VLSI circuits and systems PHI 2005

2 Neil HE Weste David Harris and Ayan Banerjee ―CMOS VLSI Design A circuits and Systems Perspective (3e) Pearson 2006

3 W Wolf ―Modern VLSI Design (3e) Pearson 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode - 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

THEORY

07340101S Applied Mathematics 3 1 0 4 50 50 100

07340102C Advanced Digital Signal Processing 3 1 0 4 50 50 100

07340103S Advanced Digital System Design 3 0 0 3 50 50 100

07340104C VLSI Design Techniques 3 0 0 3 50 50 100

07340105C Advanced Microprocessors 3 0 0 3 50 50 100

0734++E Elective I 3 0 0 3 50 50 100

PRACTICAL

07340107P Electronics Design Laboratory I 0 0 3 2 50 50 100

Total 18 2 3 22 700

Semester II

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

THEORY

07340201S Analysis and Design of Analog Integrated Circuits

3 0 0 3 50 50 100

07340202S CAD of VLSI Circuits 3 0 0 3 50 50 100

07340203C Digital control engineering 3 1 0 4 50 50 100

07340204S Embedded Systems 3 0 0 3 50 50 100

073402E Elective II 3 0 0 3 50 50 100

073402E Elective III 3 0 0 3 50 50 100

PRACTICAL

07340207P Electronics Design Laboratory II 0 0 3 2 50 50 100

07340208P Technical Seminar I 0 0 3 2 100 00 100

07340209P Technical Report Preparation amp Presentation I

0 0 3 2 50 50 100

Total 18 1 9 25 900

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode ndash 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name 34 ME Applied Electronics

Semester III

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

THEORY

073403E Elective IV 3 0 0 3 50 50 100

073403E Elective V 3 0 0 3 50 50 100

073403E Elective VI 3 0 0 3 50 50 100

PRACTICAL

07340304P Project Work - Phase I 0 0 3 6 100 00 100

07340305P Technical Report Preparation amp Presentation II

0 0 3 2 100 00 100

Total 9 0 6 17 500

Semester IV

Course Code Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

PRACTICAL

07340401P Project Work - Phase II 0 0 30 20 50 50 100

Total 30 20 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode - 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name

34 ME Applied Electronics

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

List of Electives

073441E High Performance Communication Networks

3 0 0 3 50 50 100

073442E Wavelet transforms and applications

3 0 0 3 50 50 100

073443E Neural Networks and Applications 3 0 0 3 50 50 100

073444E Design of Semiconductor Memories

3 0 0 3 50 50 100

073445E Computational Intelligent Techniques

3 0 0 3 50 50 100

073446E Advanced Microprocessors and Microcontrollers

3 0 0 3 50 50 100

073447E Low Power VLSI Design 3 0 0 3 50 50 100

073448E Analog VLSI Design 3 0 0 3 50 50 100

073449E ASIC Design 3 0 0 3 50 50 100

073450E DSP Integrated Circuits 3 0 0 3 50 50 100

073451E Electromagnetic Interference and Compatibility in System Design

3 0 0 3 50 50 100

073452E Speech And Audio Signal Processing

3 0 0 3 50 50 100

073453E Reliability Engineering 3 0 0 3 50 50 100

073454E DSP Processor Architecture and programming

3 0 0 3 50 50 100

073455E Physical Design of VLSI Circuits 3 0 0 3 50 50 100

073456E Digital Image Processing 3 0 0 3 50 50 100

073457E Robotics 3 0 0 3 50 50 100

073458E Design and Analysis of Algorithms 3 0 0 3 50 50 100

073459E VLSI Signal Processing 3 0 0 3 50 50 100

073460E Internet Technologies and application

3 0 0 3 50 50 100

073461E Internetworking Multimedia 3 0 0 3 50 50 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340101S APPLIED MATHEMATICS 3 1 0 4 50 50 100

Objective(s) To develop efficient algorithms for solving numerical methods and to learn the basics and gained the skill for specialized studies and research To acquire skills in handling situation involving random variable

1 LINEAR ALGEBRAIC EQUATION AND EIGEN VALUE PROBLEMS

Total Hrs 12

System of equations- Solution by Gauss Elimination Gauss-Jordan and LU decomposition method- Jacobi Gauss-Seidal iteration method- Eigen values of a matrix by Jacobi and Power method

2 WAVE EQUATION Total Hrs 12

Solution of initial and boundary value problems- Characteristics- DlsquoAlembertlsquos Solution - Significance of characteristic curves - Laplace transform solutions for displacement in a long string - a long string under its weight - a bar with prescribed force on one end- free vibrations of a string

3 SPECIAL FUNCTIONS Total Hrs 12

Bessellsquos equation - Bessel Functions- Legendrelsquos equation - Legendre polynomials - Rodriguelsquos formula - Recurrence relations- generating functions and orthogonal property for Bessel functions - Legendre polynomials

4 RANDOM VARIABLES Total Hrs 12

One dimensional Random Variable - Moments and MGF ndash Binomial Poisson Geometric Normal Distributions- Two dimensional Random Variables ndash Marginal and Conditional Distributions ndash Covariance and Correlation Coefficient - Functions of Two dimensional random variable

5 QUEUEING THEORY Total Hrs 12

Single and Multiple server Markovian queueing models - Steady state system size probabilities ndash Littlelsquos formula - Priority queues - MG1 queueing system ndash PK formula

Total hours to be taught 60

Reference(s)

1 Sankara RaoK ―Introduction to Partial Differential Equation ― PHI 1995

2 Taha HA ―Operations Research- An Introduction ―6th Edition PHI 1997

3 Jain MK Iyengar SRK amp Jain RK ―International Methods for Scientific and Engineering Computation New Age International (P) Ltd Publlishers 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340102C ADVANCED DIGITAL SIGNAL PROCESSING

3 1 0 4 50 50 100

Objective(s) To learn spectrum estimation linear estimation prediction and adaptive filtering concepts

1 DISCRETE RANDOM SIGNAL PROCESSING Total Hrs 12

Discrete random process ndash stationary process ensemble averages auto correlation auto covariance matrices mean ergodic process and correlation ndash ergodic process Parsevallsquos theorem ndash Wiener Khintchine relation ndash power density spectrum ndash low pass and high pass filters

2 SPECTRUM ESTIMATION AND ANALYSIS Total Hrs 12

Principles ndash Traditional methods pitfalls windowing periodogram modified periodogram Blackman ndash Tukey method fast correlation method AR model ndash Yule- Walker method Burg method ndash MA model ndash ARMA model

3 LINEAR PREDICTION Total Hrs 12

Forward and backward predictions Solution of the normal equations ndash Levinson- Durbin algorithms Least mean squared error criterion ndash FIR Wiener filter and Wiener IIR filters ndash Wiener filter for filtering and prediction

4 ADAPTIVE FILTER Total Hrs 12

Concepts of adaptive filter ndash FIR adaptive filters ndash LMS adaptive algorithm ndash Adaptive recursive filters ndash design by time domain and frequency domain equivalence criterion ndash Adaptive noise and echo cancellation ndash AR lattice and ARMA lattice ndash ladder filters

5 MULTIRATE DIGITAL SIGNAL PROCESSING Total Hrs 12

Mathematical description of sampling rate ndash Interpolation and Decimation by integer factor ndash Sampling rate conversion by rational factor- Filter design for sampling rate conversion direct form FIR structures Polyphase structures time-varient structures Multistage implementation of multirate system Applications ndash High quality analogue to digital conversion for digital audio efficient implementation of narrowband digital filters

Total hours to be taught 60

Reference(s)

1 John G Proakis Dimitris GManolakis ―Digital Signal Processing Principles Algorithms and Applications PHI 12th Indian reprint 2001

2 Emmanuel C Ifeachor Barrie N Jervis ―Digital Signal Processing ndash A Practical approach Addison ndash Wesley publishing company 2002

3 SK Mitra ―Digital Signal Processing ndash A computer based approach Tata McGraw HillNew Delhi 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340103S

ADVANCED DIGITAL SYSTEM DESIGN Common to ME (Applied Electronics amp VLSI Design )

3 0 0 3 50 50 100

Objective(s) To learn how to design programmable logic circuits logic synthesis compiler based on VHDL To determine the types of fault that occur in digital circuits

1 SEQUENTIAL LOGIC OPTIMIZATION Total Hrs 12

Sequential Circuit Optimization Using State Based Models Sequential Circuit Optimization Using Network Models Implicit Finite State machine Traversal Methods Testability Considerations for Synchronous Circuits

2 ASYNCHRONOUS FINITE STATE MACHINES Total Hrs 12

Scope Asynchronous Analysis Design of Asynchronous Machines Cycle and Races Plotting and Reading the Excitation Map Hazards Essential Hazards Map Entered Variable MEV Approaches to Asynchronous Design Hazards in Circuit Developed by MEV Method

3 DIGITAL SYSTEM TESTING Total Hrs 12

Fault Models Fault Equivalence Fault Location Fault Dominance Single and Multiple Stack Faults Testing for Single Stack Faults Algorithms Random test Generation Adhoc Design for Testability Techniques Classical Scan Designs Boundary Scan Standards Built-In-Self-Test Test Pattern Generation BIST Architecture examples

4 HIGH SPEED DIGITAL DESIGN Total Hrs 12

Frequency Time and Distance Capacitance and Inductance Effects High Speed Properties of Logical Gates Speed And Power Measurement Techniques Rise Time and Bandwidth of Oscilloscope probes Self Inductance Signal pickup and loading effects of probes clock distribution clock skew and methods to reduce skew Controlling crosstalk on clock lines Delay adjustments Clock oscillators and clock jitter

5 SYSTEM DESIGN USING VHDL Total Hrs 12

Specification of combinational systems using VHDL Basic language element of VHDL Types of Modeling Design of serial adder with accumulator State graph for Control network Design of Binary Multiplier and Binary Divider Flip-Flops Registers Counters Sequential Machines Combinational Logic Circuits

Total hours to be taught 60

Reference(s)

1 Fletcher An Engineering Approach to Digital Design PHI 2004

2 Parag K Lala Digital Circuit Testing And Testability Academic 1997

3 Miron Abramovici et al Digital System Testing And Testable Design Jaico Publishing House 2001

4 Howard Johnson and Martin Graham High Speed Digital Design Handbook of Black Magic PHI PTR

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340104C VLSI DESIGN TECHNIQUES 3 0 0 3 50 50 100

Objective(s) To learn the CMOS processing technology and basic CMOS circuits CMOS transistor theory and logic design To study about verilog HDL programming

1 OVERVIEW OF VLSI DESIGN TECHNOLOGY Total Hrs 12

The VLSI design process ndash Architectural design ndash Logical design ndash physical design ndash Layout styles ndash Full custom ndash Semi custom approaches Basic electrical properties of MOS and CMOS circuits Ids versus Vds relationships ndash Transconductance ndash pass transistor ndash nMOS inverter ndash Determination of pull up to pull down ratio for an Nmos inverter ndash CMOS inverter ndash MOS transistor circuit model

2 VLSI FABRICATION TECHNOLOGY Total Hrs 12

Overview of wafer fabrication ndash wafer processing ndash oxidation ndash patterning ndash Diffusion ndash Ion implantation ndash Deposition ndash Silicon gate nMOS process ndash nwell CMOS process ndash pwell CMOS process ndash Twintub process ndash Silicon on insulator

3 MOS AND CMOS CIRCUIT DESIGN PROCESS Total Hrs 12

MOS layers ndash Stick diagrams ndash nMOs design style ndash CMOS design style ndash Design rules and layout ndash Lambda based design rules ndash Contact cuts ndash Double metal MOS process rules ndash CMOS lambda based design rules ndash Sheet resistance ndash Inverter delay ndash Driving large capacitive loads ndash Wiring capacitance

4 SUBSYSTEM DESIGN Total Hrs 12

Switch logic ndash pass transistor and transmission gates ndash Gate logic ndash inverter ndash Two input NAND gate ndash NOR gate ndash other forms of CMOS logic ndash Dynamic CMOS logic ndash Clocked CMOS logic ndash CMOS domain logic ndash simple combinational logic design examples ndash Parity generator ndash Multiplexers

5 SEQUENTIAL CIRCUITS Total Hrs 12

Two phase clocking ndash Charge storage ndash Dynamic shift register ndash precharged bus ndash General arrangement of a 4 bit arithmetic processor ndash Design of a 4 bit shifter ndash FPGAs and PLDs

Total hours to be taught 60

Reference(s)

1 E Eshranghian DA Pucknell and S Eshraghian ―Essentials of VLSI circuits and systems PHI 2005

2 Neil HE Weste David Harris and Ayan Banerjee ―CMOS VLSI Design A circuits and Systems Perspective (3e) Pearson 2006

3 W Wolf ―Modern VLSI Design (3e) Pearson 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode ndash 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name 34 ME Applied Electronics

Semester III

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

THEORY

073403E Elective IV 3 0 0 3 50 50 100

073403E Elective V 3 0 0 3 50 50 100

073403E Elective VI 3 0 0 3 50 50 100

PRACTICAL

07340304P Project Work - Phase I 0 0 3 6 100 00 100

07340305P Technical Report Preparation amp Presentation II

0 0 3 2 100 00 100

Total 9 0 6 17 500

Semester IV

Course Code Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

PRACTICAL

07340401P Project Work - Phase II 0 0 30 20 50 50 100

Total 30 20 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode - 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name

34 ME Applied Electronics

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

List of Electives

073441E High Performance Communication Networks

3 0 0 3 50 50 100

073442E Wavelet transforms and applications

3 0 0 3 50 50 100

073443E Neural Networks and Applications 3 0 0 3 50 50 100

073444E Design of Semiconductor Memories

3 0 0 3 50 50 100

073445E Computational Intelligent Techniques

3 0 0 3 50 50 100

073446E Advanced Microprocessors and Microcontrollers

3 0 0 3 50 50 100

073447E Low Power VLSI Design 3 0 0 3 50 50 100

073448E Analog VLSI Design 3 0 0 3 50 50 100

073449E ASIC Design 3 0 0 3 50 50 100

073450E DSP Integrated Circuits 3 0 0 3 50 50 100

073451E Electromagnetic Interference and Compatibility in System Design

3 0 0 3 50 50 100

073452E Speech And Audio Signal Processing

3 0 0 3 50 50 100

073453E Reliability Engineering 3 0 0 3 50 50 100

073454E DSP Processor Architecture and programming

3 0 0 3 50 50 100

073455E Physical Design of VLSI Circuits 3 0 0 3 50 50 100

073456E Digital Image Processing 3 0 0 3 50 50 100

073457E Robotics 3 0 0 3 50 50 100

073458E Design and Analysis of Algorithms 3 0 0 3 50 50 100

073459E VLSI Signal Processing 3 0 0 3 50 50 100

073460E Internet Technologies and application

3 0 0 3 50 50 100

073461E Internetworking Multimedia 3 0 0 3 50 50 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340101S APPLIED MATHEMATICS 3 1 0 4 50 50 100

Objective(s) To develop efficient algorithms for solving numerical methods and to learn the basics and gained the skill for specialized studies and research To acquire skills in handling situation involving random variable

1 LINEAR ALGEBRAIC EQUATION AND EIGEN VALUE PROBLEMS

Total Hrs 12

System of equations- Solution by Gauss Elimination Gauss-Jordan and LU decomposition method- Jacobi Gauss-Seidal iteration method- Eigen values of a matrix by Jacobi and Power method

2 WAVE EQUATION Total Hrs 12

Solution of initial and boundary value problems- Characteristics- DlsquoAlembertlsquos Solution - Significance of characteristic curves - Laplace transform solutions for displacement in a long string - a long string under its weight - a bar with prescribed force on one end- free vibrations of a string

3 SPECIAL FUNCTIONS Total Hrs 12

Bessellsquos equation - Bessel Functions- Legendrelsquos equation - Legendre polynomials - Rodriguelsquos formula - Recurrence relations- generating functions and orthogonal property for Bessel functions - Legendre polynomials

4 RANDOM VARIABLES Total Hrs 12

One dimensional Random Variable - Moments and MGF ndash Binomial Poisson Geometric Normal Distributions- Two dimensional Random Variables ndash Marginal and Conditional Distributions ndash Covariance and Correlation Coefficient - Functions of Two dimensional random variable

5 QUEUEING THEORY Total Hrs 12

Single and Multiple server Markovian queueing models - Steady state system size probabilities ndash Littlelsquos formula - Priority queues - MG1 queueing system ndash PK formula

Total hours to be taught 60

Reference(s)

1 Sankara RaoK ―Introduction to Partial Differential Equation ― PHI 1995

2 Taha HA ―Operations Research- An Introduction ―6th Edition PHI 1997

3 Jain MK Iyengar SRK amp Jain RK ―International Methods for Scientific and Engineering Computation New Age International (P) Ltd Publlishers 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340102C ADVANCED DIGITAL SIGNAL PROCESSING

3 1 0 4 50 50 100

Objective(s) To learn spectrum estimation linear estimation prediction and adaptive filtering concepts

1 DISCRETE RANDOM SIGNAL PROCESSING Total Hrs 12

Discrete random process ndash stationary process ensemble averages auto correlation auto covariance matrices mean ergodic process and correlation ndash ergodic process Parsevallsquos theorem ndash Wiener Khintchine relation ndash power density spectrum ndash low pass and high pass filters

2 SPECTRUM ESTIMATION AND ANALYSIS Total Hrs 12

Principles ndash Traditional methods pitfalls windowing periodogram modified periodogram Blackman ndash Tukey method fast correlation method AR model ndash Yule- Walker method Burg method ndash MA model ndash ARMA model

3 LINEAR PREDICTION Total Hrs 12

Forward and backward predictions Solution of the normal equations ndash Levinson- Durbin algorithms Least mean squared error criterion ndash FIR Wiener filter and Wiener IIR filters ndash Wiener filter for filtering and prediction

4 ADAPTIVE FILTER Total Hrs 12

Concepts of adaptive filter ndash FIR adaptive filters ndash LMS adaptive algorithm ndash Adaptive recursive filters ndash design by time domain and frequency domain equivalence criterion ndash Adaptive noise and echo cancellation ndash AR lattice and ARMA lattice ndash ladder filters

5 MULTIRATE DIGITAL SIGNAL PROCESSING Total Hrs 12

Mathematical description of sampling rate ndash Interpolation and Decimation by integer factor ndash Sampling rate conversion by rational factor- Filter design for sampling rate conversion direct form FIR structures Polyphase structures time-varient structures Multistage implementation of multirate system Applications ndash High quality analogue to digital conversion for digital audio efficient implementation of narrowband digital filters

Total hours to be taught 60

Reference(s)

1 John G Proakis Dimitris GManolakis ―Digital Signal Processing Principles Algorithms and Applications PHI 12th Indian reprint 2001

2 Emmanuel C Ifeachor Barrie N Jervis ―Digital Signal Processing ndash A Practical approach Addison ndash Wesley publishing company 2002

3 SK Mitra ―Digital Signal Processing ndash A computer based approach Tata McGraw HillNew Delhi 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340103S

ADVANCED DIGITAL SYSTEM DESIGN Common to ME (Applied Electronics amp VLSI Design )

3 0 0 3 50 50 100

Objective(s) To learn how to design programmable logic circuits logic synthesis compiler based on VHDL To determine the types of fault that occur in digital circuits

1 SEQUENTIAL LOGIC OPTIMIZATION Total Hrs 12

Sequential Circuit Optimization Using State Based Models Sequential Circuit Optimization Using Network Models Implicit Finite State machine Traversal Methods Testability Considerations for Synchronous Circuits

2 ASYNCHRONOUS FINITE STATE MACHINES Total Hrs 12

Scope Asynchronous Analysis Design of Asynchronous Machines Cycle and Races Plotting and Reading the Excitation Map Hazards Essential Hazards Map Entered Variable MEV Approaches to Asynchronous Design Hazards in Circuit Developed by MEV Method

3 DIGITAL SYSTEM TESTING Total Hrs 12

Fault Models Fault Equivalence Fault Location Fault Dominance Single and Multiple Stack Faults Testing for Single Stack Faults Algorithms Random test Generation Adhoc Design for Testability Techniques Classical Scan Designs Boundary Scan Standards Built-In-Self-Test Test Pattern Generation BIST Architecture examples

4 HIGH SPEED DIGITAL DESIGN Total Hrs 12

Frequency Time and Distance Capacitance and Inductance Effects High Speed Properties of Logical Gates Speed And Power Measurement Techniques Rise Time and Bandwidth of Oscilloscope probes Self Inductance Signal pickup and loading effects of probes clock distribution clock skew and methods to reduce skew Controlling crosstalk on clock lines Delay adjustments Clock oscillators and clock jitter

5 SYSTEM DESIGN USING VHDL Total Hrs 12

Specification of combinational systems using VHDL Basic language element of VHDL Types of Modeling Design of serial adder with accumulator State graph for Control network Design of Binary Multiplier and Binary Divider Flip-Flops Registers Counters Sequential Machines Combinational Logic Circuits

Total hours to be taught 60

Reference(s)

1 Fletcher An Engineering Approach to Digital Design PHI 2004

2 Parag K Lala Digital Circuit Testing And Testability Academic 1997

3 Miron Abramovici et al Digital System Testing And Testable Design Jaico Publishing House 2001

4 Howard Johnson and Martin Graham High Speed Digital Design Handbook of Black Magic PHI PTR

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340104C VLSI DESIGN TECHNIQUES 3 0 0 3 50 50 100

Objective(s) To learn the CMOS processing technology and basic CMOS circuits CMOS transistor theory and logic design To study about verilog HDL programming

1 OVERVIEW OF VLSI DESIGN TECHNOLOGY Total Hrs 12

The VLSI design process ndash Architectural design ndash Logical design ndash physical design ndash Layout styles ndash Full custom ndash Semi custom approaches Basic electrical properties of MOS and CMOS circuits Ids versus Vds relationships ndash Transconductance ndash pass transistor ndash nMOS inverter ndash Determination of pull up to pull down ratio for an Nmos inverter ndash CMOS inverter ndash MOS transistor circuit model

2 VLSI FABRICATION TECHNOLOGY Total Hrs 12

Overview of wafer fabrication ndash wafer processing ndash oxidation ndash patterning ndash Diffusion ndash Ion implantation ndash Deposition ndash Silicon gate nMOS process ndash nwell CMOS process ndash pwell CMOS process ndash Twintub process ndash Silicon on insulator

3 MOS AND CMOS CIRCUIT DESIGN PROCESS Total Hrs 12

MOS layers ndash Stick diagrams ndash nMOs design style ndash CMOS design style ndash Design rules and layout ndash Lambda based design rules ndash Contact cuts ndash Double metal MOS process rules ndash CMOS lambda based design rules ndash Sheet resistance ndash Inverter delay ndash Driving large capacitive loads ndash Wiring capacitance

4 SUBSYSTEM DESIGN Total Hrs 12

Switch logic ndash pass transistor and transmission gates ndash Gate logic ndash inverter ndash Two input NAND gate ndash NOR gate ndash other forms of CMOS logic ndash Dynamic CMOS logic ndash Clocked CMOS logic ndash CMOS domain logic ndash simple combinational logic design examples ndash Parity generator ndash Multiplexers

5 SEQUENTIAL CIRCUITS Total Hrs 12

Two phase clocking ndash Charge storage ndash Dynamic shift register ndash precharged bus ndash General arrangement of a 4 bit arithmetic processor ndash Design of a 4 bit shifter ndash FPGAs and PLDs

Total hours to be taught 60

Reference(s)

1 E Eshranghian DA Pucknell and S Eshraghian ―Essentials of VLSI circuits and systems PHI 2005

2 Neil HE Weste David Harris and Ayan Banerjee ―CMOS VLSI Design A circuits and Systems Perspective (3e) Pearson 2006

3 W Wolf ―Modern VLSI Design (3e) Pearson 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - CURRICULUM

KSRangasamy College of Technology Tiruchengode - 637215

Curriculum for the Programmes under Autonomous Scheme

Regulation R 2007

Department Department of Electronics and Communication Engineering

Programme Code amp Name

34 ME Applied Electronics

Course Code

Course Name Hours Week Credit Maximum marks

L T P C CA ES Total

List of Electives

073441E High Performance Communication Networks

3 0 0 3 50 50 100

073442E Wavelet transforms and applications

3 0 0 3 50 50 100

073443E Neural Networks and Applications 3 0 0 3 50 50 100

073444E Design of Semiconductor Memories

3 0 0 3 50 50 100

073445E Computational Intelligent Techniques

3 0 0 3 50 50 100

073446E Advanced Microprocessors and Microcontrollers

3 0 0 3 50 50 100

073447E Low Power VLSI Design 3 0 0 3 50 50 100

073448E Analog VLSI Design 3 0 0 3 50 50 100

073449E ASIC Design 3 0 0 3 50 50 100

073450E DSP Integrated Circuits 3 0 0 3 50 50 100

073451E Electromagnetic Interference and Compatibility in System Design

3 0 0 3 50 50 100

073452E Speech And Audio Signal Processing

3 0 0 3 50 50 100

073453E Reliability Engineering 3 0 0 3 50 50 100

073454E DSP Processor Architecture and programming

3 0 0 3 50 50 100

073455E Physical Design of VLSI Circuits 3 0 0 3 50 50 100

073456E Digital Image Processing 3 0 0 3 50 50 100

073457E Robotics 3 0 0 3 50 50 100

073458E Design and Analysis of Algorithms 3 0 0 3 50 50 100

073459E VLSI Signal Processing 3 0 0 3 50 50 100

073460E Internet Technologies and application

3 0 0 3 50 50 100

073461E Internetworking Multimedia 3 0 0 3 50 50 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340101S APPLIED MATHEMATICS 3 1 0 4 50 50 100

Objective(s) To develop efficient algorithms for solving numerical methods and to learn the basics and gained the skill for specialized studies and research To acquire skills in handling situation involving random variable

1 LINEAR ALGEBRAIC EQUATION AND EIGEN VALUE PROBLEMS

Total Hrs 12

System of equations- Solution by Gauss Elimination Gauss-Jordan and LU decomposition method- Jacobi Gauss-Seidal iteration method- Eigen values of a matrix by Jacobi and Power method

2 WAVE EQUATION Total Hrs 12

Solution of initial and boundary value problems- Characteristics- DlsquoAlembertlsquos Solution - Significance of characteristic curves - Laplace transform solutions for displacement in a long string - a long string under its weight - a bar with prescribed force on one end- free vibrations of a string

3 SPECIAL FUNCTIONS Total Hrs 12

Bessellsquos equation - Bessel Functions- Legendrelsquos equation - Legendre polynomials - Rodriguelsquos formula - Recurrence relations- generating functions and orthogonal property for Bessel functions - Legendre polynomials

4 RANDOM VARIABLES Total Hrs 12

One dimensional Random Variable - Moments and MGF ndash Binomial Poisson Geometric Normal Distributions- Two dimensional Random Variables ndash Marginal and Conditional Distributions ndash Covariance and Correlation Coefficient - Functions of Two dimensional random variable

5 QUEUEING THEORY Total Hrs 12

Single and Multiple server Markovian queueing models - Steady state system size probabilities ndash Littlelsquos formula - Priority queues - MG1 queueing system ndash PK formula

Total hours to be taught 60

Reference(s)

1 Sankara RaoK ―Introduction to Partial Differential Equation ― PHI 1995

2 Taha HA ―Operations Research- An Introduction ―6th Edition PHI 1997

3 Jain MK Iyengar SRK amp Jain RK ―International Methods for Scientific and Engineering Computation New Age International (P) Ltd Publlishers 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340102C ADVANCED DIGITAL SIGNAL PROCESSING

3 1 0 4 50 50 100

Objective(s) To learn spectrum estimation linear estimation prediction and adaptive filtering concepts

1 DISCRETE RANDOM SIGNAL PROCESSING Total Hrs 12

Discrete random process ndash stationary process ensemble averages auto correlation auto covariance matrices mean ergodic process and correlation ndash ergodic process Parsevallsquos theorem ndash Wiener Khintchine relation ndash power density spectrum ndash low pass and high pass filters

2 SPECTRUM ESTIMATION AND ANALYSIS Total Hrs 12

Principles ndash Traditional methods pitfalls windowing periodogram modified periodogram Blackman ndash Tukey method fast correlation method AR model ndash Yule- Walker method Burg method ndash MA model ndash ARMA model

3 LINEAR PREDICTION Total Hrs 12

Forward and backward predictions Solution of the normal equations ndash Levinson- Durbin algorithms Least mean squared error criterion ndash FIR Wiener filter and Wiener IIR filters ndash Wiener filter for filtering and prediction

4 ADAPTIVE FILTER Total Hrs 12

Concepts of adaptive filter ndash FIR adaptive filters ndash LMS adaptive algorithm ndash Adaptive recursive filters ndash design by time domain and frequency domain equivalence criterion ndash Adaptive noise and echo cancellation ndash AR lattice and ARMA lattice ndash ladder filters

5 MULTIRATE DIGITAL SIGNAL PROCESSING Total Hrs 12

Mathematical description of sampling rate ndash Interpolation and Decimation by integer factor ndash Sampling rate conversion by rational factor- Filter design for sampling rate conversion direct form FIR structures Polyphase structures time-varient structures Multistage implementation of multirate system Applications ndash High quality analogue to digital conversion for digital audio efficient implementation of narrowband digital filters

Total hours to be taught 60

Reference(s)

1 John G Proakis Dimitris GManolakis ―Digital Signal Processing Principles Algorithms and Applications PHI 12th Indian reprint 2001

2 Emmanuel C Ifeachor Barrie N Jervis ―Digital Signal Processing ndash A Practical approach Addison ndash Wesley publishing company 2002

3 SK Mitra ―Digital Signal Processing ndash A computer based approach Tata McGraw HillNew Delhi 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340103S

ADVANCED DIGITAL SYSTEM DESIGN Common to ME (Applied Electronics amp VLSI Design )

3 0 0 3 50 50 100

Objective(s) To learn how to design programmable logic circuits logic synthesis compiler based on VHDL To determine the types of fault that occur in digital circuits

1 SEQUENTIAL LOGIC OPTIMIZATION Total Hrs 12

Sequential Circuit Optimization Using State Based Models Sequential Circuit Optimization Using Network Models Implicit Finite State machine Traversal Methods Testability Considerations for Synchronous Circuits

2 ASYNCHRONOUS FINITE STATE MACHINES Total Hrs 12

Scope Asynchronous Analysis Design of Asynchronous Machines Cycle and Races Plotting and Reading the Excitation Map Hazards Essential Hazards Map Entered Variable MEV Approaches to Asynchronous Design Hazards in Circuit Developed by MEV Method

3 DIGITAL SYSTEM TESTING Total Hrs 12

Fault Models Fault Equivalence Fault Location Fault Dominance Single and Multiple Stack Faults Testing for Single Stack Faults Algorithms Random test Generation Adhoc Design for Testability Techniques Classical Scan Designs Boundary Scan Standards Built-In-Self-Test Test Pattern Generation BIST Architecture examples

4 HIGH SPEED DIGITAL DESIGN Total Hrs 12

Frequency Time and Distance Capacitance and Inductance Effects High Speed Properties of Logical Gates Speed And Power Measurement Techniques Rise Time and Bandwidth of Oscilloscope probes Self Inductance Signal pickup and loading effects of probes clock distribution clock skew and methods to reduce skew Controlling crosstalk on clock lines Delay adjustments Clock oscillators and clock jitter

5 SYSTEM DESIGN USING VHDL Total Hrs 12

Specification of combinational systems using VHDL Basic language element of VHDL Types of Modeling Design of serial adder with accumulator State graph for Control network Design of Binary Multiplier and Binary Divider Flip-Flops Registers Counters Sequential Machines Combinational Logic Circuits

Total hours to be taught 60

Reference(s)

1 Fletcher An Engineering Approach to Digital Design PHI 2004

2 Parag K Lala Digital Circuit Testing And Testability Academic 1997

3 Miron Abramovici et al Digital System Testing And Testable Design Jaico Publishing House 2001

4 Howard Johnson and Martin Graham High Speed Digital Design Handbook of Black Magic PHI PTR

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340104C VLSI DESIGN TECHNIQUES 3 0 0 3 50 50 100

Objective(s) To learn the CMOS processing technology and basic CMOS circuits CMOS transistor theory and logic design To study about verilog HDL programming

1 OVERVIEW OF VLSI DESIGN TECHNOLOGY Total Hrs 12

The VLSI design process ndash Architectural design ndash Logical design ndash physical design ndash Layout styles ndash Full custom ndash Semi custom approaches Basic electrical properties of MOS and CMOS circuits Ids versus Vds relationships ndash Transconductance ndash pass transistor ndash nMOS inverter ndash Determination of pull up to pull down ratio for an Nmos inverter ndash CMOS inverter ndash MOS transistor circuit model

2 VLSI FABRICATION TECHNOLOGY Total Hrs 12

Overview of wafer fabrication ndash wafer processing ndash oxidation ndash patterning ndash Diffusion ndash Ion implantation ndash Deposition ndash Silicon gate nMOS process ndash nwell CMOS process ndash pwell CMOS process ndash Twintub process ndash Silicon on insulator

3 MOS AND CMOS CIRCUIT DESIGN PROCESS Total Hrs 12

MOS layers ndash Stick diagrams ndash nMOs design style ndash CMOS design style ndash Design rules and layout ndash Lambda based design rules ndash Contact cuts ndash Double metal MOS process rules ndash CMOS lambda based design rules ndash Sheet resistance ndash Inverter delay ndash Driving large capacitive loads ndash Wiring capacitance

4 SUBSYSTEM DESIGN Total Hrs 12

Switch logic ndash pass transistor and transmission gates ndash Gate logic ndash inverter ndash Two input NAND gate ndash NOR gate ndash other forms of CMOS logic ndash Dynamic CMOS logic ndash Clocked CMOS logic ndash CMOS domain logic ndash simple combinational logic design examples ndash Parity generator ndash Multiplexers

5 SEQUENTIAL CIRCUITS Total Hrs 12

Two phase clocking ndash Charge storage ndash Dynamic shift register ndash precharged bus ndash General arrangement of a 4 bit arithmetic processor ndash Design of a 4 bit shifter ndash FPGAs and PLDs

Total hours to be taught 60

Reference(s)

1 E Eshranghian DA Pucknell and S Eshraghian ―Essentials of VLSI circuits and systems PHI 2005

2 Neil HE Weste David Harris and Ayan Banerjee ―CMOS VLSI Design A circuits and Systems Perspective (3e) Pearson 2006

3 W Wolf ―Modern VLSI Design (3e) Pearson 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340101S APPLIED MATHEMATICS 3 1 0 4 50 50 100

Objective(s) To develop efficient algorithms for solving numerical methods and to learn the basics and gained the skill for specialized studies and research To acquire skills in handling situation involving random variable

1 LINEAR ALGEBRAIC EQUATION AND EIGEN VALUE PROBLEMS

Total Hrs 12

System of equations- Solution by Gauss Elimination Gauss-Jordan and LU decomposition method- Jacobi Gauss-Seidal iteration method- Eigen values of a matrix by Jacobi and Power method

2 WAVE EQUATION Total Hrs 12

Solution of initial and boundary value problems- Characteristics- DlsquoAlembertlsquos Solution - Significance of characteristic curves - Laplace transform solutions for displacement in a long string - a long string under its weight - a bar with prescribed force on one end- free vibrations of a string

3 SPECIAL FUNCTIONS Total Hrs 12

Bessellsquos equation - Bessel Functions- Legendrelsquos equation - Legendre polynomials - Rodriguelsquos formula - Recurrence relations- generating functions and orthogonal property for Bessel functions - Legendre polynomials

4 RANDOM VARIABLES Total Hrs 12

One dimensional Random Variable - Moments and MGF ndash Binomial Poisson Geometric Normal Distributions- Two dimensional Random Variables ndash Marginal and Conditional Distributions ndash Covariance and Correlation Coefficient - Functions of Two dimensional random variable

5 QUEUEING THEORY Total Hrs 12

Single and Multiple server Markovian queueing models - Steady state system size probabilities ndash Littlelsquos formula - Priority queues - MG1 queueing system ndash PK formula

Total hours to be taught 60

Reference(s)

1 Sankara RaoK ―Introduction to Partial Differential Equation ― PHI 1995

2 Taha HA ―Operations Research- An Introduction ―6th Edition PHI 1997

3 Jain MK Iyengar SRK amp Jain RK ―International Methods for Scientific and Engineering Computation New Age International (P) Ltd Publlishers 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340102C ADVANCED DIGITAL SIGNAL PROCESSING

3 1 0 4 50 50 100

Objective(s) To learn spectrum estimation linear estimation prediction and adaptive filtering concepts

1 DISCRETE RANDOM SIGNAL PROCESSING Total Hrs 12

Discrete random process ndash stationary process ensemble averages auto correlation auto covariance matrices mean ergodic process and correlation ndash ergodic process Parsevallsquos theorem ndash Wiener Khintchine relation ndash power density spectrum ndash low pass and high pass filters

2 SPECTRUM ESTIMATION AND ANALYSIS Total Hrs 12

Principles ndash Traditional methods pitfalls windowing periodogram modified periodogram Blackman ndash Tukey method fast correlation method AR model ndash Yule- Walker method Burg method ndash MA model ndash ARMA model

3 LINEAR PREDICTION Total Hrs 12

Forward and backward predictions Solution of the normal equations ndash Levinson- Durbin algorithms Least mean squared error criterion ndash FIR Wiener filter and Wiener IIR filters ndash Wiener filter for filtering and prediction

4 ADAPTIVE FILTER Total Hrs 12

Concepts of adaptive filter ndash FIR adaptive filters ndash LMS adaptive algorithm ndash Adaptive recursive filters ndash design by time domain and frequency domain equivalence criterion ndash Adaptive noise and echo cancellation ndash AR lattice and ARMA lattice ndash ladder filters

5 MULTIRATE DIGITAL SIGNAL PROCESSING Total Hrs 12

Mathematical description of sampling rate ndash Interpolation and Decimation by integer factor ndash Sampling rate conversion by rational factor- Filter design for sampling rate conversion direct form FIR structures Polyphase structures time-varient structures Multistage implementation of multirate system Applications ndash High quality analogue to digital conversion for digital audio efficient implementation of narrowband digital filters

Total hours to be taught 60

Reference(s)

1 John G Proakis Dimitris GManolakis ―Digital Signal Processing Principles Algorithms and Applications PHI 12th Indian reprint 2001

2 Emmanuel C Ifeachor Barrie N Jervis ―Digital Signal Processing ndash A Practical approach Addison ndash Wesley publishing company 2002

3 SK Mitra ―Digital Signal Processing ndash A computer based approach Tata McGraw HillNew Delhi 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340103S

ADVANCED DIGITAL SYSTEM DESIGN Common to ME (Applied Electronics amp VLSI Design )

3 0 0 3 50 50 100

Objective(s) To learn how to design programmable logic circuits logic synthesis compiler based on VHDL To determine the types of fault that occur in digital circuits

1 SEQUENTIAL LOGIC OPTIMIZATION Total Hrs 12

Sequential Circuit Optimization Using State Based Models Sequential Circuit Optimization Using Network Models Implicit Finite State machine Traversal Methods Testability Considerations for Synchronous Circuits

2 ASYNCHRONOUS FINITE STATE MACHINES Total Hrs 12

Scope Asynchronous Analysis Design of Asynchronous Machines Cycle and Races Plotting and Reading the Excitation Map Hazards Essential Hazards Map Entered Variable MEV Approaches to Asynchronous Design Hazards in Circuit Developed by MEV Method

3 DIGITAL SYSTEM TESTING Total Hrs 12

Fault Models Fault Equivalence Fault Location Fault Dominance Single and Multiple Stack Faults Testing for Single Stack Faults Algorithms Random test Generation Adhoc Design for Testability Techniques Classical Scan Designs Boundary Scan Standards Built-In-Self-Test Test Pattern Generation BIST Architecture examples

4 HIGH SPEED DIGITAL DESIGN Total Hrs 12

Frequency Time and Distance Capacitance and Inductance Effects High Speed Properties of Logical Gates Speed And Power Measurement Techniques Rise Time and Bandwidth of Oscilloscope probes Self Inductance Signal pickup and loading effects of probes clock distribution clock skew and methods to reduce skew Controlling crosstalk on clock lines Delay adjustments Clock oscillators and clock jitter

5 SYSTEM DESIGN USING VHDL Total Hrs 12

Specification of combinational systems using VHDL Basic language element of VHDL Types of Modeling Design of serial adder with accumulator State graph for Control network Design of Binary Multiplier and Binary Divider Flip-Flops Registers Counters Sequential Machines Combinational Logic Circuits

Total hours to be taught 60

Reference(s)

1 Fletcher An Engineering Approach to Digital Design PHI 2004

2 Parag K Lala Digital Circuit Testing And Testability Academic 1997

3 Miron Abramovici et al Digital System Testing And Testable Design Jaico Publishing House 2001

4 Howard Johnson and Martin Graham High Speed Digital Design Handbook of Black Magic PHI PTR

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340104C VLSI DESIGN TECHNIQUES 3 0 0 3 50 50 100

Objective(s) To learn the CMOS processing technology and basic CMOS circuits CMOS transistor theory and logic design To study about verilog HDL programming

1 OVERVIEW OF VLSI DESIGN TECHNOLOGY Total Hrs 12

The VLSI design process ndash Architectural design ndash Logical design ndash physical design ndash Layout styles ndash Full custom ndash Semi custom approaches Basic electrical properties of MOS and CMOS circuits Ids versus Vds relationships ndash Transconductance ndash pass transistor ndash nMOS inverter ndash Determination of pull up to pull down ratio for an Nmos inverter ndash CMOS inverter ndash MOS transistor circuit model

2 VLSI FABRICATION TECHNOLOGY Total Hrs 12

Overview of wafer fabrication ndash wafer processing ndash oxidation ndash patterning ndash Diffusion ndash Ion implantation ndash Deposition ndash Silicon gate nMOS process ndash nwell CMOS process ndash pwell CMOS process ndash Twintub process ndash Silicon on insulator

3 MOS AND CMOS CIRCUIT DESIGN PROCESS Total Hrs 12

MOS layers ndash Stick diagrams ndash nMOs design style ndash CMOS design style ndash Design rules and layout ndash Lambda based design rules ndash Contact cuts ndash Double metal MOS process rules ndash CMOS lambda based design rules ndash Sheet resistance ndash Inverter delay ndash Driving large capacitive loads ndash Wiring capacitance

4 SUBSYSTEM DESIGN Total Hrs 12

Switch logic ndash pass transistor and transmission gates ndash Gate logic ndash inverter ndash Two input NAND gate ndash NOR gate ndash other forms of CMOS logic ndash Dynamic CMOS logic ndash Clocked CMOS logic ndash CMOS domain logic ndash simple combinational logic design examples ndash Parity generator ndash Multiplexers

5 SEQUENTIAL CIRCUITS Total Hrs 12

Two phase clocking ndash Charge storage ndash Dynamic shift register ndash precharged bus ndash General arrangement of a 4 bit arithmetic processor ndash Design of a 4 bit shifter ndash FPGAs and PLDs

Total hours to be taught 60

Reference(s)

1 E Eshranghian DA Pucknell and S Eshraghian ―Essentials of VLSI circuits and systems PHI 2005

2 Neil HE Weste David Harris and Ayan Banerjee ―CMOS VLSI Design A circuits and Systems Perspective (3e) Pearson 2006

3 W Wolf ―Modern VLSI Design (3e) Pearson 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340102C ADVANCED DIGITAL SIGNAL PROCESSING

3 1 0 4 50 50 100

Objective(s) To learn spectrum estimation linear estimation prediction and adaptive filtering concepts

1 DISCRETE RANDOM SIGNAL PROCESSING Total Hrs 12

Discrete random process ndash stationary process ensemble averages auto correlation auto covariance matrices mean ergodic process and correlation ndash ergodic process Parsevallsquos theorem ndash Wiener Khintchine relation ndash power density spectrum ndash low pass and high pass filters

2 SPECTRUM ESTIMATION AND ANALYSIS Total Hrs 12

Principles ndash Traditional methods pitfalls windowing periodogram modified periodogram Blackman ndash Tukey method fast correlation method AR model ndash Yule- Walker method Burg method ndash MA model ndash ARMA model

3 LINEAR PREDICTION Total Hrs 12

Forward and backward predictions Solution of the normal equations ndash Levinson- Durbin algorithms Least mean squared error criterion ndash FIR Wiener filter and Wiener IIR filters ndash Wiener filter for filtering and prediction

4 ADAPTIVE FILTER Total Hrs 12

Concepts of adaptive filter ndash FIR adaptive filters ndash LMS adaptive algorithm ndash Adaptive recursive filters ndash design by time domain and frequency domain equivalence criterion ndash Adaptive noise and echo cancellation ndash AR lattice and ARMA lattice ndash ladder filters

5 MULTIRATE DIGITAL SIGNAL PROCESSING Total Hrs 12

Mathematical description of sampling rate ndash Interpolation and Decimation by integer factor ndash Sampling rate conversion by rational factor- Filter design for sampling rate conversion direct form FIR structures Polyphase structures time-varient structures Multistage implementation of multirate system Applications ndash High quality analogue to digital conversion for digital audio efficient implementation of narrowband digital filters

Total hours to be taught 60

Reference(s)

1 John G Proakis Dimitris GManolakis ―Digital Signal Processing Principles Algorithms and Applications PHI 12th Indian reprint 2001

2 Emmanuel C Ifeachor Barrie N Jervis ―Digital Signal Processing ndash A Practical approach Addison ndash Wesley publishing company 2002

3 SK Mitra ―Digital Signal Processing ndash A computer based approach Tata McGraw HillNew Delhi 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340103S

ADVANCED DIGITAL SYSTEM DESIGN Common to ME (Applied Electronics amp VLSI Design )

3 0 0 3 50 50 100

Objective(s) To learn how to design programmable logic circuits logic synthesis compiler based on VHDL To determine the types of fault that occur in digital circuits

1 SEQUENTIAL LOGIC OPTIMIZATION Total Hrs 12

Sequential Circuit Optimization Using State Based Models Sequential Circuit Optimization Using Network Models Implicit Finite State machine Traversal Methods Testability Considerations for Synchronous Circuits

2 ASYNCHRONOUS FINITE STATE MACHINES Total Hrs 12

Scope Asynchronous Analysis Design of Asynchronous Machines Cycle and Races Plotting and Reading the Excitation Map Hazards Essential Hazards Map Entered Variable MEV Approaches to Asynchronous Design Hazards in Circuit Developed by MEV Method

3 DIGITAL SYSTEM TESTING Total Hrs 12

Fault Models Fault Equivalence Fault Location Fault Dominance Single and Multiple Stack Faults Testing for Single Stack Faults Algorithms Random test Generation Adhoc Design for Testability Techniques Classical Scan Designs Boundary Scan Standards Built-In-Self-Test Test Pattern Generation BIST Architecture examples

4 HIGH SPEED DIGITAL DESIGN Total Hrs 12

Frequency Time and Distance Capacitance and Inductance Effects High Speed Properties of Logical Gates Speed And Power Measurement Techniques Rise Time and Bandwidth of Oscilloscope probes Self Inductance Signal pickup and loading effects of probes clock distribution clock skew and methods to reduce skew Controlling crosstalk on clock lines Delay adjustments Clock oscillators and clock jitter

5 SYSTEM DESIGN USING VHDL Total Hrs 12

Specification of combinational systems using VHDL Basic language element of VHDL Types of Modeling Design of serial adder with accumulator State graph for Control network Design of Binary Multiplier and Binary Divider Flip-Flops Registers Counters Sequential Machines Combinational Logic Circuits

Total hours to be taught 60

Reference(s)

1 Fletcher An Engineering Approach to Digital Design PHI 2004

2 Parag K Lala Digital Circuit Testing And Testability Academic 1997

3 Miron Abramovici et al Digital System Testing And Testable Design Jaico Publishing House 2001

4 Howard Johnson and Martin Graham High Speed Digital Design Handbook of Black Magic PHI PTR

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340104C VLSI DESIGN TECHNIQUES 3 0 0 3 50 50 100

Objective(s) To learn the CMOS processing technology and basic CMOS circuits CMOS transistor theory and logic design To study about verilog HDL programming

1 OVERVIEW OF VLSI DESIGN TECHNOLOGY Total Hrs 12

The VLSI design process ndash Architectural design ndash Logical design ndash physical design ndash Layout styles ndash Full custom ndash Semi custom approaches Basic electrical properties of MOS and CMOS circuits Ids versus Vds relationships ndash Transconductance ndash pass transistor ndash nMOS inverter ndash Determination of pull up to pull down ratio for an Nmos inverter ndash CMOS inverter ndash MOS transistor circuit model

2 VLSI FABRICATION TECHNOLOGY Total Hrs 12

Overview of wafer fabrication ndash wafer processing ndash oxidation ndash patterning ndash Diffusion ndash Ion implantation ndash Deposition ndash Silicon gate nMOS process ndash nwell CMOS process ndash pwell CMOS process ndash Twintub process ndash Silicon on insulator

3 MOS AND CMOS CIRCUIT DESIGN PROCESS Total Hrs 12

MOS layers ndash Stick diagrams ndash nMOs design style ndash CMOS design style ndash Design rules and layout ndash Lambda based design rules ndash Contact cuts ndash Double metal MOS process rules ndash CMOS lambda based design rules ndash Sheet resistance ndash Inverter delay ndash Driving large capacitive loads ndash Wiring capacitance

4 SUBSYSTEM DESIGN Total Hrs 12

Switch logic ndash pass transistor and transmission gates ndash Gate logic ndash inverter ndash Two input NAND gate ndash NOR gate ndash other forms of CMOS logic ndash Dynamic CMOS logic ndash Clocked CMOS logic ndash CMOS domain logic ndash simple combinational logic design examples ndash Parity generator ndash Multiplexers

5 SEQUENTIAL CIRCUITS Total Hrs 12

Two phase clocking ndash Charge storage ndash Dynamic shift register ndash precharged bus ndash General arrangement of a 4 bit arithmetic processor ndash Design of a 4 bit shifter ndash FPGAs and PLDs

Total hours to be taught 60

Reference(s)

1 E Eshranghian DA Pucknell and S Eshraghian ―Essentials of VLSI circuits and systems PHI 2005

2 Neil HE Weste David Harris and Ayan Banerjee ―CMOS VLSI Design A circuits and Systems Perspective (3e) Pearson 2006

3 W Wolf ―Modern VLSI Design (3e) Pearson 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340103S

ADVANCED DIGITAL SYSTEM DESIGN Common to ME (Applied Electronics amp VLSI Design )

3 0 0 3 50 50 100

Objective(s) To learn how to design programmable logic circuits logic synthesis compiler based on VHDL To determine the types of fault that occur in digital circuits

1 SEQUENTIAL LOGIC OPTIMIZATION Total Hrs 12

Sequential Circuit Optimization Using State Based Models Sequential Circuit Optimization Using Network Models Implicit Finite State machine Traversal Methods Testability Considerations for Synchronous Circuits

2 ASYNCHRONOUS FINITE STATE MACHINES Total Hrs 12

Scope Asynchronous Analysis Design of Asynchronous Machines Cycle and Races Plotting and Reading the Excitation Map Hazards Essential Hazards Map Entered Variable MEV Approaches to Asynchronous Design Hazards in Circuit Developed by MEV Method

3 DIGITAL SYSTEM TESTING Total Hrs 12

Fault Models Fault Equivalence Fault Location Fault Dominance Single and Multiple Stack Faults Testing for Single Stack Faults Algorithms Random test Generation Adhoc Design for Testability Techniques Classical Scan Designs Boundary Scan Standards Built-In-Self-Test Test Pattern Generation BIST Architecture examples

4 HIGH SPEED DIGITAL DESIGN Total Hrs 12

Frequency Time and Distance Capacitance and Inductance Effects High Speed Properties of Logical Gates Speed And Power Measurement Techniques Rise Time and Bandwidth of Oscilloscope probes Self Inductance Signal pickup and loading effects of probes clock distribution clock skew and methods to reduce skew Controlling crosstalk on clock lines Delay adjustments Clock oscillators and clock jitter

5 SYSTEM DESIGN USING VHDL Total Hrs 12

Specification of combinational systems using VHDL Basic language element of VHDL Types of Modeling Design of serial adder with accumulator State graph for Control network Design of Binary Multiplier and Binary Divider Flip-Flops Registers Counters Sequential Machines Combinational Logic Circuits

Total hours to be taught 60

Reference(s)

1 Fletcher An Engineering Approach to Digital Design PHI 2004

2 Parag K Lala Digital Circuit Testing And Testability Academic 1997

3 Miron Abramovici et al Digital System Testing And Testable Design Jaico Publishing House 2001

4 Howard Johnson and Martin Graham High Speed Digital Design Handbook of Black Magic PHI PTR

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340104C VLSI DESIGN TECHNIQUES 3 0 0 3 50 50 100

Objective(s) To learn the CMOS processing technology and basic CMOS circuits CMOS transistor theory and logic design To study about verilog HDL programming

1 OVERVIEW OF VLSI DESIGN TECHNOLOGY Total Hrs 12

The VLSI design process ndash Architectural design ndash Logical design ndash physical design ndash Layout styles ndash Full custom ndash Semi custom approaches Basic electrical properties of MOS and CMOS circuits Ids versus Vds relationships ndash Transconductance ndash pass transistor ndash nMOS inverter ndash Determination of pull up to pull down ratio for an Nmos inverter ndash CMOS inverter ndash MOS transistor circuit model

2 VLSI FABRICATION TECHNOLOGY Total Hrs 12

Overview of wafer fabrication ndash wafer processing ndash oxidation ndash patterning ndash Diffusion ndash Ion implantation ndash Deposition ndash Silicon gate nMOS process ndash nwell CMOS process ndash pwell CMOS process ndash Twintub process ndash Silicon on insulator

3 MOS AND CMOS CIRCUIT DESIGN PROCESS Total Hrs 12

MOS layers ndash Stick diagrams ndash nMOs design style ndash CMOS design style ndash Design rules and layout ndash Lambda based design rules ndash Contact cuts ndash Double metal MOS process rules ndash CMOS lambda based design rules ndash Sheet resistance ndash Inverter delay ndash Driving large capacitive loads ndash Wiring capacitance

4 SUBSYSTEM DESIGN Total Hrs 12

Switch logic ndash pass transistor and transmission gates ndash Gate logic ndash inverter ndash Two input NAND gate ndash NOR gate ndash other forms of CMOS logic ndash Dynamic CMOS logic ndash Clocked CMOS logic ndash CMOS domain logic ndash simple combinational logic design examples ndash Parity generator ndash Multiplexers

5 SEQUENTIAL CIRCUITS Total Hrs 12

Two phase clocking ndash Charge storage ndash Dynamic shift register ndash precharged bus ndash General arrangement of a 4 bit arithmetic processor ndash Design of a 4 bit shifter ndash FPGAs and PLDs

Total hours to be taught 60

Reference(s)

1 E Eshranghian DA Pucknell and S Eshraghian ―Essentials of VLSI circuits and systems PHI 2005

2 Neil HE Weste David Harris and Ayan Banerjee ―CMOS VLSI Design A circuits and Systems Perspective (3e) Pearson 2006

3 W Wolf ―Modern VLSI Design (3e) Pearson 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340104C VLSI DESIGN TECHNIQUES 3 0 0 3 50 50 100

Objective(s) To learn the CMOS processing technology and basic CMOS circuits CMOS transistor theory and logic design To study about verilog HDL programming

1 OVERVIEW OF VLSI DESIGN TECHNOLOGY Total Hrs 12

The VLSI design process ndash Architectural design ndash Logical design ndash physical design ndash Layout styles ndash Full custom ndash Semi custom approaches Basic electrical properties of MOS and CMOS circuits Ids versus Vds relationships ndash Transconductance ndash pass transistor ndash nMOS inverter ndash Determination of pull up to pull down ratio for an Nmos inverter ndash CMOS inverter ndash MOS transistor circuit model

2 VLSI FABRICATION TECHNOLOGY Total Hrs 12

Overview of wafer fabrication ndash wafer processing ndash oxidation ndash patterning ndash Diffusion ndash Ion implantation ndash Deposition ndash Silicon gate nMOS process ndash nwell CMOS process ndash pwell CMOS process ndash Twintub process ndash Silicon on insulator

3 MOS AND CMOS CIRCUIT DESIGN PROCESS Total Hrs 12

MOS layers ndash Stick diagrams ndash nMOs design style ndash CMOS design style ndash Design rules and layout ndash Lambda based design rules ndash Contact cuts ndash Double metal MOS process rules ndash CMOS lambda based design rules ndash Sheet resistance ndash Inverter delay ndash Driving large capacitive loads ndash Wiring capacitance

4 SUBSYSTEM DESIGN Total Hrs 12

Switch logic ndash pass transistor and transmission gates ndash Gate logic ndash inverter ndash Two input NAND gate ndash NOR gate ndash other forms of CMOS logic ndash Dynamic CMOS logic ndash Clocked CMOS logic ndash CMOS domain logic ndash simple combinational logic design examples ndash Parity generator ndash Multiplexers

5 SEQUENTIAL CIRCUITS Total Hrs 12

Two phase clocking ndash Charge storage ndash Dynamic shift register ndash precharged bus ndash General arrangement of a 4 bit arithmetic processor ndash Design of a 4 bit shifter ndash FPGAs and PLDs

Total hours to be taught 60

Reference(s)

1 E Eshranghian DA Pucknell and S Eshraghian ―Essentials of VLSI circuits and systems PHI 2005

2 Neil HE Weste David Harris and Ayan Banerjee ―CMOS VLSI Design A circuits and Systems Perspective (3e) Pearson 2006

3 W Wolf ―Modern VLSI Design (3e) Pearson 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340105C ADVANCED MICROPROCESSORS 3 0 0 3 50 50 100

Objective(s) To introduce the architecture and programming of 8086 68000 and advanced microprocessors and interfacing of peripheral devices with 8086 microprocessors

1 THE 8086 MICROPROCESSOR Total Hrs 12

Introduction - architecture addressing modes Instruction Format Data transfer Arithmetic Bit and Logical manipulation string program transfer and processor control instructions dependent instructions Pseudo instructions - Use of assembler and assembler directives simple math programme moving block of data arrange a block of data in ascending descending order

2 SYSTEM DESIGN USING 8086 Total Hrs 12

Pins and signals Basic system concepts interfacing with memories IO ports - Programmed IO - Input Output processor - Interrupts - DMA - 8086 based microcomputer - Math co processor 8087

3 MOTOROLA 68000 Total Hrs 12

Introduction - Registers - Memory addressing - Instruction format ndash addressing modes - Instruction set - Pins and signals - Memory interface - System diagram Programmed IO - Interrupt system - DMA - 68000 based microcomputer

4 OTHER MICROPROCESSOR Total Hrs 12

Intel 80386 80486 Pentium microprocessor - SUNlsquos SPARC microprocessor ndash AMD microprocessor - MOTOROLA 68040 MC88100

5 PERIPHERAL INTERFACING AND BUS STANDARDS Total Hrs 12

Parallel versus serial transmission USART Interfacing of hexadecimal keyboard and Display unit to a microprocessor - CRT Printer interface - DMA Controllers ISA bus PCI bus USB - RS232C RS423A RS-449 IDE ATA SCSI IEEE-488 bus

Total hours to be taught 60

Reference(s)

1 M Rafiquzzaman ―Microprocessors - Theory and applications Prentice Hall of India private Limited 2005

2 Barry BBrey ―The Intel Microprocessor Prentice Hall International Inc 2000

3 Badri Ram ―Advance Microprocessors and Interfacing Tata McGraw Hill Publishing Company limited 2007

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340107P ELECTRONICS DESIGN LABORATORY I

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Modeling of Combinational Digital system using VHDL 2 Modeling and design of 256 x 8bit RAM using VHDL 3 Implementation of MAC(Multiply and Accumulate) Unit using FPGA 4 Design and Implementation of ALU using FPGA 5 Design and Simulation of NMOS and CMOS Logic Gates using SPICE 6 Design and Simulation of CMOS Memory cell using SPICE 7 Design and Implementation of Convolution algorithm using DSP 8 Implementation of Adaptive Filters using DSP 9 Implementation of multi rate systems using DSP 10 Searching and sorting algorithms using 16 bit Microprocessor 11 Traffic Light Controller using 16- bit Microprocessor 12 FFT implementation using MASM-86 (Microsoft Assembler)

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 35 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340201S ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 3 50 50 100

Objective(s) It depend heavily on the utilization of suitable models for integrated circuit components It analyze the various circuit configuration n encountered in Linear Integrated Circuits It Explore several applications of opamps to illustrate their versatility in analog circuit and system design

1 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Total Hrs 12

Depletion region of a pn junction ndash large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors ndash weak inversion in MOS transistors- substrate current flow in MOS transistor

2 CIRCUIT CONFIGURATION FOR LINEAR IC Total Hrs 12

Current sources Analysis of difference amplifiers with active load using BJT and FET supply and temperature independent biasing techniques voltage references Output stages Emitter follower source follower and Push pull output stages

3 OPERATIONAL AMPLIFIERS Total Hrs 12

Analysis of operational amplifiers circuit slew rate model and high frequency analysis Frequency response of integrated circuits Single stage and multistage amplifiers Operational amplifier noise

4 ANALOG MULTIPLIER AND PLL Total Hrs 12

Analysis of four quadrant and variable trans conductance multiplier voltage controlled oscillator closed loop analysis of PLL Monolithic PLL design in integrated circuits Sources of noise- Noise models of Integrated-circuit Components ndash Circuit Noise Calculations ndash Equivalent Input Noise Generators ndash Noise Bandwidth ndash Noise Figure and Noise Temperature

5 ANALOG DESIGN WITH MOS TECHNOLOGY Total Hrs 12

MOS Current Mirrors ndash Simple Cascode Wilson and Widlar current source ndash CMOS Class AB output stages ndash Two stage MOS Operational Amplifiers with Cascode MOS Telescopic-Cascode Operational Amplifier ndash MOS Folded Cascode and MOS Active Cascode Operational Amplifiers

Total hours to be taught 60

Reference(s)

1 Gray Meyer Lewis Hurst ―Analysis and design of Analog IClsquos 4th

Edition Wiley International 2002

2 Behzad Razavi ―Design of Analog CMOS Integrated Circuits SChand and company ltd 2000

3 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modelling and Technology Prentice Hall of Indiapvtltd2004

4 Nandita Dasgupata Amitava Dasgupta Semiconductor Devices Modeling and Technology Prentice Hall of India PvtLtd 2004

5 Phillip EAllen Douglas R Holberg ―CMOS Analog Circuit Design Second Edition-Oxford University Press-2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340202C CAD OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To know about the algorithms that are used inside VLSI design automation tools and how these tools are used to design a VLSI chip

1 DESIGN METHODOLOGIES Total Hrs 12

Introduction to VLSI Design methodologies - Review of VLSI Design automation tools -

Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general

purpose methods for combinatorial optimization

2 LAYOUT DESIGN - I Total Hrs 12

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction -

placement and partitioning - Circuit representation - Placement algorithms ndash partitioning

3 LAYOUT DESIGN - II Total Hrs 12

Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems -

Area routing - channel routing - global routing - algorithms for global routing

4 SIMULATION AND SYNTHESIS Total Hrs 12

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -

Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis

5 HIGH LEVEL SYNTHESIS Total Hrs 12

High level Synthesis - Hardware models - Internal representation - Allocation - assignment and

scheduling - Simple scheduling algorithm - Assignment problem ndash High level transformations

Total hours to be taught 60

Reference(s)

1 SH Gerez Algorithms for VLSI Design Automation John Wiley amp Sons 2002

2 NA Sherwani Algorithms for VLSI Physical Design Automation Kluwar Academic Publishers 2002

3 Drechsler R Evolutionary Algorithms for VLSI CAD Kluwer Academic Publishers Boston 1998

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340203C DIGITAL CONTROL ENGINEERING 3 1 0 4 50 50 100

Objective(s) To learn and study about the signal processing in digital control and analysis of sampled data control system To learn design of digital control algorithms

1 INTRODUCTION Total Hrs 12

Overview of frequency and time response analysis and specifications of control systems - Digital

control systems ndash basic concepts of sampled data control systems ndash principle of sampling quantization

and coding ndash Reconstruction of signals ndash Sample and Hold circuits ndash Practical aspects of choice

of sampling rate -Basic discrete time signals ndash Time domain models for discrete time systems

2 MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS

Total Hrs 12

Z domain description of sampled continuous time plants ndash models of AD and DA converters ndash Z

Domain description of systems with dead time ndash Implementation of digital controllers ndash Digital PID

controllers ndashPosition velocity algorithms ndash Tuning ndash Zeigler ndash Nichols tuning method

3 STATE VARIABLE ANALYSIS Total Hrs 12

State space representation of discrete time systems ndash Solution of discrete time state space equation ndash

State transition matrix ndash Decomposition techniques ndash Controllability and Observability ndash Multi variable

discrete systems

4 STABILITY ANALYSIS Total Hrs 12

Mapping between S plane and Z plane- Jurys stability test - Bilinear transformation and extended

Routh array- Root Locus Method ndash Liapunov Stability Analysis of discrete time systems

5 DESIGN OF DIGITAL CONTROL SYSTEM Total Hrs 12

Z plane specifications of control system design ndash Digital compensator design ndash Frequency response method - State feed back ndash Pole placement design ndash State Observers ndash Digital filter properties ndash Frequency response ndash Kalmanlsquos filter

Total hours to be taught 60

Reference(s)

1 Gopal M Digital Control and State Variable methodslsquo Tata Mc Graw Hill Publishing Company Ltd New Delhi India 2003

2 Kuo BC Digital Control Systemslsquo Oxford University Press Inc 2003

3 Ogata K Discrete Time Control Systemslsquo Prentice Hall International New Gercy USA 2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340204S EMBEDDED SYSTEMS 3 0 0 3 50 50 100

Objective(s) To understand the concept of embedded Architecture and emphasis the knowledge of various processors and embedded networking

1 PIC MICROCONTROLLER 16F87X Total Hrs 12

Architecture - Features ndash Resets ndashMemory Organisations Program Memory Data Memory ndash Instruction Set ndash simple programs Interrupts ndashIO PortsndashTimers- CCP Modules- Master Synchronous serial Port

(MSSP)- USART ndashADC- I2C

2 EMBEDDED PROCESSORS Total Hrs 12

ARM processor- processor and memory organization Data operations Flow of Control CPU Bus configuration ARM Bus Memory devices Inputoutput devices Component interfacing designing with microprocessor development and debugging Design Example Alarm Clock

3 EMBEDDED PROGRAMMING Total Hrs 12

Programming in Assembly Language(ALP) Vs High level language ndash C program elements Macros and Functions ndash Use of pointers ndash NULL pointers ndash use of function calls ndash multiple function calls in a cyclic order in the main function pointers ndash Function queues and interrupt service Routines queues pointers ndash Concepts of Embedded programming in C++ - Object oriented programming ndash Embedded programming in C++ C program compilers ndash Cross compiler ndash optimization of memory codes

4 EMBEDDED SYSTEM CO-DESIGN Total Hrs 12

Embedded System project management ndash Embedded system design and Co-Design Issues in System Development process ndash Design cycle in the development phase for an embedded system ndash Uses of Target system or its emulator and In-Circuit Emulator ndash Use of software Tools for Development of an embedded system ndash Use of scopes and logic analyzers for system hardware tests ndash Issues in Embedded System Design

5 REAL-TIME OPERATING SYSTEMS Total Hrs 12

Operating system services ndashIO subsystems ndash Network operating systems ndashInterrupt Routines in RTOS Environment ndash RTOS Task scheduling models Interrupt ndash Performance Metric in Scheduling Models ndash IEEE standard POSIX functions for standardization of RTOS and inter-task communication functions ndash List of Basic functions in a Preemptive scheduler ndash Fifteen point strategy for synchronization between processors ISRs OS Functions and Tasks ndash OS security issues- Mobile OS

Total hours to be taught 60

Reference(s)

1 Raj Kamal Embedded Systems Architecture Programming and Design Tata McGraw-Hill New Delhi 2003

2 Wayne Wolf Computers as Components Principles of Embedded Computing System Design Morgan Kaufman Publishers 2001

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340207P ELECTRONICS DESIGN LAB0RAT0RY II

0 0 3 2 50 50 100

LIST OF EXPERIMENTS

1 Design and simulation of Operational amplifier using PSPICE 2 Design and simulation of analog multiplier using PSPICE 3 Design of PLL using PSPICE MATLAB

4 Keyboard Interface using embedded micro controller

5 LED and LCD Interface using embedded micro controller

6 EEPROM Interface using embedded micro controller

7 RTD and Thermocouple Interface using embedded micro controller 8 ADC and DAC Interface using embedded micro controller

9 I2C RTC interface using embedded micro controller

10 Alarm clock using embedded micro controller

11 Simulation of Non adaptive Digital Control System using MATLAB control system toolbox 12 Simulation of Adaptive Digital Control System using MATLAB control system toolbox

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester II

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

07340209P TECHNICAL REPORT PREPARATION amp PRESENTATION I

0 0 3 2 100 00 100

Objective(s) To provide exposure to the students to refer read and review the research articles in referred journals and conference proceedings To Improve the technical report writing and presentation skills of the students

Methodology Each student is allotted to a faculty of the department by the HOD

By mutual discussions the faculty guide will assign a topic in the general subject area to the student

The students have to refer the Journals and Conference proceedings and collect the published literature

The student is expected to collect atleast 20 such Research Papers published in the last 5 years

Using OHPPower Point the student has to make presentation for 15-20 minutes followed by 10 minutes discussion

The student has make two presentations one at the middle and the other near the end of the semester

The student has to write a Technical Report for about 30-50 pages (Title page One page Abstract Review of Research paper under various subheadings Concluding Remarks and List of References) The technical report has to be submitted to the HOD one week before the final presentation after the approval of the faculty guide

Execution

Week Activity

I Allotment of Faculty Guide by the HoD

II Finalizing the topic with the approval of Faculty Guide

III-IV Collection of Technical papers

V-VI Mid semester presentation

VII-VIII Report writing

IX Report submission

X-XI Final presentation

Evaluation

50 by Continuous Assessment and 50 by End Semester examination 3 Hrsweek and 2 credits

Component Weightage

Mid semester presentation 25

Final presentation (Internal) 25

End Semester Examination Report 30

Presentation 20

Total 100

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073441E HIGH PERFORMANCE COMMUNICATION NETWORKS

3 0 0 3 50 50 100

Objective(s) To understand the wired and wireless local area networks To learn the various services interfaces and signaling protocols in ISDN and the basis of ATM and the internetworking with ATM

1 PACKET SWITCHED NETWORKS Total Hrs 9

OSI and IP models Ethernet (IEEE 8023) Token ring (IEEE 8025) Wireless LAN (IEEE 80211) FDDI DQDB SMDS Internetworking with SMDS

2 ISDN AND BROADBAND ISDN Total Hrs 9

ISDN - overview interfaces and functions Layers and services - Signaling System 7 - Broadband ISDN architecture and Protocols

3 ATM AND FRAME RELAY Total Hrs 9

ATM Main features-addressing signaling and routing ATM header structure-adaptation layer management and control ATM switching and transmission Frame Relay Protocols and services Congestion control Internetworking with ATM Internet and ATM Frame relay via ATM

4 ADVANCED NETWORK ARCHITECTURE Total Hrs 9

IP forwarding architectures overlay model Multi Protocol Label Switching (MPLS) integrated services in the Internet Resource Reservation Protocol (RSVP) Differentiated services

5 BLUE TOOTH TECHNOLOGY Total Hrs 9

The Blue tooth module-Protocol stack Part I Antennas Radio interface Base band The Link controller Audio The Link Manager The Host controller interface The Blue tooth module-Protocol stack Part I Logical link control and adaptation protocol RFCOMM Service discovery protocol Wireless access protocol Telephony control protocol

Total hours to be taught 45

Reference(s)

1 William StallingsISDN and Broadband ISDN with Frame Relay and ATM 4

th edition Pearson

education Asia 2002

2 Leon Gracia Widjaja ―Communication networks Tata McGraw-Hill New Delhi 2000

3 Jennifer Bray and Charles FSturmanBlue Tooth Pearson education Asia 2001

4 Sumit Kasera Pankaj Sethi ―ATM Networks Tata McGraw-Hill New Delhi 2000

5 Rainer Handel Manfred NHuber Stefan SchroderATM Networks3

rd edition Pearson education

asia2002

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073442E WAVELET TRANSFORMS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) To study about the wavelet transform and multire solution analysis and applications of Digital Signal Processing

1 MATHEMATICAL PRELIMINARIES Total Hrs 9

Linear spaces ndash Vectors and vector spaces ndash Basis functions ndash Dimensions ndash Orthogonality and biorthogonalilty ndash Local basis and Riesz basis ndash Discrete linear normed space ndash Approximation by orthogonal projection ndash Matrix algebra and linear transformation

2 TIME FREQUENCY ANALYSIS Total Hrs 9

Window function ndash Short time Fourier transform ndash Discrete short time Fourier transform ndash Discrete Gabor representation ndash Continuous wavelet transform ndash Discrete wavelet transform ndash Wigner-Ville distribution ndash Properties of Wigner -Ville distribution

3 MULTIRESOLUTION ANALYSIS Total Hrs 9

Multiresolution spaces Orthogonal biorthogonal and semiorthogonal decomposition Two scale relations Decomposition relation Wavelets construction ndash Orthogonal wavelets ndash Orthonormal scaling functions ndash Construction of biorthogonal wavelets

4 DISCRETE WAVELET TRANSFORM AND FILTER BANK ALGORITHMS

Total Hrs 9

Decimation and interpolation ndash Signal representation in the approximation subspace ndash Wavelet decomposition algorithm ndash Reconstruction algorithm ndash Change of bases ndash Two channel perfect reconstruction filter bank ndash Polyphase representation for filter banks

5 DIGITAL SIGNAL PROCESSING APPLICATIONS Total Hrs 9

Wavelet packets ndash Wavelet packet algorithms ndash Thresholding ndash Two dimensional wavelets and wavelet packets ndash Wavelet and wavelet packet algorithms for two dimensional signals ndash image compression ndash image coding wavelet tree coder EZW code EZW example

Total hours to be taught 45

Reference(s)

1 Jaideva C Goswami and Andrew K Chan ―Fundamentals of Wavelet- Theory Algorithms and Applications A Wiley ndash Interscience Publication 1999

2 Rao RM and AS Bopardikar ―Wavelet Transforms Addison Wesley 1998

3 Strang G Nguyen T ―Wavelet and filter banks Wellesley Cambridge Press 1996

4 Vetterli M Kovacevic J ―Wavelets and Subband Coding Prentice Hall 1995

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073443E NEURAL NETWORKS AND APPLICATIONS

3 0 0 3 50 50 100

Objective(s) Students will get an introduction about artificial neural networks and its types students will be provided with an up to date developments in artificial neural networks Enable the students to know techniques involved to support pattern recognitions amp feature extraction

1 INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS Total Hrs 9

Neuro-physiology- General Processing Element ndash ADALINE ndash LMS learning rule ndash MADALINE ndash MR2 training algorithm

2 BPN AND BAM Total Hrs 9

Back Propagation Network ndash updating of output and hidden layer weights ndash application of BPN ndash associative memory ndash Bi-Associative Memory ndash Hopfield memory ndash traveling sales man problem

3 SIMULATED ANNEALING AND CPN Total Hrs 9

Annealing Boltzmann machine ndash learning ndash application ndash Counter Propagation ndash Network ndash architecture ndash training ndash Applications

4 SOM AND ART Total Hrs 9

Self organizing map- learning algorithm ndash feature map classifier ndash applications ndash architecture of Adaptive Resonance Theory ndash pattern matching in ART network

5 NEOCOGNITRON Total Hrs 9

Architecture of Neocognitron ndash Data processing and performance of architecture of sptio ndash temporal networks for speech recognition

Total hours to be taught 45

Reference(s)

1 JA Freeman and BMSkapura ―Neural Networks Algorithms Applications and Programming Techniques Addison ndash Wesely 1990

2 Laurene Fausett ―Fundamentals of Neural Networks Architecture Algorithms and Application Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073444E DESIGN OF SEMICONDUCTOR MEMORIES

3 0 0 3 50 50 100

Objective(s) To learn the technologies for designing semiconductor memories to know the methods of testing semiconductor memories To study the techniques involved in packaging of memories

1 RANDOM ACCESS MEMORY TECHNOLOGIES Total Hrs 9

STATIC RANDOM ACCESS MEMORIES (SRAMs) SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-BipolarSRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs DYNAMIC RANDOM ACCESS MEMORIES (DRAMs) DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Structures-BiCMOSDRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application Specific DRAMs

2 NONVOLATILE MEMORIES Total Hrs 9

Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) Eproms-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-AdvancedFlash Memory Architecture

3 MEMORY FAULT MODELING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE

Total Hrs 9

RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

4 SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

Total Hrs 9

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification RAM Fault Modeling Electrical Testing Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing

5 PACKAGING TECHNOLOGIES Total Hrs 9

Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magneto resistive Random Access Memories (MRAMs)-Experimental Memory Devices Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions

Total hours to be taught 45

Reference(s)

1 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Wiley-IEEE Press 2002

2 Ashok K Sharma Semiconductor Memories Two-Volume Set Wiley-IEEE Press 2003

3 Ashok K Sharma Semiconductor Memories Technology Testing and Reliability Prentice Hall of India 1997

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073445E COMPUTATIONAL INTELLIGENT TECHNIQUES

3 0 0 3 50 50 100

Objective(s) To understand the basics of Fuzzy logic and its modeling concepts and the fundamentals of neural networks and its learning concepts To learn the basics of genetic algorithm and its optimization principles

1 FUZZY LOGIC Total Hrs 9

Introduction to Neuro ndash Fuzzy and soft Computing ndash Fuzzy Sets ndash Basic Definition and Terminology ndash Set-theoretic operations ndash Member Function Formulation and parameterization ndash Fuzzy Rules and Fuzzy Reasoning- Extension principle and Fuzzy Relations ndash Fuzzy If-Then Rules ndash Fuzzy Reasoning ndash Fuzzy Inference Systems ndash Mamdani Fuzzy Models-Sugeno Fuzzy Models ndash Tsukamoto Fuzzy Models ndash Input Space Partitioning and Fuzzy Modeling

2 GENETIC ALGORITHM Total Hrs 9

Derivative-based Optimization ndash Descent Methods ndash The Method of steepest Descent ndash Classical Newtonlsquos Method ndash Step Size Determination ndash Derivative-free Optimization ndash Genetic Algorithms ndash Simulated Annealing ndash Random Search ndash Downhill Simplex Search

3 NEURAL NETWORKS1 Total Hrs 9

Introduction -Supervised Learning Neural Networks ndash Perceptrons - Adaline ndash Back propagation Multilayer perceptrons Radial Basis Function Networks ndash Unsupervised Learning and Other Neural Networks ndash Competitive Learning Networks ndash Kohonen Self ndash Organizing Networks ndash Learning Vector Quantization ndash Hebbian Learning

4 NEURO FUZZY MODELING Total Hrs 9

Adaptive Neuro-Fuzzy Inference Systems ndash Architecture ndash Hybrid Learning Algorithm ndash learning Methods that Cross-fertilize ANFIS and RBFN ndash Coactive Neuro-Fuzzy Modeling ndash Framework ndash Neuron Functions for Adaptive Networks ndash Neuro Fuzzy Spectrum

5 APPLICATIONS Total Hrs 9

Printed Character Recognition ndash Inverse Kinematics Problems ndash Automobile Fuel Efficiency prediction ndash Soft Computing for Color Recipe Prediction

Total hours to be taught 45

Reference(s)

1 JSRJang CTSun and EMizutani ―Neuro-Fuzzy and Soft Computing PHI Pearson Education

2004

2 Davis EGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley NY1989

3 SRajasekaran and GAVPaiNeural Networks Fuzzy Logic and Genetic AlgorithmsPHI 2003

4 REberhart PSimpson and RDobbins Computational Intelligence PC Tools AP professional Boston 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073446E ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

3 0 0 3 50 50 100

Objective(s) If explain the architecture and addressing modes of 8086 MOTOROLA 68000 microprocessor and Also it explain the peripheral interface

1 MICROPROCESSOR ARCHITECTURE Total Hrs 9

Instruction set ndash Data formats ndash Instruction formats ndash Addressing modes ndash Memory hierarchy ndash register file ndash Cache ndash Virtual memory and paging ndash Segmentation ndash Pipelining ndash The instruction pipeline ndash pipeline hazards ndash Instruction level parallelism ndash reduced instruction set ndash Computer principles ndash RISC versus CISC ndash RISC properties ndash RISC evaluation ndash On-chip register files versus cache evaluation

2 HIGH PERFORMANCE CISC ARCHITECTURE ndash PENTIUM Total Hrs 9

The software model ndash functional description ndash CPU pin descriptions ndash RISC concepts ndash bus operations ndash Super scalar architecture ndash pipe lining ndash Branch prediction ndash The instruction and caches ndash Floating point unit ndashprotected mode operation ndash Segmentation ndash paging ndash Protection ndash multitasking ndash Exception and interrupts ndash Input Output ndash Virtual 8086 model ndash Interrupt processing -Instruction types ndash Addressing modes ndash Processor flags ndash Instruction set -programming the Pentium processor

3 HIGH PERFORMANCE RISC ARCHITECTURE ARM Total Hrs 9

The ARM architecture ndash ARM assembly language program ndash ARM organization and implementation ndash The ARM instruction set - The thumb instruction set ndash ARM CPU cores

4 MOTOROLA 68HC11 MICROCONTROLLERS Total Hrs 9

Instructions and addressing modes ndash operating modes ndash Hardware reset ndash Interrupt system ndash Parallel IO ports ndash Flags ndash Real time clock ndash Programmable timer ndash pulse accumulator ndash serial communication interface ndash AD converter ndash hardware expansion ndash Assembly language Programming

5 PIC MICRO CONTROLLER Total Hrs 9

CPU architecture ndash Instruction set - Interrupts ndash Timers ndash IO port expansion ndashI2C bus for peripheral chip access

ndash AD converter ndash UART

Total hours to be taught 45

Reference(s)

1 Daniel Tabak lsquo Advanced Microprocessors McGraw HillInc 1995

2 James L Antonakos ― The Pentium Microprocessor lsquo Pearson Education 1997

3 Steve Furber lsquo ARM System ndashOn ndashChip architecture ―Addison Wesley 2000

4 Gene HMiller Micro Computer Engineering Pearson Educatio 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073447E LOW POWER VLSI DESIGN 3 0 0 3 50 50 100

Objective(s) To emphasize the optimization and trade ndash off techniques that involve power dissipation the basic principles methodologies and techniques that are common to CMOS digital design

1 POWER DISSIPATION IN CMOS Total Hrs 9

Hierarchy of limits of power ndash Sources of power consumption ndash Physics of power dissipation in CMOS FET devices- Basic principle of low power design

2 POWER OPTIMIZATION Total Hrs 9

Logical level power optimization ndash Circuit level low power design ndash Circuit techniques for reducing power consumption in adders and multipliers

3 DESIGN OF LOW POWER CMOS CIRCUITS Total Hrs 9

Computer Arithmetic techniques for low power systems ndash Reducing power consumption in memories ndash Low power clock Interconnect and layout design ndash Advanced techniques ndash Special techniques

4 POWER ESTIMATION Total Hrs 9

Power estimation techniques ndash Logic level power estimation ndash Simulation power analysis ndash Probabilistic power analysis

5 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Total Hrs 9

Synthesis for low power ndashBehavioral level transforms- Software design for low power

Total hours to be taught 45

Reference(s)

1 KRoy and SC Prasad LOW POWER CMOS VLSI circuit design Wiley2000

2 Dimitrios Soudris Chirstian Pignet Costas Goutis DESIGNING CMOS CIRCUITS FOR LOW POWER Kluwer2002

3 JB Kuo and JH Lou Low voltage CMOS VLSI Circuits Wiley 1999

4 SY Kung HJ White House T Kailath ―VLSI and Modern Signal Processing Prentice Hall 1985

5 Jose E France Yannis Tsividis ―Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing Prentice Hall 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073448E ANALOG VLSI DESIGN 3 0 0 3 50 50 100

Objective(s)

Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques and Concepts of Continuous-Time Signal Processing- Low-Voltage Signal Processing and Current-Mode Signal Processing Neural Information Processing and Analog VLSI Interconnects

1 BASIC CMOS CIRCUIT TECHNIQUES CONTINUOUS TIME AND LOW-VOLTAGE SIGNALPROCESSING

Total Hrs 9

Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOS Transistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters

2 BASIC BICMOS CIRCUIT TECHNIQUES CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING

Total Hrs 9

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina

3 SAMPLED-DATA ANALOG FILTERS OVER SAMPLED AD CONVERTERS AND ANALOG INTEGRATED SENSORS

Total Hrs 9

First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-Switched-Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate AD Converters-Modulators for Over sampled AD Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators ndashCascaded Architecture-Decimation Filters-mechanical Thermal Humidity and Magnetic Sensors-Sensor Interfaces

4 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Total Hrs 9

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits

5 STATISTICAL MODELING AND SIMULATION ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT

Total Hrs 9

Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout

Total hours to be taught 45

Reference(s)

1 Mohammed Ismail Terri Fiez ―Analog VLSI signal and Information Processing McGraw-Hill International Editons 1994

2 Malcom RHaskard Lan CMay ―Analog VLSI Design - NMOS and CMOS Prentice Hall 1998

3 Randall L Geiger Phillip E Allen Noel KStrader VLSI Design Techniques for Analog and Digital Circuits Mc Graw Hill International Company 1990

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073449E ASIC DESIGN 3 0 0 3 50 50 100

Objective(s) To Know about the hardware and software which are involved in an application specific integrated circuits And to know how to design an application specific integrated circuits for a specific application

1 INTRODUCTION TO ASICS CMOS LOGIC AND ASIC LIBRARY DESIGN

Total Hrs 9

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell ndash Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort ndashLibrary cell design - Library architecture

2 PROGRAMMABLE ASICS PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC IO CELLS

Total Hrs 9

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA ndash Altera FLEX - Altera MAX DC amp AC inputs and outputs - Clock amp Power inputs - Xilinx IO blocks

3 PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY

Total Hrs 9

Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera FLEX ndash Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design representation

4 LOGIC SYNTHESIS SIMULATION AND TESTING Total Hrs 9

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation

5 ASIC CONSTRUCTION FLOOR PLANNING PLACEMENT AND ROUTING

Total Hrs 9

System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow global routing - detailed routing - special routing - circuit extraction - DRC

Total hours to be taught 45

Reference(s)

1 MJS Smith Application Specific Integrated Circuits Addison -Wesley Longman Inc 1997

2 Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs A Practical Approach Prentice Hall PTR 2003

3 Wayne Wolf FPGA-Based System Design Prentice Hall PTR 2004

4 R Rajsuman System-on-a-Chip Design and Test Santa Clara CA Artech House Publishers 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and

Communication Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073450E DSP INTEGRATED CIRCUITS 3 0 0 3 50 50 100

Objective(s) To study DSP system design amp CMOS technologies and study DFT amp FFT computation To introduce the architecture of synthesis of DSP

1 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Total Hrs 9

Standard digital signal processors Application specific IClsquos for DSP DSP systems DSP system design Integrated circuit design MOS transistors MOS logic VLSI process technologies Trends in CMOS technologies

2 DIGITAL SIGNAL PROCESSING Total Hrs 9

Digital signal processing Sampling of analog signals Selection of sample frequency Signal-processing systems Frequency response Transfer functions Signal flow graphs Filter structures Adaptive DSP algorithms DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding Discrete cosine transforms

3 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

Total Hrs 9

FIR filters FIR filter structures FIR chips IIR filters Specifications of IIR filters Mapping of analog transfer functions Mapping of analog filter structures Multirate systems Interpolation with an integer factor L Sampling rate change with a ratio LM Multirate filters Finite word length effects -Parasitic oscillations Scaling of signal levels Round-off noise Measuring round-off noise Coefficient sensitivity Sensitivity and noise

4 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

Total Hrs 9

DSP system architectures Standard DSP architecture Ideal DSP architectures Multiprocessors and multicomputers Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit ndash serial PEs

5 NUMBER SYSTEMS ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN

Total Hrs 9

Conventional number system Redundant Number system Residue Number System Bit-parallel and Bit-Serial arithmetic Basic shift accumulator Reducing the memory size Complex multipliers Improved shift-accumulator Layout of VLSI circuits FFT processor DCT processor and Interpolator as case studies

Total hours to be taught 45

Reference(s)

1 Lars Wanhammer ―DSP INTEGRATED CIRCUITS Academic press New York 1999

2 AVOppenheim etal Discrete-time Signal Processinglsquo Pearson education 2000

3 Emmanuel C Ifeachor Barrie W Jervis ―Digital signal processing ndash A practical

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073451E ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN

3 0 0 3 50 50 100

Objective(s) To learn about EMI Environment EMI Coupling Principles and EMI Specification Standards and Limits

1 EMI ENVIRONMENT Total Hrs 9

EMIEMC concepts and definitions Sources of EMI conducted and radiated EMI Transient EMI Time domain Vs Frequency domain EMI Units of measurement parameters Emission and immunity concepts ESD

2 EMI COUPLING PRINCIPLES Total Hrs 9

Conducted Radiated and Transient Coupling Common Impedance Ground Coupling Radiated Common Mode and Ground Loop Coupling Radiated Differential Mode Coupling Near Field Cable to Cable Coupling Power Mains and Power Supply coupling

3 EMIEMC STANDARDS AND MEASUREMENTS Total Hrs 9

Civilian standards - FCC CISPR IEC EN Military standards - MIL STD 461D462 EMI Test Instruments Systems EMI Shielded Chamber Open Area Test Site TEM Cell SensorsInjectorsCouplers Test beds for ESD and EFT Military Test Method and Procedures (462)

4 EMI CONTROL TECHNIQUES Total Hrs 9

Shielding Filtering Grounding Bonding Isolation Transformer Transient Suppressors Cable Routing Signal Control Component Selection and Mounting

5 EMC DESIGN OF PCBs Total Hrs 9

PCB Traces Cross Talk Impedance Control Power Distribution Decoupling Zoning Motherboard Designs and Propagation Delay Performance Models

Total hours to be taught 45

Reference(s)

1 Henry WOtt Noise Reduction Techniques in Electronic Systems John Wiley and Sons NewYork 1988

2 CRPaul ―Introduction to Electromagnetic Compatibility John Wiley and Sons Inc 1992

3 VPKodali Engineering EMC Principles Measurements and Technologies IEEE Press 1996

4 Bernhard Keiser Principles of Electromagnetic Compatibility Artech house 3rd Ed 1986

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073452E SPEECH AND AUDIO SIGNAL PROCESSING

3 0 0 3 50 50 100

Objective(s) Introduction to Analog VLSI and Basic CMOS and BiCMOS Circuit Techniques Mode Signal Processing and Neural Information Processing and Analog VLSI Interconnects

1 MECHANICS OF SPEECH Total Hrs 9

Speech production mechanism ndash Nature of Speech signal ndash Discrete time modelling of Speech production ndash Representation of Speech signals ndash Classification of Speech sounds ndash Phones ndash Phonemes ndash Phonetic and Phonemic alphabets ndash Articulatory features Music production ndash Auditory perception ndash Anatomical pathways from the ear to the perception of sound ndash Peripheral auditory system ndash Psycho acoustics

2 TIME DOMAIN METHODS FOR SPEECH PROCESSING Total Hrs 9

Time domain parameters of Speech signal ndash Methods for extracting the parameters Energy Average Magnitude ndash Zero crossing Rate ndash Silence Discrimination using ZCR and energy ndash Short Time Auto Correlation Function ndash Pitch period estimation using Auto Correlation Function

3 FREQUENCY DOMAIN METHOD FOR SPEECH PROCESSING

Total Hrs 9

Short Time Fourier analysis ndash Filter bank analysis ndash Formant extraction ndash Pitch Extraction ndash Analysis by Synthesis- Analysis synthesis systems- Phase vocodermdashChannel Vocoder HOMOMORPHIC SPEECH ANALYSIS Cepstral analysis of Speech ndash Formant and Pitch Estimation ndash Homomorphic Vocoders

4 LINEAR PREDICTIVE ANALYSIS OF SPEECH Total Hrs 9

Formulation of Linear Prediction problem in Time Domain ndash Basic Principle ndash Auto correlation method ndash Covariance method ndash Solution of LPC equations ndash Cholesky method ndash Durbinlsquos Recursive algorithm ndash lattice formation and solutions ndash Comparison of different methods ndash Application of LPC parameters ndash Pitch detection using LPC parameters ndash Formant analysis ndash VELP ndash CELP

5 APPLICATION OF SPEECH amp AUDIO SIGNAL PROCESSING Total Hrs 9

Algorithms Spectral Estimation dynamic time warping hidden Markov model ndash Music analysis ndash Pitch Detection ndash Feature analysis for recognition ndash Music synthesis ndash Automatic Speech Recognition ndash Feature Extraction for ASR ndash Deterministic sequence recognition ndash Statistical Sequence recognition ndash ASR systems ndash Speaker identification and verification ndash Voice response system ndash Speech Synthesis Text to speech voice over IP

Total hours to be taught 45

Reference(s)

1 Ben Gold and Nelson Morgan Speech and Audio Signal Processing John Wiley and Sons Inc Singapore 2004

2 LRRabiner and RWSchaffer ndash Digital Processing of Speech signals ndash Prentice Hall -1978

3 Quatieri ndash Discrete-time Speech Signal Processing ndash Prentice Hall ndash 2001

4 JLFlanagan ndash Speech analysis Synthesis and Perception ndash 2nd

edition ndash Berlin ndash 1972

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073453E RELIABILITY ENGINEERING 3 0 0 3 50 50 100

Objective(s) To study about Reliability Fundamentals Basics of System Reliability and Device Reliability and Reliability Techniques

1 PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Total Hrs 9

Statistical distribution statistical confidence and hypothesis testing probability plotting techniques ndash Weibull extreme value hazard binomial data Analysis of load ndash strength interference Safety margin and loading roughness on reliability

2 RELIABILITY PREDICTION MODELLING AND DESIGN Total Hrs 9

Statistical design of experiments and analysis of variance Taguchi method Reliability prediction Reliability modeling Block diagram and Fault tree Analysis petric Nets State space Analysis Monte carlo simulation Design analysis methods ndash quality function deployment load strength analysis failure modes effects and criticality analysis

3 ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY Total Hrs 9

Reliability of electronic components component types and failure mechanisms Electronic system reliability prediction Reliability in electronic system design software errors software structure and modularity fault tolerance software reliability prediction and measurement hardwaresoftware interfaces

4 RELIABILITY TESTING AND ANALYSIS Total Hrs 9

Test environments testing for reliability and durability failure reporting Pareto analysis Accelerated test data analysis CUSUM charts Exploratory data analysis and proportional hazards modeling reliability demonstration reliability growth monitoring

5 MANUFACTURE AND RELIABILITY MAQNAGEMENT Total Hrs 9

Control of production variability Acceptance sampling Quality control and stress screening Production failure reporting preventive maintenance strategy Maintenance schedules Design for maintainability Integrated reliability programmes reliability and costs standard for reliability quality and safety specifying reliability organization for reliability

Total hours to be taught 45

Reference(s)

1 Patrick DT OlsquoConnor David Newton and Richard Bromley Practical Reliability Engineering Fourth edition John Wiley amp Sons 2002

2 David J Klinger Yoshinao Nakada and Maria A Menendez Von Nostrand Reinhold New York AT amp T Reliability Manual 5th Edition 1998

3 Gregg K Hobbs Accelerated Reliability Engineering - HALT and HASS John Wiley amp Sons New York 2000

4 Lewis Introduction to Reliability Engineering 2nd Edition Wiley International 1996

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073454E DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

3 0 0 3 50 50 100

Objective(s) Introduction to DSP Processors DSP family processors and Architecture of TMS320C5X and TMS320C3X Processor

1 FUNDAMENTALS OF PROGRAMMABLE DSPs Total Hrs 9

Multiplier and Multiplier accumulator ndash Modified Bus Structures and Memory access in P-DSPs ndash Multiple access memory ndash Multi-port memory ndash VLIW architecture- Pipelining ndash Special Addressing modes in P-DSPs ndash On chip Peripherals

2 TMS320C5X PROCESSOR Total Hrs 9

Architecture ndash Assembly language syntax - Addressing modes ndash Assembly language Instructions - Pipeline structure Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals

3 TMS320C3X PROCESSOR Total Hrs 9

Architecture ndash Data formats - Addressing modes ndash Groups of addressing modes - Instruction sets - Operation ndash Block Diagram of DSP starter kit ndash Application Programs for processing real time signals ndash Generating and finding the sum of series Convolution of two sequences Filter design

4 ADSP PROCESSORS Total Hrs 9

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors - Addressing modes and assembly language instructions ndash Application programs ndashFilter design FFT calculation

5 ADVANCED PROCESSORS Total Hrs 9

Architecture of TMS320C54X Pipe line operation Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX ndash Comparison of the features of DSP family processors

Total hours to be taught 45

Reference(s)

1 BVenkataramani and MBhaskar ―Digital Signal Processors ndash Architecture Programming and Applications ndash Tata McGraw ndash Hill Publishing Company Limited New Delhi 2003

2 User guides Texas Instrumentation Analog Devices Motorola

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073455E PHYSICAL DESIGN OF VLSI CIRCUITS 3 0 0 3 50 50 100

Objective(s) To learn the standard algorithms for VLSI physical design automation placement and routing algorithms and floor planning algorithms

1 INTRODUCTION TO VLSI TECHNOLOGY Total Hrs 9

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates field programmable gate array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms

2 PLACEMENT USING TOP-DOWN APPROACH Total Hrs 9

Partitioning Approximation of Hyper Graphs with Graphs Kernighan-Lin Heuristic- Ratiocut- partition with capacity and io constrantsFloor planning Rectangular dual floor planning- hierarchial approach- simulated annealing- Floor plan sizing-Placement Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network ndash regular placement- linear placement

3 ROUTING USING TOP DOWN APPROACH Total Hrs 9

Fundamentals Maze Running- line searching- Steiner trees Global Routing Sequential Approaches- hierarchial approaches- multicommodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming Detailed Routing Channel Routing- Switch box routing Routing in FPGA Array based FPGA- Row based FPGAs

4 PERFORMANCE ISSUES IN CIRCUIT LAYOUT Total Hrs 9

Delay Models Gate Delay Models- Models for interconnected Delay- Delay in RC trees Timing ndash Driven Placement Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing Delay Minimization- Click Skew Problem- Buffered Clock Trees Minimization constrained via Minimization- unconstrained via Minimization- Other issues in minimization

5 SINGLE LAYER ROUTING CELL GENERATION AND COMPACTION

Total Hrs 9

Planar subset problem(PSP)- Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique ndash Over The Cell (OTC) Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction

Total hours to be taught 45

Reference(s)

1 Sarafzadeh CK Wong ―An Introduction to VLSI Physical Design Mc Graw Hill International Edition 1995

2 Preas M Lorenzatti ― Physical Design and Automation of VLSI systems The Benjamin Cummins Publishers 1998

3 Naveed A Sherwani ―Algorithm for VLSI Physical Design Automation 3rd

Edition Springer 1998

4 Ban Wong Anurag Mittal Yu Cao Greg Starr ―Nano CMOS Circuit and Physical Design Wiley John amp Sons Incorporated 2004

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073456E DIGITAL IMAGE PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the image fundamentals and mathematical transforms necessary for image processing image enhancement techniques and image restoration procedures

1 DIGITAL IMAGE FUNDAMENTALS Total Hrs 9

Fundamental steps in Digital Image processing ndash Components of an image processing system - - elements of visual perception ndash Image sensing and acquisition- image sampling and quantization

2 IMAGE TRANSFORMS Total Hrs 9

Two dimensional orthogonal and unitary transforms - properties of unitary transforms - one dimensional DFT - - two dimensional DFT- DCT Discrete sine Walsh Hadamard Slant Haar KLT SVD Radom and wavelet transforms

3 IMAGE ENHANCEMENT AND RESTORATION Total Hrs 9

Basic gray level transformations ndash Histogram equalization ndash Histogram matching -spatial filtering ndash smoothing spatial filters ndash sharpening spatial filters- model of the image degradation Restoration process- mean filters ndash order ndash statistics filters- Adaptive filters ndash Inverse filtering ndash minimum mean square error filtering ndash constrained least squares filtering ndash Geometric mean filter ndash geometric transformations

4 IMAGE SEGMENTATION AND RECOGNITION Total Hrs 9

Detection of Discontinuities ndash Edge linking and boundary detection ndash Region based segmentation ndash morphological operators Dilation erosion opening and closing Image recognition patterns and pattern classes Recognition based on decision ndash theoretic methods

5 IMAGE COMPRESSION Total Hrs 9

Fundamentals of Image compression - Image compression models ndash Error free Compression ndash Lossy Compression ndash Image compression standards

Total hours to be taught 45

Reference(s)

1 Gonzalez Rafel C Woods Richard E Digital Image Processing second edition Prentice Hall 2006

2 Jain Anil K Fundamentals of Digital Image Processing- Prentice Hall of India 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073457E ROBOTICS 3 0 0 3 50 50 100

Objective(s) To understand the sensing mechanism and the intelligence of robots To learn know the robots realize the images and recognize the captured images functions of different types of sensors

1 INTRODUCTION TO ROBOTICS Total Hrs 9

Motion - Potential Function Road maps Cell decomposition and Sensor and sensor planning Kinematics Forward and Inverse Kinematics - Transformation matrix and DH transformation Inverse Kinematics - Geometric methods and Algebraic methods Non-Holonomic constraints

2 COMPUTER VISION Total Hrs 9

Projection - Optics Projection on the Image Plane and Radiometry Image Processing - Connectivity Images-Gray Scale and Binary Images Blob Filling Thresholding Histogram Convolution - Digital Convolution and Filtering and Masking Techniques Edge Detection - Mono and Stereo Vision

3 SENSORS AND SENSING DEVICES Total Hrs 9

Introduction to various types of sensor Resistive sensors Range sensors - Ladar (laser distance and ranging) Sonar Radar and Infra-red Introduction to sensing - Light sensing Heat sensing Touch sensing and Position sensing

4 ARTIFICIAL INTELLIGENCE Total Hrs 9

Uniform Search strategies - Breadth first Depth first Depth limited Iterative and deepening depth first search and Bidirectional search The A algorithm Planning - State-Space Planning Plan-Space Planning GraphplanSatPlan and their Comparison Multi-agent planning 1 and Multi-agent planning 2 Probabilistic Reasoning - Bayesian Networks Decision Trees and Bayes net inference

5 INTEGRATION TO ROBOT Total Hrs 9

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for obstacle detection - AI algorithms for path finding and decision making

Total hours to be taught 45

Reference(s)

1 Duda Hart and Stork Pattern Recognition Wiley-Interscience 2000

2 Mallot Computational Vision Information Processing in Perception and Visual Behavior Cambridge MA MIT Press 2000

3 Fundamentals of Robotics Analysis and control By Robert Schilling and Craig Hall of India Private Limied New Delhi 2003

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073458E DESIGN AND ANALYSIS OF ALGORITHMS

3 0 0 3 50 50 100

Objective(s) To introduce the basic concepts of algorithms mathematical aspects and analysis of algorithms To introduce various algorithm techniques

1 INTRODUCTION Total Hrs 9

Polynomial and Exponential algorithms big oh and small oh notation exact algorithms and heuristics direct indirect deterministic algorithms static and dynamic complexity stepwise refinement

2 DESIGN TECHNIQUES Total Hrs 9

Subgoals method working backwards work tracking branch and bound algorithms for traveling salesman problem and knapsack problem hill climbing techniques divide and conquer method dynamic programming greedy methods

3 SEARCHING AND SORTING Total Hrs 9

Sequential search binary search block search Fibonacci search bubble sort bucket sorting quick sort heap sort average case and worst case behavior FFT

4 GRAPH ALGORITHMS Total Hrs 9

Minimum spanning tree shortest path algorithms R-connected graphs Evens and Kleitmans algorithms ax-flow min cut theorem Steiglitzs link deficit algorithm

5 SELECTED TOPICS Total Hrs 9

NP Completeness Approximation Algorithms NP Hard Problems Strasseus Matrix Multiplication Algorithms Magic Squares Introduction To Parallel Algorithms and Genetic Algorithms Monti-Carlo Methods Amortised Analysis

Total hours to be taught 45

Reference(s)

1 Sara Baase Computer Algorithms Introduction to Design and Analysis Addison Wesley 1988

2 THCorman CELeiserson and RLRioest Introduction to Algorithms Mc Graw Hill 1994

3 DEGoldberg Genetic Algorithms Search Optimization and Machine Learning Addison Wesley 1989

4 EHorowitz and SSahni Fundamentals of Computer Algorithms Galgotia Publications 1988

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp

Name 34 ME Applied

Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073459E VLSI SIGNAL PROCESSING 3 0 0 3 50 50 100

Objective(s) To study the transformations for high speed using pipelining returning and parallel processing techniques To gain experience on power reduction transformation for supply voltages reduction capacitance To learn area reduction using folding techniques

1 INTRODUCTION TO DSP SYSTEMS Total Hrs 9

Introduction To DSP Systems -Typical DSP algorithms Iteration Bound ndash data flow graph representations loop bound and iteration bound Longest path Matrix algorithm Pipelining and parallel processing ndash Pipelining of FIR digital filters parallel processing pipelining and parallel processing for low power

2 RETIMING Total Hrs 9

Retiming - definitions and properties Unfolding ndash an algorithm for Unfolding properties of unfolding sample period reduction and parallel processing application Algorithmic strength reduction in filters and transforms ndash 2-parallel FIR filter 2-parallel fast FIR filter DCT algorithm architecture transformation parallel architectures for rank-order filters Odd- Even Merge- Sort architecture parallel rank-order filters

3 FAST CONVOLUTION Total Hrs 9

Fast convolution ndash Cook-Toom algorithm modified Cook-Took algorithm Pipelined and parallel recursive and adaptive filters ndash inefficientefficient single channel interleaving Look- Ahead pipelining in first- order IIR filters Look-Ahead pipelining with power-of-two decomposition Clustered Look-Ahead pipelining parallel processing of IIR filters combined pipelining and parallel processing of IIR filters pipelined adaptive digital filters relaxed look-ahead pipelined LMS adaptive filter

4 BIT-LEVEL ARITHMETIC ARCHITECTURES Total Hrs 9

Scaling and roundoff noise- scaling operation roundoff noise state variable description of digital filters scaling and roundoff noise computation roundoff noise in pipelined first-order filters Bit-Level Arithmetic Architectures- parallel multipliers with sign extension parallel carry-ripple array multipliers parallel carry-save multiplier 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation design of Lyonlsquos bit-serial multipliers using Hornerlsquos rule bit-serial FIR filter CSD representation CSD multiplication using Hornerlsquos rule for precision improvement

5 PROGRAMMING DIGITAL SIGNAL PROCESSORS Total Hrs 9

Numerical Strength Reduction ndash sub expression elimination multiple constant multiplications iterative matching Linear transformations Synchronous Wave and asynchronous pipelining- synchronous pipelining and clocking styles clock skew in edge-triggered single-phase clocking two-phase clocking wave pipelining asynchronous pipelining bundled data versus dual rail protocol Programming Digital Signal Processors ndash general architecture with important features Low power Design ndash needs for low power VLSI chips charging and discharging capacitance short-circuit current of an inverter CMOS leakage current basic principles of low power design

Total hours to be taught 45

Reference(s)

1 Keshab KParhi ―VLSI Digital Signal Processing systems Design and implementation Wiley Inter Science 1999

2 Gary Yeap ―Practical Low Power Digital VLSI Design Kluwer Academic Publishers 1998

3 Mohammed Isamail and Terri Fiez ―Analog VLSI Signal and Information Processing Mc Graw-Hill 1994

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code amp Name

34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073460E INTERNET TECHNOLOGIES AND APPLICATION

3 0 0 3 50 50 100

Objective(s) To describe the elocutions of the internet to understand the protocols and standards used throughout the internet To discuss a variety of internet and WWW applications and related technologies

1 INTRODUCTION Total Hrs 9

Introduction to course Review networking concepts (Basics of Computer communication and networking - LAN WAN etc)

2 INTERNET CORE Total Hrs 9

Internet core - Fundamental Protocols (IP TCP UDP ICMP ARP and an introduction to IP multicast) - IP routing and Routing protocols (RIP RIP -II IGRP EIGRP OSPF etc) - TCP and UDP in more depth IP network design and troubleshooting The Domain Name System (DNS) DHCP and other Important IPUtilitylsquo Protocols

3 INTERNET APPLICATIONS Total Hrs 9

Internet applications - Fundamental Applications (Email Telnet File Transfer and News) - Directories amp Distributed Applications (NFS LDAP ILS NIS etc) Internet applications - Streaming amp Real time communications (H323 VTC VolP Netmeeting etc)

4 WORLD WIDE WEB Total Hrs 9

The World Wide Web Part 1 - The basics (HTML HTTP and security protocols) The World Wide

Web Part 2 - Advanced topics (CGI Perl D-HTML Java ASP VRML amp SML)

5 INTERNET MANAGEMENT amp SECURITY Total Hrs 9

SNMP RMON IPsec L2TP and others The future of the Internet amp Related applications - IPv6 Internet2 and NGI Some hardwork assignments will require the use of common network troubleshooting tools retrieval of information from the web and basic Web-related programming assignments (Typically Linux systems should be sufficient Any LAN can be converted into a Linux LAN)

Total hours to be taught 45

Reference(s)

1 Computer networking - A top down approach featuring the internet James F Kurose and Keith W Ross (pearson Addison Wesley)

2 Stevens ―Unix Network Programming Vol1 Second Edition Prentice Hall1999

3 Stevens ―Unix Network Programming Vol2 Second Edition prentice Hall1999

4 Internetworking with TCPIP Volume I Principles protocols Architecture by Dougles E Corner

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000

BoS Chairman 34 ME APPLIED ELECTRONICS - REGULATION 2007 - SYLLABUS

KSRangasamy College of Technology - Autonomous Regulation R 2007

Department Electronics and Communication

Engineering Programme Code

amp Name 34 ME Applied Electronics

Semester I

Course Code Course Name Hours Week Credit Maximum Marks

L T P C CA ES Total

073461E INTERNETWORKING MULTIMEDIA 3 0 0 3 50 50 100

Objective(s) To understand the concept of multimedia system over the internetworking To study the various compression techniques for images and video signal

1 MULTIMEDIA NETWORKING Total Hrs 9

Digital sound video and graphics basic multimedia networking multimedia characteristics evolution of Internet services model network requirements for audio video transform multimedia coding and compression for text image audio and video

2 BROAD BAND NETWORK TECHNOLOGY Total Hrs 9

Broadband services ATM and IP IPV6 High speed switching resource reservation Buffer management traffic shaping caching scheduling and policing throughput delay and jitter performance Storage and media services voice and video over IP MPEG-2 over ATMIP indexing synchronization of requests recording and remote control

3 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Total Hrs 9

Multicast over shared media network multicast routing and addressing scaping multicast and NBMA networks Reliable transport protocols TCP adaptation algorithm RTP RTCP MIME Peer- to-Peer computing shared application video conferencing centralized and distributed conference control distributed virtual reality light weight session philosophy

4 MULTIMEDIA COMMUNICATION STANDARDS Total Hrs 9

Objective of MPEG- 7 standard Functionalities and systems of MPEG-7 MPEG-21 Multimedia Framework Architecture - Content representation Content Management and usage Intellectual property management Audio visual system- H322 Guaranteed QOS LAN systems MPEG_4 video Transport across internet

5 MULTIMEDIA COMMUNICATION ACROSS NETWORK Total Hrs 9

Packet Audiovideo in the network environment video transport across Generic networks- Layered video coding error Resilient video coding techniques Scalable Rate control Streaming video across Internet Multimedia transport across ATM networks and IP network Multimedia across wireless networks

Total hours to be taught 45

Reference(s)

1 Jon Crowcroft Mark Handley Ian Wakeman Internetworking Multimedia Harcourt Asia Pvt Ltd Singapore 1998

2 BO Szuprowicz Multimedia Networking McGraw Hill NewYork 1995

3 Tay Vaughan Multimedia making it to work 4ed Tata McGraw Hill New Delhi 2000