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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2859030, IEEETransactions on Power Electronics

Family of Multiport Switched-Capacitor MultilevelInverters for High Frequency AC Power

DistributionS. Raghu Raman,Student Member, IEEE, Y.C. Fong,Student Member,IEEE, Ye Yuanmao,Member,IEEE

and K.W.E. Cheng, Senior Member, IEEE,

Abstract—This paper proposes a family of multiportswitched-capacitor multilevel inverter (SCMLI) topologiesfor high frequency AC power distribution. It employs asym-metric DC voltage sources with a common ground whichmakes it ideal to be employed in renewable energy farmsand modern electric vehicles. The proposed family of step-up SCMLI attains higher number of output voltage stepswith optimum component count in comparison to severalexisting topologies. The problem of capacitor voltage bal-ancing is solved as the capacitors are inherently chargedto a finite voltage every half cycle. In-depth study on twostaircase modulation strategies, namely selective harmonicelimination and minimum total harmonic distortion schemeis presented with study on the variation of switching anglesand THD with modulation indices under both schemes.Working principle and analysis are presented for the pro-posed family of topologies. Simulation outcomes are vali-dated with experimental results under both the aforemen-tioned modulation schemes with equal and unequal outputvoltage waveform steps.

Index Terms—H-bridge, HFAC power distribution, highfrequency DC/AC Inverter, multilevel inverter, selectiveharmonic elimination, pulse width modulation, switched-capacitor, total harmonic distortion

I. INTRODUCTION

H IGH Frequency Alternating Current Power DistributionSystems (HFAC PDS) offer numerous benefits over

conventional DC PDS. Principle advantage is that HFAC PDSomits the rectifier and a filter stage in front end, and aninverter stage in the point of load power supply [1]. Thereduction in the number of power processing stages reflects asimproved efficiency, fewer component count, higher reliabilityand lower cost. NASA, in 1980s, initiated research in HFACPDS for their space station [2]. HFAC PDS have featuresthat make them attractive to aerospace, telecommunication,lighting, computer power supply, micro-grids and automotive

This article is an extension of the conference paper titled”Switched-capacitor Multilevel Inverters for High Frequency ACMicrogrids” presented at the 2017 Applied Power ElectronicsConference and Exposition in Tampa, Florida, USA. S. RaghuRaman ([email protected]), Yat Chi Fong ([email protected]) and corresponding author K.W.ECheng ([email protected]) are with the Power ElectronicsResearch Centre, Department of Electrical Engineering, TheHong Kong Polytechnic University, Hong Kong. Ye Yuanmao([email protected]) is with the School of Automation,Guangdong University of Technology, China.

applications [1]–[8]. A HFAC PDS includes a HFAC source,a distribution track and point-of-load converters. This paperfocuses on employing a switched-capacitor multilevel inverter(SCMLI) as an HFAC source.

Renewable energy farms have several DC sources, usuallybatteries. These inverters can effectively be utilized in suchrenewable energy based microgrids as it employs multiple DCinput sources of different magnitude. HFAC PDS employingcompact transformers, smaller filters and high density powerconverters offer several advantages to the micro-grids user [8].HFAC distribution enables to filter out higher order harmonicsrelatively easily. Major hindrance for HFAC power distributionis the higher ohmic losses due to skin and proximity effects,and magnified impedance across the transmission line. Boththese factors increase with increase in length of distributionand distribution frequency.

Multilevel inverters (MLI) have attained wide acceptanceowing to the exciting features they offer. MLI output stair-case waveforms which greatly mitigates the harmonic contentwhen compared to traditional square wave inverters. MLI aregenerally classified into diode clamped, capacitor clamped(also referred to as flying capacitor) and cascaded multilevelinverters [9], [10]. Diode clamped MLI require many addi-tional diodes as the level increases, the capacitor voltages areunbalanced and the voltage rating for the blocking diodesis high. Capacitor clamped MLI also suffer from voltageimbalance and require several additional storage capacitors asthe voltage level increases which makes it more expensiveand difficult during the package process. The major drawbackin cascaded MLI is the necessity for separate isolated DCsources.

There has been growing interest in Switched-CapacitorMultilevel Inverters (SCMLI) over the past few years [11]–[26]. A seven-level SCMLI using series-parallel conversionemploying a single DC source with comparison of level andphase-shifted PWM is presented in [11]. A generalized single-source step-up SCMLI capable of driving inductive loads ispresented in [12]. A novel SCMLI proposed in [13] alsoutilizes a single DC source to obtain a voltage stepup. In[14], [15], an SC doubler circuit is employed with traditionalcascaded H-bridge to obtain a relatively higher voltage stepcount with fewer components in comparison to the traditionalcascaded MLI. The partial charging of SC technique discussedin [16] is relatively complicated as it is difficult to control the



VIN1

VIN2

D1 D2

S2

S1

S3

C2

+

S4S5

D3

C1

+Q2

Q3

VDCbusI0 load

Q1

Q4

Switched capacitor

double mode

circuit

Switched capacitor based front end DC-DC converter Full bridge inverter

(a) Proposed topology A

VIN1VIN2 S3

C2

+

S4S5

D3C1+ Q2

Q3

I0 load

Q1

Q4

S1 S2

D1

D4D2

Switched capacitor based front end DC-DC converter Full bridge inverter

Switched capacitor

half mode circuit

VDCbus

(b) Proposed topology B

Fig. 1: Two basic proposed structures of SCMLI employing (a) SC voltage double mode circuit (b) SC voltage half mode circuit

charging profile of the boost SCMLI. In [17], a multi-sourcestep-up SCMLI with reduced component count capable ofdriving inductive loads is presented. Similarly, in [18], multiplesources are utilized along with a single SC cell to realizea stepup SCMLI. A capacitive voltage divider technique isused to obtain a nine-level SCMLI in [19]. In [20], a novelSC cell with two capacitors in parallel with a DC source isproposed to realize a boost SCMLI capable of driving R-Lloads. A hybrid nineteen-level MLI utilizing the features ofboth SC and flying capacitor technique is presented in [21].In [22], the SCMLI utilizes the bipolar series-parallel or cross-switched SC technique to charge the switched-capacitors andto step-up the voltage. Asymmetric voltage sources are usedto derive multilevel output voltage waveform without steppingup in [26].

SCMLI topologies in [11], [13], [19] employ a singlevoltage source to realize higher number of output voltagelevels whereas [18], [23], [24], [26] employ multiple DCvoltage sources. However, both these types operate by chargingthe parallel SC to input voltage and discharging it whileconnecting in series to the load. SCMLI are relatively moreapt to high frequency output AC inverters [13] as the size ofthe energy storage capacitor at high frequency is small andthe quality of output waveform is better with low distortion.Several switching techniques including phase shift [14], SHE[13], [24], level and phase shifted PWM [11] for SCMLI havebeen studied.

To realize a high frequency AC micro-grid of a few kWs, itis crucial to employ power converters with fewer componentsto realize a cost effective system with higher reliability. Withthe proliferation in renewable energy based solar and windfarms, such multi-input topologies gain tremendous potential.This would make it easier to convince the customers to partic-ipate; for example to install roof top solar panels with HFAC(or even LFAC) PV inverters. This new family of inverters

naturally tend to use fewer components to realize a multilevelstaircase output when compared to traditional topologies ofMLI. Additionally, their operation principle charges the DCcapacitor to a finite voltage each half cycle, which solves thevoltage imbalance issue. However, there is a limitation on thepower level these inverters can operate at. This limitation isdue to the fact that the DC capacitor employed is used tofeed the load during certain intervals of operation and there isan inherent limitation to it due to the voltage ripple. Also, athigher power levels, the size of the capacitor becomes larger.Higher capacitance also leads to spiky charging currents whichcan impact the life of a capacitor and lead to significant EMIissues.

II. TOPOLOGIES FOR HFAC MICROGRIDS

Both the SCMLI topologies discussed in the followingsubsections are derived from [24]. The first topology (Fig.1a)increases the number of output voltage levels by employing anSC doubler circuit by cascading it with a voltage source. Thesecond topology (Fig.1b) employing SC half circuit to increasethe voltage levels. Both these basic nine-level topologies aregeneralized (Fig.4a and 4b).

A. Topology A description and operation principleIn the proposed SCMLI topology A shown in Fig. 1a, front

end SC based DC-DC converter employs two input sources(VIN1 and VIN2), five transistors (S1, S2, S3, S4 and S5),three diodes (D1, D2 and D3) and two capacitors (C1 andC2). DC levels obtained at the inverter DC bus include VIN1,2VIN1, VIN2, VIN1 +VIN2. The H-bridge inverter employingtransistors Q1 to Q4 effectively outputs 8 bipolar levels(±VIN1, ±2VIN1, ±VIN2, ±(VIN1+VIN2)) and a zero acrossthe load. For the purpose of primary analysis, it is assumedthat the switches and the voltage sources employed are ideal;



VIN1VIN2

D1 D2

S2

S1

S3

C2

+

S4S5

D3

C1

+Q2

Q3

VDCbusI0

+VIN1

loadQ1

Q4

(a)

VIN1VIN2

D1 D2

S2

S1

S3

C2

+

S4S5

D3

C1

+Q2

Q3

VDCbusI0

+ 2VIN1

loadQ1

Q4

(b)

VIN1VIN2

D1 D2

S2

S1

S3

C2

+

S4S5

D3

C1

+Q2

Q3

VDCbusI0

+VIN2

loadQ1

Q4

(c)

VIN1 VIN2

D1 D2

S2

S1

S3

C2

+

S4S5

D3

C1

+Q2

Q3

VDCbusI0

+VIN1+VIN2

loadQ1

Q4

(d)

Fig. 2: Equivalent circuits of the proposed 9-level SCMLI to obtain different voltage levels (a) Vo = VIN1 (b) Vo = 2VIN1 (c) Vo = VIN2 (d) Vo =VIN1 + VIN2

capacitances (C1 and C2) are large enough to maintain aconstant voltage and supply constant output current, and thevoltage ripple across them is small enough to be neglected.Table 1 explains the switching logic of the proposed inverter.The working states are explained in the following subsections.In general, to obtain a positive voltage across the load, H-bridge transistors Q1 and Q3 are turned ON. Similarly, toobtain a negative voltage across the load, transistors Q2 andQ4 are turned ON.

TABLE I: Switching logic for the proposed topology A

S1 S2 S3 S4 S5 VDCbus

0 1 0 0 1 VIN1

1 0 0 0 0 2V1N1

0 0 1 0 0 VIN2

0 0 1 1 0 VIN2+VIN1

0 1 0 0 1 0

TABLE II: Switching logic for proposed topology B

S1 S2 S3 S4 S5 VDCbus

1 0 0 0 1 0.5VIN1

1 1 0 0 0 VIN1

0 0 1 0 0 VIN2

0 0 1 1 0 0.5VIN1+VIN2

0 1 0 0 1 0

1) Output voltage = ±VIN1 state: Capacitor C1, is chargedequal to the input voltage source VIN1 through D1 by turningON transistor S2, while capacitor C2 is charged to VIN1

by turning ON transistor S5, through diodes D1 and D2.Transistors S1, S3, S4 and diode D3 remain turned OFF. TheDC bus voltage at this state is equal to VIN1 as VIN2 isblocked by OFF transistor S3. Fig. 2(a) depicts the equivalentstate for V0 = +VIN1.

2) Output voltage = ±2VIN1 state: Transistor S1 is turnedON, while S2 is OFF, which connects VIN1 in series withcapacitor C1 (charged to VIN1) and diode D2. At this state,VDCbus is equal to 2VIN1. Transistors S3, S4 and S5 remain

turned OFF. Diodes D1 and D3 are reverse biased. Fig. 2(b)depicts the equivalent state for V0 = +2VIN1.

3) Output voltage = ±VIN2 state: For normal operationof the proposed inverter, VIN2 > VIN1. In the SC front endDC-DC converter, only transistor S3 is turned ON while othertransistors are turned OFF. Therefore, VIN2 is connected tothe DC bus through diode D3. Diodes D1 and D2 are reversebiased and hence block VIN1. Fig. 2(c) depicts the equivalentstate for V0 = VIN2. During this interval, capacitor C1 can becharged by turning ON transistor S2 to reduce the SC voltageripple and improve the performance.

4) Output voltage = ±(VIN1 +VIN2) state: Capacitor C2,charged to VIN1, is connected in series with input voltagesource VIN2 by turning ON transistors S3 and S4. DiodesD1 and D2 are reverse biased and hence block VIN1. The netvoltage that appears across the DC bus now is equal to VIN1+VIN2. Fig. 2(d) depicts the equivalent state for V0 = (VIN1 +VIN2). During this interval, capacitor C1 can be charged byturning ON transistor S2 to reduce the SC voltage ripple andimprove the performance.

5) Output voltage = Zero level state: To obtain zero levelat the output after the positive half cycle, only transistor Q1

is turned ON, while all the other switches in the full bridgeinverter remain turned OFF. The body diode of transistor Q2,DQ2, is employed for free-wheeling. Similarly, to obtain zerolevel at the output after the negative half cycle, only transistorQ4 is turned ON, while all the other switches in the fullbridge inverter remain turned OFF. In this case, the bodydiode of transistor Q3, DQ3 is employed for free-wheeling.The switches in the front end DC level shifter remain in theirprevious states.

It is possible to charge the capacitor C2 to 2VIN1 by turningON transistors S1 and S5 to realize an output of VIN2+2V IN1.This will result in the output voltage steps becoming unequal.Let us consider this example when VIN1 = 20 V and VIN2 =60 V. If VC2

= VIN1, then the output voltage steps would be± 20V, ±40V, ±60V and ±80V (Table I). If VC2

= 2VIN1,



VIN1VIN2

S3

C2

+

S4S5

D3

C1

+ Q2

Q3

VDCbusI0 load

Q1

Q4

S1 S2

D1

D4D2

0.5VIN1

(a)

VIN1VIN2

S3

C2

+

S4S5

D3

C1

+ Q2

Q3

VDCbusI0 load

Q1

Q4

S1 S2

D1

D4D2

VIN1+

(b)

VIN1VIN2

S3

C2

+

S4S5

D3

C1

+ Q2

Q3

VDCbusI0 load

Q1

Q4

S1 S2

D1

D4D2

VIN2+

(c)

VIN1VIN2

S3

C2

+

S4S5

D3

C1

+ Q2

Q3

VDCbusI0 load

Q1

Q4

S1 S2

D1

D4D2

0.5VIN1+VIN2+

(d)

VIN1VIN2

S3

C2

+

S4S5

D3

C1

+ Q2

Q3

VDCbusI0 load

Q1

Q4

S1 S2

D1

D4D2

+

(e)

Fig. 3: Equivalent circuits of the proposed 9-level SC MLI to obtain differentvoltage levels (a) Vo = 0.5VIN1 (b) Vo = VIN1 (c) Vo = VIN2 (d) Vo =0.5VIN1 + VIN2 (e) Zero state and balancing voltage of capacitor C1 andC2

then the output voltage steps would be ±20V, ±40V, ±60Vand ±100V (Table I). If VC2

= 2VIN1, the output voltagewould have a higher step up ratio, however, the THD wouldbe slightly poorer due to non-equal voltage steps as validatedin section III of the paper.

B. Topology B description and operation principleIn the proposed SCMLI of Fig. 2, front end SC based DC-

DC converter employs two input sources (VIN1 and VIN2),five transistors (S1, S2, S3, S4 and S5), four diodes (D1,D2, D3 and D4) and two capacitors (C1 and C2). DC levels

obtained at the inverter DC bus include 0.5VIN1, VIN1, VIN2,0.5VIN1 + VIN2. The H-bridge inverter employing transistorsQ1 to Q4 effectively produces 8 bipolar levels (±0.5VIN1,±VIN1, ±VIN2, ±(0.5VIN1 + VIN2)) and a zero across theload. Table II explains the switching logic of the proposedinverter. The working states are explained in the followingsubsections.

1) Output voltage = ±0.5VIN1 state: Capacitors C1 andC2, are charged to 50% the input voltage source VIN1 byturning ON transistors S1 and S5, through diodes D2 and D4.Transistors S2, S3, S4 and diodes D1 and D3 remain turnedOFF. The DC bus voltage at this state is equal to 0.5VIN1

as VIN2 is blocked by OFF transistor S3. Fig. 3a depicts theequivalent state for V0 = +0.5VIN1.

2) Output voltage = ±VIN1 state: Transistors S1 and S2

are turned ON, which connects VIN1 to the DC bus throughdiode D4. Transistors S3, S4 and S5 remain turned OFF.Diodes D1, D2 and D3 are reverse biased. Fig. 3b depictsthe equivalent state for V0 = +VIN1.

3) Output voltage = ±VIN2 state: For normal operationof the proposed inverter, VIN2 6= VIN1. In the SC front endDC-DC converter, only transistor S3 is turned ON while othertransistors are turned OFF. Therefore, VIN2 is connected to theDC bus through diode D3. Diodes D1, D2 and D4 are reversebiased. Fig. 3c depicts the equivalent state for V0 = VIN2.

4) Output voltage = ±(0.5VIN1 + VIN2) state: CapacitorC2, charged to 0.5VIN1, is connected in series with inputvoltage source VIN2 by turning ON transistors S3 and S4.All the diodes are reverse biased. The net voltage that appearsacross the DC bus now is equal to 0.5VIN1 + VIN2. Fig.3ddepicts the equivalent state for V0 = (VIN1 + VIN2).

5) Output voltage = Zero voltage state: Under this state,the load is shorted to get a zero voltage across it by turningON Q1 and Q3. In the front end side, this state is utilizedto balance the capacitor voltages. The capacitor voltages areimbalanced since C1 never discharges to the load. Therefore,by connecting C1 and C2 in parallel by turning ON S2

and S5, the capacitor voltages can be effectively balancedFig.3e depicts the equivalent state for zero voltage state whilebalancing the capacitor voltages.

C. Topology improvisation

The proposed topologies can be further extended toincrease the number of output voltage levels. A generalizedfront end topology for the proposed SCMLI in Fig.1ais shown in Fig.4a. An additional unit comprising of avoltage source and SC based double-mode circuit alongwith a few switches are included. If an additional voltagesource VIN3 is added, then the output voltage levels wouldbe ±VIN1,±VIN2,±VIN3,±2VIN1,±2VIN3,±(VIN1 +VIN2),±(VIN1 +VIN3),±(VIN2 +VIN3),±(2VIN2 +VIN3),±(VIN1 +VIN2 +VIN3) and a zero level (21 bi-polar levels).Similarly, the same accentuated part can be added over the21-level inverter to realize a higher level inverter. Switchinglogic for the generalized topology is given in Table III.

A generalized front end topology for the SCMLI proposedin Fig.1b is shown in Fig.4b. By inserting an additional voltage



VIN2

VIN1

D1 D2S1

C2+

S4S5

D3C1+

C4

S10

C3

D5D4D6

VIN3

S8

S6+

+

VDCbus

S2S7

S9

S3

(a)

VIN2

VIN1

S3

C2

+

S4S5

D3C1+S1 S2

D1

D4D2

VDCbus

VIN2

VIN3

S6 S7

S8

S9

S10

C3

C4D5

D6

D7++

(b)

VIN1

VIN2

D1 D2

S2

S1

S3S4

D3

C1

+Q2

Q3

VDCbusI0

+

load

Q1

Q4

D4

(c)

VIN1 VIN2

DX

SX

CX

+

SX

SX

DX Q2

Q3

VDCbus

I0

+

load

Q1

Q4

Double –

mode

OR

half –

mode

circuit

Double –

mode

OR

half – mode

circuit

(d)

Fig. 4: (a) Generalized topology A with asymmetric sources. (b) Generalized topology B with asymmetric sources. (c) Modified topology A with fewertransistors and SCs. (d) General structure for SCMLI combining both half-mode and double mode SC converters.

TABLE III: Switching logic for the generalized topology for Fig. 1a

S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 VDCBUS

0 0 0 0 0 0 1 0 0 1 VIN3

0 0 0 0 0 1 0 0 0 0 2VIN3

0 1 0 0 1 0 0 1 0 0 VIN2

1 0 0 0 0 0 0 1 0 0 2VIN2

0 0 1 0 0 0 0 1 0 0 VIN1

0 0 0 0 0 0 0 0 1 0 VIN3 + VIN2

0 0 1 0 0 0 0 0 1 0 VIN3 + VIN1

0 0 1 1 0 0 0 1 0 0 VIN2 + VIN1

1 0 0 0 0 0 0 0 1 0 2VIN2 + VIN3

0 0 1 1 0 0 0 0 1 0 VIN1 + VIN2 + VIN3

source as shown, the new set of output voltages would be±VIN1,±VIN2,±VIN3,±0.5VIN3,±0.5VIN2,±(0.5VIN3 +0.5VIN2),±(VIN2+0.5VIN3),±(VIN1+0.5VIN2),±(VIN1+0.5VIN3),±(VIN1 + 0.5VIN2 + 0.5VIN3) and a zero level.Switching logic for the generalized topology is given in TableIV. A single unit is highlighted with dotted lines.

In the proposed topology A, shown in Fig. 1a, it can beobserved that the switches S2 and S5 have identical switchinglogic (highlighted in Table I). Additionally, the SCs C1 andC2 are charged to the same voltage VIN1. This provides anopportunity to merge both the switches and utilize a singleSC to realize a nine-level output. Fig. 4c presents a modifiedtopology eliminating one transistor (S5) and an SC from theoriginal topology A without sacrificing the number of outputvoltage levels. This innovation results in the cutting down thecost and the size of the inverter.

Fig.4d depicts a generic way of increasing the number ofoutput voltage levels by inserting an SC double-mode or ahalf-mode circuit. Any one of the SC circuit can be cascadedto either of voltage sources to realize higher output voltagelevels.

D. Comparisons with other proposed topologiesFor the topology in Fig. 4a, the number of output levels are

increased by inserting SC doubler circuitry to additional volt-

0 100 200 300 400 500 60065

70

75

80

85

90

95

100

Output Power (Watt)

Effi

cien

cy (

%)

Efficiency comparison based on simulation

Topology ATopology BModified Topology A[12][14]

Fig. 5: Efficiency comparison of different topologies using simulation

age sources whereas for topology in Fig. 4d, SC half circuitryis employed. Employing an SC doubler circuit increases thestep-up capability of the SCMLI enabling relatively highervoltage operations thereby utilizing all the advantages of alower current system. However, it also relatively increases thevoltage stress of the H-bridge. Fig.4c shows an innovative way



TABLE IV: Switching logic for the generalized topology for Fig. 1b

S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 VDCBUS

0 0 0 0 0 1 1 0 0 0 VIN3

0 0 0 0 0 1 0 0 0 1 0.5 VIN3

1 1 0 0 1 0 0 1 0 0 VIN2

1 0 0 0 0 0 0 1 0 0 0.5 VIN2

0 0 1 0 0 0 0 1 0 0 VIN1

1 0 0 0 0 0 0 0 1 0 0.5 (VIN3+ VIN2)1 1 0 0 0 0 0 0 1 0 0.5 VIN3 + VIN2

0 0 1 1 0 0 0 1 0 0 VIN1 + 0.5 VIN2

1 0 0 0 0 0 0 0 1 0 VIN1 + 0.5 VIN3

0 0 1 1 0 0 0 0 1 0 VIN1 + 0.5 VIN2 + 0.5 VIN3

to reduce the active switches and SC count in the proposedinverter based on SC doubler (Fig.1a).

In Table V, several proposed SCMLI structures are com-pared with respect to the number of active switches (nT ) anddiodes(nD) used, number of output levels (nl) generated andthe number of voltage sources (i) by choosing the numberof switched-capacitors employed (n) as the reference. It isseen that the proposed SCMLI offers a good trade-off betweenthe number of components employed to the output levelsgenerated. In Table VI, multi-input SCMLI topologies withsymmetric output voltage levels are compared using costfunction (CF), similar to the cost function analysis proposedin [17], [20]. The cost function is simplified and dependantonly on the number of components. It is given by -

CF =(2nT + nD + n)nDC

nl(1)

The cost function in the above equation takes into accountthe number of transistors and drivers, diodes, DC sources andSCs. For simplicity, the number of drivers is assumed to beequal to the number of transistors and written as 2nT . FromTable VI, it can be seen that proposed family of SCMLI havea CF in the similar range with the Modified Topology Ahaving the least CF. The topology from [20] and the ModifiedTopology A offer the least CF which means that they producehigher number of symmetric output voltage levels with fewercomponents.

Most SCMLI topologies in the literature, including theproposed family, employ fewer semiconductor switches andcapacitors when compared to traditional MLI. The novelFibonacci inverter proposed in Fig.2 of [25] uses fewer com-ponents than the conventional inverter. However, the proposedSCMLI employs relatively fewer components even when com-pared to the novel Fibonacci inverter. For example, to realizea 15-level inverter (7 x step up) the novel Fibonacci inverteremploys eight SCs, twenty four transistors and six diodes witha single voltage source. In comparison, the proposed invertercan obtain twenty-one levels with only four SCs, fourteentransistors, six diodes and three asymmetric voltage sources.

The ability of the proposed family of inverters to drive largeinductive loads is restricted. This limitation can be observedfrom the topology. This is because there is no path for theinductor current to flow to the ground during certain intervals.The maximum angle between the voltage and current can onlybe θ1 (Refer Fig.6), similar to the topologies in [13], [24].However, topologies proposed in [12], [17], [20] can drive

large inductive loads. This is one shortcoming of the proposedfamily of SCMLI.

The efficiency comparison is carried out in Fig.5 for differ-ent nine level inverters under pure resistive loading. To obtaina fair comparison, the following parameters and non-idealitieswere chosen. RdsON = 0.09Ω, Rin = 0.1Ω, ESR = 0.05Ω,Rd = 0.05Ω, VF = 0.42V , C = 1000µF and fS = 400Hz.The peak voltage for all topologies was adjusted to ±80 Vwith steps of ± 20 V. All the topologies were switched usingstaircase modulation. The common trend is that the efficiencydrops as the power increases. Another observation is that withincrease in the number of switches, and especially SCs, thefall in efficiency is higher. The proposed family of SCMLIutilizes the SC voltage only to obtain very few output voltagelevels when compared to single source SCMLI proposed in[12], [13], [15], [17]–[19]. For example, topology A and Butilizes the SC voltage directly in four out of nine outputvoltage levels. The remainder levels are directly supported bythe voltage source. In comparison, the topology proposed in[12], having the least efficiency among the compared ones,utilizes the SC voltage in five out of seven voltage levels.This allows the proposed family of SCMLI to operate at acomparatively higher efficiency as the loss effect from SCripple voltage is mitigated.

III. MODULATION STRATEGIES FOR THE PROPOSEDSCMLI

Pulse width modulation (PWM) techniques for inverterscan be broadly categorized into carrier based high frequencyswitching PWM and fundamental switching frequency basedPWM. In high frequency switching PWM, the switching lossesare severe as the transistors and diodes are commutated severaltimes per switching cycle. In the case of fundamental switch-ing frequency based PWM, the transistors are commutated justonce or twice per switching cycle. This reduces switching lossconsiderably. However, high switching frequency techniquesare popular as they can realize a better output voltage harmonicspectra. Since the HFAC inverters already switch at higherfrequencies relatively to low-frequency switching inverter,fundamental switching frequency approaches are investigatedto minimize the switching losses without compromising on thequality of the output voltage waveform quantified by the TotalHarmonic Distortion (THD).

Staircase modulation is a subset of fundamental switch-ing frequency which can further be classified into time and



TABLE V: Comparison of SCMLI topologies

nT nD i nl Max voltageFig. 1 [12] 3n+ 4 0 1 2n+ 3 (n+ 1)VcFig. 1 [13] n+ 5 2n 1 2n+ 3 (n+ 1)VcFig. 1 [14] 6n n n 4n+ 1 nVINFig. 2 [17] 3n+ 3 n 1 2n+ 3 (n+ 1)VcFig. 3 [15] 2n+ 4 n 1 2n+ 3 (n+ 1)VcFig. 2 [19] 4n+ 1 n 1 4n+ 1 nVINFig. 1 [20] 4n+ 1 n/2 n/2 4n+ 1 4nVINFig. 4 [24] 3n+ 4 2n n+ 1 2(n+2) − 1

∑Vci+VIN0

Fig.4a 2.5n+ 4 1.5n (n/2) + 1 6n− 3∑VINi

Fig.4b 2.5n+ 4 4n− 4 (n/2) + 1 6n− 3 VIN1 +∑VINi/2

TABLE VI: Comparison of SCMLI topologies with symmetric output voltagelevels

nT nD n nDC nl CFTopology A 9 3 2 2 9 5.11Topology B 9 4 2 2 9 5.33

Modified Topology A 8 4 1 2 9 4.66Fig. 8 [18] 10 1 1 3 13 5.07

[14] 12 2 2 2 9 6.22[20] 18 2 4 2 18 4.66[24] 10 4 2 3 15 5.2

Va

Vb

Vc

Vd

-Va

-Vb

-Vc

-Vd

Synthesized Output Voltage (V0)

Modulating signal (VMod )

VMod V0

ω t

V1

V2

V3

V4

-V1

-V2

-V3

-V4

θ1 θ2 θ3 θ4 π/2

T

π 3π/2 2πθ5 θ6 θ7 θ8

δ3 δ4 δ5 δ2 δ1

Fig. 6: Multilevel staircase modulation principle

frequency domain based approaches [18]. Simple staircasemodulation employed for the proposed SCMLI is shown inFig. 6. Va, Vb , Vc and Vd are different output voltage levelscorresponding to the value set by reference voltage levelsV1, V2, V3 and V4 respectively. The reference voltages caneither be set using potentiometers in analog controllers orthe corresponding angles (θ1, θ2, θ3 and θ4) can directlybe programmed into digital controllers. In this paper, twomodulation approaches for the proposed inverters are studied.

A. Selective Harmonic Elimination

Selective harmonic elimination [27] is a popular example forthe frequency domain based approach. This technique obtainsthe required fundamental output voltage and also eliminatesspecific lower order harmonics by choosing pre-calculatedswitching angles for a given modulation index. The majordrawback of this technique is the demand for higher processingpower to solve a set of non-linear transcendental equations asshown for an m-level inverter in (2) [24].

cosθ1 + ......+ cosθs = zMI

cos3θ1 + ......+ cos3θs = 0

cos5θ1 + ......+ cos5θs = 0

cos7θ1 + ......+ cos7θs = 0

.....

(2)

where the switching angles (θ1..θs) are

0 < θ1 < θ2 < ... < θs <π

2(3)

where z(z = m−1

2

)is a function of the number of output

levels. MI is the modulation index (the ratio of the desiredfundamental voltage (V1) to the maximum obtainable funda-mental voltage) given by (4)

MI =πV1

4zVIN(4)

For an m level inverter,(m−12

)specific harmonics can be

eliminated as shown in (2). Triplen harmonics are usually notincluded in the SHE calculations as they cancel out themselvesin a 3-phase inverter. Switching angles for various modulationindices (solutions for (2)) are plotted in Fig. 7. Fig. 7a and 7bshows the plot of the switching angles for a 7 level (θ1, θ2, θ3)and 9 level SCMLI (θ1, θ2, θ3.θ4) respectively, for a widerange of MI . Fig. 7c shows the plot of THD versus MI for both7 level and 9 level SCMLI calculated using the correspondingswitching angles. It is seen that the 9 level waveform has alower THD value in comparison to the 7 level one. THD (γ) ofthe output waveform is given by (5). For three phase inverteroutput, triplen harmonics cancel out and therefore the THD iscomparatively lower than their single phase counterparts.

γ =

√(Vrms

V1rms

)2

− 1 (5)

B. Minimum THD

Nearest switching scheme [28] is a time domain basedapproach and demands relatively lesser processing powerwhen compared to the SHE. Additionally, it is proven thatthis technique enables to obtain the minimum possible THDwith equal and unequal input voltage sources [29], [30].



Modulation indices0.66 0.68 0.7 0.72 0.74 0.76 0.78 0.8 0.82 0.84

Ang

le in

deg

ree

0

10

20

30

40

50

60

70

80

90

Selective Harmonic Elimination

31

32

33

(a)


Ang

le in

deg

ree

0

10

20

30

40

50

60

70

80

90Selective Harmonic Elimination

31

32

33

34

(b)


TH

D

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45THD vs. Modulation index - Selective Harmonic Elimination

7 level9 level

(c)

Fig. 7: Selective harmonic elimination angles for (a) 7 level inverter (b) 9 level inverter (c) THD vs modulation indices for 7 (with 5th and 7th harmonicseliminated) and 9 (with 5th, 7th and 11th harmonics eliminated) level inverter

1) Equal voltage steps: A simple equation with a singlevariable for iteration to solve for the switching angles whenthe voltage steps are equal [29] is given by -

s∑i=1

√√√√1−

(i− 0.5

s− 0.5ρ

)2

= sMI (6)

θi = sin−1

(i− 0.5

s− 0.5ρ

)i = 1, 2, ...s. (7)

where MI denotes the modulation index, s denotes thenumber of number of H bridges in the given cascaded H-bridgeinverter and ρ is the only variable to be solved. This techniqueis relatively simpler to implement on a digital control platformwhen compared to SHE because there is only one variable tobe solved using iteration.

Fig.8a and Fig.8b shows the plot of different switchingangles versus the modulation indices for seven-level and nine-level waveforms respectively. These angles are computed using(6) and (7). Fig.8c shows the plot of THD versus MI for bothseven-level and nine-level staircase waveform.

2) Unequal voltage steps: Similarly for staircase AC wave-forms with unequal voltage steps, [30] provides a solutiongiven by -

MI =s∑

k=1

ek√

1− (µkρ)2 (8)

ek =Ek∑si=1El

(9)

µk =

∑ki=1Ei − Ek/2∑si=1Ei − Es/2

(10)

θk = sin−1(µkρ) k = 1, 2.., s (11)

In the above equations, Ek is the magnitude of the cor-responding voltage step and Es is the magnitude of thelast voltage step (refer Fig. 2 in [30]). For the modulationscheme, the inputs to the algorithm include the magnitudeof the voltage sources (E1 to Es) and MI . The algorithmoutputs switching angles (θ1..θs) such that the THD of the

output voltage waveform is minimum. Fig.8d and Fig.8e showsthe plot of different switching angles versus the modulationindices for seven-level and nine-level waveforms respectively.These angles are computed using (8), (9), (10) and (11).Fig.8f shows the plot of THD versus MI for both seven-leveland nine-level staircase waveform when the voltage steps areunequal. For seven-level waveform the ratio of the unequalvoltage sources were E1 : E2 : E3 = 10 : 8 : 17. Similarly,for the nine-level waveform, the ratio of the unequal voltagesources were E1 : E2 : E3 : E4 = 10 : 8 : 12 : 15.

IV. CIRCUIT CHARACTERISTICS AND ANALYSIS

For the family of proposed multi-port SCMLI topologies,it is essential to identify the nature of the voltage sourcesthat can be employed. There are several voltage sourcesavailable including batteries (Li-ion, Pb-acid, Ni based), super-capacitors and fuel cells. The type of voltage source to beemployed can be analysed using the input current waveforms.Input current waveforms of both topology A and topology Bare shown in Fig. 9a and Fig. 9b respectively. From thesewaveforms, it is clear that the input current of the voltagesource VIN1 is relatively spiky and pulsating. Therefore, VIN1

can either be a super-capacitor bank or an old Pb-acid batterybank. The voltage source VIN2 which has a lesser spikycurrent profile can be a Li-ion battery. By choosing the voltagesource keeping in mind the current profile, it is possible toextend the operating life of the energy source. Additionally,the waveforms also reveal vital information on the powerrequirements from each voltage source. HFAC SCMLI areused for a few kWs, like in an auxiliary power supply fora car or microgrids. The proposed multiport converters makean ideal choice as the aforementioned applications generallyemploy more than one type of voltage source.

In a SCMLI, the SC is charged by the input voltage sourceto a finite value and the energy stored in the SC is dischargedto the load every cycle. During this cyclic process, there is a in-herent loss due to several parasitic resistive components. Theyinclude the ESR, MOSFETs on-state resistances (RdsON ),voltage source internal resistances (Rin) and diode internalresistance (Rd). Therefore, the maximum voltage that the SC



Modulation indices0.65 0.7 0.75 0.8 0.85

Ang

le in

deg

ree

0

10

20

30

40

50

60

70

80

90

Min. THD with equal voltage steps

31

32

33

(a)


Ang

le in

deg

ree

0

10

20

30

40

50

60

70

80

90

Min. THD with equal voltage steps

31

32

33

34

(b)


TH

D

0.08

0.1

0.12

0.14

0.16

0.18

THD vs. Modulation index - Min. THD with equal voltage steps

7 level9 level

(c)


Ang

le in

deg

ree

0

10

20

30

40

50

60

70

80

Min THD with unequal voltage steps

31

32

33

(d)

Modulation indices0.65 0.7 0.75 0.8 0.85 0.9

Ang

le in

deg

ree

0

10

20

30

40

50

60

70

80

90Min. THD with unequal voltage steps

31

32

33

34

(e)


TH

D

0.09

0.1

0.11

0.12

0.13

0.14

0.15

0.16

0.17

0.18THD vs. Modulation index - Min. THD with unequal voltage steps

7 level9 level

(f)

Fig. 8: Minimum THD angles with equal voltage steps for (a) 7 level inverter and (b) 9 level inverter. Minimum THD angles with unequal voltage steps for(d) 7 level inverter (ratio of sources were E1 : E2 : E3 = 10 : 8 : 17) and (e) 9 level inverter(E1 : E2 : E3 : E4 = 10 : 8 : 12 : 15). THD vs modulationindices for 7 and 9 level inverter for (c) equal voltage steps and (f) unequal voltage steps

TABLE VII: Least computed THD for different PWM switching schemes

PWM SHE 7-level SHE 9-level MTHD eq 7-level MTHD eq 9-level MTHD uneq 7-level MTHD uneq 9-level

MI 0.8 0.81 0.83 0.82 0.79 0.8THD 0.12 0.091 0.1103 0.0836 0.1222 0.0971

is charged to is determined by the net voltage drop across theseresistive components and diode voltage drop (VF ), if any.

The general expression for RMS value of the m-level volt-age staircase waveform (Fig. 6) is given by (12). If the SCMLIis connected to a R-L load then the I0RMS is represented by(13)

V0RMS=

√2

π(V 2

a δ1 + V 2b δ2 + .........+ V 2

n δn) (12)

I0RMS=

V0RMS√(RL)2 + (XL)2

6 tan−1(XL

RL

)(13)

where, Va, Vb...Vn are voltage levels at the output. For thenine-level SCMLI in Fig.1a, Fig.1b and Fig.4c the voltagelevels are given by (14) (15) and (16) respectively.

Va = VIN1 − 2VF − I0(2RdsON+Rin)

Vb = VIN1 + VC1 − VF − Io(3RdsON+ ESR+Rin)

Vc = VIN2 − VF + Io(3RdsON+Rin)

Vd = VIN2 + VC2 − I0(4RdsON+Rin + ESR)

VC1 = VC2 ≈ VIN1 − VF − Ic1(RdsON+Rin + ESR)

(14)

Va = VIN1 − VC1 − 2VF − I0(3RdsON+Rin + ESR)

Vb = VIN1 − VF − Io(4RdsON+Rin)



VC1 = VC2 ≈ 0.5VIN1 − IC(2RdsON+Rin + 2ESR)

(15)



time (ms)5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

I 0 (

A)

-10

0

10

time (ms)5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

I IN2 (

A)

0

5

10

time (ms)5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

I IN1 (

A)

0

20

40

(a)

time (ms)5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

I 0 (

A)

-10

0

10

time (ms)5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

I IN2 (

A)

0

5

10

time (ms)5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

I IN1 (

A)

0

5

10

(b)

Fig. 9: Input currents (a) (IIN1 and IIN2) profile for Topology A of Fig.1a and (b) (IIN1 and IIN2) profile for Topology B of Fig.1b operating at 400 Hz

Va = VIN1 − 3VF − I0(2RdsON+Rin)

Vb = VIN1 + VC1 − 2VF − Io(3RdsON+Rin + ESR)



VC1 ≈ VIN1 − IC(RdsON+Rin + ESR)

(16)

A. Ripple analysis

The ripple voltage in general depends on the load current,fundamental frequency, and the value of the capacitance. Fortopology A (Fig.1a), the capacitors C1 and C2 are charged to afinite value (14) when connected in parallel to the input voltagesources. The capacitor C1 and C2 are discharged only duringδ3 (during V0 = 2VIN1) and δ5 (during V0 = VIN1 + VIN2)respectively. This period occurs twice in a half cycle. Similarlyin topology B (Fig.1b), C1 and C2 are charged to a finite value(14) and are discharged only during δ3 and δ5 respectively. Thedischarging period results in the voltage ripple across the SCwhich can be generically represented as –

∆VC =∆QC

C=

1

ωSC

∫ td2

td1

iOsin(ωSt− φ)dωSt (17)

where, td1 and td2 correspond to the net discharging period,∆VC is the voltage ripple, ∆QC is the amount of chargereleased during the period, i0 is the output current with anangular frequency of ωS lagging the output voltage by anangle φ. For the output waveform with equal voltage steps(the difference in the magnitude of succeeding output voltagesteps are identical) scenario discharging to a purely resistiveload (RL), ∆QC can be further approximated to [13] –

∆QCi ≈V0(2δi)

2πfSRL(18)

where, VIN is the equal voltage step, RL is the resistanceof the load and fS is the fundamental frequency of theoutput waveform. Therefore, the capacitors C1 and C2, in bothtopology A and B, can be computed using –

C1 ≥2VIN1δ3

πfSRL∆VC1(19)

C2 ≥(VIN1 + VIN2)δ5πfSRL∆VC2

(20)

For the modified nine-level topology in Fig.4c, the solitarycapacitor C1 discharges during δ3 (during V0 = 2VIN1) andδ5 (during V0 = VIN1 + VIN2). Since the output current islarger during δ5, the minimum capacitance for the modifiedtopology (Fig.4c) can be computed by –

C1 ≥(VIN1 + VIN2)δ5πfSRL∆VC1

(21)

B. Loss analysisThe loss in the SCMLI is the sum of transistor switching

losses, conduction losses and switched-capacitor losses. TheMOSFET switching losses is due to the losses incurred incyclic charging and discharging of the MOSFET output ca-pacitance CT at transitor switching frequency (fT ). During theMOSFET turn-OFF transition, a linear increase in the drain-to-source voltage is observed. Therefore, CT is charged fromnearly zero volt to close to the input voltage VT (equal to thevoltage stress across the switch) . The power loss due to thisphenomenon is given by [31] -

Psw = V 2TCT fT (22)

The above equation is true for a linear capacitance. Half ofthe total switching loss is dissipated in the MOSFET andthe other in the charging path of the output capacitance CT .For example, the net switching loss incurred by topology



IC1

+

-VIN1

Rin

C1

RdsON

ESR

RdVF

IC2

+

-C2

RdsON

ESR

RdVF

2RdsON

RL

I0

(a)

VIN1

Rin

RdsON

+-

ESR

RdC1 VF

2RdsON

RLI0

(b)

VIN2

Rin

RdsON RdVF

2RdsON

RL

I0

(c)

VIN2

Rin

2RdsON

+-

ESR

C2 2RdsON

RLI0

(d)

Fig. 10: Equivalent circuits of the nine-level SCMLI topology A during (a) Capacitors C1 and C2 charging, VIN1 level(b) Capacitors C1 discharging, 2VIN1

level (c) VIN2 level (d) Capacitors C2 discharging, VIN1 + VIN2 level

TABLE VIII: Conduction loss computation using output current

Output V. VIN1 2VIN1 VIN2 VIN1 + VIN2

I0VIN1 − 2VF

Rin + 2Rd + 2RdsON +RL

2VIN1 − VF

Rin +Rd + 3RdsON +RL

VIN2 − VF

Rin +Rd + 3RdsON +RL

VIN2

Rin + 4RdsON +RL

A is presented. For the high bridge MOSFETs (Q1 to Q4),the maximum voltage stress for the topology A is equalto VIN1 + VIN2. Similarly, for MOSFETs S1 and S2 themaximum voltage stress is VIN1. For S3, S4 and S5 themaximum voltage stress is VIN2, (VIN2 - VIN1) and

∑VINi

respectively. The net maximum switching loss of topology Acan be elaborated to -

Psw = fS(VIN1 + VIN2)24∑

i=1

CQi + fT

(2V 2

IN1CS1 + V 2IN2

CS3 + (VIN2 − VIN1)2CS4 + (VIN2 + VIN1)2CS5

).

(23)

where, CSx and CQi are output capacitances of the frontend and H-bridge MOSFETs respectively and fS is the fun-damental frequency of the output. Switching loss in diodes(Psw(D)) [32] is given by

Psw(D) =VDIrrpfstr

6(24)

where, tr is the time taken by the reverse recovery current tofall from its peak value of Irrp to zero when a voltage of VDis applied across the diode.

Conduction losses in the transistors and the diodes aredue to their respective on-state resistances (RdsON

and Rd).Similarly, conduction losses in the SC is due to their respectiveESR. From Fig.10a, the maximum charging currents for theswitched-capacitors C1 and C2 can be given by -

IC1ch(m)=

VIN1 − VF − VC1i

Rin +Rd +RdsON + ESR=Veq1

Req1

IC2ch(m)=

VIN1 − 2VF − VC2i

Rin + 2Rd +RdsON + ESR=Veq2

Req2

(25)

The charging current ICichRMSis given by

ICichRMS=

√2

T

∫ tch2

tch1

(IC(i)ch(m)

e−t/Req(i)C(i)

)2(t)dt

(26)where, T is the fundamental period, tch2 − tch1 is the

charging interval during which the peak capacitor chargingcurrent (ICch(i)(m)

) decays exponentially while being dampedby the equivalent charging path resistance (Req(i)).

The SC discharging current ICidisRMSfor C1 and C2 is

equal to the magnitude of the output current during δ3 andδ5 respectively. The discharging current (ICdis(i)

) (refer toFig.10b and Fig.10d) trajectory is given by -

ICdis(i)=

VdisiReqd(i)

(e−t/Reqd(i)C(i)

)(27)

where, Reqd(i) is the equivalent resistance in the dischargingpath of the respective capacitors and Vdisi is the initial value ofcapacitor voltage prior to their respective discharging periods.ICidisRMS

is given by -

ICidisRMS=

√2

T

∫ tdis2

tdis1

VdisiReqd(i)

(e−t/Reqd(i)C(i)

)2(28)

where, the discharging period tdis2 − tdis1 for SCs C1 andC2 is equal to the period during δ3 and δ5 respectively.

For conduction loss in the switches, it is assumed that thevoltage levels V1, V2 etc (referring to Fig.6) are constant anddo not change in the respective time intervals δ1, δ2 etc.The RMS current through different semiconductor switchescan be computed from Table VIII and the capacitor currentexpressions computed above. Table VIII gives the expres-sion for I0 during different voltage levels. For example, theconduction loss in MOSFET S2 and S5 can be computedusing the charging current of capacitor C1 (IC1chRMS

) and C2

(IC2chRMS) respectively. Similarly, conduction loss of MOS-

FET S1, S3 and S4 are computed using the RMS current of I0during ±2VIN1 state, ±VIN2 and ±VIN1 + VIN2 states, and±VIN1 +VIN2 state respectively. Conduction losses of diodesD1, D2 and D3 are computed using RMS currents during theinterval of ±VIN1, ±2VIN1 and ±VIN2 respectively.

Assuming all transistors have equal RdsON, all diodes have

equal Rd, and all SC have equal ESR, the conduction lossesin the circuit can be computed by -

Pcon(T ) =∑nT

i=1 I2TiRMSRdsON

Pcon(D) =∑nD

i=1 I2DiRMSRd

Pcon(SCdis) = I2CdisRMSESR

Pcon(SCch) = I2CchRMSESR

(29)

The above set of equations suggests to employ switches andswitched-capacitors with low internal resistances to mitigate



TABLE IX: Simulation and Experimental parameters

VIN1 (V) VIN2 (V) min. C1 and C2 (F) ESR (Ω) RdsON (Ω) VF (V) RL (Ω) min. fS (Hz)

20 60 560 µ 50 m 9 m 0.4 20 400

Time (ms)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vol

tage

(V

)

-80

-60

-40

-20

0

20

40

60

80Output Voltage and Current

Cur

rent

(A

)

-4

-3

-2

-1

0

1

2

3

4

(a)

Time (ms)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vol

tage

(V

)

-80

-60

-40

-20

0

20

40

60

80Output Voltage and Current

Cur

rent

(A

)

-4

-3

-2

-1

0

1

2

3

4

(b)

Frequency (kHz)0 2 4 6 8 10 12 14 16

Vo (

V)

0

20

40

60

80

100Fast Fourier transform of the Output Voltage

THD = 9.51%Fundamental = 80.1 V3rd Harmonic = 0.23 V5th Harmonic = 0.5 V7th Harmonic = 0.4 V9th Harmonic = 1.4 V11th Harmonic = 0.65 V13th Harmonic = 0.33 V15th Harmonic = 1.83 V

(c)Frequency (kHz)

0 2 4 6 8 10 12 14 16

Vo (

V)

0

10

20

30

40

50

60

70

80

90Fast Fourier transform of the Output Voltage

THD = 9.51 %Fundamental = 80.1 V

3rd Harmonic = 1.23 V

5th Harmonic = 1.5 V



11th Harmonic = 1.65V



(d)

Fig. 11: Simulation results operating at MI = 0.8 and fundamental frequency fS = 400 Hz (a) Output voltage and current under SHE (b) Output voltageand current under Min. THD technique operating with equal voltage steps (c) FFT of the output voltage under SHE (d) FFT of the output voltage under Min.THD technique operating with equal voltage steps

conduction losses. Larger capacitance can be chosen to reducethe loss due to the capacitor ripple.

V. RESULTS

The parameters are listed in Table IX. Simulation results,for the proposed topology A, depicting the output voltage andcurrent waveforms and SC voltage and current waveformsare shown in Fig. 11. The simulation is carried out at MI

= 0.8 for both SHE and minimum THD with equal steps.The FFT waveforms for SHE and minimum THD with equalsteps are depicted in Fig. 11c and Fig. 11d respectively. UnderSHE, the 5th and 7th harmonic are minimized to 0.5 Vand 0.4 V respectively. The harmonics are not equal to zerosince non-ideal components are employed during simulations.Additionally, the switching angles have decimal points and aredifficult to emulate during simulations. For minimum THDwith equal steps the THD is relatively lower than that underSHE. This confirms the theoretical evaluation and plots in andFig. 7c and Fig. 8c.

Experiment verification for topology A is carried out withthe same parameters. The voltage and current waveforms

of the output and the SC operating at 400 Hz are shownin Fig. 12. Fig. 13 show the waveforms at different outputpower frequency and power levels. At higher power levels,the voltage droop in the output waveform is higher due tohigher voltage ripple (plotted in Fig. 17b). However, the rippleproportionately reduces with increase in the output frequencyfor a given value of capacitance as explained in (17).

FFT of the output voltage for SHE modulation is shownin Fig. 14a. The digital oscilloscope displays the RMS valueof the amplitude of different frequency components. The 5th,7th and 11th harmonic are minimized (around 1 V) similarto the simulation results. FFT results for minimum THDmodulation is shown in Fig. 14b. The 3rd, 5th and 7th

harmonics are comparatively larger when compared to theSHE modulation scheme, similar to theoretical and simulationobservations. FFT results under minimum THD scheme withunequal voltage steps (Fig. 14c) show higher value of lowerorder harmonics in comparison.

The proposed SCMLI topology A is tested with different R-L loads and the waveforms are shown in Fig. 15. Fig.15a and15b depict 400 Hz waveforms of output voltage and current



(a) (b) (c) (d)

Fig. 12: Experimental results operating at fS = 400 Hz. (Ch.1 - Voltage, Ch.2 - Current) (a) Output voltage and current under SHE (MI = 0.8) (b) switchedcapacitor voltage and current under SHE (d) Output voltage and current under Min. THD technique operating with equal voltage steps (MI = 0.82) (e)switched capacitor voltage and current under Min. THD technique operating with equal voltage steps

(a)

(b)

Fig. 13: Experimental results (a) Output voltage and current at 400 Hz withoutput power of 88 W (b) Output voltage and current at 2200 Hz with outputpower of 320 W [23]

driving a 25 Ω-220 µH and 16.7 Ω-220 µH load respectively.Fig.15c and 15d depict 400 Hz waveforms of output voltageand current driving a 25 Ω-440 µH and 16.7 Ω-440 µH loadrespectively. It can be observed that the current waveformsdriving the 440 µH load is more sinusoidal. The ability of theproposed SCMLI to drive loads with larger inductance valueis limited as discussed in section II D.

The dynamic loading experiment is performed on topologyA and the results are shown in Fig.16. In Fig.16a and 16b,initially the SCMLI is driving a pure 25 Ω load. Another pure50 Ω is added in parallel using a switch to increase the loadcurrent by approximately 50%. Similarly, in Fig.16c and 16d,initially the SCMLI is driving a pure 16.7 Ω (25 Ω in parallelwith 50 Ω) load. The 50 Ω is removed from the current pathby opening the switch to lower the load current by 33%. It isseen that under both scenarios the SCMLI responds well.

Fig. 17a shows the measured plot of efficiency versus outputpower at different output frequencies. Fig. 17b shows themeasured plot of capacitor (C2) peak to peak ripple versusoutput power at different frequencies. With increase in fre-quency, the peak to peak capacitor voltage reduces. This in turnreduces the conduction loss in the capacitor and contributes tohigher efficiency. The efficiency drops with increase in outputpower. This can be mitigated by employing larger switched-capacitors, designing zero voltage switching or zero currentswitching front end converters and by choosing transistors withlow RdsON , diodes with low Vf .

VI. CONCLUSIONS

This article proposes a family of SCMLI topologies forhigh frequency AC applications. The asymmetric sourcesemployed have a common ground enabling simpler design.Inherent charging of the capacitors every half-cycle solves theproblem of capacitor voltage imbalance afflicting conventionalMLI. Operating principles of the two topologies proposedare discussed in detail with suggestions for improvements.Generalized topology structure is derived and compared toseveral existing topologies. Table V shows that the proposedSCMLI offers a good trade-off with respect to the number ofcomponents employed to generate a specific number of voltagelevels. Such inverters are extremely beneficial at situationswhere several DC sources are available, for example in thecase of renewable energy farms. To achieve higher power, itis better to employ multiple DC sources as input to a singleinverter than connecting several individual DC sources fedinverters in parallel.

Two different staircase modulation approaches - frequency-domain based selective harmonic elimination and time-domainbased minimum THD schemes were investigated. MinimumTHD scheme can even be used when the output voltagewaveform steps are not equal. Several switching angle versusmodulation indices plots for three variations of the aforemen-tioned staircase modulation approaches are presented. Theseplots give an idea to the reader on how the switching anglestypically vary with modulation index. THD values for thecorresponding switching angles are computed and plottedagainst modulation indices to obtain better understanding ofthe variation of THD with modulation index and the region of



(a) (b) (c)

Fig. 14: Experimental results (a) FFT of the output voltage under SHE technique operating (b) FFT of the output voltage under Min. THD technique operatingwith equal voltage steps (c) FFT of the output voltage under Min. THD technique operating with unequal voltage steps (Step size = 15V, 15V, 30V, 15V)

(a) (b) (c)

(d) (e) (f)

Fig. 15: Experimental results with R-L load (a) 25 Ω, 220 µH (b) 16.7 Ω, 220 µH (c) 25 Ω, 440 µH (d) 16.7 Ω, 440 µH (e) Zoomed in waveform 25 Ω, 220µH (f) Zoomed in waveform 16.7 Ω, 440 µH. Channel 1 - Output voltage, scale - 40 V per division. Channel 2 - Output current, scale - 5 A per division.

(a) (b)

(c) (d)

Fig. 16: Experimental results with dynamic loading (a) and (b) 50% increase in load current (c) and (d) 33% decrease in load current. Channel 1 - Outputvoltage, scale - 40 V per division. Channel 2 - Output current, scale - 5 A per division



Output Power (Watt)0 50 100 150 200 250 300 350

Effi

cien

cy (2)

(%)

75

80

85

90

95

100

400 Hz1 kHz1.5 kHz2 kHz

(a)

Output Power (Watt)0 50 100 150 200 250 300 350 400

Pea

k to

pea

k rip

ple

volta

ge (

in v

olts

)

0

0.5

1

1.5

2

2.5

3

3.5

4

400 Hz1 kHz1.5 kHz2 kHz

(b)

Fig. 17: Measured at MI = 0.8 using SHE for Topology A (a) efficiency versus output power at different output frequencies (b) peak to peak capacitor ripplevoltage (VC2, C2 = 560µF) versus output power at different output frequencies

the plot at which the THD is minimum. The proposed topologyA is tested under both modulation schemes. The experimentalresults validate the theoretical and simulation outcomes.

ACKNOWLEDGMENT

This work was supported by Innovation and TechnologyFund and the Automotive Parts and Accessory Systems R&Dcentre under Project GHP/057/14AP. The authors wish toacknowledge the support provided by the members of thePower Electronics Research Centre (PERC) at The Hong KongPolytechnic University. The authors appreciate the reviewersand the associate editor for their valuable suggestions whichhelped improve the quality of the paper.

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S. Raghu Raman (S’13) received the B.E. de-gree in electrical and electronics engineeringfrom Visvesvaraya Technological University, Be-lagavi, India in June 2012. He is working towardthe Ph.D. degree in power electronics from theHong Kong Polytechnic University, Hong Kong.

He interned in the Department of AerospaceEngineering, Indian Institute of Science (IISc),Bengaluru, India, during summer 2010. Aftergraduation, he joined the Power ElectronicsGroup, Department of Electrical Engineering,

IISc as a Research Assistant. In February 2014, he joined PowerElectronics Research Centre, Department of Electrical Engineering, TheHong Kong Polytechnic University as a Research Assistant.

His research interests include design and control power converters,battery, super-capacitors and fuel cell based systems, electric vehicle,and renewable energy technologies. He received the first prize paperaward during the Student Competition on Electric Transportation Design- Automotive, Vessel and Aircraft organized by the IEEE TransportationElectrification Committee in Dec. 2017.

Yat Chi Fong (S’16) received the B.Eng. degreein electrical engineering from The Hong KongPolytechnic University, Hong Kong, in 2013,where he is currently pursuing the Ph.D. degree.

In 2013, he joined the Department of Elec-trical Engineering, The Hong Kong PolytechnicUniversity, as a Research Intern, where he isalso a Research Student. His research interestsinclude dc-dc power converters, multilevel in-verters, switched-capacitor circuits, and batterymanagement systems.

Yuanmao Ye (M’16) received the B.Sc. degreein electrical engineering from University of Jinan,Jinan, China, in 2007, the M.Sc. degree in con-trol theory and control engineering from SouthChina University of Technology, Guangzhou,China, in 2010, and the Ph.D. degree from theHong Kong Polytechnic University, Hong Kong,in 2016. From September 2010 to January 2014,he was with the Department of Electrical Engi-neering, Hong Kong Polytechnic University, as aResearch Assistant.

He is currently a full Professor in School of Automation, Guangdong Uni-versity of Technology. His research interests include various dc-dc powerconverters, switched-capacitor technique and its applications, multilevelinverters, power conversion and energy management for smart-grids,protection and control techniques for DC distribution, wireless chargingtechnique for EVs.

K. W. E. Cheng (M’90-SM’06) received the B.Sc.and Ph.D. degrees from the University of Bath,Bath, U.K., in 1987 and 1990, respectively. Be-fore joining the Hong Kong Polytechnic Univer-sity, Kowloon, Hong Kong, in 1997, he was withLucas Aerospace, U.K., as a Principal Engineer,where he led a number of power electronicsprojects. He has authored / co-authored morethan 250 papers and 7 books. He is currentlya Professor at the dept. of Electrical Engineer-ing and Director of Power Electronics Research

Centre, Hong Kong Polytechnic University.Dr. Cheng’s research interests include all aspects of power electron-ics, motor drives, electromagnetic interference, electric vehicle, batterymanagement, and energy saving. He received the IEE Sebastian Z DeFerranti Premium Award in 1995, the Outstanding Consultancy Award in2000, the Faculty Merit Award for best teaching in 2003 from the HongKong Polytechnic University, the Faculty of Engineering Industrial andEngineering Services Grant Achievement Award in 2006, the BrusselsInnova Energy Gold Medal with Mention in 2007, the Consumer ProductDesign Award in 2008, the Electric Vehicle Team Merit Award of theFaculty in 2009, Geneva Invention Expo Silver Medal in 2011, EcoStar Award in 2012, Gold Prize for the design and development ofbody integrated super-capacitor panels for electric vehicles, at SeoulInternational Invention (2015) and iCAN 2016 for contribution in activesuspension for vehicles.

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