KL82 Sub-Family Reference Manual...KL82 Sub-Family Reference Manual, Rev. 3, 08/2016 NXP Semiconductors 3 Section number Title Page Core Overview 3.1 ARM Cortex-M0 3.1.1 Buses, interconnects,

KL82 Sub-Family Reference ManualSupports: MKL82Z128VMC7(R), MKL82Z128VLK7(R),

MKL82Z128VLL7(R), MKL82Z128VLH7(R), MKL82Z128VMP7(R)

Document Number: KL82P121M72SF0RMRev. 3, 08/2016

KL82 Sub-Family Reference Manual, Rev. 3, 08/2016

2 NXP Semiconductors

Contents

Section number Title Page

Chapter 1About This Manual

1.1 Audience....................................................................................................................................................................... 53

1.2 Organization..................................................................................................................................................................53

1.3 Module descriptions......................................................................................................................................................53

1.3.1 Example: chip-specific information that supersedes content in the same chapter.......................................54

1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 55

1.4 Register descriptions.....................................................................................................................................................56

1.5 Conventions.................................................................................................................................................................. 57

1.5.1 Numbering systems......................................................................................................................................57

1.5.2 Typographic notation................................................................................................................................... 57

1.5.3 Special terms................................................................................................................................................ 58

Chapter 2Introduction

2.1 Overview.......................................................................................................................................................................59

2.2 Block diagram...............................................................................................................................................................59

2.3 Module functional categories........................................................................................................................................60

2.3.1 ARM® Cortex®-M0+ Core Modules..........................................................................................................62

2.3.2 System modules........................................................................................................................................... 62

2.3.3 Memories and memory interfaces................................................................................................................63

2.3.4 Clocks...........................................................................................................................................................64

2.3.5 Analog modules........................................................................................................................................... 64

2.3.6 Timer modules............................................................................................................................................. 65

2.3.7 Security and Integrity modules.................................................................................................................... 65

2.3.8 Communication interfaces........................................................................................................................... 66

2.3.9 Human-machine interfaces.......................................................................................................................... 66

2.4 Ordering information.................................................................................................................................................... 67

Chapter 3


NXP Semiconductors 3


Core Overview

3.1 ARM Cortex-M0+ Core................................................................................................................................................69

3.1.1 Buses, interconnects, and interfaces............................................................................................................ 69

3.1.2 System tick timer......................................................................................................................................... 69

3.1.3 Debug facilities............................................................................................................................................ 69

3.1.4 Core privilege levels.................................................................................................................................... 70

3.2 Nested vectored interrupt controller (NVIC) configuration......................................................................................... 70

3.2.1 Interrupt priority levels................................................................................................................................ 70

3.2.2 Non-maskable interrupt................................................................................................................................70

3.2.3 Interrupt connections....................................................................................................................................70

3.2.4 Interrupt channel assignments......................................................................................................................72

3.2.5 INTMUX0 input mux assignment............................................................................................................... 73

3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................................ 74

3.3.1 AWIC overview........................................................................................................................................... 74

3.3.2 Wake-up sources.......................................................................................................................................... 75

Chapter 4Memories and Memory Interfaces

4.1 Flash memory............................................................................................................................................................... 77

4.1.1 Flash memory types..................................................................................................................................... 77

4.1.2 Flash memory sizes......................................................................................................................................77

4.1.3 Flash security............................................................................................................................................... 77

4.1.4 Flash modes..................................................................................................................................................77

4.1.5 Erase all flash contents.................................................................................................................................78

4.1.6 FTFA_FOPT register................................................................................................................................... 78

4.1.7 Flash access control introduction.................................................................................................................78

4.2 SRAM........................................................................................................................................................................... 79

4.2.1 SRAM sizes..................................................................................................................................................79

4.2.2 SRAM retention in low power modes..........................................................................................................79

4.3 QuadSPI memory interface...........................................................................................................................................80




4.4 System register file....................................................................................................................................................... 80

4.5 VBAT register file........................................................................................................................................................ 80

4.6 Memory map.................................................................................................................................................................80

4.6.1 Introduction..................................................................................................................................................80

4.6.2 System memory map....................................................................................................................................81

4.6.3 Flash memory map.......................................................................................................................................83

4.6.4 SRAM memory map.................................................................................................................................... 84

4.6.5 Peripheral bridge (AIPS-Lite) memory map................................................................................................84

4.6.6 Private peripherals........................................................................................................................................89

4.6.7 Private peripheral bus (PPB) memory map..................................................................................................89

Chapter 5Clock Distribution using MCG

5.1 Introduction...................................................................................................................................................................91

5.2 Programming model......................................................................................................................................................91

5.3 High-Level device clocking diagram............................................................................................................................91

5.4 Clock definitions...........................................................................................................................................................92

5.4.1 Device clock summary.................................................................................................................................93

5.5 Internal clocking requirements..................................................................................................................................... 96

5.5.1 Clock divider values after reset....................................................................................................................96

5.5.2 VLPR mode clocking...................................................................................................................................97

5.6 Clock gating..................................................................................................................................................................97

5.7 Module clocks...............................................................................................................................................................98

5.7.1 PMC 1-kHz LPO clock................................................................................................................................ 99

5.7.2 IRC 48MHz clock........................................................................................................................................ 99

5.7.3 WDOG clocking.......................................................................................................................................... 100

5.7.4 PORT digital filter clocking.........................................................................................................................101

5.7.5 LPTMR clocking..........................................................................................................................................101

5.7.6 TPM clocking...............................................................................................................................................102

5.7.7 USB FS OTG Controller clocking............................................................................................................... 102




5.7.8 LPUART clocking....................................................................................................................................... 103

5.7.9 QSPI clocking.............................................................................................................................................. 103

5.7.10 LP Trusted Cryptography (LTC) clocking...................................................................................................104

5.7.11 TRNG clocking............................................................................................................................................ 104

5.7.12 FlexIO clocking............................................................................................................................................104

5.7.13 EMVSIM clocking.......................................................................................................................................105

Chapter 6Reset and Boot

6.1 Introduction...................................................................................................................................................................107

6.2 Reset..............................................................................................................................................................................107

6.2.1 Power-on reset (POR).................................................................................................................................. 108

6.2.2 System reset sources.................................................................................................................................... 108

6.2.3 MCU Resets................................................................................................................................................. 111

6.2.4 Reset Pin ..................................................................................................................................................... 113

6.2.5 Debug resets.................................................................................................................................................113

6.3 Boot...............................................................................................................................................................................114

6.3.1 Boot sources.................................................................................................................................................114

6.3.2 Boot options................................................................................................................................................. 114

6.3.3 FOPT boot options....................................................................................................................................... 114

6.3.4 Boot sequence.............................................................................................................................................. 115

Chapter 7Kinetis ROM Bootloader

7.1 Chip-Specific Information............................................................................................................................................ 119

7.2 Introduction...................................................................................................................................................................120

7.3 Functional Description..................................................................................................................................................122

7.3.1 Memory Maps.............................................................................................................................................. 122

7.3.2 The Kinetis Bootloader Configuration Area (BCA).................................................................................... 122

7.3.3 Start-up Process............................................................................................................................................125

7.3.4 Clock Configuration.....................................................................................................................................127




7.3.5 Bootloader Entry Point.................................................................................................................................128

7.3.6 Bootloader Protocol..................................................................................................................................... 129

7.3.7 Bootloader Packet Types............................................................................................................................. 134

7.3.8 Bootloader Command API...........................................................................................................................141

7.3.9 Bootloader Exit state....................................................................................................................................165

7.4 Peripherals Supported................................................................................................................................................... 165

7.4.1 I2C Peripheral.............................................................................................................................................. 165

7.4.2 SPI Peripheral.............................................................................................................................................. 167

7.4.3 QuadSPI Peripheral .....................................................................................................................................170

7.4.4 USB peripheral.............................................................................................................................................179

7.5 Get/SetProperty Command Properties..........................................................................................................................183

7.5.1 Property Definitions.....................................................................................................................................184

7.6 SB File Decryption Support..........................................................................................................................................186

7.6.1 Decryption using LTC................................................................................................................................. 186

7.7 CRC-32 Check on Application Data.............................................................................................................................187

7.8 Kinetis Bootloader Status Error Codes.........................................................................................................................187

Chapter 8Power Management

8.1 Introduction...................................................................................................................................................................191

8.2 Clocking modes............................................................................................................................................................ 191

8.2.1 Partial Stop...................................................................................................................................................191

8.2.2 DMA Wakeup.............................................................................................................................................. 192

8.2.3 Compute Operation...................................................................................................................................... 193

8.2.4 Peripheral Doze............................................................................................................................................194

8.2.5 Clock Gating................................................................................................................................................ 195

8.3 Power modes description.............................................................................................................................................. 195

8.4 Entering and exiting power modes............................................................................................................................... 198

8.5 Power mode transitions.................................................................................................................................................198

8.6 Power modes shutdown sequencing............................................................................................................................. 199




8.7 Flash Program Restrictions...........................................................................................................................................200

8.8 Module Operation in Low Power Modes......................................................................................................................200

Chapter 9Security

9.1 Introduction...................................................................................................................................................................205

9.2 Flash security................................................................................................................................................................ 205

9.3 Security interactions with other modules......................................................................................................................206

9.3.1 Security interactions with debug..................................................................................................................206

Chapter 10Debug

10.1 Introduction...................................................................................................................................................................207

10.2 Debug port pin descriptions..........................................................................................................................................207

10.3 SWD status and control registers..................................................................................................................................208

10.3.1 MDM-AP control register............................................................................................................................209

10.3.2 MDM-AP status register.............................................................................................................................. 210

10.4 Debug resets..................................................................................................................................................................212

10.5 Micro trace buffer (MTB).............................................................................................................................................212

10.6 Debug in low power modes.......................................................................................................................................... 213

10.7 Debug and security....................................................................................................................................................... 214

Chapter 11Signal Multiplexing and Signal Descriptions

11.1 Signal multiplexing introduction.................................................................................................................................. 215

11.2 Signal multiplexing integration.................................................................................................................................... 215

11.2.1 Port control and interrupt module features.................................................................................................. 216

11.2.2 Clock gating................................................................................................................................................. 217

11.2.3 Signal multiplexing constraints....................................................................................................................217

11.3 Pinous............................................................................................................................................................................217

11.3.1 KL82 signal multiplexing and pin assignments...........................................................................................217

11.3.2 KL82 Pinouts............................................................................................................................................... 222

11.4 Module signal description tables.................................................................................................................................. 228




11.4.1 Core Modules...............................................................................................................................................228

11.4.2 System modules........................................................................................................................................... 228

11.4.3 Clock Modules............................................................................................................................................. 229

11.4.4 Memories and memory interfaces................................................................................................................230

11.4.5 Analog..........................................................................................................................................................231

11.4.6 Timer Modules.............................................................................................................................................232

11.4.7 Communication interfaces........................................................................................................................... 233

11.4.8 Human-machine interfaces (HMI)............................................................................................................... 236

Chapter 12Port Control and Interrupts (PORT)

12.1 Introduction...................................................................................................................................................................237

12.2 Overview.......................................................................................................................................................................237

12.2.1 Features........................................................................................................................................................ 237

12.2.2 Modes of operation...................................................................................................................................... 238

12.3 External signal description............................................................................................................................................238

12.4 Detailed signal description............................................................................................................................................239

12.5 Memory map and register definition.............................................................................................................................239

12.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................246

12.5.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................. 249

12.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................249

12.5.4 Global Interrupt Control Low Register (PORTx_GICLR).......................................................................... 250

12.5.5 Global Interrupt Control High Register (PORTx_GICHR)......................................................................... 250

12.5.6 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 251

12.6 Functional description...................................................................................................................................................251

12.6.1 Pin control.................................................................................................................................................... 251

12.6.2 Global pin control........................................................................................................................................ 252

12.6.3 Global interrupt control................................................................................................................................253

12.6.4 External interrupts........................................................................................................................................253

Chapter 13




System Integration Module (SIM)

13.1 Introduction...................................................................................................................................................................255

13.1.1 Features........................................................................................................................................................ 255


13.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 257





13.2.6 System Device Identification Register (SIM_SDID)...................................................................................264

13.2.7 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................266




13.2.11 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................274


13.2.13 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 278

13.2.14 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 279

13.2.15 Unique Identification Register High (SIM_UIDH)..................................................................................... 280

13.2.16 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................280

13.2.17 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 281

13.2.18 Unique Identification Register Low (SIM_UIDL)...................................................................................... 281


13.2.20 Misc Control Register (SIM_MISCCTRL)................................................................................................. 283

13.2.21 Secure Key Register 0 (SIM_SECKEY0)................................................................................................... 284




Chapter 14




EMV SIM

14.1 Chip-specific EMVSIM information............................................................................................................................ 287

14.1.1 Overview......................................................................................................................................................287

14.1.2 EMV_SIM instantiations............................................................................................................................. 287

14.2 Introduction...................................................................................................................................................................287

14.2.1 Features........................................................................................................................................................ 288

14.3 Block Diagram..............................................................................................................................................................288

14.4 Design Overview.......................................................................................................................................................... 289

14.5 Signal Description.........................................................................................................................................................291

14.6 Memory Map and Registers..........................................................................................................................................291

14.6.1 Version ID Register (EMVSIMx_VER_ID)................................................................................................293

14.6.2 Parameter Register (EMVSIMx_PARAM)................................................................................................. 293

14.6.3 Clock Configuration Register (EMVSIMx_CLKCFG)............................................................................... 294

14.6.4 Baud Rate Divisor Register (EMVSIMx_DIVISOR)..................................................................................295

14.6.5 Control Register (EMVSIMx_CTRL)......................................................................................................... 296

14.6.6 Interrupt Mask Register (EMVSIMx_INT_MASK)....................................................................................300

14.6.7 Receiver Threshold Register (EMVSIMx_RX_THD).................................................................................302

14.6.8 Transmitter Threshold Register (EMVSIMx_TX_THD)............................................................................ 303

14.6.9 Receive Status Register (EMVSIMx_RX_STATUS)..................................................................................304

14.6.10 Transmitter Status Register (EMVSIMx_TX_STATUS)............................................................................ 307

14.6.11 Port Control and Status Register (EMVSIMx_PCSR).................................................................................310

14.6.12 Receive Data Read Buffer (EMVSIMx_RX_BUF).....................................................................................312

14.6.13 Transmit Data Buffer (EMVSIMx_TX_BUF).............................................................................................313

14.6.14 Transmitter Guard ETU Value Register (EMVSIMx_TX_GETU).............................................................313

14.6.15 Character Wait Time Value Register (EMVSIMx_CWT_VAL).................................................................314

14.6.16 Block Wait Time Value Register (EMVSIMx_BWT_VAL)...................................................................... 314

14.6.17 Block Guard Time Value Register (EMVSIMx_BGT_VAL)..................................................................... 314

14.6.18 General Purpose Counter 0 Timeout Value Register (EMVSIMx_GPCNT0_VAL).................................. 315

14.6.19 General Purpose Counter 1 Timeout Value (EMVSIMx_GPCNT1_VAL)................................................ 315





14.7.1 Initialization................................................................................................................................................. 316

14.7.2 Smart Card Interface and Control................................................................................................................ 318

14.7.3 EMV SIM Receiver..................................................................................................................................... 321

14.7.4 EMV SIM Transmitter................................................................................................................................. 325

14.7.5 LRC and CRC.............................................................................................................................................. 327

14.7.6 Message Handling........................................................................................................................................329

14.7.7 Protocol Timers............................................................................................................................................331

14.7.8 Answer To Reset (ATR) Detection..............................................................................................................334

Chapter 15Reset Control Module (RCM)

15.1 Introduction...................................................................................................................................................................339

15.2 Reset memory map and register descriptions............................................................................................................... 339

15.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 340

15.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 341

15.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 343

15.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 344

15.2.5 Force Mode Register (RCM_FM)................................................................................................................345

15.2.6 Mode Register (RCM_MR)......................................................................................................................... 346

15.2.7 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................347

15.2.8 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................348

Chapter 16System Mode Controller (SMC)

16.1 Introduction...................................................................................................................................................................351

16.2 Modes of operation....................................................................................................................................................... 351

16.3 Memory map and register descriptions.........................................................................................................................353

16.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................354

16.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................355

16.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................357




16.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 358


16.4.1 Power mode transitions................................................................................................................................359

16.4.2 Power mode entry/exit sequencing.............................................................................................................. 362

16.4.3 Run modes....................................................................................................................................................364

16.4.4 Wait modes.................................................................................................................................................. 366

16.4.5 Stop modes...................................................................................................................................................367

16.4.6 Debug in low power modes......................................................................................................................... 371

Chapter 17Power Management Controller (PMC)

17.1 Introduction...................................................................................................................................................................373

17.2 Features.........................................................................................................................................................................373

17.3 Low-voltage detect (LVD) system................................................................................................................................373

17.3.1 LVD reset operation.....................................................................................................................................374

17.3.2 LVD interrupt operation...............................................................................................................................374

17.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 374

17.4 High-voltage detect (HVD) system.............................................................................................................................. 375

17.4.1 HVD reset operation.................................................................................................................................... 375

17.4.2 HVD interrupt operation.............................................................................................................................. 375

17.5 I/O retention..................................................................................................................................................................376

17.6 Memory map and register descriptions.........................................................................................................................376

17.6.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 377

17.6.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 378

17.6.3 Regulator Status And Control register (PMC_REGSC).............................................................................. 379

17.6.4 High Voltage Detect Status And Control 1 register (PMC_HVDSC1)....................................................... 381

Chapter 18Interrupt Multiplexer (INTMUX)

18.1 About this module.........................................................................................................................................................383

18.1.1 Introduction..................................................................................................................................................383




18.1.2 Features........................................................................................................................................................ 383

18.1.3 Block diagram.............................................................................................................................................. 383

18.2 Memory Map and register definition............................................................................................................................ 384

18.2.1 Channel n Control Status Register (INTMUXx_CHn_CSR)...................................................................... 385

18.2.2 Channel n Vector Number Register (INTMUXx_CHn_VEC).................................................................... 386

18.2.3 Channel n Interrupt Enable Register (INTMUXx_CHn_IER_31_0).......................................................... 387

18.2.4 Channel n Interrupt Pending Register (INTMUXx_CHn_IPR_31_0).........................................................387


18.3.1 Configuring Output Channels...................................................................................................................... 388

18.3.2 INTMUX Vectors........................................................................................................................................ 388

Chapter 19Low-Leakage Wakeup Unit (LLWU)

19.1 Chip-specific LLWU information.................................................................................................................................391

19.1.1 Wake-up sources.......................................................................................................................................... 391

19.2 Introduction...................................................................................................................................................................392

19.2.1 Features........................................................................................................................................................ 393


19.2.3 Block diagram.............................................................................................................................................. 394

19.3 LLWU signal descriptions............................................................................................................................................ 394

19.4 Memory map/register definition................................................................................................................................... 395

19.4.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................396








19.4.9 LLWU Module Enable register (LLWU_ME)............................................................................................ 405




19.4.10 LLWU Pin Flag 1 register (LLWU_PF1).................................................................................................... 406




19.4.14 LLWU Module Flag 5 register (LLWU_MF5)............................................................................................413

19.4.15 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 415





19.5.1 LLS mode.....................................................................................................................................................419

19.5.2 VLLS modes................................................................................................................................................ 419

19.5.3 Initialization................................................................................................................................................. 420

Chapter 20Miscellaneous Control Module (MCM)

20.1 Introduction...................................................................................................................................................................421

20.1.1 Features........................................................................................................................................................ 421

20.2 Memory map/register descriptions............................................................................................................................... 421

20.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................422

20.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 422

20.2.3 Platform Control Register (MCM_PLACR)................................................................................................423

20.2.4 Compute Operation Control Register (MCM_CPO)................................................................................... 426

Chapter 21Crossbar-Lite Switch (AXBS-Lite)

21.1 Chip-specific AXBS-Lite information..........................................................................................................................429

21.1.1 Crossbar-Light Switch Master Assignments - with System MPU...............................................................429

21.1.2 Crossbar-Light Switch Slave Assignments - with System MPU.................................................................429

21.2 Introduction...................................................................................................................................................................430

21.2.1 Features........................................................................................................................................................ 430




21.3 Memory Map / Register Definition...............................................................................................................................430


21.4.1 General operation.........................................................................................................................................430

Chapter 22Peripheral Bridge (AIPS-Lite)

22.1 Chip-specific AIPS-Lite information............................................................................................................................433

22.1.1 Number of peripheral bridges...................................................................................................................... 433

22.1.2 Memory maps.............................................................................................................................................. 433

22.1.3 AIPS_Lite MPRA register reset value......................................................................................................... 433

22.1.4 AIPS_Lite PACRE-P register reset values.................................................................................................. 433

22.2 Introduction...................................................................................................................................................................434

22.2.1 Features........................................................................................................................................................ 434

22.2.2 General operation.........................................................................................................................................434


22.3.1 Master Privilege Register A (AIPS_MPRA)............................................................................................... 435

22.3.2 Peripheral Access Control Register (AIPS_PACRn)...................................................................................438

22.3.3 Peripheral Access Control Register (AIPS_PACRn)...................................................................................444


22.4.1 Access support............................................................................................................................................. 448

Chapter 23Memory Protection Unit (MPU)

23.1 Chip-specific MPU information................................................................................................................................... 451

23.1.1 MPU slave port assignments........................................................................................................................451

23.1.2 MPU logical bus master assignments.......................................................................................................... 451

23.1.3 MPU access violation indications................................................................................................................ 451

23.1.4 Reset values for RGD0 registers..................................................................................................................452

23.1.5 Write access restrictions for RGD0 registers...............................................................................................452

23.2 Introduction...................................................................................................................................................................453

23.3 Overview.......................................................................................................................................................................453




23.3.1 Block diagram.............................................................................................................................................. 453

23.3.2 Features........................................................................................................................................................ 454


23.4.1 Control/Error Status Register (MPU_CESR).............................................................................................. 457

23.4.2 Error Address Register, slave port n (MPU_EARn)....................................................................................459

23.4.3 Error Detail Register, slave port n (MPU_EDRn)....................................................................................... 459

23.4.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0).............................................................................. 460




23.4.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................465


23.5.1 Access evaluation macro..............................................................................................................................467

23.5.2 Putting it all together and error terminations............................................................................................... 469

23.5.3 Power management...................................................................................................................................... 470

23.6 Initialization information.............................................................................................................................................. 470

23.7 Application information................................................................................................................................................470

Chapter 24Bit Manipulation Engine (BME)

24.1 Introduction...................................................................................................................................................................473

24.1.1 Overview......................................................................................................................................................474

24.1.2 Features........................................................................................................................................................ 474




24.3.1 BME decorated stores.................................................................................................................................. 476

24.3.2 BME decorated loads................................................................................................................................... 483

24.3.3 Additional details on decorated addresses and GPIO accesses....................................................................489

24.4 Application information................................................................................................................................................490




Chapter 25Direct Memory Access Multiplexer (DMAMUX)

25.1 Chip-specific DMAMUX information......................................................................................................................... 493

25.1.1 DMAMUX request sources......................................................................................................................... 493

25.1.2 DMA transfers via PIT trigger..................................................................................................................... 495

25.2 Introduction...................................................................................................................................................................495

25.2.1 Overview......................................................................................................................................................495

25.2.2 Features........................................................................................................................................................ 496


25.3 External signal description............................................................................................................................................497


25.4.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 498


25.5.1 DMA channels with periodic triggering capability......................................................................................499

25.5.2 DMA channels with no triggering capability...............................................................................................501

25.5.3 Always-enabled DMA sources.................................................................................................................... 501

25.6 Initialization/application information........................................................................................................................... 503

25.6.1 Reset.............................................................................................................................................................503

25.6.2 Enabling and configuring sources................................................................................................................503

Chapter 26Enhanced Direct Memory Access (eDMA)

26.1 Introduction...................................................................................................................................................................507

26.1.1 eDMA system block diagram...................................................................................................................... 507

26.1.2 Block parts................................................................................................................................................... 508

26.1.3 Features........................................................................................................................................................ 509

26.2 Modes of operation....................................................................................................................................................... 510


26.3.1 TCD memory............................................................................................................................................... 511

26.3.2 TCD initialization........................................................................................................................................ 511




26.3.3 TCD structure...............................................................................................................................................511

26.3.4 Reserved memory and bit fields...................................................................................................................512

26.3.1 Control Register (DMA_CR).......................................................................................................................519

26.3.2 Error Status Register (DMA_ES)................................................................................................................ 522

26.3.3 Enable Request Register (DMA_ERQ)....................................................................................................... 524

26.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................526

26.3.5 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 527

26.3.6 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 528

26.3.7 Clear Enable Request Register (DMA_CERQ)........................................................................................... 529

26.3.8 Set Enable Request Register (DMA_SERQ)............................................................................................... 530

26.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................ 531

26.3.10 Set START Bit Register (DMA_SSRT)...................................................................................................... 532

26.3.11 Clear Error Register (DMA_CERR)............................................................................................................533

26.3.12 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 534

26.3.13 Interrupt Request Register (DMA_INT)......................................................................................................535

26.3.14 Error Register (DMA_ERR)........................................................................................................................ 536

26.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................ 538

26.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................540

26.3.17 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 541

26.3.18 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................542

26.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................542

26.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................543

26.3.21 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 544

26.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)

(DMA_TCDn_NBYTES_MLOFFNO)....................................................................................................... 544

26.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)

(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 546

26.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................547

26.3.25 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................547




26.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................548

26.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_CITER_ELINKYES)...........................................................................................................548

26.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 550

26.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 551

26.3.30 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 551

26.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_BITER_ELINKYES)...........................................................................................................554

26.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 555


26.4.1 eDMA basic data flow................................................................................................................................. 556

26.4.2 Fault reporting and handling........................................................................................................................ 559

26.4.3 Channel preemption..................................................................................................................................... 561

26.4.4 Performance................................................................................................................................................. 561

26.5 Initialization/application information........................................................................................................................... 566

26.5.1 eDMA initialization..................................................................................................................................... 566

26.5.2 Programming errors..................................................................................................................................... 568

26.5.3 Arbitration mode considerations..................................................................................................................568

26.5.4 Performing DMA transfers.......................................................................................................................... 569

26.5.5 Monitoring transfer descriptor status........................................................................................................... 573

26.5.6 Channel Linking...........................................................................................................................................575

26.5.7 Dynamic programming................................................................................................................................ 576

Chapter 27External Watchdog Monitor (EWM)

27.1 Chip-specific EWM information.................................................................................................................................. 581

27.1.1 EWM clocks.................................................................................................................................................581

27.1.2 EWM low-power modes.............................................................................................................................. 581

27.1.3 EWM_OUT pin state in low power modes..................................................................................................581




27.2 Introduction...................................................................................................................................................................582

27.2.1 Features........................................................................................................................................................ 582

27.2.2 Modes of Operation..................................................................................................................................... 583

27.2.3 Block Diagram............................................................................................................................................. 584

27.3 EWM Signal Descriptions............................................................................................................................................ 584

27.4 Memory Map/Register Definition.................................................................................................................................585

27.4.1 Control Register (EWM_CTRL)................................................................................................................. 585

27.4.2 Service Register (EWM_SERV)..................................................................................................................586

27.4.3 Compare Low Register (EWM_CMPL)...................................................................................................... 586

27.4.4 Compare High Register (EWM_CMPH).....................................................................................................587

27.4.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................ 587


27.5.1 The EWM_out Signal.................................................................................................................................. 588

27.5.2 The EWM_in Signal.................................................................................................................................... 589

27.5.3 EWM Counter.............................................................................................................................................. 590

27.5.4 EWM Compare Registers............................................................................................................................ 590

27.5.5 EWM Refresh Mechanism...........................................................................................................................590

27.5.6 EWM Interrupt.............................................................................................................................................591

27.5.7 Counter clock prescaler................................................................................................................................591

Chapter 28Watchdog Timer (WDOG)

28.1 Chip-specific WDOG information................................................................................................................................593

28.1.1 WDOG clocks.............................................................................................................................................. 593

28.1.2 WDOG low-power modes........................................................................................................................... 593

28.2 Introduction...................................................................................................................................................................594

28.3 Features.........................................................................................................................................................................594

28.4 Functional overview......................................................................................................................................................595

28.4.1 Unlocking and updating the watchdog.........................................................................................................597

28.4.2 Watchdog configuration time (WCT).......................................................................................................... 598




28.4.3 Refreshing the watchdog..............................................................................................................................599

28.4.4 Windowed mode of operation......................................................................................................................599

28.4.5 Watchdog disabled mode of operation.........................................................................................................599

28.4.6 Low-power modes of operation................................................................................................................... 599

28.4.7 Debug modes of operation........................................................................................................................... 600

28.5 Testing the watchdog.................................................................................................................................................... 600

28.5.1 Quick test..................................................................................................................................................... 601

28.5.2 Byte test........................................................................................................................................................601

28.6 Backup reset generator..................................................................................................................................................603

28.7 Generated resets and interrupts.....................................................................................................................................603


28.8.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 605

28.8.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 606

28.8.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................607

28.8.4 Watchdog Time-out Value Register Low (WDOG_TOVALL).................................................................. 607

28.8.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 608

28.8.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 608

28.8.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 609

28.8.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................609

28.8.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 609

28.8.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 610

28.8.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 610

28.8.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 610

28.9 Watchdog operation with 8-bit access.......................................................................................................................... 611

28.9.1 General guideline......................................................................................................................................... 611

28.9.2 Refresh and unlock operations with 8-bit access......................................................................................... 611

28.10 Restrictions on watchdog operation..............................................................................................................................612

Chapter 29Multipurpose Clock Generator (MCG)




29.1 Chip-specific MCG information................................................................................................................................

Documents

KL82 Sub-Family Reference Manual...KL82 Sub-Family Reference Manual, Rev. 3, 08/2016 NXP Semiconductors 3 Section number Title Page Core Overview 3.1 ARM Cortex-M0 3.1.1 Buses, interconnects,